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19#ifndef _R819XU_PHY_H
20#define _R819XU_PHY_H
21
22#define MAX_DOZE_WAITING_TIMES_9x 64
23
24#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
25#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
26#define RadioA_ArrayLength RadioA_ArrayLengthPciE
27#define RadioB_ArrayLength RadioB_ArrayLengthPciE
28#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
29#define RadioC_ArrayLength RadioC_ArrayLengthPciE
30#define RadioD_ArrayLength RadioD_ArrayLengthPciE
31#define PHY_REGArrayLength PHY_REGArrayLengthPciE
32#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
33
34#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
35#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
36#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
37#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
38#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
39#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
40#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
41#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
42#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
43
44extern u32 rtl819XMACPHY_Array_PG[];
45extern u32 rtl819XPHY_REG_1T2RArray[];
46extern u32 rtl819XAGCTAB_Array[];
47extern u32 rtl819XRadioA_Array[];
48extern u32 rtl819XRadioB_Array[];
49extern u32 rtl819XRadioC_Array[];
50extern u32 rtl819XRadioD_Array[];
51
52enum hw90_block {
53 HW90_BLOCK_MAC = 0,
54 HW90_BLOCK_PHY0 = 1,
55 HW90_BLOCK_PHY1 = 2,
56 HW90_BLOCK_RF = 3,
57 HW90_BLOCK_MAXIMUM = 4,
58};
59
60enum rf90_radio_path {
61 RF90_PATH_A = 0,
62 RF90_PATH_B = 1,
63 RF90_PATH_C = 2,
64 RF90_PATH_D = 3,
65 RF90_PATH_MAX
66};
67
68#define bMaskByte0 0xff
69#define bMaskByte1 0xff00
70#define bMaskByte2 0xff0000
71#define bMaskByte3 0xff000000
72#define bMaskHWord 0xffff0000
73#define bMaskLWord 0x0000ffff
74#define bMaskDWord 0xffffffff
75
76extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev,
77 u32 eRFPath);
78extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr,
79 u32 dwBitMask, u32 dwData);
80extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr,
81 u32 dwBitMask);
82extern void rtl8192_phy_SetRFReg(struct net_device *dev,
83 enum rf90_radio_path eRFPath,
84 u32 RegAddr, u32 BitMask, u32 Data);
85extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
86 enum rf90_radio_path eRFPath,
87 u32 RegAddr, u32 BitMask);
88extern void rtl8192_phy_configmac(struct net_device *dev);
89extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
90extern bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
91 enum hw90_block CheckBlock,
92 enum rf90_radio_path eRFPath);
93extern bool rtl8192_BBConfig(struct net_device *dev);
94extern void rtl8192_phy_getTxPower(struct net_device *dev);
95extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
96extern bool rtl8192_phy_RFConfig(struct net_device *dev);
97extern void rtl8192_phy_updateInitGain(struct net_device *dev);
98extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
99 enum rf90_radio_path eRFPath);
100
101extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
102extern void rtl8192_SetBWMode(struct net_device *dev,
103 enum ht_channel_width Bandwidth,
104 enum ht_extchnl_offset Offset);
105extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
106extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
107extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
108
109extern void PHY_SetRtl8192eRfOff(struct net_device *dev);
110
111bool
112SetRFPowerState(
113 struct net_device *dev,
114 enum rt_rf_power_state eRFPowerState
115 );
116#define PHY_SetRFPowerState SetRFPowerState
117
118extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation);
119
120#endif
121