linux/drivers/tty/serial/bcm63xx_uart.c
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   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Derived from many drivers using generic_serial interface.
   7 *
   8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   9 *
  10 *  Serial driver for BCM63xx integrated UART.
  11 *
  12 * Hardware flow control was _not_ tested since I only have RX/TX on
  13 * my board.
  14 */
  15
  16#if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  17#define SUPPORT_SYSRQ
  18#endif
  19
  20#include <linux/kernel.h>
  21#include <linux/platform_device.h>
  22#include <linux/init.h>
  23#include <linux/delay.h>
  24#include <linux/module.h>
  25#include <linux/console.h>
  26#include <linux/clk.h>
  27#include <linux/tty.h>
  28#include <linux/tty_flip.h>
  29#include <linux/sysrq.h>
  30#include <linux/serial.h>
  31#include <linux/serial_core.h>
  32
  33#include <bcm63xx_clk.h>
  34#include <bcm63xx_irq.h>
  35#include <bcm63xx_regs.h>
  36#include <bcm63xx_io.h>
  37
  38#define BCM63XX_NR_UARTS        2
  39
  40static struct uart_port ports[BCM63XX_NR_UARTS];
  41
  42/*
  43 * rx interrupt mask / stat
  44 *
  45 * mask:
  46 *  - rx fifo full
  47 *  - rx fifo above threshold
  48 *  - rx fifo not empty for too long
  49 */
  50#define UART_RX_INT_MASK        (UART_IR_MASK(UART_IR_RXOVER) |         \
  51                                UART_IR_MASK(UART_IR_RXTHRESH) |        \
  52                                UART_IR_MASK(UART_IR_RXTIMEOUT))
  53
  54#define UART_RX_INT_STAT        (UART_IR_STAT(UART_IR_RXOVER) |         \
  55                                UART_IR_STAT(UART_IR_RXTHRESH) |        \
  56                                UART_IR_STAT(UART_IR_RXTIMEOUT))
  57
  58/*
  59 * tx interrupt mask / stat
  60 *
  61 * mask:
  62 * - tx fifo empty
  63 * - tx fifo below threshold
  64 */
  65#define UART_TX_INT_MASK        (UART_IR_MASK(UART_IR_TXEMPTY) |        \
  66                                UART_IR_MASK(UART_IR_TXTRESH))
  67
  68#define UART_TX_INT_STAT        (UART_IR_STAT(UART_IR_TXEMPTY) |        \
  69                                UART_IR_STAT(UART_IR_TXTRESH))
  70
  71/*
  72 * external input interrupt
  73 *
  74 * mask: any edge on CTS, DCD
  75 */
  76#define UART_EXTINP_INT_MASK    (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
  77                                 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
  78
  79/*
  80 * handy uart register accessor
  81 */
  82static inline unsigned int bcm_uart_readl(struct uart_port *port,
  83                                         unsigned int offset)
  84{
  85        return bcm_readl(port->membase + offset);
  86}
  87
  88static inline void bcm_uart_writel(struct uart_port *port,
  89                                  unsigned int value, unsigned int offset)
  90{
  91        bcm_writel(value, port->membase + offset);
  92}
  93
  94/*
  95 * serial core request to check if uart tx fifo is empty
  96 */
  97static unsigned int bcm_uart_tx_empty(struct uart_port *port)
  98{
  99        unsigned int val;
 100
 101        val = bcm_uart_readl(port, UART_IR_REG);
 102        return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
 103}
 104
 105/*
 106 * serial core request to set RTS and DTR pin state and loopback mode
 107 */
 108static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 109{
 110        unsigned int val;
 111
 112        val = bcm_uart_readl(port, UART_MCTL_REG);
 113        val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
 114        /* invert of written value is reflected on the pin */
 115        if (!(mctrl & TIOCM_DTR))
 116                val |= UART_MCTL_DTR_MASK;
 117        if (!(mctrl & TIOCM_RTS))
 118                val |= UART_MCTL_RTS_MASK;
 119        bcm_uart_writel(port, val, UART_MCTL_REG);
 120
 121        val = bcm_uart_readl(port, UART_CTL_REG);
 122        if (mctrl & TIOCM_LOOP)
 123                val |= UART_CTL_LOOPBACK_MASK;
 124        else
 125                val &= ~UART_CTL_LOOPBACK_MASK;
 126        bcm_uart_writel(port, val, UART_CTL_REG);
 127}
 128
 129/*
 130 * serial core request to return RI, CTS, DCD and DSR pin state
 131 */
 132static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
 133{
 134        unsigned int val, mctrl;
 135
 136        mctrl = 0;
 137        val = bcm_uart_readl(port, UART_EXTINP_REG);
 138        if (val & UART_EXTINP_RI_MASK)
 139                mctrl |= TIOCM_RI;
 140        if (val & UART_EXTINP_CTS_MASK)
 141                mctrl |= TIOCM_CTS;
 142        if (val & UART_EXTINP_DCD_MASK)
 143                mctrl |= TIOCM_CD;
 144        if (val & UART_EXTINP_DSR_MASK)
 145                mctrl |= TIOCM_DSR;
 146        return mctrl;
 147}
 148
 149/*
 150 * serial core request to disable tx ASAP (used for flow control)
 151 */
 152static void bcm_uart_stop_tx(struct uart_port *port)
 153{
 154        unsigned int val;
 155
 156        val = bcm_uart_readl(port, UART_CTL_REG);
 157        val &= ~(UART_CTL_TXEN_MASK);
 158        bcm_uart_writel(port, val, UART_CTL_REG);
 159
 160        val = bcm_uart_readl(port, UART_IR_REG);
 161        val &= ~UART_TX_INT_MASK;
 162        bcm_uart_writel(port, val, UART_IR_REG);
 163}
 164
 165/*
 166 * serial core request to (re)enable tx
 167 */
 168static void bcm_uart_start_tx(struct uart_port *port)
 169{
 170        unsigned int val;
 171
 172        val = bcm_uart_readl(port, UART_IR_REG);
 173        val |= UART_TX_INT_MASK;
 174        bcm_uart_writel(port, val, UART_IR_REG);
 175
 176        val = bcm_uart_readl(port, UART_CTL_REG);
 177        val |= UART_CTL_TXEN_MASK;
 178        bcm_uart_writel(port, val, UART_CTL_REG);
 179}
 180
 181/*
 182 * serial core request to stop rx, called before port shutdown
 183 */
 184static void bcm_uart_stop_rx(struct uart_port *port)
 185{
 186        unsigned int val;
 187
 188        val = bcm_uart_readl(port, UART_IR_REG);
 189        val &= ~UART_RX_INT_MASK;
 190        bcm_uart_writel(port, val, UART_IR_REG);
 191}
 192
 193/*
 194 * serial core request to enable modem status interrupt reporting
 195 */
 196static void bcm_uart_enable_ms(struct uart_port *port)
 197{
 198        unsigned int val;
 199
 200        val = bcm_uart_readl(port, UART_IR_REG);
 201        val |= UART_IR_MASK(UART_IR_EXTIP);
 202        bcm_uart_writel(port, val, UART_IR_REG);
 203}
 204
 205/*
 206 * serial core request to start/stop emitting break char
 207 */
 208static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
 209{
 210        unsigned long flags;
 211        unsigned int val;
 212
 213        spin_lock_irqsave(&port->lock, flags);
 214
 215        val = bcm_uart_readl(port, UART_CTL_REG);
 216        if (ctl)
 217                val |= UART_CTL_XMITBRK_MASK;
 218        else
 219                val &= ~UART_CTL_XMITBRK_MASK;
 220        bcm_uart_writel(port, val, UART_CTL_REG);
 221
 222        spin_unlock_irqrestore(&port->lock, flags);
 223}
 224
 225/*
 226 * return port type in string format
 227 */
 228static const char *bcm_uart_type(struct uart_port *port)
 229{
 230        return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
 231}
 232
 233/*
 234 * read all chars in rx fifo and send them to core
 235 */
 236static void bcm_uart_do_rx(struct uart_port *port)
 237{
 238        struct tty_struct *tty;
 239        unsigned int max_count;
 240
 241        /* limit number of char read in interrupt, should not be
 242         * higher than fifo size anyway since we're much faster than
 243         * serial port */
 244        max_count = 32;
 245        tty = port->state->port.tty;
 246        do {
 247                unsigned int iestat, c, cstat;
 248                char flag;
 249
 250                /* get overrun/fifo empty information from ier
 251                 * register */
 252                iestat = bcm_uart_readl(port, UART_IR_REG);
 253
 254                if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
 255                        unsigned int val;
 256
 257                        /* fifo reset is required to clear
 258                         * interrupt */
 259                        val = bcm_uart_readl(port, UART_CTL_REG);
 260                        val |= UART_CTL_RSTRXFIFO_MASK;
 261                        bcm_uart_writel(port, val, UART_CTL_REG);
 262
 263                        port->icount.overrun++;
 264                        tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 265                }
 266
 267                if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
 268                        break;
 269
 270                cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
 271                port->icount.rx++;
 272                flag = TTY_NORMAL;
 273                c &= 0xff;
 274
 275                if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
 276                        /* do stats first */
 277                        if (cstat & UART_FIFO_BRKDET_MASK) {
 278                                port->icount.brk++;
 279                                if (uart_handle_break(port))
 280                                        continue;
 281                        }
 282
 283                        if (cstat & UART_FIFO_PARERR_MASK)
 284                                port->icount.parity++;
 285                        if (cstat & UART_FIFO_FRAMEERR_MASK)
 286                                port->icount.frame++;
 287
 288                        /* update flag wrt read_status_mask */
 289                        cstat &= port->read_status_mask;
 290                        if (cstat & UART_FIFO_BRKDET_MASK)
 291                                flag = TTY_BREAK;
 292                        if (cstat & UART_FIFO_FRAMEERR_MASK)
 293                                flag = TTY_FRAME;
 294                        if (cstat & UART_FIFO_PARERR_MASK)
 295                                flag = TTY_PARITY;
 296                }
 297
 298                if (uart_handle_sysrq_char(port, c))
 299                        continue;
 300
 301
 302                if ((cstat & port->ignore_status_mask) == 0)
 303                        tty_insert_flip_char(tty, c, flag);
 304
 305        } while (--max_count);
 306
 307        tty_flip_buffer_push(tty);
 308}
 309
 310/*
 311 * fill tx fifo with chars to send, stop when fifo is about to be full
 312 * or when all chars have been sent.
 313 */
 314static void bcm_uart_do_tx(struct uart_port *port)
 315{
 316        struct circ_buf *xmit;
 317        unsigned int val, max_count;
 318
 319        if (port->x_char) {
 320                bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
 321                port->icount.tx++;
 322                port->x_char = 0;
 323                return;
 324        }
 325
 326        if (uart_tx_stopped(port)) {
 327                bcm_uart_stop_tx(port);
 328                return;
 329        }
 330
 331        xmit = &port->state->xmit;
 332        if (uart_circ_empty(xmit))
 333                goto txq_empty;
 334
 335        val = bcm_uart_readl(port, UART_MCTL_REG);
 336        val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
 337        max_count = port->fifosize - val;
 338
 339        while (max_count--) {
 340                unsigned int c;
 341
 342                c = xmit->buf[xmit->tail];
 343                bcm_uart_writel(port, c, UART_FIFO_REG);
 344                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 345                port->icount.tx++;
 346                if (uart_circ_empty(xmit))
 347                        break;
 348        }
 349
 350        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 351                uart_write_wakeup(port);
 352
 353        if (uart_circ_empty(xmit))
 354                goto txq_empty;
 355        return;
 356
 357txq_empty:
 358        /* nothing to send, disable transmit interrupt */
 359        val = bcm_uart_readl(port, UART_IR_REG);
 360        val &= ~UART_TX_INT_MASK;
 361        bcm_uart_writel(port, val, UART_IR_REG);
 362        return;
 363}
 364
 365/*
 366 * process uart interrupt
 367 */
 368static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
 369{
 370        struct uart_port *port;
 371        unsigned int irqstat;
 372
 373        port = dev_id;
 374        spin_lock(&port->lock);
 375
 376        irqstat = bcm_uart_readl(port, UART_IR_REG);
 377        if (irqstat & UART_RX_INT_STAT)
 378                bcm_uart_do_rx(port);
 379
 380        if (irqstat & UART_TX_INT_STAT)
 381                bcm_uart_do_tx(port);
 382
 383        if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
 384                unsigned int estat;
 385
 386                estat = bcm_uart_readl(port, UART_EXTINP_REG);
 387                if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
 388                        uart_handle_cts_change(port,
 389                                               estat & UART_EXTINP_CTS_MASK);
 390                if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
 391                        uart_handle_dcd_change(port,
 392                                               estat & UART_EXTINP_DCD_MASK);
 393        }
 394
 395        spin_unlock(&port->lock);
 396        return IRQ_HANDLED;
 397}
 398
 399/*
 400 * enable rx & tx operation on uart
 401 */
 402static void bcm_uart_enable(struct uart_port *port)
 403{
 404        unsigned int val;
 405
 406        val = bcm_uart_readl(port, UART_CTL_REG);
 407        val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
 408        bcm_uart_writel(port, val, UART_CTL_REG);
 409}
 410
 411/*
 412 * disable rx & tx operation on uart
 413 */
 414static void bcm_uart_disable(struct uart_port *port)
 415{
 416        unsigned int val;
 417
 418        val = bcm_uart_readl(port, UART_CTL_REG);
 419        val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
 420                 UART_CTL_RXEN_MASK);
 421        bcm_uart_writel(port, val, UART_CTL_REG);
 422}
 423
 424/*
 425 * clear all unread data in rx fifo and unsent data in tx fifo
 426 */
 427static void bcm_uart_flush(struct uart_port *port)
 428{
 429        unsigned int val;
 430
 431        /* empty rx and tx fifo */
 432        val = bcm_uart_readl(port, UART_CTL_REG);
 433        val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
 434        bcm_uart_writel(port, val, UART_CTL_REG);
 435
 436        /* read any pending char to make sure all irq status are
 437         * cleared */
 438        (void)bcm_uart_readl(port, UART_FIFO_REG);
 439}
 440
 441/*
 442 * serial core request to initialize uart and start rx operation
 443 */
 444static int bcm_uart_startup(struct uart_port *port)
 445{
 446        unsigned int val;
 447        int ret;
 448
 449        /* mask all irq and flush port */
 450        bcm_uart_disable(port);
 451        bcm_uart_writel(port, 0, UART_IR_REG);
 452        bcm_uart_flush(port);
 453
 454        /* clear any pending external input interrupt */
 455        (void)bcm_uart_readl(port, UART_EXTINP_REG);
 456
 457        /* set rx/tx fifo thresh to fifo half size */
 458        val = bcm_uart_readl(port, UART_MCTL_REG);
 459        val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
 460        val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
 461        val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
 462        bcm_uart_writel(port, val, UART_MCTL_REG);
 463
 464        /* set rx fifo timeout to 1 char time */
 465        val = bcm_uart_readl(port, UART_CTL_REG);
 466        val &= ~UART_CTL_RXTMOUTCNT_MASK;
 467        val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
 468        bcm_uart_writel(port, val, UART_CTL_REG);
 469
 470        /* report any edge on dcd and cts */
 471        val = UART_EXTINP_INT_MASK;
 472        val |= UART_EXTINP_DCD_NOSENSE_MASK;
 473        val |= UART_EXTINP_CTS_NOSENSE_MASK;
 474        bcm_uart_writel(port, val, UART_EXTINP_REG);
 475
 476        /* register irq and enable rx interrupts */
 477        ret = request_irq(port->irq, bcm_uart_interrupt, 0,
 478                          bcm_uart_type(port), port);
 479        if (ret)
 480                return ret;
 481        bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
 482        bcm_uart_enable(port);
 483        return 0;
 484}
 485
 486/*
 487 * serial core request to flush & disable uart
 488 */
 489static void bcm_uart_shutdown(struct uart_port *port)
 490{
 491        unsigned long flags;
 492
 493        spin_lock_irqsave(&port->lock, flags);
 494        bcm_uart_writel(port, 0, UART_IR_REG);
 495        spin_unlock_irqrestore(&port->lock, flags);
 496
 497        bcm_uart_disable(port);
 498        bcm_uart_flush(port);
 499        free_irq(port->irq, port);
 500}
 501
 502/*
 503 * serial core request to change current uart setting
 504 */
 505static void bcm_uart_set_termios(struct uart_port *port,
 506                                 struct ktermios *new,
 507                                 struct ktermios *old)
 508{
 509        unsigned int ctl, baud, quot, ier;
 510        unsigned long flags;
 511
 512        spin_lock_irqsave(&port->lock, flags);
 513
 514        /* disable uart while changing speed */
 515        bcm_uart_disable(port);
 516        bcm_uart_flush(port);
 517
 518        /* update Control register */
 519        ctl = bcm_uart_readl(port, UART_CTL_REG);
 520        ctl &= ~UART_CTL_BITSPERSYM_MASK;
 521
 522        switch (new->c_cflag & CSIZE) {
 523        case CS5:
 524                ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
 525                break;
 526        case CS6:
 527                ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
 528                break;
 529        case CS7:
 530                ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
 531                break;
 532        default:
 533                ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
 534                break;
 535        }
 536
 537        ctl &= ~UART_CTL_STOPBITS_MASK;
 538        if (new->c_cflag & CSTOPB)
 539                ctl |= UART_CTL_STOPBITS_2;
 540        else
 541                ctl |= UART_CTL_STOPBITS_1;
 542
 543        ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
 544        if (new->c_cflag & PARENB)
 545                ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
 546        ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
 547        if (new->c_cflag & PARODD)
 548                ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
 549        bcm_uart_writel(port, ctl, UART_CTL_REG);
 550
 551        /* update Baudword register */
 552        baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
 553        quot = uart_get_divisor(port, baud) - 1;
 554        bcm_uart_writel(port, quot, UART_BAUD_REG);
 555
 556        /* update Interrupt register */
 557        ier = bcm_uart_readl(port, UART_IR_REG);
 558
 559        ier &= ~UART_IR_MASK(UART_IR_EXTIP);
 560        if (UART_ENABLE_MS(port, new->c_cflag))
 561                ier |= UART_IR_MASK(UART_IR_EXTIP);
 562
 563        bcm_uart_writel(port, ier, UART_IR_REG);
 564
 565        /* update read/ignore mask */
 566        port->read_status_mask = UART_FIFO_VALID_MASK;
 567        if (new->c_iflag & INPCK) {
 568                port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
 569                port->read_status_mask |= UART_FIFO_PARERR_MASK;
 570        }
 571        if (new->c_iflag & (BRKINT))
 572                port->read_status_mask |= UART_FIFO_BRKDET_MASK;
 573
 574        port->ignore_status_mask = 0;
 575        if (new->c_iflag & IGNPAR)
 576                port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
 577        if (new->c_iflag & IGNBRK)
 578                port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
 579        if (!(new->c_cflag & CREAD))
 580                port->ignore_status_mask |= UART_FIFO_VALID_MASK;
 581
 582        uart_update_timeout(port, new->c_cflag, baud);
 583        bcm_uart_enable(port);
 584        spin_unlock_irqrestore(&port->lock, flags);
 585}
 586
 587/*
 588 * serial core request to claim uart iomem
 589 */
 590static int bcm_uart_request_port(struct uart_port *port)
 591{
 592        unsigned int size;
 593
 594        size = RSET_UART_SIZE;
 595        if (!request_mem_region(port->mapbase, size, "bcm63xx")) {
 596                dev_err(port->dev, "Memory region busy\n");
 597                return -EBUSY;
 598        }
 599
 600        port->membase = ioremap(port->mapbase, size);
 601        if (!port->membase) {
 602                dev_err(port->dev, "Unable to map registers\n");
 603                release_mem_region(port->mapbase, size);
 604                return -EBUSY;
 605        }
 606        return 0;
 607}
 608
 609/*
 610 * serial core request to release uart iomem
 611 */
 612static void bcm_uart_release_port(struct uart_port *port)
 613{
 614        release_mem_region(port->mapbase, RSET_UART_SIZE);
 615        iounmap(port->membase);
 616}
 617
 618/*
 619 * serial core request to do any port required autoconfiguration
 620 */
 621static void bcm_uart_config_port(struct uart_port *port, int flags)
 622{
 623        if (flags & UART_CONFIG_TYPE) {
 624                if (bcm_uart_request_port(port))
 625                        return;
 626                port->type = PORT_BCM63XX;
 627        }
 628}
 629
 630/*
 631 * serial core request to check that port information in serinfo are
 632 * suitable
 633 */
 634static int bcm_uart_verify_port(struct uart_port *port,
 635                                struct serial_struct *serinfo)
 636{
 637        if (port->type != PORT_BCM63XX)
 638                return -EINVAL;
 639        if (port->irq != serinfo->irq)
 640                return -EINVAL;
 641        if (port->iotype != serinfo->io_type)
 642                return -EINVAL;
 643        if (port->mapbase != (unsigned long)serinfo->iomem_base)
 644                return -EINVAL;
 645        return 0;
 646}
 647
 648/* serial core callbacks */
 649static struct uart_ops bcm_uart_ops = {
 650        .tx_empty       = bcm_uart_tx_empty,
 651        .get_mctrl      = bcm_uart_get_mctrl,
 652        .set_mctrl      = bcm_uart_set_mctrl,
 653        .start_tx       = bcm_uart_start_tx,
 654        .stop_tx        = bcm_uart_stop_tx,
 655        .stop_rx        = bcm_uart_stop_rx,
 656        .enable_ms      = bcm_uart_enable_ms,
 657        .break_ctl      = bcm_uart_break_ctl,
 658        .startup        = bcm_uart_startup,
 659        .shutdown       = bcm_uart_shutdown,
 660        .set_termios    = bcm_uart_set_termios,
 661        .type           = bcm_uart_type,
 662        .release_port   = bcm_uart_release_port,
 663        .request_port   = bcm_uart_request_port,
 664        .config_port    = bcm_uart_config_port,
 665        .verify_port    = bcm_uart_verify_port,
 666};
 667
 668
 669
 670#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
 671static inline void wait_for_xmitr(struct uart_port *port)
 672{
 673        unsigned int tmout;
 674
 675        /* Wait up to 10ms for the character(s) to be sent. */
 676        tmout = 10000;
 677        while (--tmout) {
 678                unsigned int val;
 679
 680                val = bcm_uart_readl(port, UART_IR_REG);
 681                if (val & UART_IR_STAT(UART_IR_TXEMPTY))
 682                        break;
 683                udelay(1);
 684        }
 685
 686        /* Wait up to 1s for flow control if necessary */
 687        if (port->flags & UPF_CONS_FLOW) {
 688                tmout = 1000000;
 689                while (--tmout) {
 690                        unsigned int val;
 691
 692                        val = bcm_uart_readl(port, UART_EXTINP_REG);
 693                        if (val & UART_EXTINP_CTS_MASK)
 694                                break;
 695                        udelay(1);
 696                }
 697        }
 698}
 699
 700/*
 701 * output given char
 702 */
 703static void bcm_console_putchar(struct uart_port *port, int ch)
 704{
 705        wait_for_xmitr(port);
 706        bcm_uart_writel(port, ch, UART_FIFO_REG);
 707}
 708
 709/*
 710 * console core request to output given string
 711 */
 712static void bcm_console_write(struct console *co, const char *s,
 713                              unsigned int count)
 714{
 715        struct uart_port *port;
 716        unsigned long flags;
 717        int locked;
 718
 719        port = &ports[co->index];
 720
 721        local_irq_save(flags);
 722        if (port->sysrq) {
 723                /* bcm_uart_interrupt() already took the lock */
 724                locked = 0;
 725        } else if (oops_in_progress) {
 726                locked = spin_trylock(&port->lock);
 727        } else {
 728                spin_lock(&port->lock);
 729                locked = 1;
 730        }
 731
 732        /* call helper to deal with \r\n */
 733        uart_console_write(port, s, count, bcm_console_putchar);
 734
 735        /* and wait for char to be transmitted */
 736        wait_for_xmitr(port);
 737
 738        if (locked)
 739                spin_unlock(&port->lock);
 740        local_irq_restore(flags);
 741}
 742
 743/*
 744 * console core request to setup given console, find matching uart
 745 * port and setup it.
 746 */
 747static int bcm_console_setup(struct console *co, char *options)
 748{
 749        struct uart_port *port;
 750        int baud = 9600;
 751        int bits = 8;
 752        int parity = 'n';
 753        int flow = 'n';
 754
 755        if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
 756                return -EINVAL;
 757        port = &ports[co->index];
 758        if (!port->membase)
 759                return -ENODEV;
 760        if (options)
 761                uart_parse_options(options, &baud, &parity, &bits, &flow);
 762
 763        return uart_set_options(port, co, baud, parity, bits, flow);
 764}
 765
 766static struct uart_driver bcm_uart_driver;
 767
 768static struct console bcm63xx_console = {
 769        .name           = "ttyS",
 770        .write          = bcm_console_write,
 771        .device         = uart_console_device,
 772        .setup          = bcm_console_setup,
 773        .flags          = CON_PRINTBUFFER,
 774        .index          = -1,
 775        .data           = &bcm_uart_driver,
 776};
 777
 778static int __init bcm63xx_console_init(void)
 779{
 780        register_console(&bcm63xx_console);
 781        return 0;
 782}
 783
 784console_initcall(bcm63xx_console_init);
 785
 786#define BCM63XX_CONSOLE (&bcm63xx_console)
 787#else
 788#define BCM63XX_CONSOLE NULL
 789#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
 790
 791static struct uart_driver bcm_uart_driver = {
 792        .owner          = THIS_MODULE,
 793        .driver_name    = "bcm63xx_uart",
 794        .dev_name       = "ttyS",
 795        .major          = TTY_MAJOR,
 796        .minor          = 64,
 797        .nr             = BCM63XX_NR_UARTS,
 798        .cons           = BCM63XX_CONSOLE,
 799};
 800
 801/*
 802 * platform driver probe/remove callback
 803 */
 804static int bcm_uart_probe(struct platform_device *pdev)
 805{
 806        struct resource *res_mem, *res_irq;
 807        struct uart_port *port;
 808        struct clk *clk;
 809        int ret;
 810
 811        if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
 812                return -EINVAL;
 813
 814        if (ports[pdev->id].membase)
 815                return -EBUSY;
 816
 817        res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 818        if (!res_mem)
 819                return -ENODEV;
 820
 821        res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 822        if (!res_irq)
 823                return -ENODEV;
 824
 825        clk = clk_get(&pdev->dev, "periph");
 826        if (IS_ERR(clk))
 827                return -ENODEV;
 828
 829        port = &ports[pdev->id];
 830        memset(port, 0, sizeof(*port));
 831        port->iotype = UPIO_MEM;
 832        port->mapbase = res_mem->start;
 833        port->irq = res_irq->start;
 834        port->ops = &bcm_uart_ops;
 835        port->flags = UPF_BOOT_AUTOCONF;
 836        port->dev = &pdev->dev;
 837        port->fifosize = 16;
 838        port->uartclk = clk_get_rate(clk) / 2;
 839        port->line = pdev->id;
 840        clk_put(clk);
 841
 842        ret = uart_add_one_port(&bcm_uart_driver, port);
 843        if (ret) {
 844                ports[pdev->id].membase = 0;
 845                return ret;
 846        }
 847        platform_set_drvdata(pdev, port);
 848        return 0;
 849}
 850
 851static int bcm_uart_remove(struct platform_device *pdev)
 852{
 853        struct uart_port *port;
 854
 855        port = platform_get_drvdata(pdev);
 856        uart_remove_one_port(&bcm_uart_driver, port);
 857        platform_set_drvdata(pdev, NULL);
 858        /* mark port as free */
 859        ports[pdev->id].membase = 0;
 860        return 0;
 861}
 862
 863/*
 864 * platform driver stuff
 865 */
 866static struct platform_driver bcm_uart_platform_driver = {
 867        .probe  = bcm_uart_probe,
 868        .remove = bcm_uart_remove,
 869        .driver = {
 870                .owner = THIS_MODULE,
 871                .name  = "bcm63xx_uart",
 872        },
 873};
 874
 875static int __init bcm_uart_init(void)
 876{
 877        int ret;
 878
 879        ret = uart_register_driver(&bcm_uart_driver);
 880        if (ret)
 881                return ret;
 882
 883        ret = platform_driver_register(&bcm_uart_platform_driver);
 884        if (ret)
 885                uart_unregister_driver(&bcm_uart_driver);
 886
 887        return ret;
 888}
 889
 890static void __exit bcm_uart_exit(void)
 891{
 892        platform_driver_unregister(&bcm_uart_platform_driver);
 893        uart_unregister_driver(&bcm_uart_driver);
 894}
 895
 896module_init(bcm_uart_init);
 897module_exit(bcm_uart_exit);
 898
 899MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
 900MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver");
 901MODULE_LICENSE("GPL");
 902