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53
54#if defined(__i386__)
55# define BREAKPOINT() asm(" int $3");
56#else
57# define BREAKPOINT() { }
58#endif
59
60#define MAX_ISA_DEVICES 10
61#define MAX_PCI_DEVICES 10
62#define MAX_TOTAL_DEVICES 20
63
64#include <linux/module.h>
65#include <linux/errno.h>
66#include <linux/signal.h>
67#include <linux/sched.h>
68#include <linux/timer.h>
69#include <linux/interrupt.h>
70#include <linux/pci.h>
71#include <linux/tty.h>
72#include <linux/tty_flip.h>
73#include <linux/serial.h>
74#include <linux/major.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
78#include <linux/ioport.h>
79#include <linux/mm.h>
80#include <linux/seq_file.h>
81#include <linux/slab.h>
82#include <linux/delay.h>
83#include <linux/netdevice.h>
84#include <linux/vmalloc.h>
85#include <linux/init.h>
86#include <linux/ioctl.h>
87#include <linux/synclink.h>
88
89#include <asm/io.h>
90#include <asm/irq.h>
91#include <asm/dma.h>
92#include <linux/bitops.h>
93#include <asm/types.h>
94#include <linux/termios.h>
95#include <linux/workqueue.h>
96#include <linux/hdlc.h>
97#include <linux/dma-mapping.h>
98
99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100#define SYNCLINK_GENERIC_HDLC 1
101#else
102#define SYNCLINK_GENERIC_HDLC 0
103#endif
104
105#define GET_USER(error,value,addr) error = get_user(value,addr)
106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107#define PUT_USER(error,value,addr) error = put_user(value,addr)
108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
109
110#include <asm/uaccess.h>
111
112#define RCLRVALUE 0xffff
113
114static MGSL_PARAMS default_params = {
115 MGSL_MODE_HDLC,
116 0,
117 HDLC_FLAG_UNDERRUN_ABORT15,
118 HDLC_ENCODING_NRZI_SPACE,
119 0,
120 0xff,
121 HDLC_CRC_16_CCITT,
122 HDLC_PREAMBLE_LENGTH_8BITS,
123 HDLC_PREAMBLE_PATTERN_NONE,
124 9600,
125 8,
126 1,
127 ASYNC_PARITY_NONE
128};
129
130#define SHARED_MEM_ADDRESS_SIZE 0x40000
131#define BUFFERLISTSIZE 4096
132#define DMABUFFERSIZE 4096
133#define MAXRXFRAMES 7
134
135typedef struct _DMABUFFERENTRY
136{
137 u32 phys_addr;
138 volatile u16 count;
139 volatile u16 status;
140 volatile u16 rcc;
141 u16 reserved;
142 u32 link;
143 char *virt_addr;
144 u32 phys_entry;
145 dma_addr_t dma_addr;
146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
147
148
149
150#define BH_RECEIVE 1
151#define BH_TRANSMIT 2
152#define BH_STATUS 4
153
154#define IO_PIN_SHUTDOWN_LIMIT 100
155
156struct _input_signal_events {
157 int ri_up;
158 int ri_down;
159 int dsr_up;
160 int dsr_down;
161 int dcd_up;
162 int dcd_down;
163 int cts_up;
164 int cts_down;
165};
166
167
168#define MAX_TX_HOLDING_BUFFERS 5
169struct tx_holding_buffer {
170 int buffer_size;
171 unsigned char * buffer;
172};
173
174
175
176
177
178
179struct mgsl_struct {
180 int magic;
181 struct tty_port port;
182 int line;
183 int hw_version;
184
185 struct mgsl_icount icount;
186
187 int timeout;
188 int x_char;
189 u16 read_status_mask;
190 u16 ignore_status_mask;
191 unsigned char *xmit_buf;
192 int xmit_head;
193 int xmit_tail;
194 int xmit_cnt;
195
196 wait_queue_head_t status_event_wait_q;
197 wait_queue_head_t event_wait_q;
198 struct timer_list tx_timer;
199 struct mgsl_struct *next_device;
200
201 spinlock_t irq_spinlock;
202 struct work_struct task;
203
204 u32 EventMask;
205 u32 RecordedEvents;
206
207 u32 max_frame_size;
208
209 u32 pending_bh;
210
211 bool bh_running;
212 int isr_overflow;
213 bool bh_requested;
214
215 int dcd_chkcount;
216 int cts_chkcount;
217 int dsr_chkcount;
218 int ri_chkcount;
219
220 char *buffer_list;
221 u32 buffer_list_phys;
222 dma_addr_t buffer_list_dma_addr;
223
224 unsigned int rx_buffer_count;
225 DMABUFFERENTRY *rx_buffer_list;
226 unsigned int current_rx_buffer;
227
228 int num_tx_dma_buffers;
229 int tx_dma_buffers_used;
230 unsigned int tx_buffer_count;
231 DMABUFFERENTRY *tx_buffer_list;
232 int start_tx_dma_buffer;
233 int current_tx_buffer;
234
235 unsigned char *intermediate_rxbuffer;
236
237 int num_tx_holding_buffers;
238 int get_tx_holding_index;
239 int put_tx_holding_index;
240 int tx_holding_count;
241 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
242
243 bool rx_enabled;
244 bool rx_overflow;
245 bool rx_rcc_underrun;
246
247 bool tx_enabled;
248 bool tx_active;
249 u32 idle_mode;
250
251 u16 cmr_value;
252 u16 tcsr_value;
253
254 char device_name[25];
255
256 unsigned int bus_type;
257 unsigned char bus;
258 unsigned char function;
259
260 unsigned int io_base;
261 unsigned int io_addr_size;
262 bool io_addr_requested;
263
264 unsigned int irq_level;
265 unsigned long irq_flags;
266 bool irq_requested;
267
268 unsigned int dma_level;
269 bool dma_requested;
270
271 u16 mbre_bit;
272 u16 loopback_bits;
273 u16 usc_idle_mode;
274
275 MGSL_PARAMS params;
276
277 unsigned char serial_signals;
278
279 bool irq_occurred;
280 unsigned int init_error;
281 int fDiagnosticsmode;
282
283 u32 last_mem_alloc;
284 unsigned char* memory_base;
285 u32 phys_memory_base;
286 bool shared_mem_requested;
287
288 unsigned char* lcr_base;
289 u32 phys_lcr_base;
290 u32 lcr_offset;
291 bool lcr_mem_requested;
292
293 u32 misc_ctrl_value;
294 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
295 char char_buf[MAX_ASYNC_BUFFER_SIZE];
296 bool drop_rts_on_tx_done;
297
298 bool loopmode_insert_requested;
299 bool loopmode_send_done_requested;
300
301 struct _input_signal_events input_signal_events;
302
303
304 int netcount;
305 spinlock_t netlock;
306
307#if SYNCLINK_GENERIC_HDLC
308 struct net_device *netdev;
309#endif
310};
311
312#define MGSL_MAGIC 0x5401
313
314
315
316
317#ifndef SERIAL_XMIT_SIZE
318#define SERIAL_XMIT_SIZE 4096
319#endif
320
321
322
323
324
325
326
327#define DCPIN 2
328#define SDPIN 4
329
330#define DCAR 0
331#define CCAR SDPIN
332#define DATAREG DCPIN + SDPIN
333#define MSBONLY 0x41
334#define LSBONLY 0x40
335
336
337
338
339
340
341#define CMR 0x02
342#define CCSR 0x04
343#define CCR 0x06
344#define PSR 0x08
345#define PCR 0x0a
346#define TMDR 0x0c
347#define TMCR 0x0e
348#define CMCR 0x10
349#define HCR 0x12
350#define IVR 0x14
351#define IOCR 0x16
352#define ICR 0x18
353#define DCCR 0x1a
354#define MISR 0x1c
355#define SICR 0x1e
356#define RDR 0x20
357#define RMR 0x22
358#define RCSR 0x24
359#define RICR 0x26
360#define RSR 0x28
361#define RCLR 0x2a
362#define RCCR 0x2c
363#define TC0R 0x2e
364#define TDR 0x30
365#define TMR 0x32
366#define TCSR 0x34
367#define TICR 0x36
368#define TSR 0x38
369#define TCLR 0x3a
370#define TCCR 0x3c
371#define TC1R 0x3e
372
373
374
375
376
377
378#define DCR 0x06
379#define DACR 0x08
380#define BDCR 0x12
381#define DIVR 0x14
382#define DICR 0x18
383#define CDIR 0x1a
384#define SDIR 0x1c
385
386#define TDMR 0x02
387#define TDIAR 0x1e
388#define TBCR 0x2a
389#define TARL 0x2c
390#define TARU 0x2e
391#define NTBCR 0x3a
392#define NTARL 0x3c
393#define NTARU 0x3e
394
395#define RDMR 0x82
396#define RDIAR 0x9e
397#define RBCR 0xaa
398#define RARL 0xac
399#define RARU 0xae
400#define NRBCR 0xba
401#define NRARL 0xbc
402#define NRARU 0xbe
403
404
405
406
407
408
409#define MODEMSTATUS_DTR 0x80
410#define MODEMSTATUS_DSR 0x40
411#define MODEMSTATUS_RTS 0x20
412#define MODEMSTATUS_CTS 0x10
413#define MODEMSTATUS_RI 0x04
414#define MODEMSTATUS_DCD 0x01
415
416
417
418
419
420
421#define RTCmd_Null 0x0000
422#define RTCmd_ResetHighestIus 0x1000
423#define RTCmd_TriggerChannelLoadDma 0x2000
424#define RTCmd_TriggerRxDma 0x2800
425#define RTCmd_TriggerTxDma 0x3000
426#define RTCmd_TriggerRxAndTxDma 0x3800
427#define RTCmd_PurgeRxFifo 0x4800
428#define RTCmd_PurgeTxFifo 0x5000
429#define RTCmd_PurgeRxAndTxFifo 0x5800
430#define RTCmd_LoadRcc 0x6800
431#define RTCmd_LoadTcc 0x7000
432#define RTCmd_LoadRccAndTcc 0x7800
433#define RTCmd_LoadTC0 0x8800
434#define RTCmd_LoadTC1 0x9000
435#define RTCmd_LoadTC0AndTC1 0x9800
436#define RTCmd_SerialDataLSBFirst 0xa000
437#define RTCmd_SerialDataMSBFirst 0xa800
438#define RTCmd_SelectBigEndian 0xb000
439#define RTCmd_SelectLittleEndian 0xb800
440
441
442
443
444
445
446#define DmaCmd_Null 0x0000
447#define DmaCmd_ResetTxChannel 0x1000
448#define DmaCmd_ResetRxChannel 0x1200
449#define DmaCmd_StartTxChannel 0x2000
450#define DmaCmd_StartRxChannel 0x2200
451#define DmaCmd_ContinueTxChannel 0x3000
452#define DmaCmd_ContinueRxChannel 0x3200
453#define DmaCmd_PauseTxChannel 0x4000
454#define DmaCmd_PauseRxChannel 0x4200
455#define DmaCmd_AbortTxChannel 0x5000
456#define DmaCmd_AbortRxChannel 0x5200
457#define DmaCmd_InitTxChannel 0x7000
458#define DmaCmd_InitRxChannel 0x7200
459#define DmaCmd_ResetHighestDmaIus 0x8000
460#define DmaCmd_ResetAllChannels 0x9000
461#define DmaCmd_StartAllChannels 0xa000
462#define DmaCmd_ContinueAllChannels 0xb000
463#define DmaCmd_PauseAllChannels 0xc000
464#define DmaCmd_AbortAllChannels 0xd000
465#define DmaCmd_InitAllChannels 0xf000
466
467#define TCmd_Null 0x0000
468#define TCmd_ClearTxCRC 0x2000
469#define TCmd_SelectTicrTtsaData 0x4000
470#define TCmd_SelectTicrTxFifostatus 0x5000
471#define TCmd_SelectTicrIntLevel 0x6000
472#define TCmd_SelectTicrdma_level 0x7000
473#define TCmd_SendFrame 0x8000
474#define TCmd_SendAbort 0x9000
475#define TCmd_EnableDleInsertion 0xc000
476#define TCmd_DisableDleInsertion 0xd000
477#define TCmd_ClearEofEom 0xe000
478#define TCmd_SetEofEom 0xf000
479
480#define RCmd_Null 0x0000
481#define RCmd_ClearRxCRC 0x2000
482#define RCmd_EnterHuntmode 0x3000
483#define RCmd_SelectRicrRtsaData 0x4000
484#define RCmd_SelectRicrRxFifostatus 0x5000
485#define RCmd_SelectRicrIntLevel 0x6000
486#define RCmd_SelectRicrdma_level 0x7000
487
488
489
490
491
492#define RECEIVE_STATUS BIT5
493#define RECEIVE_DATA BIT4
494#define TRANSMIT_STATUS BIT3
495#define TRANSMIT_DATA BIT2
496#define IO_PIN BIT1
497#define MISC BIT0
498
499
500
501
502
503
504#define RXSTATUS_SHORT_FRAME BIT8
505#define RXSTATUS_CODE_VIOLATION BIT8
506#define RXSTATUS_EXITED_HUNT BIT7
507#define RXSTATUS_IDLE_RECEIVED BIT6
508#define RXSTATUS_BREAK_RECEIVED BIT5
509#define RXSTATUS_ABORT_RECEIVED BIT5
510#define RXSTATUS_RXBOUND BIT4
511#define RXSTATUS_CRC_ERROR BIT3
512#define RXSTATUS_FRAMING_ERROR BIT3
513#define RXSTATUS_ABORT BIT2
514#define RXSTATUS_PARITY_ERROR BIT2
515#define RXSTATUS_OVERRUN BIT1
516#define RXSTATUS_DATA_AVAILABLE BIT0
517#define RXSTATUS_ALL 0x01f6
518#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
519
520
521
522
523
524#define IDLEMODE_FLAGS 0x0000
525#define IDLEMODE_ALT_ONE_ZERO 0x0100
526#define IDLEMODE_ZERO 0x0200
527#define IDLEMODE_ONE 0x0300
528#define IDLEMODE_ALT_MARK_SPACE 0x0500
529#define IDLEMODE_SPACE 0x0600
530#define IDLEMODE_MARK 0x0700
531#define IDLEMODE_MASK 0x0700
532
533
534
535
536#define IUSC_SL1660 0x4d44
537#define IUSC_PRE_SL1660 0x4553
538
539
540
541
542
543#define TCSR_PRESERVE 0x0F00
544
545#define TCSR_UNDERWAIT BIT11
546#define TXSTATUS_PREAMBLE_SENT BIT7
547#define TXSTATUS_IDLE_SENT BIT6
548#define TXSTATUS_ABORT_SENT BIT5
549#define TXSTATUS_EOF_SENT BIT4
550#define TXSTATUS_EOM_SENT BIT4
551#define TXSTATUS_CRC_SENT BIT3
552#define TXSTATUS_ALL_SENT BIT2
553#define TXSTATUS_UNDERRUN BIT1
554#define TXSTATUS_FIFO_EMPTY BIT0
555#define TXSTATUS_ALL 0x00fa
556#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
557
558
559#define MISCSTATUS_RXC_LATCHED BIT15
560#define MISCSTATUS_RXC BIT14
561#define MISCSTATUS_TXC_LATCHED BIT13
562#define MISCSTATUS_TXC BIT12
563#define MISCSTATUS_RI_LATCHED BIT11
564#define MISCSTATUS_RI BIT10
565#define MISCSTATUS_DSR_LATCHED BIT9
566#define MISCSTATUS_DSR BIT8
567#define MISCSTATUS_DCD_LATCHED BIT7
568#define MISCSTATUS_DCD BIT6
569#define MISCSTATUS_CTS_LATCHED BIT5
570#define MISCSTATUS_CTS BIT4
571#define MISCSTATUS_RCC_UNDERRUN BIT3
572#define MISCSTATUS_DPLL_NO_SYNC BIT2
573#define MISCSTATUS_BRG1_ZERO BIT1
574#define MISCSTATUS_BRG0_ZERO BIT0
575
576#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
577#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
578
579#define SICR_RXC_ACTIVE BIT15
580#define SICR_RXC_INACTIVE BIT14
581#define SICR_RXC (BIT15+BIT14)
582#define SICR_TXC_ACTIVE BIT13
583#define SICR_TXC_INACTIVE BIT12
584#define SICR_TXC (BIT13+BIT12)
585#define SICR_RI_ACTIVE BIT11
586#define SICR_RI_INACTIVE BIT10
587#define SICR_RI (BIT11+BIT10)
588#define SICR_DSR_ACTIVE BIT9
589#define SICR_DSR_INACTIVE BIT8
590#define SICR_DSR (BIT9+BIT8)
591#define SICR_DCD_ACTIVE BIT7
592#define SICR_DCD_INACTIVE BIT6
593#define SICR_DCD (BIT7+BIT6)
594#define SICR_CTS_ACTIVE BIT5
595#define SICR_CTS_INACTIVE BIT4
596#define SICR_CTS (BIT5+BIT4)
597#define SICR_RCC_UNDERFLOW BIT3
598#define SICR_DPLL_NO_SYNC BIT2
599#define SICR_BRG1_ZERO BIT1
600#define SICR_BRG0_ZERO BIT0
601
602void usc_DisableMasterIrqBit( struct mgsl_struct *info );
603void usc_EnableMasterIrqBit( struct mgsl_struct *info );
604void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
605void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
606void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
607
608#define usc_EnableInterrupts( a, b ) \
609 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610
611#define usc_DisableInterrupts( a, b ) \
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613
614#define usc_EnableMasterIrqBit(a) \
615 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616
617#define usc_DisableMasterIrqBit(a) \
618 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
619
620#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
621
622
623
624
625
626
627#define TXSTATUS_PREAMBLE_SENT BIT7
628#define TXSTATUS_IDLE_SENT BIT6
629#define TXSTATUS_ABORT_SENT BIT5
630#define TXSTATUS_EOF BIT4
631#define TXSTATUS_CRC_SENT BIT3
632#define TXSTATUS_ALL_SENT BIT2
633#define TXSTATUS_UNDERRUN BIT1
634#define TXSTATUS_FIFO_EMPTY BIT0
635
636#define DICR_MASTER BIT15
637#define DICR_TRANSMIT BIT0
638#define DICR_RECEIVE BIT1
639
640#define usc_EnableDmaInterrupts(a,b) \
641 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642
643#define usc_DisableDmaInterrupts(a,b) \
644 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
645
646#define usc_EnableStatusIrqs(a,b) \
647 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648
649#define usc_DisablestatusIrqs(a,b) \
650 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
651
652
653
654
655
656#define DISABLE_UNCONDITIONAL 0
657#define DISABLE_END_OF_FRAME 1
658#define ENABLE_UNCONDITIONAL 2
659#define ENABLE_AUTO_CTS 3
660#define ENABLE_AUTO_DCD 3
661#define usc_EnableTransmitter(a,b) \
662 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
663#define usc_EnableReceiver(a,b) \
664 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
665
666static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
667static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
668static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
669
670static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
671static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
672static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
673void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
674void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
675
676#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
677#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
678
679#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
680
681static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
682static void usc_start_receiver( struct mgsl_struct *info );
683static void usc_stop_receiver( struct mgsl_struct *info );
684
685static void usc_start_transmitter( struct mgsl_struct *info );
686static void usc_stop_transmitter( struct mgsl_struct *info );
687static void usc_set_txidle( struct mgsl_struct *info );
688static void usc_load_txfifo( struct mgsl_struct *info );
689
690static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
691static void usc_enable_loopback( struct mgsl_struct *info, int enable );
692
693static void usc_get_serial_signals( struct mgsl_struct *info );
694static void usc_set_serial_signals( struct mgsl_struct *info );
695
696static void usc_reset( struct mgsl_struct *info );
697
698static void usc_set_sync_mode( struct mgsl_struct *info );
699static void usc_set_sdlc_mode( struct mgsl_struct *info );
700static void usc_set_async_mode( struct mgsl_struct *info );
701static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
702
703static void usc_loopback_frame( struct mgsl_struct *info );
704
705static void mgsl_tx_timeout(unsigned long context);
706
707
708static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
709static void usc_loopmode_insert_request( struct mgsl_struct * info );
710static int usc_loopmode_active( struct mgsl_struct * info);
711static void usc_loopmode_send_done( struct mgsl_struct * info );
712
713static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
714
715#if SYNCLINK_GENERIC_HDLC
716#define dev_to_port(D) (dev_to_hdlc(D)->priv)
717static void hdlcdev_tx_done(struct mgsl_struct *info);
718static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
719static int hdlcdev_init(struct mgsl_struct *info);
720static void hdlcdev_exit(struct mgsl_struct *info);
721#endif
722
723
724
725
726
727
728#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
729(0x00400020 + \
730((WrHold) << 30) + \
731((WrDly) << 28) + \
732((RdDly) << 26) + \
733((Nwdd) << 20) + \
734((Nwad) << 15) + \
735((Nxda) << 13) + \
736((Nrdd) << 11) + \
737((Nrad) << 6) )
738
739static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
740
741
742
743
744static bool mgsl_register_test( struct mgsl_struct *info );
745static bool mgsl_irq_test( struct mgsl_struct *info );
746static bool mgsl_dma_test( struct mgsl_struct *info );
747static bool mgsl_memory_test( struct mgsl_struct *info );
748static int mgsl_adapter_test( struct mgsl_struct *info );
749
750
751
752
753static int mgsl_claim_resources(struct mgsl_struct *info);
754static void mgsl_release_resources(struct mgsl_struct *info);
755static void mgsl_add_device(struct mgsl_struct *info);
756static struct mgsl_struct* mgsl_allocate_device(void);
757
758
759
760
761static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
762static bool mgsl_get_rx_frame( struct mgsl_struct *info );
763static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
764static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
765static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
766static int num_free_tx_dma_buffers(struct mgsl_struct *info);
767static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
768static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
769
770
771
772
773static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
774static void mgsl_free_dma_buffers(struct mgsl_struct *info);
775static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
776static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
777static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
778static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
779static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
780static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
781static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
782static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
783static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
784static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
785
786
787
788
789static void mgsl_bh_handler(struct work_struct *work);
790static void mgsl_bh_receive(struct mgsl_struct *info);
791static void mgsl_bh_transmit(struct mgsl_struct *info);
792static void mgsl_bh_status(struct mgsl_struct *info);
793
794
795
796
797static void mgsl_isr_null( struct mgsl_struct *info );
798static void mgsl_isr_transmit_data( struct mgsl_struct *info );
799static void mgsl_isr_receive_data( struct mgsl_struct *info );
800static void mgsl_isr_receive_status( struct mgsl_struct *info );
801static void mgsl_isr_transmit_status( struct mgsl_struct *info );
802static void mgsl_isr_io_pin( struct mgsl_struct *info );
803static void mgsl_isr_misc( struct mgsl_struct *info );
804static void mgsl_isr_receive_dma( struct mgsl_struct *info );
805static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
806
807typedef void (*isr_dispatch_func)(struct mgsl_struct *);
808
809static isr_dispatch_func UscIsrTable[7] =
810{
811 mgsl_isr_null,
812 mgsl_isr_misc,
813 mgsl_isr_io_pin,
814 mgsl_isr_transmit_data,
815 mgsl_isr_transmit_status,
816 mgsl_isr_receive_data,
817 mgsl_isr_receive_status
818};
819
820
821
822
823static int tiocmget(struct tty_struct *tty);
824static int tiocmset(struct tty_struct *tty,
825 unsigned int set, unsigned int clear);
826static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
827 __user *user_icount);
828static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
829static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
830static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
831static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
832static int mgsl_txenable(struct mgsl_struct * info, int enable);
833static int mgsl_txabort(struct mgsl_struct * info);
834static int mgsl_rxenable(struct mgsl_struct * info, int enable);
835static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
836static int mgsl_loopmode_send_done( struct mgsl_struct * info );
837
838
839static bool pci_registered;
840
841
842
843
844static struct mgsl_struct *mgsl_device_list;
845static int mgsl_device_count;
846
847
848
849
850
851
852static bool break_on_load;
853
854
855
856
857
858static int ttymajor;
859
860
861
862
863static int io[MAX_ISA_DEVICES];
864static int irq[MAX_ISA_DEVICES];
865static int dma[MAX_ISA_DEVICES];
866static int debug_level;
867static int maxframe[MAX_TOTAL_DEVICES];
868static int txdmabufs[MAX_TOTAL_DEVICES];
869static int txholdbufs[MAX_TOTAL_DEVICES];
870
871module_param(break_on_load, bool, 0);
872module_param(ttymajor, int, 0);
873module_param_array(io, int, NULL, 0);
874module_param_array(irq, int, NULL, 0);
875module_param_array(dma, int, NULL, 0);
876module_param(debug_level, int, 0);
877module_param_array(maxframe, int, NULL, 0);
878module_param_array(txdmabufs, int, NULL, 0);
879module_param_array(txholdbufs, int, NULL, 0);
880
881static char *driver_name = "SyncLink serial driver";
882static char *driver_version = "$Revision: 4.38 $";
883
884static int synclink_init_one (struct pci_dev *dev,
885 const struct pci_device_id *ent);
886static void synclink_remove_one (struct pci_dev *dev);
887
888static struct pci_device_id synclink_pci_tbl[] = {
889 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
890 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
891 { 0, },
892};
893MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
894
895MODULE_LICENSE("GPL");
896
897static struct pci_driver synclink_pci_driver = {
898 .name = "synclink",
899 .id_table = synclink_pci_tbl,
900 .probe = synclink_init_one,
901 .remove = synclink_remove_one,
902};
903
904static struct tty_driver *serial_driver;
905
906
907#define WAKEUP_CHARS 256
908
909
910static void mgsl_change_params(struct mgsl_struct *info);
911static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
912
913
914
915
916
917
918
919static void* mgsl_get_text_ptr(void)
920{
921 return mgsl_get_text_ptr;
922}
923
924static inline int mgsl_paranoia_check(struct mgsl_struct *info,
925 char *name, const char *routine)
926{
927#ifdef MGSL_PARANOIA_CHECK
928 static const char *badmagic =
929 "Warning: bad magic number for mgsl struct (%s) in %s\n";
930 static const char *badinfo =
931 "Warning: null mgsl_struct for (%s) in %s\n";
932
933 if (!info) {
934 printk(badinfo, name, routine);
935 return 1;
936 }
937 if (info->magic != MGSL_MAGIC) {
938 printk(badmagic, name, routine);
939 return 1;
940 }
941#else
942 if (!info)
943 return 1;
944#endif
945 return 0;
946}
947
948
949
950
951
952
953
954
955
956
957static void ldisc_receive_buf(struct tty_struct *tty,
958 const __u8 *data, char *flags, int count)
959{
960 struct tty_ldisc *ld;
961 if (!tty)
962 return;
963 ld = tty_ldisc_ref(tty);
964 if (ld) {
965 if (ld->ops->receive_buf)
966 ld->ops->receive_buf(tty, data, flags, count);
967 tty_ldisc_deref(ld);
968 }
969}
970
971
972
973
974
975
976static void mgsl_stop(struct tty_struct *tty)
977{
978 struct mgsl_struct *info = tty->driver_data;
979 unsigned long flags;
980
981 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
982 return;
983
984 if ( debug_level >= DEBUG_LEVEL_INFO )
985 printk("mgsl_stop(%s)\n",info->device_name);
986
987 spin_lock_irqsave(&info->irq_spinlock,flags);
988 if (info->tx_enabled)
989 usc_stop_transmitter(info);
990 spin_unlock_irqrestore(&info->irq_spinlock,flags);
991
992}
993
994
995
996
997
998
999static void mgsl_start(struct tty_struct *tty)
1000{
1001 struct mgsl_struct *info = tty->driver_data;
1002 unsigned long flags;
1003
1004 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1005 return;
1006
1007 if ( debug_level >= DEBUG_LEVEL_INFO )
1008 printk("mgsl_start(%s)\n",info->device_name);
1009
1010 spin_lock_irqsave(&info->irq_spinlock,flags);
1011 if (!info->tx_enabled)
1012 usc_start_transmitter(info);
1013 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1014
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024static int mgsl_bh_action(struct mgsl_struct *info)
1025{
1026 unsigned long flags;
1027 int rc = 0;
1028
1029 spin_lock_irqsave(&info->irq_spinlock,flags);
1030
1031 if (info->pending_bh & BH_RECEIVE) {
1032 info->pending_bh &= ~BH_RECEIVE;
1033 rc = BH_RECEIVE;
1034 } else if (info->pending_bh & BH_TRANSMIT) {
1035 info->pending_bh &= ~BH_TRANSMIT;
1036 rc = BH_TRANSMIT;
1037 } else if (info->pending_bh & BH_STATUS) {
1038 info->pending_bh &= ~BH_STATUS;
1039 rc = BH_STATUS;
1040 }
1041
1042 if (!rc) {
1043
1044 info->bh_running = false;
1045 info->bh_requested = false;
1046 }
1047
1048 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1049
1050 return rc;
1051}
1052
1053
1054
1055
1056static void mgsl_bh_handler(struct work_struct *work)
1057{
1058 struct mgsl_struct *info =
1059 container_of(work, struct mgsl_struct, task);
1060 int action;
1061
1062 if (!info)
1063 return;
1064
1065 if ( debug_level >= DEBUG_LEVEL_BH )
1066 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1067 __FILE__,__LINE__,info->device_name);
1068
1069 info->bh_running = true;
1070
1071 while((action = mgsl_bh_action(info)) != 0) {
1072
1073
1074 if ( debug_level >= DEBUG_LEVEL_BH )
1075 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1076 __FILE__,__LINE__,action);
1077
1078 switch (action) {
1079
1080 case BH_RECEIVE:
1081 mgsl_bh_receive(info);
1082 break;
1083 case BH_TRANSMIT:
1084 mgsl_bh_transmit(info);
1085 break;
1086 case BH_STATUS:
1087 mgsl_bh_status(info);
1088 break;
1089 default:
1090
1091 printk("Unknown work item ID=%08X!\n", action);
1092 break;
1093 }
1094 }
1095
1096 if ( debug_level >= DEBUG_LEVEL_BH )
1097 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1098 __FILE__,__LINE__,info->device_name);
1099}
1100
1101static void mgsl_bh_receive(struct mgsl_struct *info)
1102{
1103 bool (*get_rx_frame)(struct mgsl_struct *info) =
1104 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1105
1106 if ( debug_level >= DEBUG_LEVEL_BH )
1107 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1108 __FILE__,__LINE__,info->device_name);
1109
1110 do
1111 {
1112 if (info->rx_rcc_underrun) {
1113 unsigned long flags;
1114 spin_lock_irqsave(&info->irq_spinlock,flags);
1115 usc_start_receiver(info);
1116 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1117 return;
1118 }
1119 } while(get_rx_frame(info));
1120}
1121
1122static void mgsl_bh_transmit(struct mgsl_struct *info)
1123{
1124 struct tty_struct *tty = info->port.tty;
1125 unsigned long flags;
1126
1127 if ( debug_level >= DEBUG_LEVEL_BH )
1128 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1129 __FILE__,__LINE__,info->device_name);
1130
1131 if (tty)
1132 tty_wakeup(tty);
1133
1134
1135
1136
1137 spin_lock_irqsave(&info->irq_spinlock,flags);
1138 if ( !info->tx_active && info->loopmode_send_done_requested )
1139 usc_loopmode_send_done( info );
1140 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1141}
1142
1143static void mgsl_bh_status(struct mgsl_struct *info)
1144{
1145 if ( debug_level >= DEBUG_LEVEL_BH )
1146 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1147 __FILE__,__LINE__,info->device_name);
1148
1149 info->ri_chkcount = 0;
1150 info->dsr_chkcount = 0;
1151 info->dcd_chkcount = 0;
1152 info->cts_chkcount = 0;
1153}
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164static void mgsl_isr_receive_status( struct mgsl_struct *info )
1165{
1166 u16 status = usc_InReg( info, RCSR );
1167
1168 if ( debug_level >= DEBUG_LEVEL_ISR )
1169 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1170 __FILE__,__LINE__,status);
1171
1172 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1173 info->loopmode_insert_requested &&
1174 usc_loopmode_active(info) )
1175 {
1176 ++info->icount.rxabort;
1177 info->loopmode_insert_requested = false;
1178
1179
1180 info->cmr_value &= ~BIT13;
1181 usc_OutReg(info, CMR, info->cmr_value);
1182
1183
1184 usc_OutReg(info, RICR,
1185 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1186 }
1187
1188 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1189 if (status & RXSTATUS_EXITED_HUNT)
1190 info->icount.exithunt++;
1191 if (status & RXSTATUS_IDLE_RECEIVED)
1192 info->icount.rxidle++;
1193 wake_up_interruptible(&info->event_wait_q);
1194 }
1195
1196 if (status & RXSTATUS_OVERRUN){
1197 info->icount.rxover++;
1198 usc_process_rxoverrun_sync( info );
1199 }
1200
1201 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1202 usc_UnlatchRxstatusBits( info, status );
1203
1204}
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1217{
1218 u16 status = usc_InReg( info, TCSR );
1219
1220 if ( debug_level >= DEBUG_LEVEL_ISR )
1221 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1222 __FILE__,__LINE__,status);
1223
1224 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1225 usc_UnlatchTxstatusBits( info, status );
1226
1227 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1228 {
1229
1230
1231
1232
1233
1234 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1235 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1236 }
1237
1238 if ( status & TXSTATUS_EOF_SENT )
1239 info->icount.txok++;
1240 else if ( status & TXSTATUS_UNDERRUN )
1241 info->icount.txunder++;
1242 else if ( status & TXSTATUS_ABORT_SENT )
1243 info->icount.txabort++;
1244 else
1245 info->icount.txunder++;
1246
1247 info->tx_active = false;
1248 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1249 del_timer(&info->tx_timer);
1250
1251 if ( info->drop_rts_on_tx_done ) {
1252 usc_get_serial_signals( info );
1253 if ( info->serial_signals & SerialSignal_RTS ) {
1254 info->serial_signals &= ~SerialSignal_RTS;
1255 usc_set_serial_signals( info );
1256 }
1257 info->drop_rts_on_tx_done = false;
1258 }
1259
1260#if SYNCLINK_GENERIC_HDLC
1261 if (info->netcount)
1262 hdlcdev_tx_done(info);
1263 else
1264#endif
1265 {
1266 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1267 usc_stop_transmitter(info);
1268 return;
1269 }
1270 info->pending_bh |= BH_TRANSMIT;
1271 }
1272
1273}
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283static void mgsl_isr_io_pin( struct mgsl_struct *info )
1284{
1285 struct mgsl_icount *icount;
1286 u16 status = usc_InReg( info, MISR );
1287
1288 if ( debug_level >= DEBUG_LEVEL_ISR )
1289 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1290 __FILE__,__LINE__,status);
1291
1292 usc_ClearIrqPendingBits( info, IO_PIN );
1293 usc_UnlatchIostatusBits( info, status );
1294
1295 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1296 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1297 icount = &info->icount;
1298
1299 if (status & MISCSTATUS_RI_LATCHED) {
1300 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1301 usc_DisablestatusIrqs(info,SICR_RI);
1302 icount->rng++;
1303 if ( status & MISCSTATUS_RI )
1304 info->input_signal_events.ri_up++;
1305 else
1306 info->input_signal_events.ri_down++;
1307 }
1308 if (status & MISCSTATUS_DSR_LATCHED) {
1309 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1310 usc_DisablestatusIrqs(info,SICR_DSR);
1311 icount->dsr++;
1312 if ( status & MISCSTATUS_DSR )
1313 info->input_signal_events.dsr_up++;
1314 else
1315 info->input_signal_events.dsr_down++;
1316 }
1317 if (status & MISCSTATUS_DCD_LATCHED) {
1318 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1319 usc_DisablestatusIrqs(info,SICR_DCD);
1320 icount->dcd++;
1321 if (status & MISCSTATUS_DCD) {
1322 info->input_signal_events.dcd_up++;
1323 } else
1324 info->input_signal_events.dcd_down++;
1325#if SYNCLINK_GENERIC_HDLC
1326 if (info->netcount) {
1327 if (status & MISCSTATUS_DCD)
1328 netif_carrier_on(info->netdev);
1329 else
1330 netif_carrier_off(info->netdev);
1331 }
1332#endif
1333 }
1334 if (status & MISCSTATUS_CTS_LATCHED)
1335 {
1336 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1337 usc_DisablestatusIrqs(info,SICR_CTS);
1338 icount->cts++;
1339 if ( status & MISCSTATUS_CTS )
1340 info->input_signal_events.cts_up++;
1341 else
1342 info->input_signal_events.cts_down++;
1343 }
1344 wake_up_interruptible(&info->status_event_wait_q);
1345 wake_up_interruptible(&info->event_wait_q);
1346
1347 if ( (info->port.flags & ASYNC_CHECK_CD) &&
1348 (status & MISCSTATUS_DCD_LATCHED) ) {
1349 if ( debug_level >= DEBUG_LEVEL_ISR )
1350 printk("%s CD now %s...", info->device_name,
1351 (status & MISCSTATUS_DCD) ? "on" : "off");
1352 if (status & MISCSTATUS_DCD)
1353 wake_up_interruptible(&info->port.open_wait);
1354 else {
1355 if ( debug_level >= DEBUG_LEVEL_ISR )
1356 printk("doing serial hangup...");
1357 if (info->port.tty)
1358 tty_hangup(info->port.tty);
1359 }
1360 }
1361
1362 if (tty_port_cts_enabled(&info->port) &&
1363 (status & MISCSTATUS_CTS_LATCHED) ) {
1364 if (info->port.tty->hw_stopped) {
1365 if (status & MISCSTATUS_CTS) {
1366 if ( debug_level >= DEBUG_LEVEL_ISR )
1367 printk("CTS tx start...");
1368 if (info->port.tty)
1369 info->port.tty->hw_stopped = 0;
1370 usc_start_transmitter(info);
1371 info->pending_bh |= BH_TRANSMIT;
1372 return;
1373 }
1374 } else {
1375 if (!(status & MISCSTATUS_CTS)) {
1376 if ( debug_level >= DEBUG_LEVEL_ISR )
1377 printk("CTS tx stop...");
1378 if (info->port.tty)
1379 info->port.tty->hw_stopped = 1;
1380 usc_stop_transmitter(info);
1381 }
1382 }
1383 }
1384 }
1385
1386 info->pending_bh |= BH_STATUS;
1387
1388
1389 if ( status & MISCSTATUS_TXC_LATCHED ){
1390 usc_OutReg( info, SICR,
1391 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1392 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1393 info->irq_occurred = true;
1394 }
1395
1396}
1397
1398
1399
1400
1401
1402
1403
1404
1405static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1406{
1407 if ( debug_level >= DEBUG_LEVEL_ISR )
1408 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1409 __FILE__,__LINE__,info->xmit_cnt);
1410
1411 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1412
1413 if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1414 usc_stop_transmitter(info);
1415 return;
1416 }
1417
1418 if ( info->xmit_cnt )
1419 usc_load_txfifo( info );
1420 else
1421 info->tx_active = false;
1422
1423 if (info->xmit_cnt < WAKEUP_CHARS)
1424 info->pending_bh |= BH_TRANSMIT;
1425
1426}
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437static void mgsl_isr_receive_data( struct mgsl_struct *info )
1438{
1439 int Fifocount;
1440 u16 status;
1441 int work = 0;
1442 unsigned char DataByte;
1443 struct tty_struct *tty = info->port.tty;
1444 struct mgsl_icount *icount = &info->icount;
1445
1446 if ( debug_level >= DEBUG_LEVEL_ISR )
1447 printk("%s(%d):mgsl_isr_receive_data\n",
1448 __FILE__,__LINE__);
1449
1450 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1451
1452
1453 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1454
1455
1456
1457 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1458
1459
1460
1461 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1462 int flag;
1463
1464
1465 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1466 info->io_base + CCAR );
1467 DataByte = inb( info->io_base + CCAR );
1468
1469
1470 status = usc_InReg(info, RCSR);
1471 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1472 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1473 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1474
1475 icount->rx++;
1476
1477 flag = 0;
1478 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1479 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1480 printk("rxerr=%04X\n",status);
1481
1482 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1483 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1484 icount->brk++;
1485 } else if (status & RXSTATUS_PARITY_ERROR)
1486 icount->parity++;
1487 else if (status & RXSTATUS_FRAMING_ERROR)
1488 icount->frame++;
1489 else if (status & RXSTATUS_OVERRUN) {
1490
1491
1492 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1493 icount->overrun++;
1494 }
1495
1496
1497 if (status & info->ignore_status_mask)
1498 continue;
1499
1500 status &= info->read_status_mask;
1501
1502 if (status & RXSTATUS_BREAK_RECEIVED) {
1503 flag = TTY_BREAK;
1504 if (info->port.flags & ASYNC_SAK)
1505 do_SAK(tty);
1506 } else if (status & RXSTATUS_PARITY_ERROR)
1507 flag = TTY_PARITY;
1508 else if (status & RXSTATUS_FRAMING_ERROR)
1509 flag = TTY_FRAME;
1510 }
1511 tty_insert_flip_char(tty, DataByte, flag);
1512 if (status & RXSTATUS_OVERRUN) {
1513
1514
1515
1516
1517 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1518 }
1519 }
1520
1521 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1522 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1523 __FILE__,__LINE__,icount->rx,icount->brk,
1524 icount->parity,icount->frame,icount->overrun);
1525 }
1526
1527 if(work)
1528 tty_flip_buffer_push(tty);
1529}
1530
1531
1532
1533
1534
1535
1536
1537
1538static void mgsl_isr_misc( struct mgsl_struct *info )
1539{
1540 u16 status = usc_InReg( info, MISR );
1541
1542 if ( debug_level >= DEBUG_LEVEL_ISR )
1543 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1544 __FILE__,__LINE__,status);
1545
1546 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1547 (info->params.mode == MGSL_MODE_HDLC)) {
1548
1549
1550 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1551 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1552 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1553 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1554 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1555
1556
1557 info->pending_bh |= BH_RECEIVE;
1558 info->rx_rcc_underrun = true;
1559 }
1560
1561 usc_ClearIrqPendingBits( info, MISC );
1562 usc_UnlatchMiscstatusBits( info, status );
1563
1564}
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574static void mgsl_isr_null( struct mgsl_struct *info )
1575{
1576
1577}
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1599{
1600 u16 status;
1601
1602
1603 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1604
1605
1606
1607 status = usc_InDmaReg( info, RDMR );
1608
1609 if ( debug_level >= DEBUG_LEVEL_ISR )
1610 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1611 __FILE__,__LINE__,info->device_name,status);
1612
1613 info->pending_bh |= BH_RECEIVE;
1614
1615 if ( status & BIT3 ) {
1616 info->rx_overflow = true;
1617 info->icount.buf_overrun++;
1618 }
1619
1620}
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1643{
1644 u16 status;
1645
1646
1647 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1648
1649
1650
1651
1652 status = usc_InDmaReg( info, TDMR );
1653
1654 if ( debug_level >= DEBUG_LEVEL_ISR )
1655 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1656 __FILE__,__LINE__,info->device_name,status);
1657
1658 if ( status & BIT2 ) {
1659 --info->tx_dma_buffers_used;
1660
1661
1662
1663
1664 if ( load_next_tx_holding_buffer(info) ) {
1665
1666
1667
1668 info->pending_bh |= BH_TRANSMIT;
1669 }
1670 }
1671
1672}
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1686{
1687 struct mgsl_struct *info = dev_id;
1688 u16 UscVector;
1689 u16 DmaVector;
1690
1691 if ( debug_level >= DEBUG_LEVEL_ISR )
1692 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1693 __FILE__, __LINE__, info->irq_level);
1694
1695 spin_lock(&info->irq_spinlock);
1696
1697 for(;;) {
1698
1699 UscVector = usc_InReg(info, IVR) >> 9;
1700 DmaVector = usc_InDmaReg(info, DIVR);
1701
1702 if ( debug_level >= DEBUG_LEVEL_ISR )
1703 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1704 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1705
1706 if ( !UscVector && !DmaVector )
1707 break;
1708
1709
1710 if ( UscVector )
1711 (*UscIsrTable[UscVector])(info);
1712 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1713 mgsl_isr_transmit_dma(info);
1714 else
1715 mgsl_isr_receive_dma(info);
1716
1717 if ( info->isr_overflow ) {
1718 printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1719 __FILE__, __LINE__, info->device_name, info->irq_level);
1720 usc_DisableMasterIrqBit(info);
1721 usc_DisableDmaInterrupts(info,DICR_MASTER);
1722 break;
1723 }
1724 }
1725
1726
1727
1728
1729
1730 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1731 if ( debug_level >= DEBUG_LEVEL_ISR )
1732 printk("%s(%d):%s queueing bh task.\n",
1733 __FILE__,__LINE__,info->device_name);
1734 schedule_work(&info->task);
1735 info->bh_requested = true;
1736 }
1737
1738 spin_unlock(&info->irq_spinlock);
1739
1740 if ( debug_level >= DEBUG_LEVEL_ISR )
1741 printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1742 __FILE__, __LINE__, info->irq_level);
1743
1744 return IRQ_HANDLED;
1745}
1746
1747
1748
1749
1750
1751
1752
1753
1754static int startup(struct mgsl_struct * info)
1755{
1756 int retval = 0;
1757
1758 if ( debug_level >= DEBUG_LEVEL_INFO )
1759 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1760
1761 if (info->port.flags & ASYNC_INITIALIZED)
1762 return 0;
1763
1764 if (!info->xmit_buf) {
1765
1766 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1767 if (!info->xmit_buf) {
1768 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1769 __FILE__,__LINE__,info->device_name);
1770 return -ENOMEM;
1771 }
1772 }
1773
1774 info->pending_bh = 0;
1775
1776 memset(&info->icount, 0, sizeof(info->icount));
1777
1778 setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1779
1780
1781 retval = mgsl_claim_resources(info);
1782
1783
1784 if ( !retval )
1785 retval = mgsl_adapter_test(info);
1786
1787 if ( retval ) {
1788 if (capable(CAP_SYS_ADMIN) && info->port.tty)
1789 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1790 mgsl_release_resources(info);
1791 return retval;
1792 }
1793
1794
1795 mgsl_change_params(info);
1796
1797 if (info->port.tty)
1798 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1799
1800 info->port.flags |= ASYNC_INITIALIZED;
1801
1802 return 0;
1803
1804}
1805
1806
1807
1808
1809
1810
1811
1812
1813static void shutdown(struct mgsl_struct * info)
1814{
1815 unsigned long flags;
1816
1817 if (!(info->port.flags & ASYNC_INITIALIZED))
1818 return;
1819
1820 if (debug_level >= DEBUG_LEVEL_INFO)
1821 printk("%s(%d):mgsl_shutdown(%s)\n",
1822 __FILE__,__LINE__, info->device_name );
1823
1824
1825
1826 wake_up_interruptible(&info->status_event_wait_q);
1827 wake_up_interruptible(&info->event_wait_q);
1828
1829 del_timer_sync(&info->tx_timer);
1830
1831 if (info->xmit_buf) {
1832 free_page((unsigned long) info->xmit_buf);
1833 info->xmit_buf = NULL;
1834 }
1835
1836 spin_lock_irqsave(&info->irq_spinlock,flags);
1837 usc_DisableMasterIrqBit(info);
1838 usc_stop_receiver(info);
1839 usc_stop_transmitter(info);
1840 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1841 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1842 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1843
1844
1845
1846
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1848
1849
1850
1851
1852 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1853
1854 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1855 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1856 usc_set_serial_signals(info);
1857 }
1858
1859 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1860
1861 mgsl_release_resources(info);
1862
1863 if (info->port.tty)
1864 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1865
1866 info->port.flags &= ~ASYNC_INITIALIZED;
1867
1868}
1869
1870static void mgsl_program_hw(struct mgsl_struct *info)
1871{
1872 unsigned long flags;
1873
1874 spin_lock_irqsave(&info->irq_spinlock,flags);
1875
1876 usc_stop_receiver(info);
1877 usc_stop_transmitter(info);
1878 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1879
1880 if (info->params.mode == MGSL_MODE_HDLC ||
1881 info->params.mode == MGSL_MODE_RAW ||
1882 info->netcount)
1883 usc_set_sync_mode(info);
1884 else
1885 usc_set_async_mode(info);
1886
1887 usc_set_serial_signals(info);
1888
1889 info->dcd_chkcount = 0;
1890 info->cts_chkcount = 0;
1891 info->ri_chkcount = 0;
1892 info->dsr_chkcount = 0;
1893
1894 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1895 usc_EnableInterrupts(info, IO_PIN);
1896 usc_get_serial_signals(info);
1897
1898 if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1899 usc_start_receiver(info);
1900
1901 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1902}
1903
1904
1905
1906static void mgsl_change_params(struct mgsl_struct *info)
1907{
1908 unsigned cflag;
1909 int bits_per_char;
1910
1911 if (!info->port.tty)
1912 return;
1913
1914 if (debug_level >= DEBUG_LEVEL_INFO)
1915 printk("%s(%d):mgsl_change_params(%s)\n",
1916 __FILE__,__LINE__, info->device_name );
1917
1918 cflag = info->port.tty->termios.c_cflag;
1919
1920
1921
1922 if (cflag & CBAUD)
1923 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1924 else
1925 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1926
1927
1928
1929 switch (cflag & CSIZE) {
1930 case CS5: info->params.data_bits = 5; break;
1931 case CS6: info->params.data_bits = 6; break;
1932 case CS7: info->params.data_bits = 7; break;
1933 case CS8: info->params.data_bits = 8; break;
1934
1935 default: info->params.data_bits = 7; break;
1936 }
1937
1938 if (cflag & CSTOPB)
1939 info->params.stop_bits = 2;
1940 else
1941 info->params.stop_bits = 1;
1942
1943 info->params.parity = ASYNC_PARITY_NONE;
1944 if (cflag & PARENB) {
1945 if (cflag & PARODD)
1946 info->params.parity = ASYNC_PARITY_ODD;
1947 else
1948 info->params.parity = ASYNC_PARITY_EVEN;
1949#ifdef CMSPAR
1950 if (cflag & CMSPAR)
1951 info->params.parity = ASYNC_PARITY_SPACE;
1952#endif
1953 }
1954
1955
1956
1957
1958 bits_per_char = info->params.data_bits +
1959 info->params.stop_bits + 1;
1960
1961
1962
1963
1964
1965 if (info->params.data_rate <= 460800)
1966 info->params.data_rate = tty_get_baud_rate(info->port.tty);
1967
1968 if ( info->params.data_rate ) {
1969 info->timeout = (32*HZ*bits_per_char) /
1970 info->params.data_rate;
1971 }
1972 info->timeout += HZ/50;
1973
1974 if (cflag & CRTSCTS)
1975 info->port.flags |= ASYNC_CTS_FLOW;
1976 else
1977 info->port.flags &= ~ASYNC_CTS_FLOW;
1978
1979 if (cflag & CLOCAL)
1980 info->port.flags &= ~ASYNC_CHECK_CD;
1981 else
1982 info->port.flags |= ASYNC_CHECK_CD;
1983
1984
1985
1986 info->read_status_mask = RXSTATUS_OVERRUN;
1987 if (I_INPCK(info->port.tty))
1988 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1989 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1990 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1991
1992 if (I_IGNPAR(info->port.tty))
1993 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1994 if (I_IGNBRK(info->port.tty)) {
1995 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1996
1997
1998
1999 if (I_IGNPAR(info->port.tty))
2000 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2001 }
2002
2003 mgsl_program_hw(info);
2004
2005}
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2017{
2018 struct mgsl_struct *info = tty->driver_data;
2019 unsigned long flags;
2020 int ret = 0;
2021
2022 if (debug_level >= DEBUG_LEVEL_INFO) {
2023 printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2024 __FILE__, __LINE__, ch, info->device_name);
2025 }
2026
2027 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2028 return 0;
2029
2030 if (!info->xmit_buf)
2031 return 0;
2032
2033 spin_lock_irqsave(&info->irq_spinlock, flags);
2034
2035 if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2036 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2037 info->xmit_buf[info->xmit_head++] = ch;
2038 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2039 info->xmit_cnt++;
2040 ret = 1;
2041 }
2042 }
2043 spin_unlock_irqrestore(&info->irq_spinlock, flags);
2044 return ret;
2045
2046}
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056static void mgsl_flush_chars(struct tty_struct *tty)
2057{
2058 struct mgsl_struct *info = tty->driver_data;
2059 unsigned long flags;
2060
2061 if ( debug_level >= DEBUG_LEVEL_INFO )
2062 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2063 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2064
2065 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2066 return;
2067
2068 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2069 !info->xmit_buf)
2070 return;
2071
2072 if ( debug_level >= DEBUG_LEVEL_INFO )
2073 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2074 __FILE__,__LINE__,info->device_name );
2075
2076 spin_lock_irqsave(&info->irq_spinlock,flags);
2077
2078 if (!info->tx_active) {
2079 if ( (info->params.mode == MGSL_MODE_HDLC ||
2080 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2081
2082
2083
2084 mgsl_load_tx_dma_buffer(info,
2085 info->xmit_buf,info->xmit_cnt);
2086 }
2087 usc_start_transmitter(info);
2088 }
2089
2090 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2091
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106static int mgsl_write(struct tty_struct * tty,
2107 const unsigned char *buf, int count)
2108{
2109 int c, ret = 0;
2110 struct mgsl_struct *info = tty->driver_data;
2111 unsigned long flags;
2112
2113 if ( debug_level >= DEBUG_LEVEL_INFO )
2114 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2115 __FILE__,__LINE__,info->device_name,count);
2116
2117 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2118 goto cleanup;
2119
2120 if (!info->xmit_buf)
2121 goto cleanup;
2122
2123 if ( info->params.mode == MGSL_MODE_HDLC ||
2124 info->params.mode == MGSL_MODE_RAW ) {
2125
2126 if (info->tx_active) {
2127
2128 if ( info->params.mode == MGSL_MODE_HDLC ) {
2129 ret = 0;
2130 goto cleanup;
2131 }
2132
2133
2134
2135
2136
2137 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2138
2139 ret = 0;
2140 goto cleanup;
2141 }
2142
2143
2144 ret = count;
2145 save_tx_buffer_request(info,buf,count);
2146
2147
2148
2149
2150 spin_lock_irqsave(&info->irq_spinlock,flags);
2151 load_next_tx_holding_buffer(info);
2152 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2153 goto cleanup;
2154 }
2155
2156
2157
2158
2159
2160 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2161 !usc_loopmode_active(info) )
2162 {
2163 ret = 0;
2164 goto cleanup;
2165 }
2166
2167 if ( info->xmit_cnt ) {
2168
2169
2170 ret = 0;
2171
2172
2173
2174 mgsl_load_tx_dma_buffer(info,
2175 info->xmit_buf,info->xmit_cnt);
2176 if ( debug_level >= DEBUG_LEVEL_INFO )
2177 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2178 __FILE__,__LINE__,info->device_name);
2179 } else {
2180 if ( debug_level >= DEBUG_LEVEL_INFO )
2181 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2182 __FILE__,__LINE__,info->device_name);
2183 ret = count;
2184 info->xmit_cnt = count;
2185 mgsl_load_tx_dma_buffer(info,buf,count);
2186 }
2187 } else {
2188 while (1) {
2189 spin_lock_irqsave(&info->irq_spinlock,flags);
2190 c = min_t(int, count,
2191 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2192 SERIAL_XMIT_SIZE - info->xmit_head));
2193 if (c <= 0) {
2194 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2195 break;
2196 }
2197 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2198 info->xmit_head = ((info->xmit_head + c) &
2199 (SERIAL_XMIT_SIZE-1));
2200 info->xmit_cnt += c;
2201 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2202 buf += c;
2203 count -= c;
2204 ret += c;
2205 }
2206 }
2207
2208 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2209 spin_lock_irqsave(&info->irq_spinlock,flags);
2210 if (!info->tx_active)
2211 usc_start_transmitter(info);
2212 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2213 }
2214cleanup:
2215 if ( debug_level >= DEBUG_LEVEL_INFO )
2216 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2217 __FILE__,__LINE__,info->device_name,ret);
2218
2219 return ret;
2220
2221}
2222
2223
2224
2225
2226
2227
2228
2229
2230static int mgsl_write_room(struct tty_struct *tty)
2231{
2232 struct mgsl_struct *info = tty->driver_data;
2233 int ret;
2234
2235 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2236 return 0;
2237 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2238 if (ret < 0)
2239 ret = 0;
2240
2241 if (debug_level >= DEBUG_LEVEL_INFO)
2242 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2243 __FILE__,__LINE__, info->device_name,ret );
2244
2245 if ( info->params.mode == MGSL_MODE_HDLC ||
2246 info->params.mode == MGSL_MODE_RAW ) {
2247
2248 if ( info->tx_active )
2249 return 0;
2250 else
2251 return HDLC_MAX_FRAME_SIZE;
2252 }
2253
2254 return ret;
2255
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265static int mgsl_chars_in_buffer(struct tty_struct *tty)
2266{
2267 struct mgsl_struct *info = tty->driver_data;
2268
2269 if (debug_level >= DEBUG_LEVEL_INFO)
2270 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2271 __FILE__,__LINE__, info->device_name );
2272
2273 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2274 return 0;
2275
2276 if (debug_level >= DEBUG_LEVEL_INFO)
2277 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2278 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2279
2280 if ( info->params.mode == MGSL_MODE_HDLC ||
2281 info->params.mode == MGSL_MODE_RAW ) {
2282
2283 if ( info->tx_active )
2284 return info->max_frame_size;
2285 else
2286 return 0;
2287 }
2288
2289 return info->xmit_cnt;
2290}
2291
2292
2293
2294
2295
2296
2297
2298
2299static void mgsl_flush_buffer(struct tty_struct *tty)
2300{
2301 struct mgsl_struct *info = tty->driver_data;
2302 unsigned long flags;
2303
2304 if (debug_level >= DEBUG_LEVEL_INFO)
2305 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2306 __FILE__,__LINE__, info->device_name );
2307
2308 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2309 return;
2310
2311 spin_lock_irqsave(&info->irq_spinlock,flags);
2312 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2313 del_timer(&info->tx_timer);
2314 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2315
2316 tty_wakeup(tty);
2317}
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2328{
2329 struct mgsl_struct *info = tty->driver_data;
2330 unsigned long flags;
2331
2332 if (debug_level >= DEBUG_LEVEL_INFO)
2333 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2334 __FILE__,__LINE__, info->device_name, ch );
2335
2336 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2337 return;
2338
2339 info->x_char = ch;
2340 if (ch) {
2341
2342 spin_lock_irqsave(&info->irq_spinlock,flags);
2343 if (!info->tx_enabled)
2344 usc_start_transmitter(info);
2345 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2346 }
2347}
2348
2349
2350
2351
2352
2353
2354
2355
2356static void mgsl_throttle(struct tty_struct * tty)
2357{
2358 struct mgsl_struct *info = tty->driver_data;
2359 unsigned long flags;
2360
2361 if (debug_level >= DEBUG_LEVEL_INFO)
2362 printk("%s(%d):mgsl_throttle(%s) entry\n",
2363 __FILE__,__LINE__, info->device_name );
2364
2365 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2366 return;
2367
2368 if (I_IXOFF(tty))
2369 mgsl_send_xchar(tty, STOP_CHAR(tty));
2370
2371 if (tty->termios.c_cflag & CRTSCTS) {
2372 spin_lock_irqsave(&info->irq_spinlock,flags);
2373 info->serial_signals &= ~SerialSignal_RTS;
2374 usc_set_serial_signals(info);
2375 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2376 }
2377}
2378
2379
2380
2381
2382
2383
2384
2385
2386static void mgsl_unthrottle(struct tty_struct * tty)
2387{
2388 struct mgsl_struct *info = tty->driver_data;
2389 unsigned long flags;
2390
2391 if (debug_level >= DEBUG_LEVEL_INFO)
2392 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2393 __FILE__,__LINE__, info->device_name );
2394
2395 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2396 return;
2397
2398 if (I_IXOFF(tty)) {
2399 if (info->x_char)
2400 info->x_char = 0;
2401 else
2402 mgsl_send_xchar(tty, START_CHAR(tty));
2403 }
2404
2405 if (tty->termios.c_cflag & CRTSCTS) {
2406 spin_lock_irqsave(&info->irq_spinlock,flags);
2407 info->serial_signals |= SerialSignal_RTS;
2408 usc_set_serial_signals(info);
2409 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2410 }
2411
2412}
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2424{
2425 int err;
2426
2427 if (debug_level >= DEBUG_LEVEL_INFO)
2428 printk("%s(%d):mgsl_get_params(%s)\n",
2429 __FILE__,__LINE__, info->device_name);
2430
2431 if (!user_icount) {
2432 memset(&info->icount, 0, sizeof(info->icount));
2433 } else {
2434 mutex_lock(&info->port.mutex);
2435 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2436 mutex_unlock(&info->port.mutex);
2437 if (err)
2438 return -EFAULT;
2439 }
2440
2441 return 0;
2442
2443}
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2455{
2456 int err;
2457 if (debug_level >= DEBUG_LEVEL_INFO)
2458 printk("%s(%d):mgsl_get_params(%s)\n",
2459 __FILE__,__LINE__, info->device_name);
2460
2461 mutex_lock(&info->port.mutex);
2462 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2463 mutex_unlock(&info->port.mutex);
2464 if (err) {
2465 if ( debug_level >= DEBUG_LEVEL_INFO )
2466 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2467 __FILE__,__LINE__,info->device_name);
2468 return -EFAULT;
2469 }
2470
2471 return 0;
2472
2473}
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2487{
2488 unsigned long flags;
2489 MGSL_PARAMS tmp_params;
2490 int err;
2491
2492 if (debug_level >= DEBUG_LEVEL_INFO)
2493 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2494 info->device_name );
2495 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2496 if (err) {
2497 if ( debug_level >= DEBUG_LEVEL_INFO )
2498 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2499 __FILE__,__LINE__,info->device_name);
2500 return -EFAULT;
2501 }
2502
2503 mutex_lock(&info->port.mutex);
2504 spin_lock_irqsave(&info->irq_spinlock,flags);
2505 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2506 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2507
2508 mgsl_change_params(info);
2509 mutex_unlock(&info->port.mutex);
2510
2511 return 0;
2512
2513}
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2525{
2526 int err;
2527
2528 if (debug_level >= DEBUG_LEVEL_INFO)
2529 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2530 __FILE__,__LINE__, info->device_name, info->idle_mode);
2531
2532 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2533 if (err) {
2534 if ( debug_level >= DEBUG_LEVEL_INFO )
2535 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2536 __FILE__,__LINE__,info->device_name);
2537 return -EFAULT;
2538 }
2539
2540 return 0;
2541
2542}
2543
2544
2545
2546
2547
2548
2549
2550
2551static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2552{
2553 unsigned long flags;
2554
2555 if (debug_level >= DEBUG_LEVEL_INFO)
2556 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2557 info->device_name, idle_mode );
2558
2559 spin_lock_irqsave(&info->irq_spinlock,flags);
2560 info->idle_mode = idle_mode;
2561 usc_set_txidle( info );
2562 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2563 return 0;
2564
2565}
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578static int mgsl_txenable(struct mgsl_struct * info, int enable)
2579{
2580 unsigned long flags;
2581
2582 if (debug_level >= DEBUG_LEVEL_INFO)
2583 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2584 info->device_name, enable);
2585
2586 spin_lock_irqsave(&info->irq_spinlock,flags);
2587 if ( enable ) {
2588 if ( !info->tx_enabled ) {
2589
2590 usc_start_transmitter(info);
2591
2592
2593
2594
2595
2596
2597
2598 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2599 usc_loopmode_insert_request( info );
2600 }
2601 } else {
2602 if ( info->tx_enabled )
2603 usc_stop_transmitter(info);
2604 }
2605 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2606 return 0;
2607
2608}
2609
2610
2611
2612
2613
2614
2615static int mgsl_txabort(struct mgsl_struct * info)
2616{
2617 unsigned long flags;
2618
2619 if (debug_level >= DEBUG_LEVEL_INFO)
2620 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2621 info->device_name);
2622
2623 spin_lock_irqsave(&info->irq_spinlock,flags);
2624 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2625 {
2626 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2627 usc_loopmode_cancel_transmit( info );
2628 else
2629 usc_TCmd(info,TCmd_SendAbort);
2630 }
2631 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2632 return 0;
2633
2634}
2635
2636
2637
2638
2639
2640
2641
2642static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2643{
2644 unsigned long flags;
2645
2646 if (debug_level >= DEBUG_LEVEL_INFO)
2647 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2648 info->device_name, enable);
2649
2650 spin_lock_irqsave(&info->irq_spinlock,flags);
2651 if ( enable ) {
2652 if ( !info->rx_enabled )
2653 usc_start_receiver(info);
2654 } else {
2655 if ( info->rx_enabled )
2656 usc_stop_receiver(info);
2657 }
2658 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2659 return 0;
2660
2661}
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2672{
2673 unsigned long flags;
2674 int s;
2675 int rc=0;
2676 struct mgsl_icount cprev, cnow;
2677 int events;
2678 int mask;
2679 struct _input_signal_events oldsigs, newsigs;
2680 DECLARE_WAITQUEUE(wait, current);
2681
2682 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2683 if (rc) {
2684 return -EFAULT;
2685 }
2686
2687 if (debug_level >= DEBUG_LEVEL_INFO)
2688 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2689 info->device_name, mask);
2690
2691 spin_lock_irqsave(&info->irq_spinlock,flags);
2692
2693
2694 usc_get_serial_signals(info);
2695 s = info->serial_signals;
2696 events = mask &
2697 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2698 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2699 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2700 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2701 if (events) {
2702 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2703 goto exit;
2704 }
2705
2706
2707 cprev = info->icount;
2708 oldsigs = info->input_signal_events;
2709
2710
2711 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2712 u16 oldreg = usc_InReg(info,RICR);
2713 u16 newreg = oldreg +
2714 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2715 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2716 if (oldreg != newreg)
2717 usc_OutReg(info, RICR, newreg);
2718 }
2719
2720 set_current_state(TASK_INTERRUPTIBLE);
2721 add_wait_queue(&info->event_wait_q, &wait);
2722
2723 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2724
2725
2726 for(;;) {
2727 schedule();
2728 if (signal_pending(current)) {
2729 rc = -ERESTARTSYS;
2730 break;
2731 }
2732
2733
2734 spin_lock_irqsave(&info->irq_spinlock,flags);
2735 cnow = info->icount;
2736 newsigs = info->input_signal_events;
2737 set_current_state(TASK_INTERRUPTIBLE);
2738 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2739
2740
2741 if (newsigs.dsr_up == oldsigs.dsr_up &&
2742 newsigs.dsr_down == oldsigs.dsr_down &&
2743 newsigs.dcd_up == oldsigs.dcd_up &&
2744 newsigs.dcd_down == oldsigs.dcd_down &&
2745 newsigs.cts_up == oldsigs.cts_up &&
2746 newsigs.cts_down == oldsigs.cts_down &&
2747 newsigs.ri_up == oldsigs.ri_up &&
2748 newsigs.ri_down == oldsigs.ri_down &&
2749 cnow.exithunt == cprev.exithunt &&
2750 cnow.rxidle == cprev.rxidle) {
2751 rc = -EIO;
2752 break;
2753 }
2754
2755 events = mask &
2756 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2757 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2758 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2759 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2760 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2761 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2762 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2763 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2764 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2765 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2766 if (events)
2767 break;
2768
2769 cprev = cnow;
2770 oldsigs = newsigs;
2771 }
2772
2773 remove_wait_queue(&info->event_wait_q, &wait);
2774 set_current_state(TASK_RUNNING);
2775
2776 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2777 spin_lock_irqsave(&info->irq_spinlock,flags);
2778 if (!waitqueue_active(&info->event_wait_q)) {
2779
2780 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2781 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2782 }
2783 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2784 }
2785exit:
2786 if ( rc == 0 )
2787 PUT_USER(rc, events, mask_ptr);
2788
2789 return rc;
2790
2791}
2792
2793static int modem_input_wait(struct mgsl_struct *info,int arg)
2794{
2795 unsigned long flags;
2796 int rc;
2797 struct mgsl_icount cprev, cnow;
2798 DECLARE_WAITQUEUE(wait, current);
2799
2800
2801 spin_lock_irqsave(&info->irq_spinlock,flags);
2802 cprev = info->icount;
2803 add_wait_queue(&info->status_event_wait_q, &wait);
2804 set_current_state(TASK_INTERRUPTIBLE);
2805 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2806
2807 for(;;) {
2808 schedule();
2809 if (signal_pending(current)) {
2810 rc = -ERESTARTSYS;
2811 break;
2812 }
2813
2814
2815 spin_lock_irqsave(&info->irq_spinlock,flags);
2816 cnow = info->icount;
2817 set_current_state(TASK_INTERRUPTIBLE);
2818 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2819
2820
2821 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2822 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2823 rc = -EIO;
2824 break;
2825 }
2826
2827
2828 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2829 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2830 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2831 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2832 rc = 0;
2833 break;
2834 }
2835
2836 cprev = cnow;
2837 }
2838 remove_wait_queue(&info->status_event_wait_q, &wait);
2839 set_current_state(TASK_RUNNING);
2840 return rc;
2841}
2842
2843
2844
2845static int tiocmget(struct tty_struct *tty)
2846{
2847 struct mgsl_struct *info = tty->driver_data;
2848 unsigned int result;
2849 unsigned long flags;
2850
2851 spin_lock_irqsave(&info->irq_spinlock,flags);
2852 usc_get_serial_signals(info);
2853 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2854
2855 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2856 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2857 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2858 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2859 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2860 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2861
2862 if (debug_level >= DEBUG_LEVEL_INFO)
2863 printk("%s(%d):%s tiocmget() value=%08X\n",
2864 __FILE__,__LINE__, info->device_name, result );
2865 return result;
2866}
2867
2868
2869
2870static int tiocmset(struct tty_struct *tty,
2871 unsigned int set, unsigned int clear)
2872{
2873 struct mgsl_struct *info = tty->driver_data;
2874 unsigned long flags;
2875
2876 if (debug_level >= DEBUG_LEVEL_INFO)
2877 printk("%s(%d):%s tiocmset(%x,%x)\n",
2878 __FILE__,__LINE__,info->device_name, set, clear);
2879
2880 if (set & TIOCM_RTS)
2881 info->serial_signals |= SerialSignal_RTS;
2882 if (set & TIOCM_DTR)
2883 info->serial_signals |= SerialSignal_DTR;
2884 if (clear & TIOCM_RTS)
2885 info->serial_signals &= ~SerialSignal_RTS;
2886 if (clear & TIOCM_DTR)
2887 info->serial_signals &= ~SerialSignal_DTR;
2888
2889 spin_lock_irqsave(&info->irq_spinlock,flags);
2890 usc_set_serial_signals(info);
2891 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2892
2893 return 0;
2894}
2895
2896
2897
2898
2899
2900
2901
2902static int mgsl_break(struct tty_struct *tty, int break_state)
2903{
2904 struct mgsl_struct * info = tty->driver_data;
2905 unsigned long flags;
2906
2907 if (debug_level >= DEBUG_LEVEL_INFO)
2908 printk("%s(%d):mgsl_break(%s,%d)\n",
2909 __FILE__,__LINE__, info->device_name, break_state);
2910
2911 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2912 return -EINVAL;
2913
2914 spin_lock_irqsave(&info->irq_spinlock,flags);
2915 if (break_state == -1)
2916 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2917 else
2918 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2919 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2920 return 0;
2921
2922}
2923
2924
2925
2926
2927
2928
2929
2930static int msgl_get_icount(struct tty_struct *tty,
2931 struct serial_icounter_struct *icount)
2932
2933{
2934 struct mgsl_struct * info = tty->driver_data;
2935 struct mgsl_icount cnow;
2936 unsigned long flags;
2937
2938 spin_lock_irqsave(&info->irq_spinlock,flags);
2939 cnow = info->icount;
2940 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2941
2942 icount->cts = cnow.cts;
2943 icount->dsr = cnow.dsr;
2944 icount->rng = cnow.rng;
2945 icount->dcd = cnow.dcd;
2946 icount->rx = cnow.rx;
2947 icount->tx = cnow.tx;
2948 icount->frame = cnow.frame;
2949 icount->overrun = cnow.overrun;
2950 icount->parity = cnow.parity;
2951 icount->brk = cnow.brk;
2952 icount->buf_overrun = cnow.buf_overrun;
2953 return 0;
2954}
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966static int mgsl_ioctl(struct tty_struct *tty,
2967 unsigned int cmd, unsigned long arg)
2968{
2969 struct mgsl_struct * info = tty->driver_data;
2970
2971 if (debug_level >= DEBUG_LEVEL_INFO)
2972 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2973 info->device_name, cmd );
2974
2975 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2976 return -ENODEV;
2977
2978 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2979 (cmd != TIOCMIWAIT)) {
2980 if (tty->flags & (1 << TTY_IO_ERROR))
2981 return -EIO;
2982 }
2983
2984 return mgsl_ioctl_common(info, cmd, arg);
2985}
2986
2987static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2988{
2989 void __user *argp = (void __user *)arg;
2990
2991 switch (cmd) {
2992 case MGSL_IOCGPARAMS:
2993 return mgsl_get_params(info, argp);
2994 case MGSL_IOCSPARAMS:
2995 return mgsl_set_params(info, argp);
2996 case MGSL_IOCGTXIDLE:
2997 return mgsl_get_txidle(info, argp);
2998 case MGSL_IOCSTXIDLE:
2999 return mgsl_set_txidle(info,(int)arg);
3000 case MGSL_IOCTXENABLE:
3001 return mgsl_txenable(info,(int)arg);
3002 case MGSL_IOCRXENABLE:
3003 return mgsl_rxenable(info,(int)arg);
3004 case MGSL_IOCTXABORT:
3005 return mgsl_txabort(info);
3006 case MGSL_IOCGSTATS:
3007 return mgsl_get_stats(info, argp);
3008 case MGSL_IOCWAITEVENT:
3009 return mgsl_wait_event(info, argp);
3010 case MGSL_IOCLOOPTXDONE:
3011 return mgsl_loopmode_send_done(info);
3012
3013
3014
3015 case TIOCMIWAIT:
3016 return modem_input_wait(info,(int)arg);
3017
3018 default:
3019 return -ENOIOCTLCMD;
3020 }
3021 return 0;
3022}
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3036{
3037 struct mgsl_struct *info = tty->driver_data;
3038 unsigned long flags;
3039
3040 if (debug_level >= DEBUG_LEVEL_INFO)
3041 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3042 tty->driver->name );
3043
3044 mgsl_change_params(info);
3045
3046
3047 if (old_termios->c_cflag & CBAUD &&
3048 !(tty->termios.c_cflag & CBAUD)) {
3049 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3050 spin_lock_irqsave(&info->irq_spinlock,flags);
3051 usc_set_serial_signals(info);
3052 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3053 }
3054
3055
3056 if (!(old_termios->c_cflag & CBAUD) &&
3057 tty->termios.c_cflag & CBAUD) {
3058 info->serial_signals |= SerialSignal_DTR;
3059 if (!(tty->termios.c_cflag & CRTSCTS) ||
3060 !test_bit(TTY_THROTTLED, &tty->flags)) {
3061 info->serial_signals |= SerialSignal_RTS;
3062 }
3063 spin_lock_irqsave(&info->irq_spinlock,flags);
3064 usc_set_serial_signals(info);
3065 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3066 }
3067
3068
3069 if (old_termios->c_cflag & CRTSCTS &&
3070 !(tty->termios.c_cflag & CRTSCTS)) {
3071 tty->hw_stopped = 0;
3072 mgsl_start(tty);
3073 }
3074
3075}
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089static void mgsl_close(struct tty_struct *tty, struct file * filp)
3090{
3091 struct mgsl_struct * info = tty->driver_data;
3092
3093 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3094 return;
3095
3096 if (debug_level >= DEBUG_LEVEL_INFO)
3097 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3098 __FILE__,__LINE__, info->device_name, info->port.count);
3099
3100 if (tty_port_close_start(&info->port, tty, filp) == 0)
3101 goto cleanup;
3102
3103 mutex_lock(&info->port.mutex);
3104 if (info->port.flags & ASYNC_INITIALIZED)
3105 mgsl_wait_until_sent(tty, info->timeout);
3106 mgsl_flush_buffer(tty);
3107 tty_ldisc_flush(tty);
3108 shutdown(info);
3109 mutex_unlock(&info->port.mutex);
3110
3111 tty_port_close_end(&info->port, tty);
3112 info->port.tty = NULL;
3113cleanup:
3114 if (debug_level >= DEBUG_LEVEL_INFO)
3115 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3116 tty->driver->name, info->port.count);
3117
3118}
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3132{
3133 struct mgsl_struct * info = tty->driver_data;
3134 unsigned long orig_jiffies, char_time;
3135
3136 if (!info )
3137 return;
3138
3139 if (debug_level >= DEBUG_LEVEL_INFO)
3140 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3141 __FILE__,__LINE__, info->device_name );
3142
3143 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3144 return;
3145
3146 if (!(info->port.flags & ASYNC_INITIALIZED))
3147 goto exit;
3148
3149 orig_jiffies = jiffies;
3150
3151
3152
3153
3154
3155
3156
3157 if ( info->params.data_rate ) {
3158 char_time = info->timeout/(32 * 5);
3159 if (!char_time)
3160 char_time++;
3161 } else
3162 char_time = 1;
3163
3164 if (timeout)
3165 char_time = min_t(unsigned long, char_time, timeout);
3166
3167 if ( info->params.mode == MGSL_MODE_HDLC ||
3168 info->params.mode == MGSL_MODE_RAW ) {
3169 while (info->tx_active) {
3170 msleep_interruptible(jiffies_to_msecs(char_time));
3171 if (signal_pending(current))
3172 break;
3173 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3174 break;
3175 }
3176 } else {
3177 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3178 info->tx_enabled) {
3179 msleep_interruptible(jiffies_to_msecs(char_time));
3180 if (signal_pending(current))
3181 break;
3182 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3183 break;
3184 }
3185 }
3186
3187exit:
3188 if (debug_level >= DEBUG_LEVEL_INFO)
3189 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3190 __FILE__,__LINE__, info->device_name );
3191
3192}
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202static void mgsl_hangup(struct tty_struct *tty)
3203{
3204 struct mgsl_struct * info = tty->driver_data;
3205
3206 if (debug_level >= DEBUG_LEVEL_INFO)
3207 printk("%s(%d):mgsl_hangup(%s)\n",
3208 __FILE__,__LINE__, info->device_name );
3209
3210 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3211 return;
3212
3213 mgsl_flush_buffer(tty);
3214 shutdown(info);
3215
3216 info->port.count = 0;
3217 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3218 info->port.tty = NULL;
3219
3220 wake_up_interruptible(&info->port.open_wait);
3221
3222}
3223
3224
3225
3226
3227
3228
3229
3230static int carrier_raised(struct tty_port *port)
3231{
3232 unsigned long flags;
3233 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3234
3235 spin_lock_irqsave(&info->irq_spinlock, flags);
3236 usc_get_serial_signals(info);
3237 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3238 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3239}
3240
3241static void dtr_rts(struct tty_port *port, int on)
3242{
3243 struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3244 unsigned long flags;
3245
3246 spin_lock_irqsave(&info->irq_spinlock,flags);
3247 if (on)
3248 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3249 else
3250 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3251 usc_set_serial_signals(info);
3252 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3253}
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269static int block_til_ready(struct tty_struct *tty, struct file * filp,
3270 struct mgsl_struct *info)
3271{
3272 DECLARE_WAITQUEUE(wait, current);
3273 int retval;
3274 bool do_clocal = false;
3275 bool extra_count = false;
3276 unsigned long flags;
3277 int dcd;
3278 struct tty_port *port = &info->port;
3279
3280 if (debug_level >= DEBUG_LEVEL_INFO)
3281 printk("%s(%d):block_til_ready on %s\n",
3282 __FILE__,__LINE__, tty->driver->name );
3283
3284 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3285
3286 port->flags |= ASYNC_NORMAL_ACTIVE;
3287 return 0;
3288 }
3289
3290 if (tty->termios.c_cflag & CLOCAL)
3291 do_clocal = true;
3292
3293
3294
3295
3296
3297
3298
3299
3300 retval = 0;
3301 add_wait_queue(&port->open_wait, &wait);
3302
3303 if (debug_level >= DEBUG_LEVEL_INFO)
3304 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3305 __FILE__,__LINE__, tty->driver->name, port->count );
3306
3307 spin_lock_irqsave(&info->irq_spinlock, flags);
3308 if (!tty_hung_up_p(filp)) {
3309 extra_count = true;
3310 port->count--;
3311 }
3312 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3313 port->blocked_open++;
3314
3315 while (1) {
3316 if (tty->termios.c_cflag & CBAUD)
3317 tty_port_raise_dtr_rts(port);
3318
3319 set_current_state(TASK_INTERRUPTIBLE);
3320
3321 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3322 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3323 -EAGAIN : -ERESTARTSYS;
3324 break;
3325 }
3326
3327 dcd = tty_port_carrier_raised(&info->port);
3328
3329 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || dcd))
3330 break;
3331
3332 if (signal_pending(current)) {
3333 retval = -ERESTARTSYS;
3334 break;
3335 }
3336
3337 if (debug_level >= DEBUG_LEVEL_INFO)
3338 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3339 __FILE__,__LINE__, tty->driver->name, port->count );
3340
3341 tty_unlock(tty);
3342 schedule();
3343 tty_lock(tty);
3344 }
3345
3346 set_current_state(TASK_RUNNING);
3347 remove_wait_queue(&port->open_wait, &wait);
3348
3349
3350 if (extra_count)
3351 port->count++;
3352 port->blocked_open--;
3353
3354 if (debug_level >= DEBUG_LEVEL_INFO)
3355 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3356 __FILE__,__LINE__, tty->driver->name, port->count );
3357
3358 if (!retval)
3359 port->flags |= ASYNC_NORMAL_ACTIVE;
3360
3361 return retval;
3362
3363}
3364
3365static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3366{
3367 struct mgsl_struct *info;
3368 int line = tty->index;
3369
3370
3371 if (line >= mgsl_device_count) {
3372 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3373 __FILE__, __LINE__, line);
3374 return -ENODEV;
3375 }
3376
3377
3378 info = mgsl_device_list;
3379 while (info && info->line != line)
3380 info = info->next_device;
3381 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3382 return -ENODEV;
3383 tty->driver_data = info;
3384
3385 return tty_port_install(&info->port, driver, tty);
3386}
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398static int mgsl_open(struct tty_struct *tty, struct file * filp)
3399{
3400 struct mgsl_struct *info = tty->driver_data;
3401 unsigned long flags;
3402 int retval;
3403
3404 info->port.tty = tty;
3405
3406 if (debug_level >= DEBUG_LEVEL_INFO)
3407 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3408 __FILE__,__LINE__,tty->driver->name, info->port.count);
3409
3410
3411 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
3412 if (info->port.flags & ASYNC_CLOSING)
3413 interruptible_sleep_on(&info->port.close_wait);
3414 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
3415 -EAGAIN : -ERESTARTSYS);
3416 goto cleanup;
3417 }
3418
3419 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3420
3421 spin_lock_irqsave(&info->netlock, flags);
3422 if (info->netcount) {
3423 retval = -EBUSY;
3424 spin_unlock_irqrestore(&info->netlock, flags);
3425 goto cleanup;
3426 }
3427 info->port.count++;
3428 spin_unlock_irqrestore(&info->netlock, flags);
3429
3430 if (info->port.count == 1) {
3431
3432 retval = startup(info);
3433 if (retval < 0)
3434 goto cleanup;
3435 }
3436
3437 retval = block_til_ready(tty, filp, info);
3438 if (retval) {
3439 if (debug_level >= DEBUG_LEVEL_INFO)
3440 printk("%s(%d):block_til_ready(%s) returned %d\n",
3441 __FILE__,__LINE__, info->device_name, retval);
3442 goto cleanup;
3443 }
3444
3445 if (debug_level >= DEBUG_LEVEL_INFO)
3446 printk("%s(%d):mgsl_open(%s) success\n",
3447 __FILE__,__LINE__, info->device_name);
3448 retval = 0;
3449
3450cleanup:
3451 if (retval) {
3452 if (tty->count == 1)
3453 info->port.tty = NULL;
3454 if(info->port.count)
3455 info->port.count--;
3456 }
3457
3458 return retval;
3459
3460}
3461
3462
3463
3464
3465
3466static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3467{
3468 char stat_buf[30];
3469 unsigned long flags;
3470
3471 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3472 seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3473 info->device_name, info->io_base, info->irq_level,
3474 info->phys_memory_base, info->phys_lcr_base);
3475 } else {
3476 seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3477 info->device_name, info->io_base,
3478 info->irq_level, info->dma_level);
3479 }
3480
3481
3482 spin_lock_irqsave(&info->irq_spinlock,flags);
3483 usc_get_serial_signals(info);
3484 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3485
3486 stat_buf[0] = 0;
3487 stat_buf[1] = 0;
3488 if (info->serial_signals & SerialSignal_RTS)
3489 strcat(stat_buf, "|RTS");
3490 if (info->serial_signals & SerialSignal_CTS)
3491 strcat(stat_buf, "|CTS");
3492 if (info->serial_signals & SerialSignal_DTR)
3493 strcat(stat_buf, "|DTR");
3494 if (info->serial_signals & SerialSignal_DSR)
3495 strcat(stat_buf, "|DSR");
3496 if (info->serial_signals & SerialSignal_DCD)
3497 strcat(stat_buf, "|CD");
3498 if (info->serial_signals & SerialSignal_RI)
3499 strcat(stat_buf, "|RI");
3500
3501 if (info->params.mode == MGSL_MODE_HDLC ||
3502 info->params.mode == MGSL_MODE_RAW ) {
3503 seq_printf(m, " HDLC txok:%d rxok:%d",
3504 info->icount.txok, info->icount.rxok);
3505 if (info->icount.txunder)
3506 seq_printf(m, " txunder:%d", info->icount.txunder);
3507 if (info->icount.txabort)
3508 seq_printf(m, " txabort:%d", info->icount.txabort);
3509 if (info->icount.rxshort)
3510 seq_printf(m, " rxshort:%d", info->icount.rxshort);
3511 if (info->icount.rxlong)
3512 seq_printf(m, " rxlong:%d", info->icount.rxlong);
3513 if (info->icount.rxover)
3514 seq_printf(m, " rxover:%d", info->icount.rxover);
3515 if (info->icount.rxcrc)
3516 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3517 } else {
3518 seq_printf(m, " ASYNC tx:%d rx:%d",
3519 info->icount.tx, info->icount.rx);
3520 if (info->icount.frame)
3521 seq_printf(m, " fe:%d", info->icount.frame);
3522 if (info->icount.parity)
3523 seq_printf(m, " pe:%d", info->icount.parity);
3524 if (info->icount.brk)
3525 seq_printf(m, " brk:%d", info->icount.brk);
3526 if (info->icount.overrun)
3527 seq_printf(m, " oe:%d", info->icount.overrun);
3528 }
3529
3530
3531 seq_printf(m, " %s\n", stat_buf+1);
3532
3533 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3534 info->tx_active,info->bh_requested,info->bh_running,
3535 info->pending_bh);
3536
3537 spin_lock_irqsave(&info->irq_spinlock,flags);
3538 {
3539 u16 Tcsr = usc_InReg( info, TCSR );
3540 u16 Tdmr = usc_InDmaReg( info, TDMR );
3541 u16 Ticr = usc_InReg( info, TICR );
3542 u16 Rscr = usc_InReg( info, RCSR );
3543 u16 Rdmr = usc_InDmaReg( info, RDMR );
3544 u16 Ricr = usc_InReg( info, RICR );
3545 u16 Icr = usc_InReg( info, ICR );
3546 u16 Dccr = usc_InReg( info, DCCR );
3547 u16 Tmr = usc_InReg( info, TMR );
3548 u16 Tccr = usc_InReg( info, TCCR );
3549 u16 Ccar = inw( info->io_base + CCAR );
3550 seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3551 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3552 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3553 }
3554 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3555}
3556
3557
3558static int mgsl_proc_show(struct seq_file *m, void *v)
3559{
3560 struct mgsl_struct *info;
3561
3562 seq_printf(m, "synclink driver:%s\n", driver_version);
3563
3564 info = mgsl_device_list;
3565 while( info ) {
3566 line_info(m, info);
3567 info = info->next_device;
3568 }
3569 return 0;
3570}
3571
3572static int mgsl_proc_open(struct inode *inode, struct file *file)
3573{
3574 return single_open(file, mgsl_proc_show, NULL);
3575}
3576
3577static const struct file_operations mgsl_proc_fops = {
3578 .owner = THIS_MODULE,
3579 .open = mgsl_proc_open,
3580 .read = seq_read,
3581 .llseek = seq_lseek,
3582 .release = single_release,
3583};
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3594{
3595 unsigned short BuffersPerFrame;
3596
3597 info->last_mem_alloc = 0;
3598
3599
3600
3601
3602
3603
3604 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3605 if ( info->max_frame_size % DMABUFFERSIZE )
3606 BuffersPerFrame++;
3607
3608 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3632 info->rx_buffer_count = 62 - info->tx_buffer_count;
3633 } else {
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3645 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3646
3647
3648
3649
3650
3651
3652 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3653 info->rx_buffer_count = 62 - info->tx_buffer_count;
3654
3655 }
3656
3657 if ( debug_level >= DEBUG_LEVEL_INFO )
3658 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3659 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3660
3661 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3662 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3663 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3664 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3665 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3666 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3667 return -ENOMEM;
3668 }
3669
3670 mgsl_reset_rx_dma_buffers( info );
3671 mgsl_reset_tx_dma_buffers( info );
3672
3673 return 0;
3674
3675}
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3701{
3702 unsigned int i;
3703
3704 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3705
3706 info->buffer_list = info->memory_base + info->last_mem_alloc;
3707 info->buffer_list_phys = info->last_mem_alloc;
3708 info->last_mem_alloc += BUFFERLISTSIZE;
3709 } else {
3710
3711
3712
3713
3714
3715
3716 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3717 if (info->buffer_list == NULL)
3718 return -ENOMEM;
3719 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3720 }
3721
3722
3723
3724 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3725
3726
3727
3728
3729 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3730 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3731 info->tx_buffer_list += info->rx_buffer_count;
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3743
3744 info->rx_buffer_list[i].phys_entry =
3745 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3746
3747
3748
3749
3750 info->rx_buffer_list[i].link = info->buffer_list_phys;
3751
3752 if ( i < info->rx_buffer_count - 1 )
3753 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3754 }
3755
3756 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3757
3758 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3759 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3760
3761
3762
3763
3764 info->tx_buffer_list[i].link = info->buffer_list_phys +
3765 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3766
3767 if ( i < info->tx_buffer_count - 1 )
3768 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3769 }
3770
3771 return 0;
3772
3773}
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3785{
3786 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3787 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3788
3789 info->buffer_list = NULL;
3790 info->rx_buffer_list = NULL;
3791 info->tx_buffer_list = NULL;
3792
3793}
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3812{
3813 int i;
3814 u32 phys_addr;
3815
3816
3817
3818 for ( i = 0; i < Buffercount; i++ ) {
3819 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3820
3821 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3822 phys_addr = info->last_mem_alloc;
3823 info->last_mem_alloc += DMABUFFERSIZE;
3824 } else {
3825
3826 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3827 if (BufferList[i].virt_addr == NULL)
3828 return -ENOMEM;
3829 phys_addr = (u32)(BufferList[i].dma_addr);
3830 }
3831 BufferList[i].phys_addr = phys_addr;
3832 }
3833
3834 return 0;
3835
3836}
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3853{
3854 int i;
3855
3856 if ( BufferList ) {
3857 for ( i = 0 ; i < Buffercount ; i++ ) {
3858 if ( BufferList[i].virt_addr ) {
3859 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3860 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3861 BufferList[i].virt_addr = NULL;
3862 }
3863 }
3864 }
3865
3866}
3867
3868
3869
3870
3871
3872
3873
3874
3875static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3876{
3877 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3878 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3879 mgsl_free_buffer_list_memory( info );
3880
3881}
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3897{
3898 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3899 if ( info->intermediate_rxbuffer == NULL )
3900 return -ENOMEM;
3901
3902 return 0;
3903
3904}
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3917{
3918 kfree(info->intermediate_rxbuffer);
3919 info->intermediate_rxbuffer = NULL;
3920
3921}
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3937{
3938 int i;
3939
3940 if ( debug_level >= DEBUG_LEVEL_INFO )
3941 printk("%s %s(%d) allocating %d tx holding buffers\n",
3942 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3943
3944 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3945
3946 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3947 info->tx_holding_buffers[i].buffer =
3948 kmalloc(info->max_frame_size, GFP_KERNEL);
3949 if (info->tx_holding_buffers[i].buffer == NULL) {
3950 for (--i; i >= 0; i--) {
3951 kfree(info->tx_holding_buffers[i].buffer);
3952 info->tx_holding_buffers[i].buffer = NULL;
3953 }
3954 return -ENOMEM;
3955 }
3956 }
3957
3958 return 0;
3959
3960}
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3973{
3974 int i;
3975
3976 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3977 kfree(info->tx_holding_buffers[i].buffer);
3978 info->tx_holding_buffers[i].buffer = NULL;
3979 }
3980
3981 info->get_tx_holding_index = 0;
3982 info->put_tx_holding_index = 0;
3983 info->tx_holding_count = 0;
3984
3985}
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
4003{
4004 bool ret = false;
4005
4006 if ( info->tx_holding_count ) {
4007
4008
4009
4010 struct tx_holding_buffer *ptx =
4011 &info->tx_holding_buffers[info->get_tx_holding_index];
4012 int num_free = num_free_tx_dma_buffers(info);
4013 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4014 if ( ptx->buffer_size % DMABUFFERSIZE )
4015 ++num_needed;
4016
4017 if (num_needed <= num_free) {
4018 info->xmit_cnt = ptx->buffer_size;
4019 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4020
4021 --info->tx_holding_count;
4022 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4023 info->get_tx_holding_index=0;
4024
4025
4026 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4027
4028 ret = true;
4029 }
4030 }
4031
4032 return ret;
4033}
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4049{
4050 struct tx_holding_buffer *ptx;
4051
4052 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4053 return 0;
4054 }
4055
4056 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4057 ptx->buffer_size = BufferSize;
4058 memcpy( ptx->buffer, Buffer, BufferSize);
4059
4060 ++info->tx_holding_count;
4061 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4062 info->put_tx_holding_index=0;
4063
4064 return 1;
4065}
4066
4067static int mgsl_claim_resources(struct mgsl_struct *info)
4068{
4069 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4070 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4071 __FILE__,__LINE__,info->device_name, info->io_base);
4072 return -ENODEV;
4073 }
4074 info->io_addr_requested = true;
4075
4076 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4077 info->device_name, info ) < 0 ) {
4078 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4079 __FILE__,__LINE__,info->device_name, info->irq_level );
4080 goto errout;
4081 }
4082 info->irq_requested = true;
4083
4084 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4085 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4086 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4087 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4088 goto errout;
4089 }
4090 info->shared_mem_requested = true;
4091 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4092 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4093 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4094 goto errout;
4095 }
4096 info->lcr_mem_requested = true;
4097
4098 info->memory_base = ioremap_nocache(info->phys_memory_base,
4099 0x40000);
4100 if (!info->memory_base) {
4101 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4102 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4103 goto errout;
4104 }
4105
4106 if ( !mgsl_memory_test(info) ) {
4107 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4108 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4109 goto errout;
4110 }
4111
4112 info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4113 PAGE_SIZE);
4114 if (!info->lcr_base) {
4115 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4116 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4117 goto errout;
4118 }
4119 info->lcr_base += info->lcr_offset;
4120
4121 } else {
4122
4123
4124 if (request_dma(info->dma_level,info->device_name) < 0){
4125 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4126 __FILE__,__LINE__,info->device_name, info->dma_level );
4127 mgsl_release_resources( info );
4128 return -ENODEV;
4129 }
4130 info->dma_requested = true;
4131
4132
4133 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4134 enable_dma(info->dma_level);
4135 }
4136
4137 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4138 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4139 __FILE__,__LINE__,info->device_name, info->dma_level );
4140 goto errout;
4141 }
4142
4143 return 0;
4144errout:
4145 mgsl_release_resources(info);
4146 return -ENODEV;
4147
4148}
4149
4150static void mgsl_release_resources(struct mgsl_struct *info)
4151{
4152 if ( debug_level >= DEBUG_LEVEL_INFO )
4153 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4154 __FILE__,__LINE__,info->device_name );
4155
4156 if ( info->irq_requested ) {
4157 free_irq(info->irq_level, info);
4158 info->irq_requested = false;
4159 }
4160 if ( info->dma_requested ) {
4161 disable_dma(info->dma_level);
4162 free_dma(info->dma_level);
4163 info->dma_requested = false;
4164 }
4165 mgsl_free_dma_buffers(info);
4166 mgsl_free_intermediate_rxbuffer_memory(info);
4167 mgsl_free_intermediate_txbuffer_memory(info);
4168
4169 if ( info->io_addr_requested ) {
4170 release_region(info->io_base,info->io_addr_size);
4171 info->io_addr_requested = false;
4172 }
4173 if ( info->shared_mem_requested ) {
4174 release_mem_region(info->phys_memory_base,0x40000);
4175 info->shared_mem_requested = false;
4176 }
4177 if ( info->lcr_mem_requested ) {
4178 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4179 info->lcr_mem_requested = false;
4180 }
4181 if (info->memory_base){
4182 iounmap(info->memory_base);
4183 info->memory_base = NULL;
4184 }
4185 if (info->lcr_base){
4186 iounmap(info->lcr_base - info->lcr_offset);
4187 info->lcr_base = NULL;
4188 }
4189
4190 if ( debug_level >= DEBUG_LEVEL_INFO )
4191 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4192 __FILE__,__LINE__,info->device_name );
4193
4194}
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204static void mgsl_add_device( struct mgsl_struct *info )
4205{
4206 info->next_device = NULL;
4207 info->line = mgsl_device_count;
4208 sprintf(info->device_name,"ttySL%d",info->line);
4209
4210 if (info->line < MAX_TOTAL_DEVICES) {
4211 if (maxframe[info->line])
4212 info->max_frame_size = maxframe[info->line];
4213
4214 if (txdmabufs[info->line]) {
4215 info->num_tx_dma_buffers = txdmabufs[info->line];
4216 if (info->num_tx_dma_buffers < 1)
4217 info->num_tx_dma_buffers = 1;
4218 }
4219
4220 if (txholdbufs[info->line]) {
4221 info->num_tx_holding_buffers = txholdbufs[info->line];
4222 if (info->num_tx_holding_buffers < 1)
4223 info->num_tx_holding_buffers = 1;
4224 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4225 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4226 }
4227 }
4228
4229 mgsl_device_count++;
4230
4231 if ( !mgsl_device_list )
4232 mgsl_device_list = info;
4233 else {
4234 struct mgsl_struct *current_dev = mgsl_device_list;
4235 while( current_dev->next_device )
4236 current_dev = current_dev->next_device;
4237 current_dev->next_device = info;
4238 }
4239
4240 if ( info->max_frame_size < 4096 )
4241 info->max_frame_size = 4096;
4242 else if ( info->max_frame_size > 65535 )
4243 info->max_frame_size = 65535;
4244
4245 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4246 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4247 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4248 info->phys_memory_base, info->phys_lcr_base,
4249 info->max_frame_size );
4250 } else {
4251 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4252 info->device_name, info->io_base, info->irq_level, info->dma_level,
4253 info->max_frame_size );
4254 }
4255
4256#if SYNCLINK_GENERIC_HDLC
4257 hdlcdev_init(info);
4258#endif
4259
4260}
4261
4262static const struct tty_port_operations mgsl_port_ops = {
4263 .carrier_raised = carrier_raised,
4264 .dtr_rts = dtr_rts,
4265};
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275static struct mgsl_struct* mgsl_allocate_device(void)
4276{
4277 struct mgsl_struct *info;
4278
4279 info = kzalloc(sizeof(struct mgsl_struct),
4280 GFP_KERNEL);
4281
4282 if (!info) {
4283 printk("Error can't allocate device instance data\n");
4284 } else {
4285 tty_port_init(&info->port);
4286 info->port.ops = &mgsl_port_ops;
4287 info->magic = MGSL_MAGIC;
4288 INIT_WORK(&info->task, mgsl_bh_handler);
4289 info->max_frame_size = 4096;
4290 info->port.close_delay = 5*HZ/10;
4291 info->port.closing_wait = 30*HZ;
4292 init_waitqueue_head(&info->status_event_wait_q);
4293 init_waitqueue_head(&info->event_wait_q);
4294 spin_lock_init(&info->irq_spinlock);
4295 spin_lock_init(&info->netlock);
4296 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4297 info->idle_mode = HDLC_TXIDLE_FLAGS;
4298 info->num_tx_dma_buffers = 1;
4299 info->num_tx_holding_buffers = 0;
4300 }
4301
4302 return info;
4303
4304}
4305
4306static const struct tty_operations mgsl_ops = {
4307 .install = mgsl_install,
4308 .open = mgsl_open,
4309 .close = mgsl_close,
4310 .write = mgsl_write,
4311 .put_char = mgsl_put_char,
4312 .flush_chars = mgsl_flush_chars,
4313 .write_room = mgsl_write_room,
4314 .chars_in_buffer = mgsl_chars_in_buffer,
4315 .flush_buffer = mgsl_flush_buffer,
4316 .ioctl = mgsl_ioctl,
4317 .throttle = mgsl_throttle,
4318 .unthrottle = mgsl_unthrottle,
4319 .send_xchar = mgsl_send_xchar,
4320 .break_ctl = mgsl_break,
4321 .wait_until_sent = mgsl_wait_until_sent,
4322 .set_termios = mgsl_set_termios,
4323 .stop = mgsl_stop,
4324 .start = mgsl_start,
4325 .hangup = mgsl_hangup,
4326 .tiocmget = tiocmget,
4327 .tiocmset = tiocmset,
4328 .get_icount = msgl_get_icount,
4329 .proc_fops = &mgsl_proc_fops,
4330};
4331
4332
4333
4334
4335static int mgsl_init_tty(void)
4336{
4337 int rc;
4338
4339 serial_driver = alloc_tty_driver(128);
4340 if (!serial_driver)
4341 return -ENOMEM;
4342
4343 serial_driver->driver_name = "synclink";
4344 serial_driver->name = "ttySL";
4345 serial_driver->major = ttymajor;
4346 serial_driver->minor_start = 64;
4347 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4348 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4349 serial_driver->init_termios = tty_std_termios;
4350 serial_driver->init_termios.c_cflag =
4351 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4352 serial_driver->init_termios.c_ispeed = 9600;
4353 serial_driver->init_termios.c_ospeed = 9600;
4354 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4355 tty_set_operations(serial_driver, &mgsl_ops);
4356 if ((rc = tty_register_driver(serial_driver)) < 0) {
4357 printk("%s(%d):Couldn't register serial driver\n",
4358 __FILE__,__LINE__);
4359 put_tty_driver(serial_driver);
4360 serial_driver = NULL;
4361 return rc;
4362 }
4363
4364 printk("%s %s, tty major#%d\n",
4365 driver_name, driver_version,
4366 serial_driver->major);
4367 return 0;
4368}
4369
4370
4371
4372static void mgsl_enum_isa_devices(void)
4373{
4374 struct mgsl_struct *info;
4375 int i;
4376
4377
4378
4379 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4380 if ( debug_level >= DEBUG_LEVEL_INFO )
4381 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4382 io[i], irq[i], dma[i] );
4383
4384 info = mgsl_allocate_device();
4385 if ( !info ) {
4386
4387 if ( debug_level >= DEBUG_LEVEL_ERROR )
4388 printk( "can't allocate device instance data.\n");
4389 continue;
4390 }
4391
4392
4393 info->io_base = (unsigned int)io[i];
4394 info->irq_level = (unsigned int)irq[i];
4395 info->irq_level = irq_canonicalize(info->irq_level);
4396 info->dma_level = (unsigned int)dma[i];
4397 info->bus_type = MGSL_BUS_TYPE_ISA;
4398 info->io_addr_size = 16;
4399 info->irq_flags = 0;
4400
4401 mgsl_add_device( info );
4402 }
4403}
4404
4405static void synclink_cleanup(void)
4406{
4407 int rc;
4408 struct mgsl_struct *info;
4409 struct mgsl_struct *tmp;
4410
4411 printk("Unloading %s: %s\n", driver_name, driver_version);
4412
4413 if (serial_driver) {
4414 if ((rc = tty_unregister_driver(serial_driver)))
4415 printk("%s(%d) failed to unregister tty driver err=%d\n",
4416 __FILE__,__LINE__,rc);
4417 put_tty_driver(serial_driver);
4418 }
4419
4420 info = mgsl_device_list;
4421 while(info) {
4422#if SYNCLINK_GENERIC_HDLC
4423 hdlcdev_exit(info);
4424#endif
4425 mgsl_release_resources(info);
4426 tmp = info;
4427 info = info->next_device;
4428 tty_port_destroy(&tmp->port);
4429 kfree(tmp);
4430 }
4431
4432 if (pci_registered)
4433 pci_unregister_driver(&synclink_pci_driver);
4434}
4435
4436static int __init synclink_init(void)
4437{
4438 int rc;
4439
4440 if (break_on_load) {
4441 mgsl_get_text_ptr();
4442 BREAKPOINT();
4443 }
4444
4445 printk("%s %s\n", driver_name, driver_version);
4446
4447 mgsl_enum_isa_devices();
4448 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4449 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4450 else
4451 pci_registered = true;
4452
4453 if ((rc = mgsl_init_tty()) < 0)
4454 goto error;
4455
4456 return 0;
4457
4458error:
4459 synclink_cleanup();
4460 return rc;
4461}
4462
4463static void __exit synclink_exit(void)
4464{
4465 synclink_cleanup();
4466}
4467
4468module_init(synclink_init);
4469module_exit(synclink_exit);
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4493{
4494
4495
4496
4497 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4498
4499
4500 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4501 inw( info->io_base + CCAR );
4502
4503}
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4520{
4521
4522 outw( Cmd + info->mbre_bit, info->io_base );
4523
4524
4525 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4526 inw( info->io_base );
4527
4528}
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4547{
4548
4549
4550
4551 outw( RegAddr + info->mbre_bit, info->io_base );
4552 outw( RegValue, info->io_base );
4553
4554
4555 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4556 inw( info->io_base );
4557
4558}
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4576{
4577
4578
4579
4580 outw( RegAddr + info->mbre_bit, info->io_base );
4581 return inw( info->io_base );
4582
4583}
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4603{
4604 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4605 outw( RegValue, info->io_base + CCAR );
4606
4607
4608 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4609 inw( info->io_base + CCAR );
4610
4611}
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4628{
4629 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4630 return inw( info->io_base + CCAR );
4631
4632}
4633
4634
4635
4636
4637
4638
4639
4640
4641static void usc_set_sdlc_mode( struct mgsl_struct *info )
4642{
4643 u16 RegValue;
4644 bool PreSL1660;
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655 usc_OutReg(info,TMCR,0x1f);
4656 RegValue=usc_InReg(info,TMDR);
4657 PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4658
4659 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4660 {
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673 RegValue = 0x8e06;
4674
4675
4676
4677
4678
4679 }
4680 else
4681 {
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693 if (info->params.mode == MGSL_MODE_RAW) {
4694 RegValue = 0x0001;
4695
4696 usc_OutReg( info, IOCR,
4697 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711 RegValue |= 0x0400;
4712 }
4713 else {
4714
4715 RegValue = 0x0606;
4716
4717 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4718 RegValue |= BIT14;
4719 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4720 RegValue |= BIT15;
4721 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4722 RegValue |= BIT15 + BIT14;
4723 }
4724
4725 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4726 RegValue |= BIT13;
4727 }
4728
4729 if ( info->params.mode == MGSL_MODE_HDLC &&
4730 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4731 RegValue |= BIT12;
4732
4733 if ( info->params.addr_filter != 0xff )
4734 {
4735
4736 usc_OutReg( info, RSR, info->params.addr_filter );
4737 RegValue |= BIT4;
4738 }
4739
4740 usc_OutReg( info, CMR, RegValue );
4741 info->cmr_value = RegValue;
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758 RegValue = 0x0500;
4759
4760 switch ( info->params.encoding ) {
4761 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4762 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4763 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4764 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4765 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4766 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4767 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4768 }
4769
4770 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4771 RegValue |= BIT9;
4772 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4773 RegValue |= ( BIT12 | BIT10 | BIT9 );
4774
4775 usc_OutReg( info, RMR, RegValue );
4776
4777
4778
4779
4780
4781
4782
4783
4784 usc_OutReg( info, RCLR, RCLRVALUE );
4785
4786 usc_RCmd( info, RCmd_SelectRicrdma_level );
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806 RegValue = usc_InReg( info, RICR ) & 0xc0;
4807
4808 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4809 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4810 else
4811 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4812
4813
4814
4815 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4816 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833 RegValue = 0x0400;
4834
4835 switch ( info->params.encoding ) {
4836 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4837 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4838 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4839 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4840 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4841 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4842 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4843 }
4844
4845 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4846 RegValue |= BIT9 + BIT8;
4847 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4848 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4849
4850 usc_OutReg( info, TMR, RegValue );
4851
4852 usc_set_txidle( info );
4853
4854
4855 usc_TCmd( info, TCmd_SelectTicrdma_level );
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4873 usc_OutReg( info, TICR, 0x0736 );
4874 else
4875 usc_OutReg( info, TICR, 0x1436 );
4876
4877 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4878 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897 info->tcsr_value = 0;
4898
4899 if ( !PreSL1660 )
4900 info->tcsr_value |= TCSR_UNDERWAIT;
4901
4902 usc_OutReg( info, TCSR, info->tcsr_value );
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917 RegValue = 0x0f40;
4918
4919 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4920 RegValue |= 0x0003;
4921 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4922 RegValue |= 0x0004;
4923 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4924 RegValue |= 0x0006;
4925 else
4926 RegValue |= 0x0007;
4927
4928 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4929 RegValue |= 0x0018;
4930 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4931 RegValue |= 0x0020;
4932 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4933 RegValue |= 0x0038;
4934 else
4935 RegValue |= 0x0030;
4936
4937 usc_OutReg( info, CMCR, RegValue );
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955 RegValue = 0x0000;
4956
4957 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4958 u32 XtalSpeed;
4959 u32 DpllDivisor;
4960 u16 Tc;
4961
4962
4963
4964
4965 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4966 XtalSpeed = 11059200;
4967 else
4968 XtalSpeed = 14745600;
4969
4970 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4971 DpllDivisor = 16;
4972 RegValue |= BIT10;
4973 }
4974 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4975 DpllDivisor = 8;
4976 RegValue |= BIT11;
4977 }
4978 else
4979 DpllDivisor = 32;
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995 if ( info->params.clock_speed )
4996 {
4997 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4998 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4999 / info->params.clock_speed) )
5000 Tc--;
5001 }
5002 else
5003 Tc = -1;
5004
5005
5006
5007 usc_OutReg( info, TC1R, Tc );
5008
5009 RegValue |= BIT4;
5010
5011 switch ( info->params.encoding ) {
5012 case HDLC_ENCODING_NRZ:
5013 case HDLC_ENCODING_NRZB:
5014 case HDLC_ENCODING_NRZI_MARK:
5015 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5016 case HDLC_ENCODING_BIPHASE_MARK:
5017 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5018 case HDLC_ENCODING_BIPHASE_LEVEL:
5019 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5020 }
5021 }
5022
5023 usc_OutReg( info, HCR, RegValue );
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044 usc_OutReg( info, CCSR, 0x1020 );
5045
5046
5047 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5048 usc_OutReg( info, SICR,
5049 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5050 }
5051
5052
5053
5054 usc_EnableMasterIrqBit( info );
5055
5056 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5057 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5058
5059
5060 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5061 usc_EnableInterrupts(info, MISC);
5062
5063 info->mbre_bit = 0;
5064 outw( 0, info->io_base );
5065 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5066 info->mbre_bit = BIT8;
5067 outw( BIT8, info->io_base );
5068
5069 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5070
5071
5072 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5073 }
5074
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096
5097 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5098
5099 usc_OutDmaReg( info, DCR, 0xa00b );
5100 }
5101 else
5102 usc_OutDmaReg( info, DCR, 0x800b );
5103
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118 usc_OutDmaReg( info, RDMR, 0xf200 );
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134 usc_OutDmaReg( info, TDMR, 0xf200 );
5135
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149
5150 usc_OutDmaReg( info, DICR, 0x9000 );
5151
5152 usc_InDmaReg( info, RDMR );
5153 usc_InDmaReg( info, TDMR );
5154 usc_OutDmaReg( info, CDIR, 0x0303 );
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168
5169
5170 RegValue = 0x8080;
5171
5172 switch ( info->params.preamble_length ) {
5173 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5174 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5175 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5176 }
5177
5178 switch ( info->params.preamble ) {
5179 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5180 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5181 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5182 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5183 }
5184
5185 usc_OutReg( info, CCR, RegValue );
5186
5187
5188
5189
5190
5191
5192
5193
5194
5195 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5196
5197 usc_OutDmaReg( info, BDCR, 0x0000 );
5198 }
5199 else
5200 usc_OutDmaReg( info, BDCR, 0x2000 );
5201
5202 usc_stop_transmitter(info);
5203 usc_stop_receiver(info);
5204
5205}
5206
5207
5208
5209
5210
5211
5212
5213
5214
5215
5216
5217static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5218{
5219 if (enable) {
5220
5221 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5222
5223
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235
5236 usc_OutReg( info, CMCR, 0x0f64 );
5237
5238
5239
5240 if (info->params.clock_speed) {
5241 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5242 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5243 else
5244 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5245 } else
5246 usc_OutReg(info, TC0R, (u16)8);
5247
5248
5249
5250 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5251
5252
5253 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5254
5255
5256 info->loopback_bits = 0x300;
5257 outw( 0x0300, info->io_base + CCAR );
5258 } else {
5259
5260 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5261
5262
5263 info->loopback_bits = 0;
5264 outw( 0,info->io_base + CCAR );
5265 }
5266
5267}
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280
5281static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5282{
5283 u32 XtalSpeed;
5284 u16 Tc;
5285
5286 if ( data_rate ) {
5287 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5288 XtalSpeed = 11059200;
5289 else
5290 XtalSpeed = 14745600;
5291
5292
5293
5294
5295
5296
5297
5298
5299
5300 Tc = (u16)(XtalSpeed/data_rate);
5301 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5302 Tc--;
5303
5304
5305 usc_OutReg( info, TC0R, Tc );
5306
5307
5308
5309
5310
5311
5312
5313 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5314
5315
5316 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5317 } else {
5318
5319 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5320 }
5321
5322}
5323
5324
5325
5326
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5339{
5340 int start_index;
5341 int end_index;
5342 int frame_start_index;
5343 bool start_of_frame_found = false;
5344 bool end_of_frame_found = false;
5345 bool reprogram_dma = false;
5346
5347 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5348 u32 phys_addr;
5349
5350 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5351 usc_RCmd( info, RCmd_EnterHuntmode );
5352 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5353
5354
5355
5356
5357 frame_start_index = start_index = end_index = info->current_rx_buffer;
5358
5359
5360
5361
5362
5363
5364 while( !buffer_list[end_index].count )
5365 {
5366
5367
5368
5369 if ( !start_of_frame_found )
5370 {
5371 start_of_frame_found = true;
5372 frame_start_index = end_index;
5373 end_of_frame_found = false;
5374 }
5375
5376 if ( buffer_list[end_index].status )
5377 {
5378
5379
5380
5381
5382
5383
5384 start_of_frame_found = false;
5385 end_of_frame_found = true;
5386 }
5387
5388
5389 end_index++;
5390 if ( end_index == info->rx_buffer_count )
5391 end_index = 0;
5392
5393 if ( start_index == end_index )
5394 {
5395
5396
5397
5398 mgsl_reset_rx_dma_buffers( info );
5399 frame_start_index = 0;
5400 start_of_frame_found = false;
5401 reprogram_dma = true;
5402 break;
5403 }
5404 }
5405
5406 if ( start_of_frame_found && !end_of_frame_found )
5407 {
5408
5409
5410
5411
5412
5413
5414
5415 start_index = frame_start_index;
5416
5417 do
5418 {
5419 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5420
5421
5422 if ( start_index == info->rx_buffer_count )
5423 start_index = 0;
5424
5425 } while( start_index != end_index );
5426
5427 reprogram_dma = true;
5428 }
5429
5430 if ( reprogram_dma )
5431 {
5432 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5433 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5434 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5435
5436 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5437
5438
5439 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5440
5441
5442 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5443 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5444 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5445
5446 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5447 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5448 usc_EnableInterrupts( info, RECEIVE_STATUS );
5449
5450
5451
5452
5453 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5454 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5455 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5456 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5457 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5458 else
5459 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5460 }
5461 else
5462 {
5463
5464 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5465 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5466 }
5467
5468}
5469
5470
5471
5472
5473
5474
5475
5476
5477static void usc_stop_receiver( struct mgsl_struct *info )
5478{
5479 if (debug_level >= DEBUG_LEVEL_ISR)
5480 printk("%s(%d):usc_stop_receiver(%s)\n",
5481 __FILE__,__LINE__, info->device_name );
5482
5483
5484
5485 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5486
5487 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5488 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5489 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5490
5491 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5492
5493
5494 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5495 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5496
5497 info->rx_enabled = false;
5498 info->rx_overflow = false;
5499 info->rx_rcc_underrun = false;
5500
5501}
5502
5503
5504
5505
5506
5507
5508
5509
5510static void usc_start_receiver( struct mgsl_struct *info )
5511{
5512 u32 phys_addr;
5513
5514 if (debug_level >= DEBUG_LEVEL_ISR)
5515 printk("%s(%d):usc_start_receiver(%s)\n",
5516 __FILE__,__LINE__, info->device_name );
5517
5518 mgsl_reset_rx_dma_buffers( info );
5519 usc_stop_receiver( info );
5520
5521 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5522 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5523
5524 if ( info->params.mode == MGSL_MODE_HDLC ||
5525 info->params.mode == MGSL_MODE_RAW ) {
5526
5527
5528
5529
5530
5531 phys_addr = info->rx_buffer_list[0].phys_entry;
5532 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5533 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5534
5535 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5536 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5537 usc_EnableInterrupts( info, RECEIVE_STATUS );
5538
5539
5540
5541
5542 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5543 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5544 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5545 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5546 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5547 else
5548 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5549 } else {
5550 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5551 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5552 usc_EnableInterrupts(info, RECEIVE_DATA);
5553
5554 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5555 usc_RCmd( info, RCmd_EnterHuntmode );
5556
5557 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5558 }
5559
5560 usc_OutReg( info, CCSR, 0x1020 );
5561
5562 info->rx_enabled = true;
5563
5564}
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574static void usc_start_transmitter( struct mgsl_struct *info )
5575{
5576 u32 phys_addr;
5577 unsigned int FrameSize;
5578
5579 if (debug_level >= DEBUG_LEVEL_ISR)
5580 printk("%s(%d):usc_start_transmitter(%s)\n",
5581 __FILE__,__LINE__, info->device_name );
5582
5583 if ( info->xmit_cnt ) {
5584
5585
5586
5587
5588
5589 info->drop_rts_on_tx_done = false;
5590
5591 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5592 usc_get_serial_signals( info );
5593 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5594 info->serial_signals |= SerialSignal_RTS;
5595 usc_set_serial_signals( info );
5596 info->drop_rts_on_tx_done = true;
5597 }
5598 }
5599
5600
5601 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5602 if ( !info->tx_active ) {
5603 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5604 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5605 usc_EnableInterrupts(info, TRANSMIT_DATA);
5606 usc_load_txfifo(info);
5607 }
5608 } else {
5609
5610 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5611
5612
5613
5614
5615 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5616
5617
5618
5619
5620
5621 if ( info->params.mode == MGSL_MODE_RAW )
5622 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5623
5624
5625
5626 usc_OutReg( info, TCLR, (u16)FrameSize );
5627
5628 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5629
5630
5631 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5632 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5633 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5634
5635 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5636 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5637 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5638
5639 if ( info->params.mode == MGSL_MODE_RAW &&
5640 info->num_tx_dma_buffers > 1 ) {
5641
5642
5643
5644
5645
5646
5647
5648 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5649 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5650 }
5651
5652
5653 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5654
5655 usc_TCmd( info, TCmd_SendFrame );
5656
5657 mod_timer(&info->tx_timer, jiffies +
5658 msecs_to_jiffies(5000));
5659 }
5660 info->tx_active = true;
5661 }
5662
5663 if ( !info->tx_enabled ) {
5664 info->tx_enabled = true;
5665 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5666 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5667 else
5668 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5669 }
5670
5671}
5672
5673
5674
5675
5676
5677
5678
5679
5680static void usc_stop_transmitter( struct mgsl_struct *info )
5681{
5682 if (debug_level >= DEBUG_LEVEL_ISR)
5683 printk("%s(%d):usc_stop_transmitter(%s)\n",
5684 __FILE__,__LINE__, info->device_name );
5685
5686 del_timer(&info->tx_timer);
5687
5688 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5689 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5690 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5691
5692 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5693 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5694 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5695
5696 info->tx_enabled = false;
5697 info->tx_active = false;
5698
5699}
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709static void usc_load_txfifo( struct mgsl_struct *info )
5710{
5711 int Fifocount;
5712 u8 TwoBytes[2];
5713
5714 if ( !info->xmit_cnt && !info->x_char )
5715 return;
5716
5717
5718 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5719
5720
5721
5722 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5723
5724
5725
5726 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5727
5728
5729 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5730 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5731 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5732 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5733
5734 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5735
5736 info->xmit_cnt -= 2;
5737 info->icount.tx += 2;
5738 } else {
5739
5740
5741 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5742 info->io_base + CCAR );
5743
5744 if (info->x_char) {
5745
5746 outw( info->x_char,info->io_base + CCAR );
5747 info->x_char = 0;
5748 } else {
5749 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5750 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5751 info->xmit_cnt--;
5752 }
5753 info->icount.tx++;
5754 }
5755 }
5756
5757}
5758
5759
5760
5761
5762
5763
5764
5765
5766static void usc_reset( struct mgsl_struct *info )
5767{
5768 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5769 int i;
5770 u32 readval;
5771
5772
5773
5774
5775 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5776 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5777
5778 info->misc_ctrl_value |= BIT30;
5779 *MiscCtrl = info->misc_ctrl_value;
5780
5781
5782
5783
5784
5785
5786 for(i=0;i<10;i++)
5787 readval = *MiscCtrl;
5788
5789 info->misc_ctrl_value &= ~BIT30;
5790 *MiscCtrl = info->misc_ctrl_value;
5791
5792 *LCR0BRDR = BUS_DESCRIPTOR(
5793 1,
5794 2,
5795 2,
5796 0,
5797 4,
5798 0,
5799 0,
5800 5
5801 );
5802 } else {
5803
5804 outb( 0,info->io_base + 8 );
5805 }
5806
5807 info->mbre_bit = 0;
5808 info->loopback_bits = 0;
5809 info->usc_idle_mode = 0;
5810
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828 outw( 0x000c,info->io_base + SDPIN );
5829
5830
5831 outw( 0,info->io_base );
5832 outw( 0,info->io_base + CCAR );
5833
5834
5835 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5836
5837
5838
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852 usc_OutReg( info, PCR, 0xf0f5 );
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869 usc_OutReg( info, IOCR, 0x0004 );
5870
5871}
5872
5873
5874
5875
5876
5877
5878
5879
5880static void usc_set_async_mode( struct mgsl_struct *info )
5881{
5882 u16 RegValue;
5883
5884
5885 usc_DisableMasterIrqBit( info );
5886
5887 outw( 0, info->io_base );
5888 usc_DmaCmd( info, DmaCmd_ResetAllChannels );
5889
5890 usc_loopback_frame( info );
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904 RegValue = 0;
5905 if ( info->params.stop_bits != 1 )
5906 RegValue |= BIT14;
5907 usc_OutReg( info, CMR, RegValue );
5908
5909
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922 RegValue = 0;
5923
5924 if ( info->params.data_bits != 8 )
5925 RegValue |= BIT4+BIT3+BIT2;
5926
5927 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5928 RegValue |= BIT5;
5929 if ( info->params.parity != ASYNC_PARITY_ODD )
5930 RegValue |= BIT6;
5931 }
5932
5933 usc_OutReg( info, RMR, RegValue );
5934
5935
5936
5937
5938 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961 usc_OutReg( info, RICR, 0x0000 );
5962
5963 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5964 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5965
5966
5967
5968
5969
5970
5971
5972
5973
5974
5975
5976
5977
5978
5979 RegValue = 0;
5980
5981 if ( info->params.data_bits != 8 )
5982 RegValue |= BIT4+BIT3+BIT2;
5983
5984 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5985 RegValue |= BIT5;
5986 if ( info->params.parity != ASYNC_PARITY_ODD )
5987 RegValue |= BIT6;
5988 }
5989
5990 usc_OutReg( info, TMR, RegValue );
5991
5992 usc_set_txidle( info );
5993
5994
5995
5996
5997 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5998
5999
6000
6001
6002
6003
6004
6005
6006
6007
6008
6009
6010
6011
6012
6013
6014
6015 usc_OutReg( info, TICR, 0x1f40 );
6016
6017 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6018 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6019
6020 usc_enable_async_clock( info, info->params.data_rate );
6021
6022
6023
6024
6025
6026
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037
6038
6039
6040
6041 usc_OutReg( info, CCSR, 0x0020 );
6042
6043 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6044 RECEIVE_DATA + RECEIVE_STATUS );
6045
6046 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6047 RECEIVE_DATA + RECEIVE_STATUS );
6048
6049 usc_EnableMasterIrqBit( info );
6050
6051 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6052
6053
6054 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6055 }
6056
6057 if (info->params.loopback) {
6058 info->loopback_bits = 0x300;
6059 outw(0x0300, info->io_base + CCAR);
6060 }
6061
6062}
6063
6064
6065
6066
6067
6068
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078static void usc_loopback_frame( struct mgsl_struct *info )
6079{
6080 int i;
6081 unsigned long oldmode = info->params.mode;
6082
6083 info->params.mode = MGSL_MODE_HDLC;
6084
6085 usc_DisableMasterIrqBit( info );
6086
6087 usc_set_sdlc_mode( info );
6088 usc_enable_loopback( info, 1 );
6089
6090
6091 usc_OutReg( info, TC0R, 0 );
6092
6093
6094
6095
6096
6097
6098
6099
6100
6101
6102
6103
6104
6105
6106
6107 usc_OutReg( info, CCR, 0x0100 );
6108
6109
6110 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6111 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6112
6113
6114
6115
6116 usc_OutReg( info, TCLR, 2 );
6117 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6118
6119
6120 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6121 outw(0,info->io_base + DATAREG);
6122
6123
6124 usc_TCmd( info, TCmd_SendFrame );
6125 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6126
6127
6128 for (i=0 ; i<1000 ; i++)
6129 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6130 break;
6131
6132
6133 usc_enable_loopback(info, 0);
6134
6135 usc_EnableMasterIrqBit(info);
6136
6137 info->params.mode = oldmode;
6138
6139}
6140
6141
6142
6143
6144
6145
6146static void usc_set_sync_mode( struct mgsl_struct *info )
6147{
6148 usc_loopback_frame( info );
6149 usc_set_sdlc_mode( info );
6150
6151 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6152
6153
6154 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6155 }
6156
6157 usc_enable_aux_clock(info, info->params.clock_speed);
6158
6159 if (info->params.loopback)
6160 usc_enable_loopback(info,1);
6161
6162}
6163
6164
6165
6166
6167
6168
6169static void usc_set_txidle( struct mgsl_struct *info )
6170{
6171 u16 usc_idle_mode = IDLEMODE_FLAGS;
6172
6173
6174
6175 switch( info->idle_mode ){
6176 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6177 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6178 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6179 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6180 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6181 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6182 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6183 }
6184
6185 info->usc_idle_mode = usc_idle_mode;
6186
6187 info->tcsr_value &= ~IDLEMODE_MASK;
6188 info->tcsr_value += usc_idle_mode;
6189 usc_OutReg(info, TCSR, info->tcsr_value);
6190
6191
6192
6193
6194
6195
6196
6197
6198 if ( info->params.mode == MGSL_MODE_RAW ) {
6199 unsigned char syncpat = 0;
6200 switch( info->idle_mode ) {
6201 case HDLC_TXIDLE_FLAGS:
6202 syncpat = 0x7e;
6203 break;
6204 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6205 syncpat = 0x55;
6206 break;
6207 case HDLC_TXIDLE_ZEROS:
6208 case HDLC_TXIDLE_SPACE:
6209 syncpat = 0x00;
6210 break;
6211 case HDLC_TXIDLE_ONES:
6212 case HDLC_TXIDLE_MARK:
6213 syncpat = 0xff;
6214 break;
6215 case HDLC_TXIDLE_ALT_MARK_SPACE:
6216 syncpat = 0xaa;
6217 break;
6218 }
6219
6220 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6221 }
6222
6223}
6224
6225
6226
6227
6228
6229
6230
6231
6232static void usc_get_serial_signals( struct mgsl_struct *info )
6233{
6234 u16 status;
6235
6236
6237 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6238
6239
6240
6241
6242 status = usc_InReg( info, MISR );
6243
6244
6245
6246 if ( status & MISCSTATUS_CTS )
6247 info->serial_signals |= SerialSignal_CTS;
6248
6249 if ( status & MISCSTATUS_DCD )
6250 info->serial_signals |= SerialSignal_DCD;
6251
6252 if ( status & MISCSTATUS_RI )
6253 info->serial_signals |= SerialSignal_RI;
6254
6255 if ( status & MISCSTATUS_DSR )
6256 info->serial_signals |= SerialSignal_DSR;
6257
6258}
6259
6260
6261
6262
6263
6264
6265
6266
6267
6268static void usc_set_serial_signals( struct mgsl_struct *info )
6269{
6270 u16 Control;
6271 unsigned char V24Out = info->serial_signals;
6272
6273
6274
6275 Control = usc_InReg( info, PCR );
6276
6277 if ( V24Out & SerialSignal_RTS )
6278 Control &= ~(BIT6);
6279 else
6280 Control |= BIT6;
6281
6282 if ( V24Out & SerialSignal_DTR )
6283 Control &= ~(BIT4);
6284 else
6285 Control |= BIT4;
6286
6287 usc_OutReg( info, PCR, Control );
6288
6289}
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6301{
6302 if ( data_rate ) {
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313
6314
6315
6316
6317 usc_OutReg( info, CMCR, 0x0f64 );
6318
6319
6320
6321
6322
6323
6324
6325
6326 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6327 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6328 else
6329 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6330
6331
6332
6333
6334
6335
6336
6337
6338 usc_OutReg( info, HCR,
6339 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6340
6341
6342
6343
6344 usc_OutReg( info, IOCR,
6345 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6346 } else {
6347
6348 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6349 }
6350
6351}
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394
6395
6396
6397
6398
6399
6400
6401
6402
6403
6404
6405
6406
6407
6408
6409
6410static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6411{
6412 unsigned int i;
6413
6414 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6415 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6416 }
6417
6418 info->current_tx_buffer = 0;
6419 info->start_tx_dma_buffer = 0;
6420 info->tx_dma_buffers_used = 0;
6421
6422 info->get_tx_holding_index = 0;
6423 info->put_tx_holding_index = 0;
6424 info->tx_holding_count = 0;
6425
6426}
6427
6428
6429
6430
6431
6432
6433
6434
6435
6436static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6437{
6438 return info->tx_buffer_count - info->tx_dma_buffers_used;
6439}
6440
6441
6442
6443
6444
6445
6446
6447
6448
6449
6450
6451static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6452{
6453 unsigned int i;
6454
6455 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6456 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6457
6458
6459 }
6460
6461 info->current_rx_buffer = 0;
6462
6463}
6464
6465
6466
6467
6468
6469
6470
6471
6472
6473
6474
6475
6476
6477
6478
6479static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6480{
6481 bool Done = false;
6482 DMABUFFERENTRY *pBufEntry;
6483 unsigned int Index;
6484
6485
6486
6487
6488 Index = StartIndex;
6489
6490 while( !Done ) {
6491 pBufEntry = &(info->rx_buffer_list[Index]);
6492
6493 if ( Index == EndIndex ) {
6494
6495 Done = true;
6496 }
6497
6498
6499
6500
6501 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6502
6503
6504 Index++;
6505 if ( Index == info->rx_buffer_count )
6506 Index = 0;
6507 }
6508
6509
6510 info->current_rx_buffer = Index;
6511
6512}
6513
6514
6515
6516
6517
6518
6519
6520
6521
6522static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6523{
6524 unsigned int StartIndex, EndIndex;
6525 unsigned short status;
6526 DMABUFFERENTRY *pBufEntry;
6527 unsigned int framesize = 0;
6528 bool ReturnCode = false;
6529 unsigned long flags;
6530 struct tty_struct *tty = info->port.tty;
6531 bool return_frame = false;
6532
6533
6534
6535
6536
6537
6538
6539
6540 StartIndex = EndIndex = info->current_rx_buffer;
6541
6542 while( !info->rx_buffer_list[EndIndex].status ) {
6543
6544
6545
6546
6547
6548
6549
6550 if ( info->rx_buffer_list[EndIndex].count )
6551 goto Cleanup;
6552
6553
6554 EndIndex++;
6555 if ( EndIndex == info->rx_buffer_count )
6556 EndIndex = 0;
6557
6558
6559 if ( EndIndex == StartIndex ) {
6560
6561
6562
6563
6564
6565 if ( info->rx_enabled ){
6566 spin_lock_irqsave(&info->irq_spinlock,flags);
6567 usc_start_receiver(info);
6568 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6569 }
6570 goto Cleanup;
6571 }
6572 }
6573
6574
6575
6576
6577 status = info->rx_buffer_list[EndIndex].status;
6578
6579 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6580 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6581 if ( status & RXSTATUS_SHORT_FRAME )
6582 info->icount.rxshort++;
6583 else if ( status & RXSTATUS_ABORT )
6584 info->icount.rxabort++;
6585 else if ( status & RXSTATUS_OVERRUN )
6586 info->icount.rxover++;
6587 else {
6588 info->icount.rxcrc++;
6589 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6590 return_frame = true;
6591 }
6592 framesize = 0;
6593#if SYNCLINK_GENERIC_HDLC
6594 {
6595 info->netdev->stats.rx_errors++;
6596 info->netdev->stats.rx_frame_errors++;
6597 }
6598#endif
6599 } else
6600 return_frame = true;
6601
6602 if ( return_frame ) {
6603
6604
6605
6606
6607
6608
6609 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6610
6611
6612 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6613 framesize -= 2;
6614 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6615 framesize -= 4;
6616 }
6617
6618 if ( debug_level >= DEBUG_LEVEL_BH )
6619 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6620 __FILE__,__LINE__,info->device_name,status,framesize);
6621
6622 if ( debug_level >= DEBUG_LEVEL_DATA )
6623 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6624 min_t(int, framesize, DMABUFFERSIZE),0);
6625
6626 if (framesize) {
6627 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6628 ((framesize+1) > info->max_frame_size) ) ||
6629 (framesize > info->max_frame_size) )
6630 info->icount.rxlong++;
6631 else {
6632
6633 int copy_count = framesize;
6634 int index = StartIndex;
6635 unsigned char *ptmp = info->intermediate_rxbuffer;
6636
6637 if ( !(status & RXSTATUS_CRC_ERROR))
6638 info->icount.rxok++;
6639
6640 while(copy_count) {
6641 int partial_count;
6642 if ( copy_count > DMABUFFERSIZE )
6643 partial_count = DMABUFFERSIZE;
6644 else
6645 partial_count = copy_count;
6646
6647 pBufEntry = &(info->rx_buffer_list[index]);
6648 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6649 ptmp += partial_count;
6650 copy_count -= partial_count;
6651
6652 if ( ++index == info->rx_buffer_count )
6653 index = 0;
6654 }
6655
6656 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6657 ++framesize;
6658 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6659 RX_CRC_ERROR :
6660 RX_OK);
6661
6662 if ( debug_level >= DEBUG_LEVEL_DATA )
6663 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6664 __FILE__,__LINE__,info->device_name,
6665 *ptmp);
6666 }
6667
6668#if SYNCLINK_GENERIC_HDLC
6669 if (info->netcount)
6670 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6671 else
6672#endif
6673 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6674 }
6675 }
6676
6677 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6678
6679 ReturnCode = true;
6680
6681Cleanup:
6682
6683 if ( info->rx_enabled && info->rx_overflow ) {
6684
6685
6686
6687
6688
6689 if ( !info->rx_buffer_list[EndIndex].status &&
6690 info->rx_buffer_list[EndIndex].count ) {
6691 spin_lock_irqsave(&info->irq_spinlock,flags);
6692 usc_start_receiver(info);
6693 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6694 }
6695 }
6696
6697 return ReturnCode;
6698
6699}
6700
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713
6714
6715
6716
6717
6718
6719
6720static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6721{
6722 unsigned int CurrentIndex, NextIndex;
6723 unsigned short status;
6724 DMABUFFERENTRY *pBufEntry;
6725 unsigned int framesize = 0;
6726 bool ReturnCode = false;
6727 unsigned long flags;
6728 struct tty_struct *tty = info->port.tty;
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739
6740
6741
6742
6743
6744
6745 CurrentIndex = NextIndex = info->current_rx_buffer;
6746 ++NextIndex;
6747 if ( NextIndex == info->rx_buffer_count )
6748 NextIndex = 0;
6749
6750 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6751 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6752 info->rx_buffer_list[NextIndex].count == 0)) {
6753
6754
6755
6756
6757
6758
6759
6760 status = info->rx_buffer_list[CurrentIndex].status;
6761
6762 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6763 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6764 if ( status & RXSTATUS_SHORT_FRAME )
6765 info->icount.rxshort++;
6766 else if ( status & RXSTATUS_ABORT )
6767 info->icount.rxabort++;
6768 else if ( status & RXSTATUS_OVERRUN )
6769 info->icount.rxover++;
6770 else
6771 info->icount.rxcrc++;
6772 framesize = 0;
6773 } else {
6774
6775
6776
6777
6778
6779
6780
6781
6782
6783
6784
6785
6786
6787
6788
6789
6790
6791
6792
6793
6794
6795
6796
6797 if ( status ) {
6798
6799
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809 if ( info->rx_buffer_list[CurrentIndex].rcc )
6810 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6811 else
6812 framesize = DMABUFFERSIZE;
6813 }
6814 else
6815 framesize = DMABUFFERSIZE;
6816 }
6817
6818 if ( framesize > DMABUFFERSIZE ) {
6819
6820
6821
6822
6823
6824
6825 framesize = framesize % DMABUFFERSIZE;
6826 }
6827
6828
6829 if ( debug_level >= DEBUG_LEVEL_BH )
6830 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6831 __FILE__,__LINE__,info->device_name,status,framesize);
6832
6833 if ( debug_level >= DEBUG_LEVEL_DATA )
6834 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6835 min_t(int, framesize, DMABUFFERSIZE),0);
6836
6837 if (framesize) {
6838
6839
6840
6841 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6842 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6843 info->icount.rxok++;
6844
6845 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6846 }
6847
6848
6849 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6850
6851 ReturnCode = true;
6852 }
6853
6854
6855 if ( info->rx_enabled && info->rx_overflow ) {
6856
6857
6858
6859
6860
6861 if ( !info->rx_buffer_list[CurrentIndex].status &&
6862 info->rx_buffer_list[CurrentIndex].count ) {
6863 spin_lock_irqsave(&info->irq_spinlock,flags);
6864 usc_start_receiver(info);
6865 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6866 }
6867 }
6868
6869 return ReturnCode;
6870
6871}
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6886 const char *Buffer, unsigned int BufferSize)
6887{
6888 unsigned short Copycount;
6889 unsigned int i = 0;
6890 DMABUFFERENTRY *pBufEntry;
6891
6892 if ( debug_level >= DEBUG_LEVEL_DATA )
6893 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6894
6895 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6896
6897
6898
6899 info->cmr_value |= BIT13;
6900 }
6901
6902
6903
6904
6905
6906 i = info->current_tx_buffer;
6907 info->start_tx_dma_buffer = i;
6908
6909
6910
6911
6912 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6913 info->tx_buffer_list[i].rcc = BufferSize;
6914 info->tx_buffer_list[i].count = BufferSize;
6915
6916
6917
6918
6919 while( BufferSize ){
6920
6921 pBufEntry = &info->tx_buffer_list[i++];
6922
6923 if ( i == info->tx_buffer_count )
6924 i=0;
6925
6926
6927
6928 if ( BufferSize > DMABUFFERSIZE )
6929 Copycount = DMABUFFERSIZE;
6930 else
6931 Copycount = BufferSize;
6932
6933
6934
6935 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6936 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6937 else
6938 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6939
6940 pBufEntry->count = Copycount;
6941
6942
6943 Buffer += Copycount;
6944 BufferSize -= Copycount;
6945
6946 ++info->tx_dma_buffers_used;
6947 }
6948
6949
6950 info->current_tx_buffer = i;
6951
6952}
6953
6954
6955
6956
6957
6958
6959
6960
6961
6962static bool mgsl_register_test( struct mgsl_struct *info )
6963{
6964 static unsigned short BitPatterns[] =
6965 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6966 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6967 unsigned int i;
6968 bool rc = true;
6969 unsigned long flags;
6970
6971 spin_lock_irqsave(&info->irq_spinlock,flags);
6972 usc_reset(info);
6973
6974
6975
6976 if ( (usc_InReg( info, SICR ) != 0) ||
6977 (usc_InReg( info, IVR ) != 0) ||
6978 (usc_InDmaReg( info, DIVR ) != 0) ){
6979 rc = false;
6980 }
6981
6982 if ( rc ){
6983
6984
6985
6986 for ( i = 0 ; i < Patterncount ; i++ ) {
6987 usc_OutReg( info, TC0R, BitPatterns[i] );
6988 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6989 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6990 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6991 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6992 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6993
6994 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6995 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6996 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6997 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6998 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6999 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7000 rc = false;
7001 break;
7002 }
7003 }
7004 }
7005
7006 usc_reset(info);
7007 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7008
7009 return rc;
7010
7011}
7012
7013
7014
7015
7016
7017
7018static bool mgsl_irq_test( struct mgsl_struct *info )
7019{
7020 unsigned long EndTime;
7021 unsigned long flags;
7022
7023 spin_lock_irqsave(&info->irq_spinlock,flags);
7024 usc_reset(info);
7025
7026
7027
7028
7029
7030
7031 info->irq_occurred = false;
7032
7033
7034
7035
7036
7037 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7038
7039 usc_EnableMasterIrqBit(info);
7040 usc_EnableInterrupts(info, IO_PIN);
7041 usc_ClearIrqPendingBits(info, IO_PIN);
7042
7043 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7044 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7045
7046 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7047
7048 EndTime=100;
7049 while( EndTime-- && !info->irq_occurred ) {
7050 msleep_interruptible(10);
7051 }
7052
7053 spin_lock_irqsave(&info->irq_spinlock,flags);
7054 usc_reset(info);
7055 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7056
7057 return info->irq_occurred;
7058
7059}
7060
7061
7062
7063
7064
7065
7066
7067
7068
7069
7070static bool mgsl_dma_test( struct mgsl_struct *info )
7071{
7072 unsigned short FifoLevel;
7073 unsigned long phys_addr;
7074 unsigned int FrameSize;
7075 unsigned int i;
7076 char *TmpPtr;
7077 bool rc = true;
7078 unsigned short status=0;
7079 unsigned long EndTime;
7080 unsigned long flags;
7081 MGSL_PARAMS tmp_params;
7082
7083
7084 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7085
7086 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7087
7088#define TESTFRAMESIZE 40
7089
7090 spin_lock_irqsave(&info->irq_spinlock,flags);
7091
7092
7093
7094 usc_reset(info);
7095 usc_set_sdlc_mode(info);
7096 usc_enable_loopback(info,1);
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115
7116
7117
7118 usc_OutDmaReg( info, RDMR, 0xe200 );
7119
7120 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7121
7122
7123
7124
7125 FrameSize = TESTFRAMESIZE;
7126
7127
7128
7129
7130 info->tx_buffer_list[0].count = FrameSize;
7131 info->tx_buffer_list[0].rcc = FrameSize;
7132 info->tx_buffer_list[0].status = 0x4000;
7133
7134
7135
7136 TmpPtr = info->tx_buffer_list[0].virt_addr;
7137 for (i = 0; i < FrameSize; i++ )
7138 *TmpPtr++ = i;
7139
7140
7141
7142
7143 info->rx_buffer_list[0].status = 0;
7144 info->rx_buffer_list[0].count = FrameSize + 4;
7145
7146
7147
7148 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7149
7150
7151
7152
7153 info->tx_buffer_list[1].count = 0;
7154 info->rx_buffer_list[1].count = 0;
7155
7156
7157
7158
7159
7160
7161 spin_lock_irqsave(&info->irq_spinlock,flags);
7162
7163
7164 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7165
7166
7167 phys_addr = info->rx_buffer_list[0].phys_entry;
7168 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7169 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7170
7171
7172 usc_InDmaReg( info, RDMR );
7173 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7174
7175
7176 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7177
7178 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7179
7180
7181
7182
7183
7184
7185
7186 EndTime = jiffies + msecs_to_jiffies(100);
7187
7188 for(;;) {
7189 if (time_after(jiffies, EndTime)) {
7190 rc = false;
7191 break;
7192 }
7193
7194 spin_lock_irqsave(&info->irq_spinlock,flags);
7195 status = usc_InDmaReg( info, RDMR );
7196 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7197
7198 if ( !(status & BIT4) && (status & BIT5) ) {
7199
7200
7201
7202 break;
7203 }
7204 }
7205
7206
7207
7208
7209
7210
7211 spin_lock_irqsave(&info->irq_spinlock,flags);
7212
7213
7214
7215
7216 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7217 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7218
7219
7220
7221 phys_addr = info->tx_buffer_list[0].phys_entry;
7222 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7223 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7224
7225
7226
7227 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7228 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7229
7230
7231
7232 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7233
7234 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7235
7236
7237
7238
7239
7240
7241
7242 EndTime = jiffies + msecs_to_jiffies(100);
7243
7244 for(;;) {
7245 if (time_after(jiffies, EndTime)) {
7246 rc = false;
7247 break;
7248 }
7249
7250 spin_lock_irqsave(&info->irq_spinlock,flags);
7251 FifoLevel = usc_InReg(info, TICR) >> 8;
7252 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7253
7254 if ( FifoLevel < 16 )
7255 break;
7256 else
7257 if ( FrameSize < 32 ) {
7258
7259
7260 if ( FifoLevel <= (32 - FrameSize) )
7261 break;
7262 }
7263 }
7264
7265
7266 if ( rc )
7267 {
7268
7269
7270 spin_lock_irqsave(&info->irq_spinlock,flags);
7271
7272
7273 usc_TCmd( info, TCmd_SendFrame );
7274 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7275
7276 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7277
7278
7279
7280
7281
7282
7283
7284 EndTime = jiffies + msecs_to_jiffies(100);
7285
7286
7287
7288 spin_lock_irqsave(&info->irq_spinlock,flags);
7289 status = usc_InReg( info, TCSR );
7290 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7291
7292 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7293 if (time_after(jiffies, EndTime)) {
7294 rc = false;
7295 break;
7296 }
7297
7298 spin_lock_irqsave(&info->irq_spinlock,flags);
7299 status = usc_InReg( info, TCSR );
7300 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7301 }
7302 }
7303
7304
7305 if ( rc ){
7306
7307 if ( status & (BIT5 + BIT1) )
7308 rc = false;
7309 }
7310
7311 if ( rc ) {
7312
7313
7314
7315 EndTime = jiffies + msecs_to_jiffies(100);
7316
7317
7318 status=info->rx_buffer_list[0].status;
7319 while ( status == 0 ) {
7320 if (time_after(jiffies, EndTime)) {
7321 rc = false;
7322 break;
7323 }
7324 status=info->rx_buffer_list[0].status;
7325 }
7326 }
7327
7328
7329 if ( rc ) {
7330
7331 status = info->rx_buffer_list[0].status;
7332
7333 if ( status & (BIT8 + BIT3 + BIT1) ) {
7334
7335 rc = false;
7336 } else {
7337 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7338 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7339 rc = false;
7340 }
7341 }
7342 }
7343
7344 spin_lock_irqsave(&info->irq_spinlock,flags);
7345 usc_reset( info );
7346 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7347
7348
7349 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7350
7351 return rc;
7352
7353}
7354
7355
7356
7357
7358
7359
7360
7361
7362static int mgsl_adapter_test( struct mgsl_struct *info )
7363{
7364 if ( debug_level >= DEBUG_LEVEL_INFO )
7365 printk( "%s(%d):Testing device %s\n",
7366 __FILE__,__LINE__,info->device_name );
7367
7368 if ( !mgsl_register_test( info ) ) {
7369 info->init_error = DiagStatus_AddressFailure;
7370 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7371 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7372 return -ENODEV;
7373 }
7374
7375 if ( !mgsl_irq_test( info ) ) {
7376 info->init_error = DiagStatus_IrqFailure;
7377 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7378 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7379 return -ENODEV;
7380 }
7381
7382 if ( !mgsl_dma_test( info ) ) {
7383 info->init_error = DiagStatus_DmaFailure;
7384 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7385 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7386 return -ENODEV;
7387 }
7388
7389 if ( debug_level >= DEBUG_LEVEL_INFO )
7390 printk( "%s(%d):device %s passed diagnostics\n",
7391 __FILE__,__LINE__,info->device_name );
7392
7393 return 0;
7394
7395}
7396
7397
7398
7399
7400
7401
7402
7403
7404static bool mgsl_memory_test( struct mgsl_struct *info )
7405{
7406 static unsigned long BitPatterns[] =
7407 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7408 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7409 unsigned long i;
7410 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7411 unsigned long * TestAddr;
7412
7413 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7414 return true;
7415
7416 TestAddr = (unsigned long *)info->memory_base;
7417
7418
7419
7420 for ( i = 0 ; i < Patterncount ; i++ ) {
7421 *TestAddr = BitPatterns[i];
7422 if ( *TestAddr != BitPatterns[i] )
7423 return false;
7424 }
7425
7426
7427
7428
7429 for ( i = 0 ; i < TestLimit ; i++ ) {
7430 *TestAddr = i * 4;
7431 TestAddr++;
7432 }
7433
7434 TestAddr = (unsigned long *)info->memory_base;
7435
7436 for ( i = 0 ; i < TestLimit ; i++ ) {
7437 if ( *TestAddr != i * 4 )
7438 return false;
7439 TestAddr++;
7440 }
7441
7442 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7443
7444 return true;
7445
7446}
7447
7448
7449
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471
7472
7473
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484
7485static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7486 unsigned short count )
7487{
7488
7489#define PCI_LOAD_INTERVAL 64
7490
7491 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7492 unsigned short Index;
7493 unsigned long Dummy;
7494
7495 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7496 {
7497 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7498 Dummy = *((volatile unsigned long *)TargetPtr);
7499 TargetPtr += PCI_LOAD_INTERVAL;
7500 SourcePtr += PCI_LOAD_INTERVAL;
7501 }
7502
7503 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7504
7505}
7506
7507static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7508{
7509 int i;
7510 int linecount;
7511 if (xmit)
7512 printk("%s tx data:\n",info->device_name);
7513 else
7514 printk("%s rx data:\n",info->device_name);
7515
7516 while(count) {
7517 if (count > 16)
7518 linecount = 16;
7519 else
7520 linecount = count;
7521
7522 for(i=0;i<linecount;i++)
7523 printk("%02X ",(unsigned char)data[i]);
7524 for(;i<17;i++)
7525 printk(" ");
7526 for(i=0;i<linecount;i++) {
7527 if (data[i]>=040 && data[i]<=0176)
7528 printk("%c",data[i]);
7529 else
7530 printk(".");
7531 }
7532 printk("\n");
7533
7534 data += linecount;
7535 count -= linecount;
7536 }
7537}
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547static void mgsl_tx_timeout(unsigned long context)
7548{
7549 struct mgsl_struct *info = (struct mgsl_struct*)context;
7550 unsigned long flags;
7551
7552 if ( debug_level >= DEBUG_LEVEL_INFO )
7553 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7554 __FILE__,__LINE__,info->device_name);
7555 if(info->tx_active &&
7556 (info->params.mode == MGSL_MODE_HDLC ||
7557 info->params.mode == MGSL_MODE_RAW) ) {
7558 info->icount.txtimeout++;
7559 }
7560 spin_lock_irqsave(&info->irq_spinlock,flags);
7561 info->tx_active = false;
7562 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7563
7564 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7565 usc_loopmode_cancel_transmit( info );
7566
7567 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7568
7569#if SYNCLINK_GENERIC_HDLC
7570 if (info->netcount)
7571 hdlcdev_tx_done(info);
7572 else
7573#endif
7574 mgsl_bh_transmit(info);
7575
7576}
7577
7578
7579
7580
7581
7582static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7583{
7584 unsigned long flags;
7585
7586 spin_lock_irqsave(&info->irq_spinlock,flags);
7587 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7588 if (info->tx_active)
7589 info->loopmode_send_done_requested = true;
7590 else
7591 usc_loopmode_send_done(info);
7592 }
7593 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7594
7595 return 0;
7596}
7597
7598
7599
7600
7601static void usc_loopmode_send_done( struct mgsl_struct * info )
7602{
7603 info->loopmode_send_done_requested = false;
7604
7605 info->cmr_value &= ~BIT13;
7606 usc_OutReg(info, CMR, info->cmr_value);
7607}
7608
7609
7610
7611static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7612{
7613
7614 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7615 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7616 usc_loopmode_send_done( info );
7617}
7618
7619
7620
7621
7622
7623static void usc_loopmode_insert_request( struct mgsl_struct * info )
7624{
7625 info->loopmode_insert_requested = true;
7626
7627
7628
7629
7630 usc_OutReg( info, RICR,
7631 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7632
7633
7634 info->cmr_value |= BIT13;
7635 usc_OutReg(info, CMR, info->cmr_value);
7636}
7637
7638
7639
7640static int usc_loopmode_active( struct mgsl_struct * info)
7641{
7642 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7643}
7644
7645#if SYNCLINK_GENERIC_HDLC
7646
7647
7648
7649
7650
7651
7652
7653
7654
7655
7656
7657static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7658 unsigned short parity)
7659{
7660 struct mgsl_struct *info = dev_to_port(dev);
7661 unsigned char new_encoding;
7662 unsigned short new_crctype;
7663
7664
7665 if (info->port.count)
7666 return -EBUSY;
7667
7668 switch (encoding)
7669 {
7670 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7671 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7672 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7673 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7674 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7675 default: return -EINVAL;
7676 }
7677
7678 switch (parity)
7679 {
7680 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7681 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7682 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7683 default: return -EINVAL;
7684 }
7685
7686 info->params.encoding = new_encoding;
7687 info->params.crc_type = new_crctype;
7688
7689
7690 if (info->netcount)
7691 mgsl_program_hw(info);
7692
7693 return 0;
7694}
7695
7696
7697
7698
7699
7700
7701
7702static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7703 struct net_device *dev)
7704{
7705 struct mgsl_struct *info = dev_to_port(dev);
7706 unsigned long flags;
7707
7708 if (debug_level >= DEBUG_LEVEL_INFO)
7709 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7710
7711
7712 netif_stop_queue(dev);
7713
7714
7715 info->xmit_cnt = skb->len;
7716 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7717
7718
7719 dev->stats.tx_packets++;
7720 dev->stats.tx_bytes += skb->len;
7721
7722
7723 dev_kfree_skb(skb);
7724
7725
7726 dev->trans_start = jiffies;
7727
7728
7729 spin_lock_irqsave(&info->irq_spinlock,flags);
7730 if (!info->tx_active)
7731 usc_start_transmitter(info);
7732 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7733
7734 return NETDEV_TX_OK;
7735}
7736
7737
7738
7739
7740
7741
7742
7743
7744
7745static int hdlcdev_open(struct net_device *dev)
7746{
7747 struct mgsl_struct *info = dev_to_port(dev);
7748 int rc;
7749 unsigned long flags;
7750
7751 if (debug_level >= DEBUG_LEVEL_INFO)
7752 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7753
7754
7755 if ((rc = hdlc_open(dev)))
7756 return rc;
7757
7758
7759 spin_lock_irqsave(&info->netlock, flags);
7760 if (info->port.count != 0 || info->netcount != 0) {
7761 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7762 spin_unlock_irqrestore(&info->netlock, flags);
7763 return -EBUSY;
7764 }
7765 info->netcount=1;
7766 spin_unlock_irqrestore(&info->netlock, flags);
7767
7768
7769 if ((rc = startup(info)) != 0) {
7770 spin_lock_irqsave(&info->netlock, flags);
7771 info->netcount=0;
7772 spin_unlock_irqrestore(&info->netlock, flags);
7773 return rc;
7774 }
7775
7776
7777 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7778 mgsl_program_hw(info);
7779
7780
7781 dev->trans_start = jiffies;
7782 netif_start_queue(dev);
7783
7784
7785 spin_lock_irqsave(&info->irq_spinlock, flags);
7786 usc_get_serial_signals(info);
7787 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7788 if (info->serial_signals & SerialSignal_DCD)
7789 netif_carrier_on(dev);
7790 else
7791 netif_carrier_off(dev);
7792 return 0;
7793}
7794
7795
7796
7797
7798
7799
7800
7801
7802
7803static int hdlcdev_close(struct net_device *dev)
7804{
7805 struct mgsl_struct *info = dev_to_port(dev);
7806 unsigned long flags;
7807
7808 if (debug_level >= DEBUG_LEVEL_INFO)
7809 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7810
7811 netif_stop_queue(dev);
7812
7813
7814 shutdown(info);
7815
7816 hdlc_close(dev);
7817
7818 spin_lock_irqsave(&info->netlock, flags);
7819 info->netcount=0;
7820 spin_unlock_irqrestore(&info->netlock, flags);
7821
7822 return 0;
7823}
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7835{
7836 const size_t size = sizeof(sync_serial_settings);
7837 sync_serial_settings new_line;
7838 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7839 struct mgsl_struct *info = dev_to_port(dev);
7840 unsigned int flags;
7841
7842 if (debug_level >= DEBUG_LEVEL_INFO)
7843 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7844
7845
7846 if (info->port.count)
7847 return -EBUSY;
7848
7849 if (cmd != SIOCWANDEV)
7850 return hdlc_ioctl(dev, ifr, cmd);
7851
7852 switch(ifr->ifr_settings.type) {
7853 case IF_GET_IFACE:
7854
7855 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7856 if (ifr->ifr_settings.size < size) {
7857 ifr->ifr_settings.size = size;
7858 return -ENOBUFS;
7859 }
7860
7861 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7862 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7863 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7864 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7865
7866 switch (flags){
7867 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7868 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7869 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7870 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7871 default: new_line.clock_type = CLOCK_DEFAULT;
7872 }
7873
7874 new_line.clock_rate = info->params.clock_speed;
7875 new_line.loopback = info->params.loopback ? 1:0;
7876
7877 if (copy_to_user(line, &new_line, size))
7878 return -EFAULT;
7879 return 0;
7880
7881 case IF_IFACE_SYNC_SERIAL:
7882
7883 if(!capable(CAP_NET_ADMIN))
7884 return -EPERM;
7885 if (copy_from_user(&new_line, line, size))
7886 return -EFAULT;
7887
7888 switch (new_line.clock_type)
7889 {
7890 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7891 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7892 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7893 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7894 case CLOCK_DEFAULT: flags = info->params.flags &
7895 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7896 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7897 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7898 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7899 default: return -EINVAL;
7900 }
7901
7902 if (new_line.loopback != 0 && new_line.loopback != 1)
7903 return -EINVAL;
7904
7905 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7906 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7907 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7908 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7909 info->params.flags |= flags;
7910
7911 info->params.loopback = new_line.loopback;
7912
7913 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7914 info->params.clock_speed = new_line.clock_rate;
7915 else
7916 info->params.clock_speed = 0;
7917
7918
7919 if (info->netcount)
7920 mgsl_program_hw(info);
7921 return 0;
7922
7923 default:
7924 return hdlc_ioctl(dev, ifr, cmd);
7925 }
7926}
7927
7928
7929
7930
7931
7932
7933static void hdlcdev_tx_timeout(struct net_device *dev)
7934{
7935 struct mgsl_struct *info = dev_to_port(dev);
7936 unsigned long flags;
7937
7938 if (debug_level >= DEBUG_LEVEL_INFO)
7939 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7940
7941 dev->stats.tx_errors++;
7942 dev->stats.tx_aborted_errors++;
7943
7944 spin_lock_irqsave(&info->irq_spinlock,flags);
7945 usc_stop_transmitter(info);
7946 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7947
7948 netif_wake_queue(dev);
7949}
7950
7951
7952
7953
7954
7955
7956
7957static void hdlcdev_tx_done(struct mgsl_struct *info)
7958{
7959 if (netif_queue_stopped(info->netdev))
7960 netif_wake_queue(info->netdev);
7961}
7962
7963
7964
7965
7966
7967
7968
7969
7970
7971static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7972{
7973 struct sk_buff *skb = dev_alloc_skb(size);
7974 struct net_device *dev = info->netdev;
7975
7976 if (debug_level >= DEBUG_LEVEL_INFO)
7977 printk("hdlcdev_rx(%s)\n", dev->name);
7978
7979 if (skb == NULL) {
7980 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7981 dev->name);
7982 dev->stats.rx_dropped++;
7983 return;
7984 }
7985
7986 memcpy(skb_put(skb, size), buf, size);
7987
7988 skb->protocol = hdlc_type_trans(skb, dev);
7989
7990 dev->stats.rx_packets++;
7991 dev->stats.rx_bytes += size;
7992
7993 netif_rx(skb);
7994}
7995
7996static const struct net_device_ops hdlcdev_ops = {
7997 .ndo_open = hdlcdev_open,
7998 .ndo_stop = hdlcdev_close,
7999 .ndo_change_mtu = hdlc_change_mtu,
8000 .ndo_start_xmit = hdlc_start_xmit,
8001 .ndo_do_ioctl = hdlcdev_ioctl,
8002 .ndo_tx_timeout = hdlcdev_tx_timeout,
8003};
8004
8005
8006
8007
8008
8009
8010
8011
8012
8013static int hdlcdev_init(struct mgsl_struct *info)
8014{
8015 int rc;
8016 struct net_device *dev;
8017 hdlc_device *hdlc;
8018
8019
8020
8021 if (!(dev = alloc_hdlcdev(info))) {
8022 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8023 return -ENOMEM;
8024 }
8025
8026
8027 dev->base_addr = info->io_base;
8028 dev->irq = info->irq_level;
8029 dev->dma = info->dma_level;
8030
8031
8032 dev->netdev_ops = &hdlcdev_ops;
8033 dev->watchdog_timeo = 10 * HZ;
8034 dev->tx_queue_len = 50;
8035
8036
8037 hdlc = dev_to_hdlc(dev);
8038 hdlc->attach = hdlcdev_attach;
8039 hdlc->xmit = hdlcdev_xmit;
8040
8041
8042 if ((rc = register_hdlc_device(dev))) {
8043 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8044 free_netdev(dev);
8045 return rc;
8046 }
8047
8048 info->netdev = dev;
8049 return 0;
8050}
8051
8052
8053
8054
8055
8056
8057
8058static void hdlcdev_exit(struct mgsl_struct *info)
8059{
8060 unregister_hdlc_device(info->netdev);
8061 free_netdev(info->netdev);
8062 info->netdev = NULL;
8063}
8064
8065#endif
8066
8067
8068static int synclink_init_one (struct pci_dev *dev,
8069 const struct pci_device_id *ent)
8070{
8071 struct mgsl_struct *info;
8072
8073 if (pci_enable_device(dev)) {
8074 printk("error enabling pci device %p\n", dev);
8075 return -EIO;
8076 }
8077
8078 if (!(info = mgsl_allocate_device())) {
8079 printk("can't allocate device instance data.\n");
8080 return -EIO;
8081 }
8082
8083
8084
8085 info->io_base = pci_resource_start(dev, 2);
8086 info->irq_level = dev->irq;
8087 info->phys_memory_base = pci_resource_start(dev, 3);
8088
8089
8090
8091
8092
8093 info->phys_lcr_base = pci_resource_start(dev, 0);
8094 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8095 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8096
8097 info->bus_type = MGSL_BUS_TYPE_PCI;
8098 info->io_addr_size = 8;
8099 info->irq_flags = IRQF_SHARED;
8100
8101 if (dev->device == 0x0210) {
8102
8103 info->misc_ctrl_value = 0x007c4080;
8104 info->hw_version = 1;
8105 } else {
8106
8107
8108
8109
8110
8111 info->misc_ctrl_value = 0x087e4546;
8112 info->hw_version = 0;
8113 }
8114
8115 mgsl_add_device(info);
8116
8117 return 0;
8118}
8119
8120static void synclink_remove_one (struct pci_dev *dev)
8121{
8122}
8123
8124