1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14#define __DRIVERS_USB_CHIPIDEA_CI_H
15
16#include <linux/list.h>
17#include <linux/irqreturn.h>
18#include <linux/usb.h>
19#include <linux/usb/gadget.h>
20
21
22
23
24#define CI13XXX_PAGE_SIZE 4096ul
25#define ENDPT_MAX 32
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43struct ci13xxx_ep {
44 struct usb_ep ep;
45 u8 dir;
46 u8 num;
47 u8 type;
48 char name[16];
49 struct {
50 struct list_head queue;
51 struct ci13xxx_qh *ptr;
52 dma_addr_t dma;
53 } qh;
54 int wedge;
55
56
57 struct ci13xxx *ci;
58 spinlock_t *lock;
59 struct dma_pool *td_pool;
60};
61
62enum ci_role {
63 CI_ROLE_HOST = 0,
64 CI_ROLE_GADGET,
65 CI_ROLE_END,
66};
67
68
69
70
71
72
73
74
75struct ci_role_driver {
76 int (*start)(struct ci13xxx *);
77 void (*stop)(struct ci13xxx *);
78 irqreturn_t (*irq)(struct ci13xxx *);
79 const char *name;
80};
81
82
83
84
85
86
87
88
89
90
91
92struct hw_bank {
93 unsigned lpm;
94 resource_size_t phys;
95 void __iomem *abs;
96 void __iomem *cap;
97 void __iomem *op;
98 size_t size;
99 void __iomem **regmap;
100};
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133struct ci13xxx {
134 struct device *dev;
135 spinlock_t lock;
136 struct hw_bank hw_bank;
137 int irq;
138 struct ci_role_driver *roles[CI_ROLE_END];
139 enum ci_role role;
140 bool is_otg;
141 struct work_struct work;
142 struct work_struct vbus_work;
143 struct workqueue_struct *wq;
144
145 struct dma_pool *qh_pool;
146 struct dma_pool *td_pool;
147
148 struct usb_gadget gadget;
149 struct usb_gadget_driver *driver;
150 unsigned hw_ep_max;
151 struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX];
152 u32 ep0_dir;
153 struct ci13xxx_ep *ep0out, *ep0in;
154
155 struct usb_request *status;
156 bool setaddr;
157 u8 address;
158 u8 remote_wakeup;
159 u8 suspended;
160 u8 test_mode;
161
162 struct ci13xxx_platform_data *platdata;
163 int vbus_active;
164
165 bool global_phy;
166 struct usb_phy *transceiver;
167 struct usb_hcd *hcd;
168};
169
170static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
171{
172 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
173 return ci->roles[ci->role];
174}
175
176static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
177{
178 int ret;
179
180 if (role >= CI_ROLE_END)
181 return -EINVAL;
182
183 if (!ci->roles[role])
184 return -ENXIO;
185
186 ret = ci->roles[role]->start(ci);
187 if (!ret)
188 ci->role = role;
189 return ret;
190}
191
192static inline void ci_role_stop(struct ci13xxx *ci)
193{
194 enum ci_role role = ci->role;
195
196 if (role == CI_ROLE_END)
197 return;
198
199 ci->role = CI_ROLE_END;
200
201 ci->roles[role]->stop(ci);
202}
203
204
205
206
207
208#define REG_BITS (32)
209
210
211enum ci13xxx_regs {
212 CAP_CAPLENGTH,
213 CAP_HCCPARAMS,
214 CAP_DCCPARAMS,
215 CAP_TESTMODE,
216 CAP_LAST = CAP_TESTMODE,
217 OP_USBCMD,
218 OP_USBSTS,
219 OP_USBINTR,
220 OP_DEVICEADDR,
221 OP_ENDPTLISTADDR,
222 OP_PORTSC,
223 OP_DEVLC,
224 OP_OTGSC,
225 OP_USBMODE,
226 OP_ENDPTSETUPSTAT,
227 OP_ENDPTPRIME,
228 OP_ENDPTFLUSH,
229 OP_ENDPTSTAT,
230 OP_ENDPTCOMPLETE,
231 OP_ENDPTCTRL,
232
233 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
234};
235
236
237
238
239
240
241
242static inline int ffs_nr(u32 x)
243{
244 int n = ffs(x);
245
246 return n ? n-1 : 32;
247}
248
249
250
251
252
253
254
255
256static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
257{
258 return ioread32(ci->hw_bank.regmap[reg]) & mask;
259}
260
261
262
263
264
265
266
267static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
268 u32 mask, u32 data)
269{
270 if (~mask)
271 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
272 | (data & mask);
273
274 iowrite32(data, ci->hw_bank.regmap[reg]);
275}
276
277
278
279
280
281
282
283
284static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
285 u32 mask)
286{
287 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
288
289 iowrite32(val, ci->hw_bank.regmap[reg]);
290 return val;
291}
292
293
294
295
296
297
298
299
300
301static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
302 u32 mask, u32 data)
303{
304 u32 val = hw_read(ci, reg, ~0);
305
306 hw_write(ci, reg, mask, data);
307 return (val & mask) >> ffs_nr(mask);
308}
309
310int hw_device_reset(struct ci13xxx *ci, u32 mode);
311
312int hw_port_test_set(struct ci13xxx *ci, u8 mode);
313
314u8 hw_port_test_get(struct ci13xxx *ci);
315
316#endif
317