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16#ifndef TSI148_H
17#define TSI148_H
18
19#ifndef PCI_VENDOR_ID_TUNDRA
20#define PCI_VENDOR_ID_TUNDRA 0x10e3
21#endif
22
23#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
24#define PCI_DEVICE_ID_TUNDRA_TSI148 0x148
25#endif
26
27
28
29
30#define TSI148_MAX_MASTER 8
31#define TSI148_MAX_SLAVE 8
32#define TSI148_MAX_DMA 2
33#define TSI148_MAX_MAILBOX 4
34#define TSI148_MAX_SEMAPHORE 8
35
36
37struct tsi148_driver {
38 void __iomem *base;
39 wait_queue_head_t dma_queue[2];
40 wait_queue_head_t iack_queue;
41 void (*lm_callback[4])(int);
42 void *crcsr_kernel;
43 dma_addr_t crcsr_bus;
44 struct vme_master_resource *flush_image;
45 struct mutex vme_rmw;
46 struct mutex vme_int;
47
48
49
50};
51
52
53
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55
56
57
58struct tsi148_dma_descriptor {
59 __be32 dsau;
60 __be32 dsal;
61 __be32 ddau;
62 __be32 ddal;
63 __be32 dsat;
64 __be32 ddat;
65 __be32 dnlau;
66 __be32 dnlal;
67 __be32 dcnt;
68 __be32 ddbs;
69};
70
71struct tsi148_dma_entry {
72
73
74
75
76 struct tsi148_dma_descriptor descriptor;
77 struct list_head list;
78 dma_addr_t dma_handle;
79};
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96
97#define TSI148_PCFS_ID 0x0
98#define TSI148_PCFS_CSR 0x4
99#define TSI148_PCFS_CLASS 0x8
100#define TSI148_PCFS_MISC0 0xC
101#define TSI148_PCFS_MBARL 0x10
102#define TSI148_PCFS_MBARU 0x14
103
104#define TSI148_PCFS_SUBID 0x28
105
106#define TSI148_PCFS_CAPP 0x34
107
108#define TSI148_PCFS_MISC1 0x3C
109
110#define TSI148_PCFS_XCAPP 0x40
111#define TSI148_PCFS_XSTAT 0x44
112
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118
119
120#define TSI148_LCSR_OT0_OTSAU 0x100
121#define TSI148_LCSR_OT0_OTSAL 0x104
122#define TSI148_LCSR_OT0_OTEAU 0x108
123#define TSI148_LCSR_OT0_OTEAL 0x10C
124#define TSI148_LCSR_OT0_OTOFU 0x110
125#define TSI148_LCSR_OT0_OTOFL 0x114
126#define TSI148_LCSR_OT0_OTBS 0x118
127#define TSI148_LCSR_OT0_OTAT 0x11C
128
129#define TSI148_LCSR_OT1_OTSAU 0x120
130#define TSI148_LCSR_OT1_OTSAL 0x124
131#define TSI148_LCSR_OT1_OTEAU 0x128
132#define TSI148_LCSR_OT1_OTEAL 0x12C
133#define TSI148_LCSR_OT1_OTOFU 0x130
134#define TSI148_LCSR_OT1_OTOFL 0x134
135#define TSI148_LCSR_OT1_OTBS 0x138
136#define TSI148_LCSR_OT1_OTAT 0x13C
137
138#define TSI148_LCSR_OT2_OTSAU 0x140
139#define TSI148_LCSR_OT2_OTSAL 0x144
140#define TSI148_LCSR_OT2_OTEAU 0x148
141#define TSI148_LCSR_OT2_OTEAL 0x14C
142#define TSI148_LCSR_OT2_OTOFU 0x150
143#define TSI148_LCSR_OT2_OTOFL 0x154
144#define TSI148_LCSR_OT2_OTBS 0x158
145#define TSI148_LCSR_OT2_OTAT 0x15C
146
147#define TSI148_LCSR_OT3_OTSAU 0x160
148#define TSI148_LCSR_OT3_OTSAL 0x164
149#define TSI148_LCSR_OT3_OTEAU 0x168
150#define TSI148_LCSR_OT3_OTEAL 0x16C
151#define TSI148_LCSR_OT3_OTOFU 0x170
152#define TSI148_LCSR_OT3_OTOFL 0x174
153#define TSI148_LCSR_OT3_OTBS 0x178
154#define TSI148_LCSR_OT3_OTAT 0x17C
155
156#define TSI148_LCSR_OT4_OTSAU 0x180
157#define TSI148_LCSR_OT4_OTSAL 0x184
158#define TSI148_LCSR_OT4_OTEAU 0x188
159#define TSI148_LCSR_OT4_OTEAL 0x18C
160#define TSI148_LCSR_OT4_OTOFU 0x190
161#define TSI148_LCSR_OT4_OTOFL 0x194
162#define TSI148_LCSR_OT4_OTBS 0x198
163#define TSI148_LCSR_OT4_OTAT 0x19C
164
165#define TSI148_LCSR_OT5_OTSAU 0x1A0
166#define TSI148_LCSR_OT5_OTSAL 0x1A4
167#define TSI148_LCSR_OT5_OTEAU 0x1A8
168#define TSI148_LCSR_OT5_OTEAL 0x1AC
169#define TSI148_LCSR_OT5_OTOFU 0x1B0
170#define TSI148_LCSR_OT5_OTOFL 0x1B4
171#define TSI148_LCSR_OT5_OTBS 0x1B8
172#define TSI148_LCSR_OT5_OTAT 0x1BC
173
174#define TSI148_LCSR_OT6_OTSAU 0x1C0
175#define TSI148_LCSR_OT6_OTSAL 0x1C4
176#define TSI148_LCSR_OT6_OTEAU 0x1C8
177#define TSI148_LCSR_OT6_OTEAL 0x1CC
178#define TSI148_LCSR_OT6_OTOFU 0x1D0
179#define TSI148_LCSR_OT6_OTOFL 0x1D4
180#define TSI148_LCSR_OT6_OTBS 0x1D8
181#define TSI148_LCSR_OT6_OTAT 0x1DC
182
183#define TSI148_LCSR_OT7_OTSAU 0x1E0
184#define TSI148_LCSR_OT7_OTSAL 0x1E4
185#define TSI148_LCSR_OT7_OTEAU 0x1E8
186#define TSI148_LCSR_OT7_OTEAL 0x1EC
187#define TSI148_LCSR_OT7_OTOFU 0x1F0
188#define TSI148_LCSR_OT7_OTOFL 0x1F4
189#define TSI148_LCSR_OT7_OTBS 0x1F8
190#define TSI148_LCSR_OT7_OTAT 0x1FC
191
192#define TSI148_LCSR_OT0 0x100
193#define TSI148_LCSR_OT1 0x120
194#define TSI148_LCSR_OT2 0x140
195#define TSI148_LCSR_OT3 0x160
196#define TSI148_LCSR_OT4 0x180
197#define TSI148_LCSR_OT5 0x1A0
198#define TSI148_LCSR_OT6 0x1C0
199#define TSI148_LCSR_OT7 0x1E0
200
201static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
202 TSI148_LCSR_OT2, TSI148_LCSR_OT3,
203 TSI148_LCSR_OT4, TSI148_LCSR_OT5,
204 TSI148_LCSR_OT6, TSI148_LCSR_OT7 };
205
206#define TSI148_LCSR_OFFSET_OTSAU 0x0
207#define TSI148_LCSR_OFFSET_OTSAL 0x4
208#define TSI148_LCSR_OFFSET_OTEAU 0x8
209#define TSI148_LCSR_OFFSET_OTEAL 0xC
210#define TSI148_LCSR_OFFSET_OTOFU 0x10
211#define TSI148_LCSR_OFFSET_OTOFL 0x14
212#define TSI148_LCSR_OFFSET_OTBS 0x18
213#define TSI148_LCSR_OFFSET_OTAT 0x1C
214
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218
219#define TSI148_LCSR_VIACK1 0x204
220#define TSI148_LCSR_VIACK2 0x208
221#define TSI148_LCSR_VIACK3 0x20C
222#define TSI148_LCSR_VIACK4 0x210
223#define TSI148_LCSR_VIACK5 0x214
224#define TSI148_LCSR_VIACK6 0x218
225#define TSI148_LCSR_VIACK7 0x21C
226
227static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
228 TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3,
229 TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5,
230 TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 };
231
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234
235
236#define TSI148_LCSR_RMWAU 0x220
237#define TSI148_LCSR_RMWAL 0x224
238#define TSI148_LCSR_RMWEN 0x228
239#define TSI148_LCSR_RMWC 0x22C
240#define TSI148_LCSR_RMWS 0x230
241
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245
246#define TSI148_LCSR_VMCTRL 0x234
247#define TSI148_LCSR_VCTRL 0x238
248#define TSI148_LCSR_VSTAT 0x23C
249
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253
254#define TSI148_LCSR_PSTAT 0x240
255
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259
260#define TSI148_LCSR_VMEFL 0x250
261
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265
266#define TSI148_LCSR_VEAU 0x260
267#define TSI148_LCSR_VEAL 0x264
268#define TSI148_LCSR_VEAT 0x268
269
270
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273
274#define TSI148_LCSR_EDPAU 0x270
275#define TSI148_LCSR_EDPAL 0x274
276#define TSI148_LCSR_EDPXA 0x278
277#define TSI148_LCSR_EDPXS 0x27C
278#define TSI148_LCSR_EDPAT 0x280
279
280
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282
283
284#define TSI148_LCSR_IT0_ITSAU 0x300
285#define TSI148_LCSR_IT0_ITSAL 0x304
286#define TSI148_LCSR_IT0_ITEAU 0x308
287#define TSI148_LCSR_IT0_ITEAL 0x30C
288#define TSI148_LCSR_IT0_ITOFU 0x310
289#define TSI148_LCSR_IT0_ITOFL 0x314
290#define TSI148_LCSR_IT0_ITAT 0x318
291
292#define TSI148_LCSR_IT1_ITSAU 0x320
293#define TSI148_LCSR_IT1_ITSAL 0x324
294#define TSI148_LCSR_IT1_ITEAU 0x328
295#define TSI148_LCSR_IT1_ITEAL 0x32C
296#define TSI148_LCSR_IT1_ITOFU 0x330
297#define TSI148_LCSR_IT1_ITOFL 0x334
298#define TSI148_LCSR_IT1_ITAT 0x338
299
300#define TSI148_LCSR_IT2_ITSAU 0x340
301#define TSI148_LCSR_IT2_ITSAL 0x344
302#define TSI148_LCSR_IT2_ITEAU 0x348
303#define TSI148_LCSR_IT2_ITEAL 0x34C
304#define TSI148_LCSR_IT2_ITOFU 0x350
305#define TSI148_LCSR_IT2_ITOFL 0x354
306#define TSI148_LCSR_IT2_ITAT 0x358
307
308#define TSI148_LCSR_IT3_ITSAU 0x360
309#define TSI148_LCSR_IT3_ITSAL 0x364
310#define TSI148_LCSR_IT3_ITEAU 0x368
311#define TSI148_LCSR_IT3_ITEAL 0x36C
312#define TSI148_LCSR_IT3_ITOFU 0x370
313#define TSI148_LCSR_IT3_ITOFL 0x374
314#define TSI148_LCSR_IT3_ITAT 0x378
315
316#define TSI148_LCSR_IT4_ITSAU 0x380
317#define TSI148_LCSR_IT4_ITSAL 0x384
318#define TSI148_LCSR_IT4_ITEAU 0x388
319#define TSI148_LCSR_IT4_ITEAL 0x38C
320#define TSI148_LCSR_IT4_ITOFU 0x390
321#define TSI148_LCSR_IT4_ITOFL 0x394
322#define TSI148_LCSR_IT4_ITAT 0x398
323
324#define TSI148_LCSR_IT5_ITSAU 0x3A0
325#define TSI148_LCSR_IT5_ITSAL 0x3A4
326#define TSI148_LCSR_IT5_ITEAU 0x3A8
327#define TSI148_LCSR_IT5_ITEAL 0x3AC
328#define TSI148_LCSR_IT5_ITOFU 0x3B0
329#define TSI148_LCSR_IT5_ITOFL 0x3B4
330#define TSI148_LCSR_IT5_ITAT 0x3B8
331
332#define TSI148_LCSR_IT6_ITSAU 0x3C0
333#define TSI148_LCSR_IT6_ITSAL 0x3C4
334#define TSI148_LCSR_IT6_ITEAU 0x3C8
335#define TSI148_LCSR_IT6_ITEAL 0x3CC
336#define TSI148_LCSR_IT6_ITOFU 0x3D0
337#define TSI148_LCSR_IT6_ITOFL 0x3D4
338#define TSI148_LCSR_IT6_ITAT 0x3D8
339
340#define TSI148_LCSR_IT7_ITSAU 0x3E0
341#define TSI148_LCSR_IT7_ITSAL 0x3E4
342#define TSI148_LCSR_IT7_ITEAU 0x3E8
343#define TSI148_LCSR_IT7_ITEAL 0x3EC
344#define TSI148_LCSR_IT7_ITOFU 0x3F0
345#define TSI148_LCSR_IT7_ITOFL 0x3F4
346#define TSI148_LCSR_IT7_ITAT 0x3F8
347
348
349#define TSI148_LCSR_IT0 0x300
350#define TSI148_LCSR_IT1 0x320
351#define TSI148_LCSR_IT2 0x340
352#define TSI148_LCSR_IT3 0x360
353#define TSI148_LCSR_IT4 0x380
354#define TSI148_LCSR_IT5 0x3A0
355#define TSI148_LCSR_IT6 0x3C0
356#define TSI148_LCSR_IT7 0x3E0
357
358static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
359 TSI148_LCSR_IT2, TSI148_LCSR_IT3,
360 TSI148_LCSR_IT4, TSI148_LCSR_IT5,
361 TSI148_LCSR_IT6, TSI148_LCSR_IT7 };
362
363#define TSI148_LCSR_OFFSET_ITSAU 0x0
364#define TSI148_LCSR_OFFSET_ITSAL 0x4
365#define TSI148_LCSR_OFFSET_ITEAU 0x8
366#define TSI148_LCSR_OFFSET_ITEAL 0xC
367#define TSI148_LCSR_OFFSET_ITOFU 0x10
368#define TSI148_LCSR_OFFSET_ITOFL 0x14
369#define TSI148_LCSR_OFFSET_ITAT 0x18
370
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374
375#define TSI148_LCSR_GBAU 0x400
376#define TSI148_LCSR_GBAL 0x404
377#define TSI148_LCSR_GCSRAT 0x408
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382
383#define TSI148_LCSR_CBAU 0x40C
384#define TSI148_LCSR_CBAL 0x410
385#define TSI148_LCSR_CSRAT 0x414
386
387
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390
391
392#define TSI148_LCSR_CROU 0x418
393#define TSI148_LCSR_CROL 0x41C
394#define TSI148_LCSR_CRAT 0x420
395
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399
400#define TSI148_LCSR_LMBAU 0x424
401#define TSI148_LCSR_LMBAL 0x428
402#define TSI148_LCSR_LMAT 0x42C
403
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407
408#define TSI148_LCSR_BCU 0x430
409#define TSI148_LCSR_BCL 0x434
410#define TSI148_LCSR_BPGTR 0x438
411#define TSI148_LCSR_BPCTR 0x43C
412#define TSI148_LCSR_VICR 0x440
413
414
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416
417
418#define TSI148_LCSR_INTEN 0x448
419#define TSI148_LCSR_INTEO 0x44C
420#define TSI148_LCSR_INTS 0x450
421#define TSI148_LCSR_INTC 0x454
422#define TSI148_LCSR_INTM1 0x458
423#define TSI148_LCSR_INTM2 0x45C
424
425
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427
428
429#define TSI148_LCSR_DCTL0 0x500
430#define TSI148_LCSR_DSTA0 0x504
431#define TSI148_LCSR_DCSAU0 0x508
432#define TSI148_LCSR_DCSAL0 0x50C
433#define TSI148_LCSR_DCDAU0 0x510
434#define TSI148_LCSR_DCDAL0 0x514
435#define TSI148_LCSR_DCLAU0 0x518
436#define TSI148_LCSR_DCLAL0 0x51C
437#define TSI148_LCSR_DSAU0 0x520
438#define TSI148_LCSR_DSAL0 0x524
439#define TSI148_LCSR_DDAU0 0x528
440#define TSI148_LCSR_DDAL0 0x52C
441#define TSI148_LCSR_DSAT0 0x530
442#define TSI148_LCSR_DDAT0 0x534
443#define TSI148_LCSR_DNLAU0 0x538
444#define TSI148_LCSR_DNLAL0 0x53C
445#define TSI148_LCSR_DCNT0 0x540
446#define TSI148_LCSR_DDBS0 0x544
447
448#define TSI148_LCSR_DCTL1 0x580
449#define TSI148_LCSR_DSTA1 0x584
450#define TSI148_LCSR_DCSAU1 0x588
451#define TSI148_LCSR_DCSAL1 0x58C
452#define TSI148_LCSR_DCDAU1 0x590
453#define TSI148_LCSR_DCDAL1 0x594
454#define TSI148_LCSR_DCLAU1 0x598
455#define TSI148_LCSR_DCLAL1 0x59C
456#define TSI148_LCSR_DSAU1 0x5A0
457#define TSI148_LCSR_DSAL1 0x5A4
458#define TSI148_LCSR_DDAU1 0x5A8
459#define TSI148_LCSR_DDAL1 0x5AC
460#define TSI148_LCSR_DSAT1 0x5B0
461#define TSI148_LCSR_DDAT1 0x5B4
462#define TSI148_LCSR_DNLAU1 0x5B8
463#define TSI148_LCSR_DNLAL1 0x5BC
464#define TSI148_LCSR_DCNT1 0x5C0
465#define TSI148_LCSR_DDBS1 0x5C4
466
467#define TSI148_LCSR_DMA0 0x500
468#define TSI148_LCSR_DMA1 0x580
469
470
471static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
472 TSI148_LCSR_DMA1 };
473
474#define TSI148_LCSR_OFFSET_DCTL 0x0
475#define TSI148_LCSR_OFFSET_DSTA 0x4
476#define TSI148_LCSR_OFFSET_DCSAU 0x8
477#define TSI148_LCSR_OFFSET_DCSAL 0xC
478#define TSI148_LCSR_OFFSET_DCDAU 0x10
479#define TSI148_LCSR_OFFSET_DCDAL 0x14
480#define TSI148_LCSR_OFFSET_DCLAU 0x18
481#define TSI148_LCSR_OFFSET_DCLAL 0x1C
482#define TSI148_LCSR_OFFSET_DSAU 0x20
483#define TSI148_LCSR_OFFSET_DSAL 0x24
484#define TSI148_LCSR_OFFSET_DDAU 0x28
485#define TSI148_LCSR_OFFSET_DDAL 0x2C
486#define TSI148_LCSR_OFFSET_DSAT 0x30
487#define TSI148_LCSR_OFFSET_DDAT 0x34
488#define TSI148_LCSR_OFFSET_DNLAU 0x38
489#define TSI148_LCSR_OFFSET_DNLAL 0x3C
490#define TSI148_LCSR_OFFSET_DCNT 0x40
491#define TSI148_LCSR_OFFSET_DDBS 0x44
492
493
494
495
496
497
498
499
500
501
502
503
504#define TSI148_GCSR_ID 0x600
505#define TSI148_GCSR_CSR 0x604
506#define TSI148_GCSR_SEMA0 0x608
507#define TSI148_GCSR_SEMA1 0x60C
508
509
510
511
512
513
514#define TSI148_GCSR_MBOX0 0x610
515#define TSI148_GCSR_MBOX1 0x614
516#define TSI148_GCSR_MBOX2 0x618
517#define TSI148_GCSR_MBOX3 0x61C
518
519static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
520 TSI148_GCSR_MBOX1,
521 TSI148_GCSR_MBOX2,
522 TSI148_GCSR_MBOX3 };
523
524
525
526
527
528
529
530
531
532
533
534#define TSI148_CSRBCR 0xFF4
535#define TSI148_CSRBSR 0xFF8
536#define TSI148_CBAR 0xFFC
537
538
539
540
541
542
543
544
545
546
547
548#define TSI148_PCFS_CMMD_SERR (1<<8)
549#define TSI148_PCFS_CMMD_PERR (1<<6)
550#define TSI148_PCFS_CMMD_MSTR (1<<2)
551#define TSI148_PCFS_CMMD_MEMSP (1<<1)
552#define TSI148_PCFS_CMMD_IOSP (1<<0)
553
554#define TSI148_PCFS_STAT_RCPVE (1<<15)
555#define TSI148_PCFS_STAT_SIGSE (1<<14)
556#define TSI148_PCFS_STAT_RCVMA (1<<13)
557#define TSI148_PCFS_STAT_RCVTA (1<<12)
558#define TSI148_PCFS_STAT_SIGTA (1<<11)
559#define TSI148_PCFS_STAT_SELTIM (3<<9)
560#define TSI148_PCFS_STAT_DPAR (1<<8)
561#define TSI148_PCFS_STAT_FAST (1<<7)
562#define TSI148_PCFS_STAT_P66M (1<<5)
563#define TSI148_PCFS_STAT_CAPL (1<<4)
564
565
566
567
568#define TSI148_PCFS_CLAS_M (0xFF<<24)
569#define TSI148_PCFS_SUBCLAS_M (0xFF<<16)
570#define TSI148_PCFS_PROGIF_M (0xFF<<8)
571#define TSI148_PCFS_REVID_M (0xFF<<0)
572
573
574
575
576#define TSI148_PCFS_HEAD_M (0xFF<<16)
577#define TSI148_PCFS_MLAT_M (0xFF<<8)
578#define TSI148_PCFS_CLSZ_M (0xFF<<0)
579
580
581
582
583#define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12)
584#define TSI148_PCFS_MBARL_PRE (1<<3)
585#define TSI148_PCFS_MBARL_MTYPE_M (3<<1)
586#define TSI148_PCFS_MBARL_IOMEM (1<<0)
587
588
589
590
591#define TSI148_PCFS_MSICAP_64BAC (1<<7)
592#define TSI148_PCFS_MSICAP_MME_M (7<<4)
593#define TSI148_PCFS_MSICAP_MMC_M (7<<1)
594#define TSI148_PCFS_MSICAP_MSIEN (1<<0)
595
596
597
598
599#define TSI148_PCFS_MSIAL_M (0x3FFFFFFF<<2)
600
601
602
603
604#define TSI148_PCFS_MSIMD_M (0xFFFF<<0)
605
606
607
608
609#define TSI148_PCFS_PCIXCAP_MOST_M (7<<4)
610#define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2)
611#define TSI148_PCFS_PCIXCAP_ERO (1<<1)
612#define TSI148_PCFS_PCIXCAP_DPERE (1<<0)
613
614
615
616
617#define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29)
618#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26)
619#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23)
620
621#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21)
622#define TSI148_PCFS_PCIXSTAT_DC (1<<20)
623#define TSI148_PCFS_PCIXSTAT_USC (1<<19)
624#define TSI148_PCFS_PCIXSTAT_SCD (1<<18)
625#define TSI148_PCFS_PCIXSTAT_133C (1<<17)
626#define TSI148_PCFS_PCIXSTAT_64D (1<<16)
627#define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8)
628#define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3)
629#define TSI148_PCFS_PCIXSTAT_FN_M (7<<0)
630
631
632
633
634
635
636
637
638#define TSI148_LCSR_OTSAL_M (0xFFFF<<16)
639
640
641
642
643#define TSI148_LCSR_OTEAL_M (0xFFFF<<16)
644
645
646
647
648#define TSI148_LCSR_OTOFFL_M (0xFFFF<<16)
649
650
651
652
653#define TSI148_LCSR_OTBS_M (0xFFFFF<<0)
654
655
656
657
658#define TSI148_LCSR_OTAT_EN (1<<31)
659#define TSI148_LCSR_OTAT_MRPFD (1<<18)
660
661#define TSI148_LCSR_OTAT_PFS_M (3<<16)
662#define TSI148_LCSR_OTAT_PFS_2 (0<<16)
663#define TSI148_LCSR_OTAT_PFS_4 (1<<16)
664#define TSI148_LCSR_OTAT_PFS_8 (2<<16)
665#define TSI148_LCSR_OTAT_PFS_16 (3<<16)
666
667#define TSI148_LCSR_OTAT_2eSSTM_M (7<<11)
668#define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11)
669#define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11)
670#define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11)
671
672#define TSI148_LCSR_OTAT_TM_M (7<<8)
673#define TSI148_LCSR_OTAT_TM_SCT (0<<8)
674#define TSI148_LCSR_OTAT_TM_BLT (1<<8)
675#define TSI148_LCSR_OTAT_TM_MBLT (2<<8)
676#define TSI148_LCSR_OTAT_TM_2eVME (3<<8)
677#define TSI148_LCSR_OTAT_TM_2eSST (4<<8)
678#define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8)
679
680#define TSI148_LCSR_OTAT_DBW_M (3<<6)
681#define TSI148_LCSR_OTAT_DBW_16 (0<<6)
682#define TSI148_LCSR_OTAT_DBW_32 (1<<6)
683
684#define TSI148_LCSR_OTAT_SUP (1<<5)
685#define TSI148_LCSR_OTAT_PGM (1<<4)
686
687#define TSI148_LCSR_OTAT_AMODE_M (0xf<<0)
688#define TSI148_LCSR_OTAT_AMODE_A16 (0<<0)
689#define TSI148_LCSR_OTAT_AMODE_A24 (1<<0)
690#define TSI148_LCSR_OTAT_AMODE_A32 (2<<0)
691#define TSI148_LCSR_OTAT_AMODE_A64 (4<<0)
692#define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0)
693#define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0)
694#define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0)
695#define TSI148_LCSR_OTAT_AMODE_USER3 (10<<0)
696#define TSI148_LCSR_OTAT_AMODE_USER4 (11<<0)
697
698
699
700
701#define TSI148_LCSR_VMCTRL_VSA (1<<27)
702#define TSI148_LCSR_VMCTRL_VS (1<<26)
703#define TSI148_LCSR_VMCTRL_DHB (1<<25)
704#define TSI148_LCSR_VMCTRL_DWB (1<<24)
705
706#define TSI148_LCSR_VMCTRL_RMWEN (1<<20)
707
708#define TSI148_LCSR_VMCTRL_ATO_M (7<<16)
709
710#define TSI148_LCSR_VMCTRL_ATO_32 (0<<16)
711#define TSI148_LCSR_VMCTRL_ATO_128 (1<<16)
712#define TSI148_LCSR_VMCTRL_ATO_512 (2<<16)
713#define TSI148_LCSR_VMCTRL_ATO_2M (3<<16)
714#define TSI148_LCSR_VMCTRL_ATO_8M (4<<16)
715#define TSI148_LCSR_VMCTRL_ATO_32M (5<<16)
716#define TSI148_LCSR_VMCTRL_ATO_128M (6<<16)
717#define TSI148_LCSR_VMCTRL_ATO_DIS (7<<16)
718
719#define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12)
720#define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12)
721#define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12)
722#define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12)
723#define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12)
724#define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12)
725#define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12)
726#define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12)
727#define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12)
728
729#define TSI148_LCSR_VMCTRL_VTON_M (7<<8)
730#define TSI148_LCSR_VMCTRL_VTON_4 (0<<8)
731#define TSI148_LCSR_VMCTRL_VTON_8 (1<<8)
732#define TSI148_LCSR_VMCTRL_VTON_16 (2<<8)
733#define TSI148_LCSR_VMCTRL_VTON_32 (3<<8)
734#define TSI148_LCSR_VMCTRL_VTON_64 (4<<8)
735#define TSI148_LCSR_VMCTRL_VTON_128 (5<<8)
736#define TSI148_LCSR_VMCTRL_VTON_256 (6<<8)
737#define TSI148_LCSR_VMCTRL_VTON_512 (7<<8)
738
739#define TSI148_LCSR_VMCTRL_VREL_M (3<<3)
740
741#define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3)
742#define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3)
743#define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3)
744#define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3)
745
746#define TSI148_LCSR_VMCTRL_VFAIR (1<<2)
747#define TSI148_LCSR_VMCTRL_VREQL_M (3<<0)
748
749
750
751
752
753#define TSI148_LCSR_VCTRL_LRE (1<<31)
754
755#define TSI148_LCSR_VCTRL_DLT_M (0xF<<24)
756#define TSI148_LCSR_VCTRL_DLT_OFF (0<<24)
757#define TSI148_LCSR_VCTRL_DLT_16 (1<<24)
758#define TSI148_LCSR_VCTRL_DLT_32 (2<<24)
759#define TSI148_LCSR_VCTRL_DLT_64 (3<<24)
760#define TSI148_LCSR_VCTRL_DLT_128 (4<<24)
761#define TSI148_LCSR_VCTRL_DLT_256 (5<<24)
762#define TSI148_LCSR_VCTRL_DLT_512 (6<<24)
763#define TSI148_LCSR_VCTRL_DLT_1024 (7<<24)
764#define TSI148_LCSR_VCTRL_DLT_2048 (8<<24)
765#define TSI148_LCSR_VCTRL_DLT_4096 (9<<24)
766#define TSI148_LCSR_VCTRL_DLT_8192 (0xA<<24)
767#define TSI148_LCSR_VCTRL_DLT_16384 (0xB<<24)
768#define TSI148_LCSR_VCTRL_DLT_32768 (0xC<<24)
769
770#define TSI148_LCSR_VCTRL_NERBB (1<<20)
771
772
773#define TSI148_LCSR_VCTRL_SRESET (1<<17)
774#define TSI148_LCSR_VCTRL_LRESET (1<<16)
775
776#define TSI148_LCSR_VCTRL_SFAILAI (1<<15)
777#define TSI148_LCSR_VCTRL_BID_M (0x1F<<8)
778
779#define TSI148_LCSR_VCTRL_ATOEN (1<<7)
780#define TSI148_LCSR_VCTRL_ROBIN (1<<6)
781
782#define TSI148_LCSR_VCTRL_GTO_M (7<<0)
783
784#define TSI148_LCSR_VCTRL_GTO_8 (0<<0)
785#define TSI148_LCSR_VCTRL_GTO_16 (1<<0)
786#define TSI148_LCSR_VCTRL_GTO_32 (2<<0)
787#define TSI148_LCSR_VCTRL_GTO_64 (3<<0)
788#define TSI148_LCSR_VCTRL_GTO_128 (4<<0)
789#define TSI148_LCSR_VCTRL_GTO_256 (5<<0)
790#define TSI148_LCSR_VCTRL_GTO_512 (6<<0)
791#define TSI148_LCSR_VCTRL_GTO_DIS (7<<0)
792
793
794
795
796#define TSI148_LCSR_VSTAT_CPURST (1<<15)
797#define TSI148_LCSR_VSTAT_BRDFL (1<<14)
798#define TSI148_LCSR_VSTAT_PURSTS (1<<12)
799#define TSI148_LCSR_VSTAT_BDFAILS (1<<11)
800#define TSI148_LCSR_VSTAT_SYSFAILS (1<<10)
801#define TSI148_LCSR_VSTAT_ACFAILS (1<<9)
802#define TSI148_LCSR_VSTAT_SCONS (1<<8)
803#define TSI148_LCSR_VSTAT_GAP (1<<5)
804#define TSI148_LCSR_VSTAT_GA_M (0x1F<<0)
805
806
807
808
809#define TSI148_LCSR_PSTAT_REQ64S (1<<6)
810#define TSI148_LCSR_PSTAT_M66ENS (1<<5)
811#define TSI148_LCSR_PSTAT_FRAMES (1<<4)
812#define TSI148_LCSR_PSTAT_IRDYS (1<<3)
813#define TSI148_LCSR_PSTAT_DEVSELS (1<<2)
814#define TSI148_LCSR_PSTAT_STOPS (1<<1)
815#define TSI148_LCSR_PSTAT_TRDYS (1<<0)
816
817
818
819
820#define TSI148_LCSR_VEAT_VES (1<<31)
821#define TSI148_LCSR_VEAT_VEOF (1<<30)
822#define TSI148_LCSR_VEAT_VESCL (1<<29)
823#define TSI148_LCSR_VEAT_2EOT (1<<21)
824#define TSI148_LCSR_VEAT_2EST (1<<20)
825#define TSI148_LCSR_VEAT_BERR (1<<19)
826#define TSI148_LCSR_VEAT_LWORD (1<<18)
827#define TSI148_LCSR_VEAT_WRITE (1<<17)
828#define TSI148_LCSR_VEAT_IACK (1<<16)
829#define TSI148_LCSR_VEAT_DS1 (1<<15)
830#define TSI148_LCSR_VEAT_DS0 (1<<14)
831#define TSI148_LCSR_VEAT_AM_M (0x3F<<8)
832#define TSI148_LCSR_VEAT_XAM_M (0xFF<<0)
833
834
835
836
837
838#define TSI148_LCSR_EDPAT_EDPCL (1<<29)
839
840
841
842
843#define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16)
844#define TSI148_LCSR_ITSAL24_M (0x00FFF<<12)
845#define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4)
846
847
848
849
850#define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16)
851#define TSI148_LCSR_ITEAL24_M (0x00FFF<<12)
852#define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4)
853
854
855
856
857#define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16)
858#define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12)
859#define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4)
860
861
862
863
864#define TSI148_LCSR_ITAT_EN (1<<31)
865#define TSI148_LCSR_ITAT_TH (1<<18)
866
867#define TSI148_LCSR_ITAT_VFS_M (3<<16)
868#define TSI148_LCSR_ITAT_VFS_64 (0<<16)
869#define TSI148_LCSR_ITAT_VFS_128 (1<<16)
870#define TSI148_LCSR_ITAT_VFS_256 (2<<16)
871#define TSI148_LCSR_ITAT_VFS_512 (3<<16)
872
873#define TSI148_LCSR_ITAT_2eSSTM_M (7<<12)
874#define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12)
875#define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12)
876#define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12)
877
878#define TSI148_LCSR_ITAT_2eSSTB (1<<11)
879#define TSI148_LCSR_ITAT_2eSST (1<<10)
880#define TSI148_LCSR_ITAT_2eVME (1<<9)
881#define TSI148_LCSR_ITAT_MBLT (1<<8)
882#define TSI148_LCSR_ITAT_BLT (1<<7)
883
884#define TSI148_LCSR_ITAT_AS_M (7<<4)
885#define TSI148_LCSR_ITAT_AS_A16 (0<<4)
886#define TSI148_LCSR_ITAT_AS_A24 (1<<4)
887#define TSI148_LCSR_ITAT_AS_A32 (2<<4)
888#define TSI148_LCSR_ITAT_AS_A64 (4<<4)
889
890#define TSI148_LCSR_ITAT_SUPR (1<<3)
891#define TSI148_LCSR_ITAT_NPRIV (1<<2)
892#define TSI148_LCSR_ITAT_PGM (1<<1)
893#define TSI148_LCSR_ITAT_DATA (1<<0)
894
895
896
897
898#define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5)
899
900
901
902
903#define TSI148_LCSR_GCSRAT_EN (1<<7)
904
905#define TSI148_LCSR_GCSRAT_AS_M (7<<4)
906#define TSI148_LCSR_GCSRAT_AS_A16 (0<<4)
907#define TSI148_LCSR_GCSRAT_AS_A24 (1<<4)
908#define TSI148_LCSR_GCSRAT_AS_A32 (2<<4)
909#define TSI148_LCSR_GCSRAT_AS_A64 (4<<4)
910
911#define TSI148_LCSR_GCSRAT_SUPR (1<<3)
912#define TSI148_LCSR_GCSRAT_NPRIV (1<<2)
913#define TSI148_LCSR_GCSRAT_PGM (1<<1)
914#define TSI148_LCSR_GCSRAT_DATA (1<<0)
915
916
917
918
919#define TSI148_LCSR_CBAL_M (0xFFFFF<<12)
920
921
922
923
924#define TSI148_LCSR_CRGAT_EN (1<<7)
925
926#define TSI148_LCSR_CRGAT_AS_M (7<<4)
927#define TSI148_LCSR_CRGAT_AS_A16 (0<<4)
928#define TSI148_LCSR_CRGAT_AS_A24 (1<<4)
929#define TSI148_LCSR_CRGAT_AS_A32 (2<<4)
930#define TSI148_LCSR_CRGAT_AS_A64 (4<<4)
931
932#define TSI148_LCSR_CRGAT_SUPR (1<<3)
933#define TSI148_LCSR_CRGAT_NPRIV (1<<2)
934#define TSI148_LCSR_CRGAT_PGM (1<<1)
935#define TSI148_LCSR_CRGAT_DATA (1<<0)
936
937
938
939
940#define TSI148_LCSR_CROL_M (0x1FFF<<19)
941
942
943
944
945#define TSI148_LCSR_CRAT_EN (1<<7)
946
947
948
949
950#define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5)
951
952
953
954
955#define TSI148_LCSR_LMAT_EN (1<<7)
956
957#define TSI148_LCSR_LMAT_AS_M (7<<4)
958#define TSI148_LCSR_LMAT_AS_A16 (0<<4)
959#define TSI148_LCSR_LMAT_AS_A24 (1<<4)
960#define TSI148_LCSR_LMAT_AS_A32 (2<<4)
961#define TSI148_LCSR_LMAT_AS_A64 (4<<4)
962
963#define TSI148_LCSR_LMAT_SUPR (1<<3)
964#define TSI148_LCSR_LMAT_NPRIV (1<<2)
965#define TSI148_LCSR_LMAT_PGM (1<<1)
966#define TSI148_LCSR_LMAT_DATA (1<<0)
967
968
969
970
971#define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0)
972
973
974
975
976#define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0)
977
978
979
980
981#define TSI148_LCSR_VICR_CNTS_M (3<<22)
982#define TSI148_LCSR_VICR_CNTS_DIS (1<<22)
983#define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22)
984#define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22)
985
986#define TSI148_LCSR_VICR_EDGIS_M (3<<20)
987#define TSI148_LCSR_VICR_EDGIS_DIS (1<<20)
988#define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20)
989#define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20)
990
991#define TSI148_LCSR_VICR_IRQIF_M (3<<18)
992#define TSI148_LCSR_VICR_IRQIF_NORM (1<<18)
993#define TSI148_LCSR_VICR_IRQIF_PULSE (2<<18)
994#define TSI148_LCSR_VICR_IRQIF_PROG (3<<18)
995#define TSI148_LCSR_VICR_IRQIF_1U (4<<18)
996
997#define TSI148_LCSR_VICR_IRQ2F_M (3<<16)
998#define TSI148_LCSR_VICR_IRQ2F_NORM (1<<16)
999#define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<16)
1000#define TSI148_LCSR_VICR_IRQ2F_PROG (3<<16)
1001#define TSI148_LCSR_VICR_IRQ2F_1U (4<<16)
1002
1003#define TSI148_LCSR_VICR_BIP (1<<15)
1004
1005#define TSI148_LCSR_VICR_IRQC (1<<12)
1006#define TSI148_LCSR_VICR_IRQS (1<<11)
1007
1008#define TSI148_LCSR_VICR_IRQL_M (7<<8)
1009#define TSI148_LCSR_VICR_IRQL_1 (1<<8)
1010#define TSI148_LCSR_VICR_IRQL_2 (2<<8)
1011#define TSI148_LCSR_VICR_IRQL_3 (3<<8)
1012#define TSI148_LCSR_VICR_IRQL_4 (4<<8)
1013#define TSI148_LCSR_VICR_IRQL_5 (5<<8)
1014#define TSI148_LCSR_VICR_IRQL_6 (6<<8)
1015#define TSI148_LCSR_VICR_IRQL_7 (7<<8)
1016
1017static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1,
1018 TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3,
1019 TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5,
1020 TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 };
1021
1022#define TSI148_LCSR_VICR_STID_M (0xFF<<0)
1023
1024
1025
1026
1027#define TSI148_LCSR_INTEN_DMA1EN (1<<25)
1028#define TSI148_LCSR_INTEN_DMA0EN (1<<24)
1029#define TSI148_LCSR_INTEN_LM3EN (1<<23)
1030#define TSI148_LCSR_INTEN_LM2EN (1<<22)
1031#define TSI148_LCSR_INTEN_LM1EN (1<<21)
1032#define TSI148_LCSR_INTEN_LM0EN (1<<20)
1033#define TSI148_LCSR_INTEN_MB3EN (1<<19)
1034#define TSI148_LCSR_INTEN_MB2EN (1<<18)
1035#define TSI148_LCSR_INTEN_MB1EN (1<<17)
1036#define TSI148_LCSR_INTEN_MB0EN (1<<16)
1037#define TSI148_LCSR_INTEN_PERREN (1<<13)
1038#define TSI148_LCSR_INTEN_VERREN (1<<12)
1039#define TSI148_LCSR_INTEN_VIEEN (1<<11)
1040#define TSI148_LCSR_INTEN_IACKEN (1<<10)
1041#define TSI148_LCSR_INTEN_SYSFLEN (1<<9)
1042#define TSI148_LCSR_INTEN_ACFLEN (1<<8)
1043#define TSI148_LCSR_INTEN_IRQ7EN (1<<7)
1044#define TSI148_LCSR_INTEN_IRQ6EN (1<<6)
1045#define TSI148_LCSR_INTEN_IRQ5EN (1<<5)
1046#define TSI148_LCSR_INTEN_IRQ4EN (1<<4)
1047#define TSI148_LCSR_INTEN_IRQ3EN (1<<3)
1048#define TSI148_LCSR_INTEN_IRQ2EN (1<<2)
1049#define TSI148_LCSR_INTEN_IRQ1EN (1<<1)
1050
1051static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN,
1052 TSI148_LCSR_INTEN_LM1EN,
1053 TSI148_LCSR_INTEN_LM2EN,
1054 TSI148_LCSR_INTEN_LM3EN };
1055
1056static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN,
1057 TSI148_LCSR_INTEN_IRQ2EN,
1058 TSI148_LCSR_INTEN_IRQ3EN,
1059 TSI148_LCSR_INTEN_IRQ4EN,
1060 TSI148_LCSR_INTEN_IRQ5EN,
1061 TSI148_LCSR_INTEN_IRQ6EN,
1062 TSI148_LCSR_INTEN_IRQ7EN };
1063
1064
1065
1066
1067#define TSI148_LCSR_INTEO_DMA1EO (1<<25)
1068#define TSI148_LCSR_INTEO_DMA0EO (1<<24)
1069#define TSI148_LCSR_INTEO_LM3EO (1<<23)
1070#define TSI148_LCSR_INTEO_LM2EO (1<<22)
1071#define TSI148_LCSR_INTEO_LM1EO (1<<21)
1072#define TSI148_LCSR_INTEO_LM0EO (1<<20)
1073#define TSI148_LCSR_INTEO_MB3EO (1<<19)
1074#define TSI148_LCSR_INTEO_MB2EO (1<<18)
1075#define TSI148_LCSR_INTEO_MB1EO (1<<17)
1076#define TSI148_LCSR_INTEO_MB0EO (1<<16)
1077#define TSI148_LCSR_INTEO_PERREO (1<<13)
1078#define TSI148_LCSR_INTEO_VERREO (1<<12)
1079#define TSI148_LCSR_INTEO_VIEEO (1<<11)
1080#define TSI148_LCSR_INTEO_IACKEO (1<<10)
1081#define TSI148_LCSR_INTEO_SYSFLEO (1<<9)
1082#define TSI148_LCSR_INTEO_ACFLEO (1<<8)
1083#define TSI148_LCSR_INTEO_IRQ7EO (1<<7)
1084#define TSI148_LCSR_INTEO_IRQ6EO (1<<6)
1085#define TSI148_LCSR_INTEO_IRQ5EO (1<<5)
1086#define TSI148_LCSR_INTEO_IRQ4EO (1<<4)
1087#define TSI148_LCSR_INTEO_IRQ3EO (1<<3)
1088#define TSI148_LCSR_INTEO_IRQ2EO (1<<2)
1089#define TSI148_LCSR_INTEO_IRQ1EO (1<<1)
1090
1091static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO,
1092 TSI148_LCSR_INTEO_LM1EO,
1093 TSI148_LCSR_INTEO_LM2EO,
1094 TSI148_LCSR_INTEO_LM3EO };
1095
1096static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO,
1097 TSI148_LCSR_INTEO_IRQ2EO,
1098 TSI148_LCSR_INTEO_IRQ3EO,
1099 TSI148_LCSR_INTEO_IRQ4EO,
1100 TSI148_LCSR_INTEO_IRQ5EO,
1101 TSI148_LCSR_INTEO_IRQ6EO,
1102 TSI148_LCSR_INTEO_IRQ7EO };
1103
1104
1105
1106
1107#define TSI148_LCSR_INTS_DMA1S (1<<25)
1108#define TSI148_LCSR_INTS_DMA0S (1<<24)
1109#define TSI148_LCSR_INTS_LM3S (1<<23)
1110#define TSI148_LCSR_INTS_LM2S (1<<22)
1111#define TSI148_LCSR_INTS_LM1S (1<<21)
1112#define TSI148_LCSR_INTS_LM0S (1<<20)
1113#define TSI148_LCSR_INTS_MB3S (1<<19)
1114#define TSI148_LCSR_INTS_MB2S (1<<18)
1115#define TSI148_LCSR_INTS_MB1S (1<<17)
1116#define TSI148_LCSR_INTS_MB0S (1<<16)
1117#define TSI148_LCSR_INTS_PERRS (1<<13)
1118#define TSI148_LCSR_INTS_VERRS (1<<12)
1119#define TSI148_LCSR_INTS_VIES (1<<11)
1120#define TSI148_LCSR_INTS_IACKS (1<<10)
1121#define TSI148_LCSR_INTS_SYSFLS (1<<9)
1122#define TSI148_LCSR_INTS_ACFLS (1<<8)
1123#define TSI148_LCSR_INTS_IRQ7S (1<<7)
1124#define TSI148_LCSR_INTS_IRQ6S (1<<6)
1125#define TSI148_LCSR_INTS_IRQ5S (1<<5)
1126#define TSI148_LCSR_INTS_IRQ4S (1<<4)
1127#define TSI148_LCSR_INTS_IRQ3S (1<<3)
1128#define TSI148_LCSR_INTS_IRQ2S (1<<2)
1129#define TSI148_LCSR_INTS_IRQ1S (1<<1)
1130
1131static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S,
1132 TSI148_LCSR_INTS_LM1S,
1133 TSI148_LCSR_INTS_LM2S,
1134 TSI148_LCSR_INTS_LM3S };
1135
1136static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S,
1137 TSI148_LCSR_INTS_MB1S,
1138 TSI148_LCSR_INTS_MB2S,
1139 TSI148_LCSR_INTS_MB3S };
1140
1141
1142
1143
1144#define TSI148_LCSR_INTC_DMA1C (1<<25)
1145#define TSI148_LCSR_INTC_DMA0C (1<<24)
1146#define TSI148_LCSR_INTC_LM3C (1<<23)
1147#define TSI148_LCSR_INTC_LM2C (1<<22)
1148#define TSI148_LCSR_INTC_LM1C (1<<21)
1149#define TSI148_LCSR_INTC_LM0C (1<<20)
1150#define TSI148_LCSR_INTC_MB3C (1<<19)
1151#define TSI148_LCSR_INTC_MB2C (1<<18)
1152#define TSI148_LCSR_INTC_MB1C (1<<17)
1153#define TSI148_LCSR_INTC_MB0C (1<<16)
1154#define TSI148_LCSR_INTC_PERRC (1<<13)
1155#define TSI148_LCSR_INTC_VERRC (1<<12)
1156#define TSI148_LCSR_INTC_VIEC (1<<11)
1157#define TSI148_LCSR_INTC_IACKC (1<<10)
1158#define TSI148_LCSR_INTC_SYSFLC (1<<9)
1159#define TSI148_LCSR_INTC_ACFLC (1<<8)
1160
1161static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C,
1162 TSI148_LCSR_INTC_LM1C,
1163 TSI148_LCSR_INTC_LM2C,
1164 TSI148_LCSR_INTC_LM3C };
1165
1166static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
1167 TSI148_LCSR_INTC_MB1C,
1168 TSI148_LCSR_INTC_MB2C,
1169 TSI148_LCSR_INTC_MB3C };
1170
1171
1172
1173
1174#define TSI148_LCSR_INTM1_DMA1M_M (3<<18)
1175#define TSI148_LCSR_INTM1_DMA0M_M (3<<16)
1176#define TSI148_LCSR_INTM1_LM3M_M (3<<14)
1177#define TSI148_LCSR_INTM1_LM2M_M (3<<12)
1178#define TSI148_LCSR_INTM1_LM1M_M (3<<10)
1179#define TSI148_LCSR_INTM1_LM0M_M (3<<8)
1180#define TSI148_LCSR_INTM1_MB3M_M (3<<6)
1181#define TSI148_LCSR_INTM1_MB2M_M (3<<4)
1182#define TSI148_LCSR_INTM1_MB1M_M (3<<2)
1183#define TSI148_LCSR_INTM1_MB0M_M (3<<0)
1184
1185
1186
1187
1188#define TSI148_LCSR_INTM2_PERRM_M (3<<26)
1189#define TSI148_LCSR_INTM2_VERRM_M (3<<24)
1190#define TSI148_LCSR_INTM2_VIEM_M (3<<22)
1191#define TSI148_LCSR_INTM2_IACKM_M (3<<20)
1192#define TSI148_LCSR_INTM2_SYSFLM_M (3<<18)
1193#define TSI148_LCSR_INTM2_ACFLM_M (3<<16)
1194#define TSI148_LCSR_INTM2_IRQ7M_M (3<<14)
1195#define TSI148_LCSR_INTM2_IRQ6M_M (3<<12)
1196#define TSI148_LCSR_INTM2_IRQ5M_M (3<<10)
1197#define TSI148_LCSR_INTM2_IRQ4M_M (3<<8)
1198#define TSI148_LCSR_INTM2_IRQ3M_M (3<<6)
1199#define TSI148_LCSR_INTM2_IRQ2M_M (3<<4)
1200#define TSI148_LCSR_INTM2_IRQ1M_M (3<<2)
1201
1202
1203
1204
1205#define TSI148_LCSR_DCTL_ABT (1<<27)
1206#define TSI148_LCSR_DCTL_PAU (1<<26)
1207#define TSI148_LCSR_DCTL_DGO (1<<25)
1208
1209#define TSI148_LCSR_DCTL_MOD (1<<23)
1210
1211#define TSI148_LCSR_DCTL_VBKS_M (7<<12)
1212#define TSI148_LCSR_DCTL_VBKS_32 (0<<12)
1213#define TSI148_LCSR_DCTL_VBKS_64 (1<<12)
1214#define TSI148_LCSR_DCTL_VBKS_128 (2<<12)
1215#define TSI148_LCSR_DCTL_VBKS_256 (3<<12)
1216#define TSI148_LCSR_DCTL_VBKS_512 (4<<12)
1217#define TSI148_LCSR_DCTL_VBKS_1024 (5<<12)
1218#define TSI148_LCSR_DCTL_VBKS_2048 (6<<12)
1219#define TSI148_LCSR_DCTL_VBKS_4096 (7<<12)
1220
1221#define TSI148_LCSR_DCTL_VBOT_M (7<<8)
1222#define TSI148_LCSR_DCTL_VBOT_0 (0<<8)
1223#define TSI148_LCSR_DCTL_VBOT_1 (1<<8)
1224#define TSI148_LCSR_DCTL_VBOT_2 (2<<8)
1225#define TSI148_LCSR_DCTL_VBOT_4 (3<<8)
1226#define TSI148_LCSR_DCTL_VBOT_8 (4<<8)
1227#define TSI148_LCSR_DCTL_VBOT_16 (5<<8)
1228#define TSI148_LCSR_DCTL_VBOT_32 (6<<8)
1229#define TSI148_LCSR_DCTL_VBOT_64 (7<<8)
1230
1231#define TSI148_LCSR_DCTL_PBKS_M (7<<4)
1232#define TSI148_LCSR_DCTL_PBKS_32 (0<<4)
1233#define TSI148_LCSR_DCTL_PBKS_64 (1<<4)
1234#define TSI148_LCSR_DCTL_PBKS_128 (2<<4)
1235#define TSI148_LCSR_DCTL_PBKS_256 (3<<4)
1236#define TSI148_LCSR_DCTL_PBKS_512 (4<<4)
1237#define TSI148_LCSR_DCTL_PBKS_1024 (5<<4)
1238#define TSI148_LCSR_DCTL_PBKS_2048 (6<<4)
1239#define TSI148_LCSR_DCTL_PBKS_4096 (7<<4)
1240
1241#define TSI148_LCSR_DCTL_PBOT_M (7<<0)
1242#define TSI148_LCSR_DCTL_PBOT_0 (0<<0)
1243#define TSI148_LCSR_DCTL_PBOT_1 (1<<0)
1244#define TSI148_LCSR_DCTL_PBOT_2 (2<<0)
1245#define TSI148_LCSR_DCTL_PBOT_4 (3<<0)
1246#define TSI148_LCSR_DCTL_PBOT_8 (4<<0)
1247#define TSI148_LCSR_DCTL_PBOT_16 (5<<0)
1248#define TSI148_LCSR_DCTL_PBOT_32 (6<<0)
1249#define TSI148_LCSR_DCTL_PBOT_64 (7<<0)
1250
1251
1252
1253
1254#define TSI148_LCSR_DSTA_SMA (1<<31)
1255#define TSI148_LCSR_DSTA_RTA (1<<30)
1256#define TSI148_LCSR_DSTA_MRC (1<<29)
1257#define TSI148_LCSR_DSTA_VBE (1<<28)
1258#define TSI148_LCSR_DSTA_ABT (1<<27)
1259#define TSI148_LCSR_DSTA_PAU (1<<26)
1260#define TSI148_LCSR_DSTA_DON (1<<25)
1261#define TSI148_LCSR_DSTA_BSY (1<<24)
1262
1263
1264
1265
1266#define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6)
1267
1268
1269
1270
1271#define TSI148_LCSR_DSAT_TYP_M (3<<28)
1272#define TSI148_LCSR_DSAT_TYP_PCI (0<<28)
1273#define TSI148_LCSR_DSAT_TYP_VME (1<<28)
1274#define TSI148_LCSR_DSAT_TYP_PAT (2<<28)
1275
1276#define TSI148_LCSR_DSAT_PSZ (1<<25)
1277#define TSI148_LCSR_DSAT_NIN (1<<24)
1278
1279#define TSI148_LCSR_DSAT_2eSSTM_M (3<<11)
1280#define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11)
1281#define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11)
1282#define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11)
1283
1284#define TSI148_LCSR_DSAT_TM_M (7<<8)
1285#define TSI148_LCSR_DSAT_TM_SCT (0<<8)
1286#define TSI148_LCSR_DSAT_TM_BLT (1<<8)
1287#define TSI148_LCSR_DSAT_TM_MBLT (2<<8)
1288#define TSI148_LCSR_DSAT_TM_2eVME (3<<8)
1289#define TSI148_LCSR_DSAT_TM_2eSST (4<<8)
1290#define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8)
1291
1292#define TSI148_LCSR_DSAT_DBW_M (3<<6)
1293#define TSI148_LCSR_DSAT_DBW_16 (0<<6)
1294#define TSI148_LCSR_DSAT_DBW_32 (1<<6)
1295
1296#define TSI148_LCSR_DSAT_SUP (1<<5)
1297#define TSI148_LCSR_DSAT_PGM (1<<4)
1298
1299#define TSI148_LCSR_DSAT_AMODE_M (0xf<<0)
1300#define TSI148_LCSR_DSAT_AMODE_A16 (0<<0)
1301#define TSI148_LCSR_DSAT_AMODE_A24 (1<<0)
1302#define TSI148_LCSR_DSAT_AMODE_A32 (2<<0)
1303#define TSI148_LCSR_DSAT_AMODE_A64 (4<<0)
1304#define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0)
1305#define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0)
1306#define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0)
1307#define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0)
1308#define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0)
1309
1310
1311
1312
1313#define TSI148_LCSR_DDAT_TYP_PCI (0<<28)
1314#define TSI148_LCSR_DDAT_TYP_VME (1<<28)
1315
1316#define TSI148_LCSR_DDAT_2eSSTM_M (3<<11)
1317#define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11)
1318#define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11)
1319#define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11)
1320
1321#define TSI148_LCSR_DDAT_TM_M (7<<8)
1322#define TSI148_LCSR_DDAT_TM_SCT (0<<8)
1323#define TSI148_LCSR_DDAT_TM_BLT (1<<8)
1324#define TSI148_LCSR_DDAT_TM_MBLT (2<<8)
1325#define TSI148_LCSR_DDAT_TM_2eVME (3<<8)
1326#define TSI148_LCSR_DDAT_TM_2eSST (4<<8)
1327#define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8)
1328
1329#define TSI148_LCSR_DDAT_DBW_M (3<<6)
1330#define TSI148_LCSR_DDAT_DBW_16 (0<<6)
1331#define TSI148_LCSR_DDAT_DBW_32 (1<<6)
1332
1333#define TSI148_LCSR_DDAT_SUP (1<<5)
1334#define TSI148_LCSR_DDAT_PGM (1<<4)
1335
1336#define TSI148_LCSR_DDAT_AMODE_M (0xf<<0)
1337#define TSI148_LCSR_DDAT_AMODE_A16 (0<<0)
1338#define TSI148_LCSR_DDAT_AMODE_A24 (1<<0)
1339#define TSI148_LCSR_DDAT_AMODE_A32 (2<<0)
1340#define TSI148_LCSR_DDAT_AMODE_A64 (4<<0)
1341#define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0)
1342#define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0)
1343#define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0)
1344#define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0)
1345#define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0)
1346
1347
1348
1349
1350#define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF<<6)
1351#define TSI148_LCSR_DNLAL_LLA (1<<0)
1352
1353
1354
1355
1356#define TSI148_LCSR_DBS_M (0x1FFFFF<<0)
1357
1358
1359
1360
1361
1362
1363
1364
1365#define TSI148_GCSR_GCTRL_LRST (1<<15)
1366#define TSI148_GCSR_GCTRL_SFAILEN (1<<14)
1367#define TSI148_GCSR_GCTRL_BDFAILS (1<<13)
1368#define TSI148_GCSR_GCTRL_SCON (1<<12)
1369#define TSI148_GCSR_GCTRL_MEN (1<<11)
1370
1371#define TSI148_GCSR_GCTRL_LMI3S (1<<7)
1372#define TSI148_GCSR_GCTRL_LMI2S (1<<6)
1373#define TSI148_GCSR_GCTRL_LMI1S (1<<5)
1374#define TSI148_GCSR_GCTRL_LMI0S (1<<4)
1375#define TSI148_GCSR_GCTRL_MBI3S (1<<3)
1376#define TSI148_GCSR_GCTRL_MBI2S (1<<2)
1377#define TSI148_GCSR_GCTRL_MBI1S (1<<1)
1378#define TSI148_GCSR_GCTRL_MBI0S (1<<0)
1379
1380#define TSI148_GCSR_GAP (1<<5)
1381#define TSI148_GCSR_GA_M (0x1F<<0)
1382
1383
1384
1385
1386
1387
1388
1389
1390#define TSI148_CRCSR_CSRBCR_LRSTC (1<<7)
1391#define TSI148_CRCSR_CSRBCR_SFAILC (1<<6)
1392#define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5)
1393#define TSI148_CRCSR_CSRBCR_MENC (1<<4)
1394#define TSI148_CRCSR_CSRBCR_BERRSC (1<<3)
1395
1396
1397
1398
1399#define TSI148_CRCSR_CSRBSR_LISTS (1<<7)
1400#define TSI148_CRCSR_CSRBSR_SFAILS (1<<6)
1401#define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5)
1402#define TSI148_CRCSR_CSRBSR_MENS (1<<4)
1403#define TSI148_CRCSR_CSRBSR_BERRS (1<<3)
1404
1405
1406
1407
1408#define TSI148_CRCSR_CBAR_M (0x1F<<3)
1409
1410#endif
1411