LXR linux/include/linux/mtd/nand.h

   1/*
   2 *  linux/include/linux/mtd/nand.h
   3 *
   4 *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5 *                        Steven J. Hill <sjhill@realitydiluted.com>
   6 *                        Thomas Gleixner <tglx@linutronix.de>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * Info:
  13 *      Contains standard defines and IDs for NAND flash devices
  14 *
  15 * Changelog:
  16 *      See git changelog.
  17 */
  18#ifndef __LINUX_MTD_NAND_H
  19#define __LINUX_MTD_NAND_H
  20
  21#include <linux/wait.h>
  22#include <linux/spinlock.h>
  23#include <linux/mtd/mtd.h>
  24#include <linux/mtd/flashchip.h>
  25#include <linux/mtd/bbm.h>
  26
  27struct mtd_info;
  28struct nand_flash_dev;
  29/* Scan and identify a NAND device */
  30extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31/*
  32 * Separate phases of nand_scan(), allowing board driver to intervene
  33 * and override command or ECC setup according to flash type.
  34 */
  35extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                           struct nand_flash_dev *table);
  37extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39/* Free resources held by the NAND device */
  40extern void nand_release(struct mtd_info *mtd);
  41
  42/* Internal helper for board drivers which need to override command function */
  43extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45/* locks all blocks present in the device */
  46extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48/* unlocks specified locked blocks */
  49extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51/* The maximum number of NAND chips in an array */
  52#define NAND_MAX_CHIPS          8
  53
  54/*
  55 * This constant declares the max. oobsize / page, which
  56 * is supported now. If you add a chip with bigger oobsize/page
  57 * adjust this accordingly.
  58 */
  59#define NAND_MAX_OOBSIZE        640
  60#define NAND_MAX_PAGESIZE       8192
  61
  62/*
  63 * Constants for hardware specific CLE/ALE/NCE function
  64 *
  65 * These are bits which can be or'ed to set/clear multiple
  66 * bits in one go.
  67 */
  68/* Select the chip by setting nCE to low */
  69#define NAND_NCE                0x01
  70/* Select the command latch by setting CLE to high */
  71#define NAND_CLE                0x02
  72/* Select the address latch by setting ALE to high */
  73#define NAND_ALE                0x04
  74
  75#define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76#define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77#define NAND_CTRL_CHANGE        0x80
  78
  79/*
  80 * Standard NAND flash commands
  81 */
  82#define NAND_CMD_READ0          0
  83#define NAND_CMD_READ1          1
  84#define NAND_CMD_RNDOUT         5
  85#define NAND_CMD_PAGEPROG       0x10
  86#define NAND_CMD_READOOB        0x50
  87#define NAND_CMD_ERASE1         0x60
  88#define NAND_CMD_STATUS         0x70
  89#define NAND_CMD_STATUS_MULTI   0x71
  90#define NAND_CMD_SEQIN          0x80
  91#define NAND_CMD_RNDIN          0x85
  92#define NAND_CMD_READID         0x90
  93#define NAND_CMD_ERASE2         0xd0
  94#define NAND_CMD_PARAM          0xec
  95#define NAND_CMD_GET_FEATURES   0xee
  96#define NAND_CMD_SET_FEATURES   0xef
  97#define NAND_CMD_RESET          0xff
  98
  99#define NAND_CMD_LOCK           0x2a
 100#define NAND_CMD_UNLOCK1        0x23
 101#define NAND_CMD_UNLOCK2        0x24
 102
 103/* Extended commands for large page devices */
 104#define NAND_CMD_READSTART      0x30
 105#define NAND_CMD_RNDOUTSTART    0xE0
 106#define NAND_CMD_CACHEDPROG     0x15
 107
 108/* Extended commands for AG-AND device */
 109/*
 110 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 111 *       there is no way to distinguish that from NAND_CMD_READ0
 112 *       until the remaining sequence of commands has been completed
 113 *       so add a high order bit and mask it off in the command.
 114 */
 115#define NAND_CMD_DEPLETE1       0x100
 116#define NAND_CMD_DEPLETE2       0x38
 117#define NAND_CMD_STATUS_MULTI   0x71
 118#define NAND_CMD_STATUS_ERROR   0x72
 119/* multi-bank error status (banks 0-3) */
 120#define NAND_CMD_STATUS_ERROR0  0x73
 121#define NAND_CMD_STATUS_ERROR1  0x74
 122#define NAND_CMD_STATUS_ERROR2  0x75
 123#define NAND_CMD_STATUS_ERROR3  0x76
 124#define NAND_CMD_STATUS_RESET   0x7f
 125#define NAND_CMD_STATUS_CLEAR   0xff
 126
 127#define NAND_CMD_NONE           -1
 128
 129/* Status bits */
 130#define NAND_STATUS_FAIL        0x01
 131#define NAND_STATUS_FAIL_N1     0x02
 132#define NAND_STATUS_TRUE_READY  0x20
 133#define NAND_STATUS_READY       0x40
 134#define NAND_STATUS_WP          0x80
 135
 136/*
 137 * Constants for ECC_MODES
 138 */
 139typedef enum {
 140        NAND_ECC_NONE,
 141        NAND_ECC_SOFT,
 142        NAND_ECC_HW,
 143        NAND_ECC_HW_SYNDROME,
 144        NAND_ECC_HW_OOB_FIRST,
 145        NAND_ECC_SOFT_BCH,
 146} nand_ecc_modes_t;
 147
 148/*
 149 * Constants for Hardware ECC
 150 */
 151/* Reset Hardware ECC for read */
 152#define NAND_ECC_READ           0
 153/* Reset Hardware ECC for write */
 154#define NAND_ECC_WRITE          1
 155/* Enable Hardware ECC before syndrome is read back from flash */
 156#define NAND_ECC_READSYN        2
 157
 158/* Bit mask for flags passed to do_nand_read_ecc */
 159#define NAND_GET_DEVICE         0x80
 160
 161
 162/*
 163 * Option constants for bizarre disfunctionality and real
 164 * features.
 165 */
 166/* Buswidth is 16 bit */
 167#define NAND_BUSWIDTH_16        0x00000002
 168/* Device supports partial programming without padding */
 169#define NAND_NO_PADDING         0x00000004
 170/* Chip has cache program function */
 171#define NAND_CACHEPRG           0x00000008
 172/* Chip has copy back function */
 173#define NAND_COPYBACK           0x00000010
 174/*
 175 * AND Chip which has 4 banks and a confusing page / block
 176 * assignment. See Renesas datasheet for further information.
 177 */
 178#define NAND_IS_AND             0x00000020
 179/*
 180 * Chip has a array of 4 pages which can be read without
 181 * additional ready /busy waits.
 182 */
 183#define NAND_4PAGE_ARRAY        0x00000040
 184/*
 185 * Chip requires that BBT is periodically rewritten to prevent
 186 * bits from adjacent blocks from 'leaking' in altering data.
 187 * This happens with the Renesas AG-AND chips, possibly others.
 188 */
 189#define BBT_AUTO_REFRESH        0x00000080
 190/* Chip does not allow subpage writes */
 191#define NAND_NO_SUBPAGE_WRITE   0x00000200
 192
 193/* Device is one of 'new' xD cards that expose fake nand command set */
 194#define NAND_BROKEN_XD          0x00000400
 195
 196/* Device behaves just like nand, but is readonly */
 197#define NAND_ROM                0x00000800
 198
 199/* Device supports subpage reads */
 200#define NAND_SUBPAGE_READ       0x00001000
 201
 202/* Options valid for Samsung large page devices */
 203#define NAND_SAMSUNG_LP_OPTIONS \
 204        (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 205
 206/* Macros to identify the above */
 207#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 208#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 209#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 210#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 211
 212/* Non chip related options */
 213/* This option skips the bbt scan during initialization. */
 214#define NAND_SKIP_BBTSCAN       0x00010000
 215/*
 216 * This option is defined if the board driver allocates its own buffers
 217 * (e.g. because it needs them DMA-coherent).
 218 */
 219#define NAND_OWN_BUFFERS        0x00020000
 220/* Chip may not exist, so silence any errors in scan */
 221#define NAND_SCAN_SILENT_NODEV  0x00040000
 222/*
 223 * Autodetect nand buswidth with readid/onfi.
 224 * This suppose the driver will configure the hardware in 8 bits mode
 225 * when calling nand_scan_ident, and update its configuration
 226 * before calling nand_scan_tail.
 227 */
 228#define NAND_BUSWIDTH_AUTO      0x00080000
 229
 230/* Options set by nand scan */
 231/* Nand scan has allocated controller struct */
 232#define NAND_CONTROLLER_ALLOC   0x80000000
 233
 234/* Cell info constants */
 235#define NAND_CI_CHIPNR_MSK      0x03
 236#define NAND_CI_CELLTYPE_MSK    0x0C
 237
 238/* Keep gcc happy */
 239struct nand_chip;
 240
 241/* ONFI timing mode, used in both asynchronous and synchronous mode */
 242#define ONFI_TIMING_MODE_0              (1 << 0)
 243#define ONFI_TIMING_MODE_1              (1 << 1)
 244#define ONFI_TIMING_MODE_2              (1 << 2)
 245#define ONFI_TIMING_MODE_3              (1 << 3)
 246#define ONFI_TIMING_MODE_4              (1 << 4)
 247#define ONFI_TIMING_MODE_5              (1 << 5)
 248#define ONFI_TIMING_MODE_UNKNOWN        (1 << 6)
 249
 250/* ONFI feature address */
 251#define ONFI_FEATURE_ADDR_TIMING_MODE   0x1
 252
 253/* ONFI subfeature parameters length */
 254#define ONFI_SUBFEATURE_PARAM_LEN       4
 255
 256struct nand_onfi_params {
 257        /* rev info and features block */
 258        /* 'O' 'N' 'F' 'I'  */
 259        u8 sig[4];
 260        __le16 revision;
 261        __le16 features;
 262        __le16 opt_cmd;
 263        u8 reserved[22];
 264
 265        /* manufacturer information block */
 266        char manufacturer[12];
 267        char model[20];
 268        u8 jedec_id;
 269        __le16 date_code;
 270        u8 reserved2[13];
 271
 272        /* memory organization block */
 273        __le32 byte_per_page;
 274        __le16 spare_bytes_per_page;
 275        __le32 data_bytes_per_ppage;
 276        __le16 spare_bytes_per_ppage;
 277        __le32 pages_per_block;
 278        __le32 blocks_per_lun;
 279        u8 lun_count;
 280        u8 addr_cycles;
 281        u8 bits_per_cell;
 282        __le16 bb_per_lun;
 283        __le16 block_endurance;
 284        u8 guaranteed_good_blocks;
 285        __le16 guaranteed_block_endurance;
 286        u8 programs_per_page;
 287        u8 ppage_attr;
 288        u8 ecc_bits;
 289        u8 interleaved_bits;
 290        u8 interleaved_ops;
 291        u8 reserved3[13];
 292
 293        /* electrical parameter block */
 294        u8 io_pin_capacitance_max;
 295        __le16 async_timing_mode;
 296        __le16 program_cache_timing_mode;
 297        __le16 t_prog;
 298        __le16 t_bers;
 299        __le16 t_r;
 300        __le16 t_ccs;
 301        __le16 src_sync_timing_mode;
 302        __le16 src_ssync_features;
 303        __le16 clk_pin_capacitance_typ;
 304        __le16 io_pin_capacitance_typ;
 305        __le16 input_pin_capacitance_typ;
 306        u8 input_pin_capacitance_max;
 307        u8 driver_strenght_support;
 308        __le16 t_int_r;
 309        __le16 t_ald;
 310        u8 reserved4[7];
 311
 312        /* vendor */
 313        u8 reserved5[90];
 314
 315        __le16 crc;
 316} __attribute__((packed));
 317
 318#define ONFI_CRC_BASE   0x4F4E
 319
 320/**
 321 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 322 * @lock:               protection lock
 323 * @active:             the mtd device which holds the controller currently
 324 * @wq:                 wait queue to sleep on if a NAND operation is in
 325 *                      progress used instead of the per chip wait queue
 326 *                      when a hw controller is available.
 327 */
 328struct nand_hw_control {
 329        spinlock_t lock;
 330        struct nand_chip *active;
 331        wait_queue_head_t wq;
 332};
 333
 334/**
 335 * struct nand_ecc_ctrl - Control structure for ECC
 336 * @mode:       ECC mode
 337 * @steps:      number of ECC steps per page
 338 * @size:       data bytes per ECC step
 339 * @bytes:      ECC bytes per step
 340 * @strength:   max number of correctible bits per ECC step
 341 * @total:      total number of ECC bytes per page
 342 * @prepad:     padding information for syndrome based ECC generators
 343 * @postpad:    padding information for syndrome based ECC generators
 344 * @layout:     ECC layout control struct pointer
 345 * @priv:       pointer to private ECC control data
 346 * @hwctl:      function to control hardware ECC generator. Must only
 347 *              be provided if an hardware ECC is available
 348 * @calculate:  function for ECC calculation or readback from ECC hardware
 349 * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 350 * @read_page_raw:      function to read a raw page without ECC
 351 * @write_page_raw:     function to write a raw page without ECC
 352 * @read_page:  function to read a page according to the ECC generator
 353 *              requirements; returns maximum number of bitflips corrected in
 354 *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
 355 * @read_subpage:       function to read parts of the page covered by ECC;
 356 *                      returns same as read_page()
 357 * @write_page: function to write a page according to the ECC generator
 358 *              requirements.
 359 * @write_oob_raw:      function to write chip OOB data without ECC
 360 * @read_oob_raw:       function to read chip OOB data without ECC
 361 * @read_oob:   function to read chip OOB data
 362 * @write_oob:  function to write chip OOB data
 363 */
 364struct nand_ecc_ctrl {
 365        nand_ecc_modes_t mode;
 366        int steps;
 367        int size;
 368        int bytes;
 369        int total;
 370        int strength;
 371        int prepad;
 372        int postpad;
 373        struct nand_ecclayout   *layout;
 374        void *priv;
 375        void (*hwctl)(struct mtd_info *mtd, int mode);
 376        int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 377                        uint8_t *ecc_code);
 378        int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 379                        uint8_t *calc_ecc);
 380        int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 381                        uint8_t *buf, int oob_required, int page);
 382        int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 383                        const uint8_t *buf, int oob_required);
 384        int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 385                        uint8_t *buf, int oob_required, int page);
 386        int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 387                        uint32_t offs, uint32_t len, uint8_t *buf);
 388        int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 389                        const uint8_t *buf, int oob_required);
 390        int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 391                        int page);
 392        int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 393                        int page);
 394        int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
 395        int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 396                        int page);
 397};
 398
 399/**
 400 * struct nand_buffers - buffer structure for read/write
 401 * @ecccalc:    buffer for calculated ECC
 402 * @ecccode:    buffer for ECC read from flash
 403 * @databuf:    buffer for data - dynamically sized
 404 *
 405 * Do not change the order of buffers. databuf and oobrbuf must be in
 406 * consecutive order.
 407 */
 408struct nand_buffers {
 409        uint8_t ecccalc[NAND_MAX_OOBSIZE];
 410        uint8_t ecccode[NAND_MAX_OOBSIZE];
 411        uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 412};
 413
 414/**
 415 * struct nand_chip - NAND Private Flash Chip Data
 416 * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 417 *                      flash device
 418 * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 419 *                      flash device.
 420 * @read_byte:          [REPLACEABLE] read one byte from the chip
 421 * @read_word:          [REPLACEABLE] read one word from the chip
 422 * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 423 * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 424 * @select_chip:        [REPLACEABLE] select chip nr
 425 * @block_bad:          [REPLACEABLE] check, if the block is bad
 426 * @block_markbad:      [REPLACEABLE] mark the block bad
 427 * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 428 *                      ALE/CLE/nCE. Also used to write command and address
 429 * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 430 *                      mtd->oobsize, mtd->writesize and so on.
 431 *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 432 *                      Return with the bus width.
 433 * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 434 *                      device ready/busy line. If set to NULL no access to
 435 *                      ready/busy is available and the ready/busy information
 436 *                      is read from the chip status register.
 437 * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 438 *                      commands to the chip.
 439 * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 440 *                      ready.
 441 * @ecc:                [BOARDSPECIFIC] ECC control structure
 442 * @buffers:            buffer structure for read/write
 443 * @hwcontrol:          platform-specific hardware control structure
 444 * @erase_cmd:          [INTERN] erase command write function, selectable due
 445 *                      to AND support.
 446 * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 447 * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 448 *                      data from array to read regs (tR).
 449 * @state:              [INTERN] the current state of the NAND device
 450 * @oob_poi:            "poison value buffer," used for laying out OOB data
 451 *                      before writing
 452 * @page_shift:         [INTERN] number of address bits in a page (column
 453 *                      address bits).
 454 * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 455 * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 456 * @chip_shift:         [INTERN] number of address bits in one chip
 457 * @options:            [BOARDSPECIFIC] various chip options. They can partly
 458 *                      be set to inform nand_scan about special functionality.
 459 *                      See the defines for further explanation.
 460 * @bbt_options:        [INTERN] bad block specific options. All options used
 461 *                      here must come from bbm.h. By default, these options
 462 *                      will be copied to the appropriate nand_bbt_descr's.
 463 * @badblockpos:        [INTERN] position of the bad block marker in the oob
 464 *                      area.
 465 * @badblockbits:       [INTERN] minimum number of set bits in a good block's
 466 *                      bad block marker position; i.e., BBM == 11110111b is
 467 *                      not bad when badblockbits == 7
 468 * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 469 * @numchips:           [INTERN] number of physical chips
 470 * @chipsize:           [INTERN] the size of one chip for multichip arrays
 471 * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 472 * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 473 *                      data_buf.
 474 * @pagebuf_bitflips:   [INTERN] holds the bitflip count for the page which is
 475 *                      currently in data_buf.
 476 * @subpagesize:        [INTERN] holds the subpagesize
 477 * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 478 *                      non 0 if ONFI supported.
 479 * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 480 *                      supported, 0 otherwise.
 481 * @onfi_set_features:  [REPLACEABLE] set the features for ONFI nand
 482 * @onfi_get_features:  [REPLACEABLE] get the features for ONFI nand
 483 * @ecclayout:          [REPLACEABLE] the default ECC placement scheme
 484 * @bbt:                [INTERN] bad block table pointer
 485 * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 486 *                      lookup.
 487 * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 488 * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 489 *                      bad block scan.
 490 * @controller:         [REPLACEABLE] a pointer to a hardware controller
 491 *                      structure which is shared among multiple independent
 492 *                      devices.
 493 * @priv:               [OPTIONAL] pointer to private chip data
 494 * @errstat:            [OPTIONAL] hardware specific function to perform
 495 *                      additional error status checks (determine if errors are
 496 *                      correctable).
 497 * @write_page:         [REPLACEABLE] High-level page write function
 498 */
 499
 500struct nand_chip {
 501        void __iomem *IO_ADDR_R;
 502        void __iomem *IO_ADDR_W;
 503
 504        uint8_t (*read_byte)(struct mtd_info *mtd);
 505        u16 (*read_word)(struct mtd_info *mtd);
 506        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 507        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 508        void (*select_chip)(struct mtd_info *mtd, int chip);
 509        int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 510        int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 511        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 512        int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 513                        u8 *id_data);
 514        int (*dev_ready)(struct mtd_info *mtd);
 515        void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 516                        int page_addr);
 517        int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 518        void (*erase_cmd)(struct mtd_info *mtd, int page);
 519        int (*scan_bbt)(struct mtd_info *mtd);
 520        int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 521                        int status, int page);
 522        int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 523                        const uint8_t *buf, int oob_required, int page,
 524                        int cached, int raw);
 525        int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
 526                        int feature_addr, uint8_t *subfeature_para);
 527        int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
 528                        int feature_addr, uint8_t *subfeature_para);
 529
 530        int chip_delay;
 531        unsigned int options;
 532        unsigned int bbt_options;
 533
 534        int page_shift;
 535        int phys_erase_shift;
 536        int bbt_erase_shift;
 537        int chip_shift;
 538        int numchips;
 539        uint64_t chipsize;
 540        int pagemask;
 541        int pagebuf;
 542        unsigned int pagebuf_bitflips;
 543        int subpagesize;
 544        uint8_t cellinfo;
 545        int badblockpos;
 546        int badblockbits;
 547
 548        int onfi_version;
 549        struct nand_onfi_params onfi_params;
 550
 551        flstate_t state;
 552
 553        uint8_t *oob_poi;
 554        struct nand_hw_control *controller;
 555        struct nand_ecclayout *ecclayout;
 556
 557        struct nand_ecc_ctrl ecc;
 558        struct nand_buffers *buffers;
 559        struct nand_hw_control hwcontrol;
 560
 561        uint8_t *bbt;
 562        struct nand_bbt_descr *bbt_td;
 563        struct nand_bbt_descr *bbt_md;
 564
 565        struct nand_bbt_descr *badblock_pattern;
 566
 567        void *priv;
 568};
 569
 570/*
 571 * NAND Flash Manufacturer ID Codes
 572 */
 573#define NAND_MFR_TOSHIBA        0x98
 574#define NAND_MFR_SAMSUNG        0xec
 575#define NAND_MFR_FUJITSU        0x04
 576#define NAND_MFR_NATIONAL       0x8f
 577#define NAND_MFR_RENESAS        0x07
 578#define NAND_MFR_STMICRO        0x20
 579#define NAND_MFR_HYNIX          0xad
 580#define NAND_MFR_MICRON         0x2c
 581#define NAND_MFR_AMD            0x01
 582#define NAND_MFR_MACRONIX       0xc2
 583#define NAND_MFR_EON            0x92
 584
 585/**
 586 * struct nand_flash_dev - NAND Flash Device ID Structure
 587 * @name:       Identify the device type
 588 * @id:         device ID code
 589 * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 590 *              If the pagesize is 0, then the real pagesize
 591 *              and the eraseize are determined from the
 592 *              extended id bytes in the chip
 593 * @erasesize:  Size of an erase block in the flash device.
 594 * @chipsize:   Total chipsize in Mega Bytes
 595 * @options:    Bitfield to store chip relevant options
 596 */
 597struct nand_flash_dev {
 598        char *name;
 599        int id;
 600        unsigned long pagesize;
 601        unsigned long chipsize;
 602        unsigned long erasesize;
 603        unsigned long options;
 604};
 605
 606/**
 607 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 608 * @name:       Manufacturer name
 609 * @id:         manufacturer ID code of device.
 610*/
 611struct nand_manufacturers {
 612        int id;
 613        char *name;
 614};
 615
 616extern struct nand_flash_dev nand_flash_ids[];
 617extern struct nand_manufacturers nand_manuf_ids[];
 618
 619extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 620extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 621extern int nand_default_bbt(struct mtd_info *mtd);
 622extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 623extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 624                           int allowbbt);
 625extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 626                        size_t *retlen, uint8_t *buf);
 627
 628/**
 629 * struct platform_nand_chip - chip level device structure
 630 * @nr_chips:           max. number of chips to scan for
 631 * @chip_offset:        chip number offset
 632 * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 633 * @partitions:         mtd partition list
 634 * @chip_delay:         R/B delay value in us
 635 * @options:            Option flags, e.g. 16bit buswidth
 636 * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 637 * @ecclayout:          ECC layout info structure
 638 * @part_probe_types:   NULL-terminated array of probe types
 639 */
 640struct platform_nand_chip {
 641        int nr_chips;
 642        int chip_offset;
 643        int nr_partitions;
 644        struct mtd_partition *partitions;
 645        struct nand_ecclayout *ecclayout;
 646        int chip_delay;
 647        unsigned int options;
 648        unsigned int bbt_options;
 649        const char **part_probe_types;
 650};
 651
 652/* Keep gcc happy */
 653struct platform_device;
 654
 655/**
 656 * struct platform_nand_ctrl - controller level device structure
 657 * @probe:              platform specific function to probe/setup hardware
 658 * @remove:             platform specific function to remove/teardown hardware
 659 * @hwcontrol:          platform specific hardware control structure
 660 * @dev_ready:          platform specific function to read ready/busy pin
 661 * @select_chip:        platform specific chip select function
 662 * @cmd_ctrl:           platform specific function for controlling
 663 *                      ALE/CLE/nCE. Also used to write command and address
 664 * @write_buf:          platform specific function for write buffer
 665 * @read_buf:           platform specific function for read buffer
 666 * @read_byte:          platform specific function to read one byte from chip
 667 * @priv:               private data to transport driver specific settings
 668 *
 669 * All fields are optional and depend on the hardware driver requirements
 670 */
 671struct platform_nand_ctrl {
 672        int (*probe)(struct platform_device *pdev);
 673        void (*remove)(struct platform_device *pdev);
 674        void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 675        int (*dev_ready)(struct mtd_info *mtd);
 676        void (*select_chip)(struct mtd_info *mtd, int chip);
 677        void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 678        void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 679        void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 680        unsigned char (*read_byte)(struct mtd_info *mtd);
 681        void *priv;
 682};
 683
 684/**
 685 * struct platform_nand_data - container structure for platform-specific data
 686 * @chip:               chip level chip structure
 687 * @ctrl:               controller level device structure
 688 */
 689struct platform_nand_data {
 690        struct platform_nand_chip chip;
 691        struct platform_nand_ctrl ctrl;
 692};
 693
 694/* Some helpers to access the data structures */
 695static inline
 696struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 697{
 698        struct nand_chip *chip = mtd->priv;
 699
 700        return chip->priv;
 701}
 702
 703/* return the supported asynchronous timing mode. */
 704static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
 705{
 706        if (!chip->onfi_version)
 707                return ONFI_TIMING_MODE_UNKNOWN;
 708        return le16_to_cpu(chip->onfi_params.async_timing_mode);
 709}
 710
 711/* return the supported synchronous timing mode. */
 712static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
 713{
 714        if (!chip->onfi_version)
 715                return ONFI_TIMING_MODE_UNKNOWN;
 716        return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
 717}
 718
 719#endif /* __LINUX_MTD_NAND_H */
 720