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27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H
29
30#include <linux/types.h>
31
32#define DRM_DISPLAY_INFO_LEN 32
33#define DRM_CONNECTOR_NAME_LEN 32
34#define DRM_DISPLAY_MODE_LEN 32
35#define DRM_PROP_NAME_LEN 32
36
37#define DRM_MODE_TYPE_BUILTIN (1<<0)
38#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
39#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
40#define DRM_MODE_TYPE_PREFERRED (1<<3)
41#define DRM_MODE_TYPE_DEFAULT (1<<4)
42#define DRM_MODE_TYPE_USERDEF (1<<5)
43#define DRM_MODE_TYPE_DRIVER (1<<6)
44
45
46
47#define DRM_MODE_FLAG_PHSYNC (1<<0)
48#define DRM_MODE_FLAG_NHSYNC (1<<1)
49#define DRM_MODE_FLAG_PVSYNC (1<<2)
50#define DRM_MODE_FLAG_NVSYNC (1<<3)
51#define DRM_MODE_FLAG_INTERLACE (1<<4)
52#define DRM_MODE_FLAG_DBLSCAN (1<<5)
53#define DRM_MODE_FLAG_CSYNC (1<<6)
54#define DRM_MODE_FLAG_PCSYNC (1<<7)
55#define DRM_MODE_FLAG_NCSYNC (1<<8)
56#define DRM_MODE_FLAG_HSKEW (1<<9)
57#define DRM_MODE_FLAG_BCAST (1<<10)
58#define DRM_MODE_FLAG_PIXMUX (1<<11)
59#define DRM_MODE_FLAG_DBLCLK (1<<12)
60#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
61
62
63
64#define DRM_MODE_DPMS_ON 0
65#define DRM_MODE_DPMS_STANDBY 1
66#define DRM_MODE_DPMS_SUSPEND 2
67#define DRM_MODE_DPMS_OFF 3
68
69
70#define DRM_MODE_SCALE_NONE 0
71
72#define DRM_MODE_SCALE_FULLSCREEN 1
73#define DRM_MODE_SCALE_CENTER 2
74#define DRM_MODE_SCALE_ASPECT 3
75
76
77#define DRM_MODE_DITHERING_OFF 0
78#define DRM_MODE_DITHERING_ON 1
79#define DRM_MODE_DITHERING_AUTO 2
80
81
82#define DRM_MODE_DIRTY_OFF 0
83#define DRM_MODE_DIRTY_ON 1
84#define DRM_MODE_DIRTY_ANNOTATE 2
85
86struct drm_mode_modeinfo {
87 __u32 clock;
88 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
89 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
90
91 __u32 vrefresh;
92
93 __u32 flags;
94 __u32 type;
95 char name[DRM_DISPLAY_MODE_LEN];
96};
97
98struct drm_mode_card_res {
99 __u64 fb_id_ptr;
100 __u64 crtc_id_ptr;
101 __u64 connector_id_ptr;
102 __u64 encoder_id_ptr;
103 __u32 count_fbs;
104 __u32 count_crtcs;
105 __u32 count_connectors;
106 __u32 count_encoders;
107 __u32 min_width, max_width;
108 __u32 min_height, max_height;
109};
110
111struct drm_mode_crtc {
112 __u64 set_connectors_ptr;
113 __u32 count_connectors;
114
115 __u32 crtc_id;
116 __u32 fb_id;
117
118 __u32 x, y;
119
120 __u32 gamma_size;
121 __u32 mode_valid;
122 struct drm_mode_modeinfo mode;
123};
124
125#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
126#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
127
128
129struct drm_mode_set_plane {
130 __u32 plane_id;
131 __u32 crtc_id;
132 __u32 fb_id;
133 __u32 flags;
134
135
136 __s32 crtc_x, crtc_y;
137 __u32 crtc_w, crtc_h;
138
139
140 __u32 src_x, src_y;
141 __u32 src_h, src_w;
142};
143
144struct drm_mode_get_plane {
145 __u32 plane_id;
146
147 __u32 crtc_id;
148 __u32 fb_id;
149
150 __u32 possible_crtcs;
151 __u32 gamma_size;
152
153 __u32 count_format_types;
154 __u64 format_type_ptr;
155};
156
157struct drm_mode_get_plane_res {
158 __u64 plane_id_ptr;
159 __u32 count_planes;
160};
161
162#define DRM_MODE_ENCODER_NONE 0
163#define DRM_MODE_ENCODER_DAC 1
164#define DRM_MODE_ENCODER_TMDS 2
165#define DRM_MODE_ENCODER_LVDS 3
166#define DRM_MODE_ENCODER_TVDAC 4
167#define DRM_MODE_ENCODER_VIRTUAL 5
168
169struct drm_mode_get_encoder {
170 __u32 encoder_id;
171 __u32 encoder_type;
172
173 __u32 crtc_id;
174
175 __u32 possible_crtcs;
176 __u32 possible_clones;
177};
178
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180
181#define DRM_MODE_SUBCONNECTOR_Automatic 0
182#define DRM_MODE_SUBCONNECTOR_Unknown 0
183#define DRM_MODE_SUBCONNECTOR_DVID 3
184#define DRM_MODE_SUBCONNECTOR_DVIA 4
185#define DRM_MODE_SUBCONNECTOR_Composite 5
186#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
187#define DRM_MODE_SUBCONNECTOR_Component 8
188#define DRM_MODE_SUBCONNECTOR_SCART 9
189
190#define DRM_MODE_CONNECTOR_Unknown 0
191#define DRM_MODE_CONNECTOR_VGA 1
192#define DRM_MODE_CONNECTOR_DVII 2
193#define DRM_MODE_CONNECTOR_DVID 3
194#define DRM_MODE_CONNECTOR_DVIA 4
195#define DRM_MODE_CONNECTOR_Composite 5
196#define DRM_MODE_CONNECTOR_SVIDEO 6
197#define DRM_MODE_CONNECTOR_LVDS 7
198#define DRM_MODE_CONNECTOR_Component 8
199#define DRM_MODE_CONNECTOR_9PinDIN 9
200#define DRM_MODE_CONNECTOR_DisplayPort 10
201#define DRM_MODE_CONNECTOR_HDMIA 11
202#define DRM_MODE_CONNECTOR_HDMIB 12
203#define DRM_MODE_CONNECTOR_TV 13
204#define DRM_MODE_CONNECTOR_eDP 14
205#define DRM_MODE_CONNECTOR_VIRTUAL 15
206
207struct drm_mode_get_connector {
208
209 __u64 encoders_ptr;
210 __u64 modes_ptr;
211 __u64 props_ptr;
212 __u64 prop_values_ptr;
213
214 __u32 count_modes;
215 __u32 count_props;
216 __u32 count_encoders;
217
218 __u32 encoder_id;
219 __u32 connector_id;
220 __u32 connector_type;
221 __u32 connector_type_id;
222
223 __u32 connection;
224 __u32 mm_width, mm_height;
225 __u32 subpixel;
226};
227
228#define DRM_MODE_PROP_PENDING (1<<0)
229#define DRM_MODE_PROP_RANGE (1<<1)
230#define DRM_MODE_PROP_IMMUTABLE (1<<2)
231#define DRM_MODE_PROP_ENUM (1<<3)
232#define DRM_MODE_PROP_BLOB (1<<4)
233#define DRM_MODE_PROP_BITMASK (1<<5)
234
235struct drm_mode_property_enum {
236 __u64 value;
237 char name[DRM_PROP_NAME_LEN];
238};
239
240struct drm_mode_get_property {
241 __u64 values_ptr;
242 __u64 enum_blob_ptr;
243
244 __u32 prop_id;
245 __u32 flags;
246 char name[DRM_PROP_NAME_LEN];
247
248 __u32 count_values;
249 __u32 count_enum_blobs;
250};
251
252struct drm_mode_connector_set_property {
253 __u64 value;
254 __u32 prop_id;
255 __u32 connector_id;
256};
257
258struct drm_mode_obj_get_properties {
259 __u64 props_ptr;
260 __u64 prop_values_ptr;
261 __u32 count_props;
262 __u32 obj_id;
263 __u32 obj_type;
264};
265
266struct drm_mode_obj_set_property {
267 __u64 value;
268 __u32 prop_id;
269 __u32 obj_id;
270 __u32 obj_type;
271};
272
273struct drm_mode_get_blob {
274 __u32 blob_id;
275 __u32 length;
276 __u64 data;
277};
278
279struct drm_mode_fb_cmd {
280 __u32 fb_id;
281 __u32 width, height;
282 __u32 pitch;
283 __u32 bpp;
284 __u32 depth;
285
286 __u32 handle;
287};
288
289#define DRM_MODE_FB_INTERLACED (1<<0)
290
291struct drm_mode_fb_cmd2 {
292 __u32 fb_id;
293 __u32 width, height;
294 __u32 pixel_format;
295 __u32 flags;
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311 __u32 handles[4];
312 __u32 pitches[4];
313 __u32 offsets[4];
314};
315
316#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
317#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
318#define DRM_MODE_FB_DIRTY_FLAGS 0x03
319
320#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
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349struct drm_mode_fb_dirty_cmd {
350 __u32 fb_id;
351 __u32 flags;
352 __u32 color;
353 __u32 num_clips;
354 __u64 clips_ptr;
355};
356
357struct drm_mode_mode_cmd {
358 __u32 connector_id;
359 struct drm_mode_modeinfo mode;
360};
361
362#define DRM_MODE_CURSOR_BO 0x01
363#define DRM_MODE_CURSOR_MOVE 0x02
364#define DRM_MODE_CURSOR_FLAGS 0x03
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380struct drm_mode_cursor {
381 __u32 flags;
382 __u32 crtc_id;
383 __s32 x;
384 __s32 y;
385 __u32 width;
386 __u32 height;
387
388 __u32 handle;
389};
390
391struct drm_mode_crtc_lut {
392 __u32 crtc_id;
393 __u32 gamma_size;
394
395
396 __u64 red;
397 __u64 green;
398 __u64 blue;
399};
400
401#define DRM_MODE_PAGE_FLIP_EVENT 0x01
402#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
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426struct drm_mode_crtc_page_flip {
427 __u32 crtc_id;
428 __u32 fb_id;
429 __u32 flags;
430 __u32 reserved;
431 __u64 user_data;
432};
433
434
435struct drm_mode_create_dumb {
436 uint32_t height;
437 uint32_t width;
438 uint32_t bpp;
439 uint32_t flags;
440
441 uint32_t handle;
442 uint32_t pitch;
443 uint64_t size;
444};
445
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447struct drm_mode_map_dumb {
448
449 __u32 handle;
450 __u32 pad;
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456 __u64 offset;
457};
458
459struct drm_mode_destroy_dumb {
460 uint32_t handle;
461};
462
463#endif
464