linux/sound/soc/codecs/wm8988.c
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   1/*
   2 * wm8988.c -- WM8988 ALSA SoC audio driver
   3 *
   4 * Copyright 2009 Wolfson Microelectronics plc
   5 * Copyright 2005 Openedhand Ltd.
   6 *
   7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/moduleparam.h>
  16#include <linux/init.h>
  17#include <linux/delay.h>
  18#include <linux/pm.h>
  19#include <linux/i2c.h>
  20#include <linux/spi/spi.h>
  21#include <linux/slab.h>
  22#include <sound/core.h>
  23#include <sound/pcm.h>
  24#include <sound/pcm_params.h>
  25#include <sound/tlv.h>
  26#include <sound/soc.h>
  27#include <sound/initval.h>
  28
  29#include "wm8988.h"
  30
  31/*
  32 * wm8988 register cache
  33 * We can't read the WM8988 register space when we
  34 * are using 2 wire for device control, so we cache them instead.
  35 */
  36static const struct reg_default wm8988_reg_defaults[] = {
  37        { 0, 0x0097 },
  38        { 1, 0x0097 },
  39        { 2, 0x0079 },
  40        { 3, 0x0079 },
  41        { 5, 0x0008 },
  42        { 7, 0x000a },
  43        { 8, 0x0000 },
  44        { 10, 0x00ff },
  45        { 11, 0x00ff },
  46        { 12, 0x000f },
  47        { 13, 0x000f },
  48        { 16, 0x0000 },
  49        { 17, 0x007b },
  50        { 18, 0x0000 },
  51        { 19, 0x0032 },
  52        { 20, 0x0000 },
  53        { 21, 0x00c3 },
  54        { 22, 0x00c3 },
  55        { 23, 0x00c0 },
  56        { 24, 0x0000 },
  57        { 25, 0x0000 },
  58        { 26, 0x0000 },
  59        { 27, 0x0000 },
  60        { 31, 0x0000 },
  61        { 32, 0x0000 },
  62        { 33, 0x0000 },
  63        { 34, 0x0050 },
  64        { 35, 0x0050 },
  65        { 36, 0x0050 },
  66        { 37, 0x0050 },
  67        { 40, 0x0079 },
  68        { 41, 0x0079 },
  69        { 42, 0x0079 },
  70};
  71
  72static bool wm8988_writeable(struct device *dev, unsigned int reg)
  73{
  74        switch (reg) {
  75        case WM8988_LINVOL:
  76        case WM8988_RINVOL:
  77        case WM8988_LOUT1V:
  78        case WM8988_ROUT1V:
  79        case WM8988_ADCDAC:
  80        case WM8988_IFACE:
  81        case WM8988_SRATE:
  82        case WM8988_LDAC:
  83        case WM8988_RDAC:
  84        case WM8988_BASS:
  85        case WM8988_TREBLE:
  86        case WM8988_RESET:
  87        case WM8988_3D:
  88        case WM8988_ALC1:
  89        case WM8988_ALC2:
  90        case WM8988_ALC3:
  91        case WM8988_NGATE:
  92        case WM8988_LADC:
  93        case WM8988_RADC:
  94        case WM8988_ADCTL1:
  95        case WM8988_ADCTL2:
  96        case WM8988_PWR1:
  97        case WM8988_PWR2:
  98        case WM8988_ADCTL3:
  99        case WM8988_ADCIN:
 100        case WM8988_LADCIN:
 101        case WM8988_RADCIN:
 102        case WM8988_LOUTM1:
 103        case WM8988_LOUTM2:
 104        case WM8988_ROUTM1:
 105        case WM8988_ROUTM2:
 106        case WM8988_LOUT2V:
 107        case WM8988_ROUT2V:
 108        case WM8988_LPPB:
 109                return true;
 110        default:
 111                return false;
 112        }
 113}
 114
 115/* codec private data */
 116struct wm8988_priv {
 117        struct regmap *regmap;
 118        unsigned int sysclk;
 119        struct snd_pcm_hw_constraint_list *sysclk_constraints;
 120};
 121
 122#define wm8988_reset(c) snd_soc_write(c, WM8988_RESET, 0)
 123
 124/*
 125 * WM8988 Controls
 126 */
 127
 128static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
 129static const struct soc_enum bass_boost =
 130        SOC_ENUM_SINGLE(WM8988_BASS, 7, 2, bass_boost_txt);
 131
 132static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
 133static const struct soc_enum bass_filter =
 134        SOC_ENUM_SINGLE(WM8988_BASS, 6, 2, bass_filter_txt);
 135
 136static const char *treble_txt[] = {"8kHz", "4kHz"};
 137static const struct soc_enum treble =
 138        SOC_ENUM_SINGLE(WM8988_TREBLE, 6, 2, treble_txt);
 139
 140static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
 141static const struct soc_enum stereo_3d_lc =
 142        SOC_ENUM_SINGLE(WM8988_3D, 5, 2, stereo_3d_lc_txt);
 143
 144static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
 145static const struct soc_enum stereo_3d_uc =
 146        SOC_ENUM_SINGLE(WM8988_3D, 6, 2, stereo_3d_uc_txt);
 147
 148static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
 149static const struct soc_enum stereo_3d_func =
 150        SOC_ENUM_SINGLE(WM8988_3D, 7, 2, stereo_3d_func_txt);
 151
 152static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
 153static const struct soc_enum alc_func =
 154        SOC_ENUM_SINGLE(WM8988_ALC1, 7, 4, alc_func_txt);
 155
 156static const char *ng_type_txt[] = {"Constant PGA Gain",
 157                                    "Mute ADC Output"};
 158static const struct soc_enum ng_type =
 159        SOC_ENUM_SINGLE(WM8988_NGATE, 1, 2, ng_type_txt);
 160
 161static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
 162static const struct soc_enum deemph =
 163        SOC_ENUM_SINGLE(WM8988_ADCDAC, 1, 4, deemph_txt);
 164
 165static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
 166                                   "L + R Invert"};
 167static const struct soc_enum adcpol =
 168        SOC_ENUM_SINGLE(WM8988_ADCDAC, 5, 4, adcpol_txt);
 169
 170static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
 171static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
 172static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 173static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
 174static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
 175
 176static const struct snd_kcontrol_new wm8988_snd_controls[] = {
 177
 178SOC_ENUM("Bass Boost", bass_boost),
 179SOC_ENUM("Bass Filter", bass_filter),
 180SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
 181
 182SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
 183SOC_ENUM("Treble Cut-off", treble),
 184
 185SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
 186SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
 187SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
 188SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
 189SOC_ENUM("3D Mode", stereo_3d_func),
 190
 191SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
 192SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
 193SOC_ENUM("ALC Capture Function", alc_func),
 194SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
 195SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
 196SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
 197SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
 198SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
 199SOC_ENUM("ALC Capture NG Type", ng_type),
 200SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
 201
 202SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
 203
 204SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
 205                 0, 255, 0, adc_tlv),
 206SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
 207                 0, 63, 0, pga_tlv),
 208SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
 209SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
 210
 211SOC_ENUM("Playback De-emphasis", deemph),
 212
 213SOC_ENUM("Capture Polarity", adcpol),
 214SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
 215SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
 216
 217SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
 218
 219SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
 220               bypass_tlv),
 221SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
 222               bypass_tlv),
 223SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
 224               bypass_tlv),
 225SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
 226               bypass_tlv),
 227
 228SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
 229             WM8988_ROUT1V, 7, 1, 0),
 230SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
 231                 0, 127, 0, out_tlv),
 232
 233SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
 234             WM8988_ROUT2V, 7, 1, 0),
 235SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
 236                 0, 127, 0, out_tlv),
 237
 238};
 239
 240/*
 241 * DAPM Controls
 242 */
 243
 244static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
 245                              struct snd_kcontrol *kcontrol, int event)
 246{
 247        struct snd_soc_codec *codec = w->codec;
 248        u16 adctl2 = snd_soc_read(codec, WM8988_ADCTL2);
 249
 250        /* Use the DAC to gate LRC if active, otherwise use ADC */
 251        if (snd_soc_read(codec, WM8988_PWR2) & 0x180)
 252                adctl2 &= ~0x4;
 253        else
 254                adctl2 |= 0x4;
 255
 256        return snd_soc_write(codec, WM8988_ADCTL2, adctl2);
 257}
 258
 259static const char *wm8988_line_texts[] = {
 260        "Line 1", "Line 2", "PGA", "Differential"};
 261
 262static const unsigned int wm8988_line_values[] = {
 263        0, 1, 3, 4};
 264
 265static const struct soc_enum wm8988_lline_enum =
 266        SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
 267                              ARRAY_SIZE(wm8988_line_texts),
 268                              wm8988_line_texts,
 269                              wm8988_line_values);
 270static const struct snd_kcontrol_new wm8988_left_line_controls =
 271        SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
 272
 273static const struct soc_enum wm8988_rline_enum =
 274        SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
 275                              ARRAY_SIZE(wm8988_line_texts),
 276                              wm8988_line_texts,
 277                              wm8988_line_values);
 278static const struct snd_kcontrol_new wm8988_right_line_controls =
 279        SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
 280
 281/* Left Mixer */
 282static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
 283        SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
 284        SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
 285        SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
 286        SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
 287};
 288
 289/* Right Mixer */
 290static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
 291        SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
 292        SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
 293        SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
 294        SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
 295};
 296
 297static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
 298static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
 299
 300/* Left PGA Mux */
 301static const struct soc_enum wm8988_lpga_enum =
 302        SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
 303                              ARRAY_SIZE(wm8988_pga_sel),
 304                              wm8988_pga_sel,
 305                              wm8988_pga_val);
 306static const struct snd_kcontrol_new wm8988_left_pga_controls =
 307        SOC_DAPM_VALUE_ENUM("Route", wm8988_lpga_enum);
 308
 309/* Right PGA Mux */
 310static const struct soc_enum wm8988_rpga_enum =
 311        SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
 312                              ARRAY_SIZE(wm8988_pga_sel),
 313                              wm8988_pga_sel,
 314                              wm8988_pga_val);
 315static const struct snd_kcontrol_new wm8988_right_pga_controls =
 316        SOC_DAPM_VALUE_ENUM("Route", wm8988_rpga_enum);
 317
 318/* Differential Mux */
 319static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
 320static const struct soc_enum diffmux =
 321        SOC_ENUM_SINGLE(WM8988_ADCIN, 8, 2, wm8988_diff_sel);
 322static const struct snd_kcontrol_new wm8988_diffmux_controls =
 323        SOC_DAPM_ENUM("Route", diffmux);
 324
 325/* Mono ADC Mux */
 326static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
 327        "Mono (Right)", "Digital Mono"};
 328static const struct soc_enum monomux =
 329        SOC_ENUM_SINGLE(WM8988_ADCIN, 6, 4, wm8988_mono_mux);
 330static const struct snd_kcontrol_new wm8988_monomux_controls =
 331        SOC_DAPM_ENUM("Route", monomux);
 332
 333static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
 334        SND_SOC_DAPM_SUPPLY("Mic Bias", WM8988_PWR1, 1, 0, NULL, 0),
 335
 336        SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
 337                &wm8988_diffmux_controls),
 338        SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
 339                &wm8988_monomux_controls),
 340        SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
 341                &wm8988_monomux_controls),
 342
 343        SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
 344                &wm8988_left_pga_controls),
 345        SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
 346                &wm8988_right_pga_controls),
 347
 348        SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
 349                &wm8988_left_line_controls),
 350        SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
 351                &wm8988_right_line_controls),
 352
 353        SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
 354        SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
 355
 356        SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
 357        SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
 358
 359        SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
 360                &wm8988_left_mixer_controls[0],
 361                ARRAY_SIZE(wm8988_left_mixer_controls)),
 362        SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
 363                &wm8988_right_mixer_controls[0],
 364                ARRAY_SIZE(wm8988_right_mixer_controls)),
 365
 366        SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
 367        SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
 368        SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
 369        SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
 370
 371        SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
 372
 373        SND_SOC_DAPM_OUTPUT("LOUT1"),
 374        SND_SOC_DAPM_OUTPUT("ROUT1"),
 375        SND_SOC_DAPM_OUTPUT("LOUT2"),
 376        SND_SOC_DAPM_OUTPUT("ROUT2"),
 377        SND_SOC_DAPM_OUTPUT("VREF"),
 378
 379        SND_SOC_DAPM_INPUT("LINPUT1"),
 380        SND_SOC_DAPM_INPUT("LINPUT2"),
 381        SND_SOC_DAPM_INPUT("RINPUT1"),
 382        SND_SOC_DAPM_INPUT("RINPUT2"),
 383};
 384
 385static const struct snd_soc_dapm_route wm8988_dapm_routes[] = {
 386
 387        { "Left Line Mux", "Line 1", "LINPUT1" },
 388        { "Left Line Mux", "Line 2", "LINPUT2" },
 389        { "Left Line Mux", "PGA", "Left PGA Mux" },
 390        { "Left Line Mux", "Differential", "Differential Mux" },
 391
 392        { "Right Line Mux", "Line 1", "RINPUT1" },
 393        { "Right Line Mux", "Line 2", "RINPUT2" },
 394        { "Right Line Mux", "PGA", "Right PGA Mux" },
 395        { "Right Line Mux", "Differential", "Differential Mux" },
 396
 397        { "Left PGA Mux", "Line 1", "LINPUT1" },
 398        { "Left PGA Mux", "Line 2", "LINPUT2" },
 399        { "Left PGA Mux", "Differential", "Differential Mux" },
 400
 401        { "Right PGA Mux", "Line 1", "RINPUT1" },
 402        { "Right PGA Mux", "Line 2", "RINPUT2" },
 403        { "Right PGA Mux", "Differential", "Differential Mux" },
 404
 405        { "Differential Mux", "Line 1", "LINPUT1" },
 406        { "Differential Mux", "Line 1", "RINPUT1" },
 407        { "Differential Mux", "Line 2", "LINPUT2" },
 408        { "Differential Mux", "Line 2", "RINPUT2" },
 409
 410        { "Left ADC Mux", "Stereo", "Left PGA Mux" },
 411        { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
 412        { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
 413
 414        { "Right ADC Mux", "Stereo", "Right PGA Mux" },
 415        { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
 416        { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
 417
 418        { "Left ADC", NULL, "Left ADC Mux" },
 419        { "Right ADC", NULL, "Right ADC Mux" },
 420
 421        { "Left Line Mux", "Line 1", "LINPUT1" },
 422        { "Left Line Mux", "Line 2", "LINPUT2" },
 423        { "Left Line Mux", "PGA", "Left PGA Mux" },
 424        { "Left Line Mux", "Differential", "Differential Mux" },
 425
 426        { "Right Line Mux", "Line 1", "RINPUT1" },
 427        { "Right Line Mux", "Line 2", "RINPUT2" },
 428        { "Right Line Mux", "PGA", "Right PGA Mux" },
 429        { "Right Line Mux", "Differential", "Differential Mux" },
 430
 431        { "Left Mixer", "Playback Switch", "Left DAC" },
 432        { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
 433        { "Left Mixer", "Right Playback Switch", "Right DAC" },
 434        { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
 435
 436        { "Right Mixer", "Left Playback Switch", "Left DAC" },
 437        { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
 438        { "Right Mixer", "Playback Switch", "Right DAC" },
 439        { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
 440
 441        { "Left Out 1", NULL, "Left Mixer" },
 442        { "LOUT1", NULL, "Left Out 1" },
 443        { "Right Out 1", NULL, "Right Mixer" },
 444        { "ROUT1", NULL, "Right Out 1" },
 445
 446        { "Left Out 2", NULL, "Left Mixer" },
 447        { "LOUT2", NULL, "Left Out 2" },
 448        { "Right Out 2", NULL, "Right Mixer" },
 449        { "ROUT2", NULL, "Right Out 2" },
 450};
 451
 452struct _coeff_div {
 453        u32 mclk;
 454        u32 rate;
 455        u16 fs;
 456        u8 sr:5;
 457        u8 usb:1;
 458};
 459
 460/* codec hifi mclk clock divider coefficients */
 461static const struct _coeff_div coeff_div[] = {
 462        /* 8k */
 463        {12288000, 8000, 1536, 0x6, 0x0},
 464        {11289600, 8000, 1408, 0x16, 0x0},
 465        {18432000, 8000, 2304, 0x7, 0x0},
 466        {16934400, 8000, 2112, 0x17, 0x0},
 467        {12000000, 8000, 1500, 0x6, 0x1},
 468
 469        /* 11.025k */
 470        {11289600, 11025, 1024, 0x18, 0x0},
 471        {16934400, 11025, 1536, 0x19, 0x0},
 472        {12000000, 11025, 1088, 0x19, 0x1},
 473
 474        /* 16k */
 475        {12288000, 16000, 768, 0xa, 0x0},
 476        {18432000, 16000, 1152, 0xb, 0x0},
 477        {12000000, 16000, 750, 0xa, 0x1},
 478
 479        /* 22.05k */
 480        {11289600, 22050, 512, 0x1a, 0x0},
 481        {16934400, 22050, 768, 0x1b, 0x0},
 482        {12000000, 22050, 544, 0x1b, 0x1},
 483
 484        /* 32k */
 485        {12288000, 32000, 384, 0xc, 0x0},
 486        {18432000, 32000, 576, 0xd, 0x0},
 487        {12000000, 32000, 375, 0xa, 0x1},
 488
 489        /* 44.1k */
 490        {11289600, 44100, 256, 0x10, 0x0},
 491        {16934400, 44100, 384, 0x11, 0x0},
 492        {12000000, 44100, 272, 0x11, 0x1},
 493
 494        /* 48k */
 495        {12288000, 48000, 256, 0x0, 0x0},
 496        {18432000, 48000, 384, 0x1, 0x0},
 497        {12000000, 48000, 250, 0x0, 0x1},
 498
 499        /* 88.2k */
 500        {11289600, 88200, 128, 0x1e, 0x0},
 501        {16934400, 88200, 192, 0x1f, 0x0},
 502        {12000000, 88200, 136, 0x1f, 0x1},
 503
 504        /* 96k */
 505        {12288000, 96000, 128, 0xe, 0x0},
 506        {18432000, 96000, 192, 0xf, 0x0},
 507        {12000000, 96000, 125, 0xe, 0x1},
 508};
 509
 510static inline int get_coeff(int mclk, int rate)
 511{
 512        int i;
 513
 514        for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
 515                if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
 516                        return i;
 517        }
 518
 519        return -EINVAL;
 520}
 521
 522/* The set of rates we can generate from the above for each SYSCLK */
 523
 524static unsigned int rates_12288[] = {
 525        8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
 526};
 527
 528static struct snd_pcm_hw_constraint_list constraints_12288 = {
 529        .count  = ARRAY_SIZE(rates_12288),
 530        .list   = rates_12288,
 531};
 532
 533static unsigned int rates_112896[] = {
 534        8000, 11025, 22050, 44100,
 535};
 536
 537static struct snd_pcm_hw_constraint_list constraints_112896 = {
 538        .count  = ARRAY_SIZE(rates_112896),
 539        .list   = rates_112896,
 540};
 541
 542static unsigned int rates_12[] = {
 543        8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
 544        48000, 88235, 96000,
 545};
 546
 547static struct snd_pcm_hw_constraint_list constraints_12 = {
 548        .count  = ARRAY_SIZE(rates_12),
 549        .list   = rates_12,
 550};
 551
 552/*
 553 * Note that this should be called from init rather than from hw_params.
 554 */
 555static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 556                int clk_id, unsigned int freq, int dir)
 557{
 558        struct snd_soc_codec *codec = codec_dai->codec;
 559        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
 560
 561        switch (freq) {
 562        case 11289600:
 563        case 18432000:
 564        case 22579200:
 565        case 36864000:
 566                wm8988->sysclk_constraints = &constraints_112896;
 567                wm8988->sysclk = freq;
 568                return 0;
 569
 570        case 12288000:
 571        case 16934400:
 572        case 24576000:
 573        case 33868800:
 574                wm8988->sysclk_constraints = &constraints_12288;
 575                wm8988->sysclk = freq;
 576                return 0;
 577
 578        case 12000000:
 579        case 24000000:
 580                wm8988->sysclk_constraints = &constraints_12;
 581                wm8988->sysclk = freq;
 582                return 0;
 583        }
 584        return -EINVAL;
 585}
 586
 587static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
 588                unsigned int fmt)
 589{
 590        struct snd_soc_codec *codec = codec_dai->codec;
 591        u16 iface = 0;
 592
 593        /* set master/slave audio interface */
 594        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 595        case SND_SOC_DAIFMT_CBM_CFM:
 596                iface = 0x0040;
 597                break;
 598        case SND_SOC_DAIFMT_CBS_CFS:
 599                break;
 600        default:
 601                return -EINVAL;
 602        }
 603
 604        /* interface format */
 605        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 606        case SND_SOC_DAIFMT_I2S:
 607                iface |= 0x0002;
 608                break;
 609        case SND_SOC_DAIFMT_RIGHT_J:
 610                break;
 611        case SND_SOC_DAIFMT_LEFT_J:
 612                iface |= 0x0001;
 613                break;
 614        case SND_SOC_DAIFMT_DSP_A:
 615                iface |= 0x0003;
 616                break;
 617        case SND_SOC_DAIFMT_DSP_B:
 618                iface |= 0x0013;
 619                break;
 620        default:
 621                return -EINVAL;
 622        }
 623
 624        /* clock inversion */
 625        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 626        case SND_SOC_DAIFMT_NB_NF:
 627                break;
 628        case SND_SOC_DAIFMT_IB_IF:
 629                iface |= 0x0090;
 630                break;
 631        case SND_SOC_DAIFMT_IB_NF:
 632                iface |= 0x0080;
 633                break;
 634        case SND_SOC_DAIFMT_NB_IF:
 635                iface |= 0x0010;
 636                break;
 637        default:
 638                return -EINVAL;
 639        }
 640
 641        snd_soc_write(codec, WM8988_IFACE, iface);
 642        return 0;
 643}
 644
 645static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
 646                              struct snd_soc_dai *dai)
 647{
 648        struct snd_soc_codec *codec = dai->codec;
 649        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
 650
 651        /* The set of sample rates that can be supported depends on the
 652         * MCLK supplied to the CODEC - enforce this.
 653         */
 654        if (!wm8988->sysclk) {
 655                dev_err(codec->dev,
 656                        "No MCLK configured, call set_sysclk() on init\n");
 657                return -EINVAL;
 658        }
 659
 660        snd_pcm_hw_constraint_list(substream->runtime, 0,
 661                                   SNDRV_PCM_HW_PARAM_RATE,
 662                                   wm8988->sysclk_constraints);
 663
 664        return 0;
 665}
 666
 667static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
 668                                struct snd_pcm_hw_params *params,
 669                                struct snd_soc_dai *dai)
 670{
 671        struct snd_soc_codec *codec = dai->codec;
 672        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
 673        u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
 674        u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
 675        int coeff;
 676
 677        coeff = get_coeff(wm8988->sysclk, params_rate(params));
 678        if (coeff < 0) {
 679                coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
 680                srate |= 0x40;
 681        }
 682        if (coeff < 0) {
 683                dev_err(codec->dev,
 684                        "Unable to configure sample rate %dHz with %dHz MCLK\n",
 685                        params_rate(params), wm8988->sysclk);
 686                return coeff;
 687        }
 688
 689        /* bit size */
 690        switch (params_format(params)) {
 691        case SNDRV_PCM_FORMAT_S16_LE:
 692                break;
 693        case SNDRV_PCM_FORMAT_S20_3LE:
 694                iface |= 0x0004;
 695                break;
 696        case SNDRV_PCM_FORMAT_S24_LE:
 697                iface |= 0x0008;
 698                break;
 699        case SNDRV_PCM_FORMAT_S32_LE:
 700                iface |= 0x000c;
 701                break;
 702        }
 703
 704        /* set iface & srate */
 705        snd_soc_write(codec, WM8988_IFACE, iface);
 706        if (coeff >= 0)
 707                snd_soc_write(codec, WM8988_SRATE, srate |
 708                        (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
 709
 710        return 0;
 711}
 712
 713static int wm8988_mute(struct snd_soc_dai *dai, int mute)
 714{
 715        struct snd_soc_codec *codec = dai->codec;
 716        u16 mute_reg = snd_soc_read(codec, WM8988_ADCDAC) & 0xfff7;
 717
 718        if (mute)
 719                snd_soc_write(codec, WM8988_ADCDAC, mute_reg | 0x8);
 720        else
 721                snd_soc_write(codec, WM8988_ADCDAC, mute_reg);
 722        return 0;
 723}
 724
 725static int wm8988_set_bias_level(struct snd_soc_codec *codec,
 726                                 enum snd_soc_bias_level level)
 727{
 728        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
 729        u16 pwr_reg = snd_soc_read(codec, WM8988_PWR1) & ~0x1c1;
 730
 731        switch (level) {
 732        case SND_SOC_BIAS_ON:
 733                break;
 734
 735        case SND_SOC_BIAS_PREPARE:
 736                /* VREF, VMID=2x50k, digital enabled */
 737                snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x00c0);
 738                break;
 739
 740        case SND_SOC_BIAS_STANDBY:
 741                if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 742                        regcache_sync(wm8988->regmap);
 743
 744                        /* VREF, VMID=2x5k */
 745                        snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
 746
 747                        /* Charge caps */
 748                        msleep(100);
 749                }
 750
 751                /* VREF, VMID=2*500k, digital stopped */
 752                snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x0141);
 753                break;
 754
 755        case SND_SOC_BIAS_OFF:
 756                snd_soc_write(codec, WM8988_PWR1, 0x0000);
 757                break;
 758        }
 759        codec->dapm.bias_level = level;
 760        return 0;
 761}
 762
 763#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
 764
 765#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 766        SNDRV_PCM_FMTBIT_S24_LE)
 767
 768static const struct snd_soc_dai_ops wm8988_ops = {
 769        .startup = wm8988_pcm_startup,
 770        .hw_params = wm8988_pcm_hw_params,
 771        .set_fmt = wm8988_set_dai_fmt,
 772        .set_sysclk = wm8988_set_dai_sysclk,
 773        .digital_mute = wm8988_mute,
 774};
 775
 776static struct snd_soc_dai_driver wm8988_dai = {
 777        .name = "wm8988-hifi",
 778        .playback = {
 779                .stream_name = "Playback",
 780                .channels_min = 1,
 781                .channels_max = 2,
 782                .rates = WM8988_RATES,
 783                .formats = WM8988_FORMATS,
 784        },
 785        .capture = {
 786                .stream_name = "Capture",
 787                .channels_min = 1,
 788                .channels_max = 2,
 789                .rates = WM8988_RATES,
 790                .formats = WM8988_FORMATS,
 791         },
 792        .ops = &wm8988_ops,
 793        .symmetric_rates = 1,
 794};
 795
 796static int wm8988_suspend(struct snd_soc_codec *codec)
 797{
 798        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
 799
 800        wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
 801        regcache_mark_dirty(wm8988->regmap);
 802        return 0;
 803}
 804
 805static int wm8988_resume(struct snd_soc_codec *codec)
 806{
 807        wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 808        return 0;
 809}
 810
 811static int wm8988_probe(struct snd_soc_codec *codec)
 812{
 813        struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
 814        int ret = 0;
 815
 816        codec->control_data = wm8988->regmap;
 817        ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
 818        if (ret < 0) {
 819                dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 820                return ret;
 821        }
 822
 823        ret = wm8988_reset(codec);
 824        if (ret < 0) {
 825                dev_err(codec->dev, "Failed to issue reset\n");
 826                return ret;
 827        }
 828
 829        /* set the update bits (we always update left then right) */
 830        snd_soc_update_bits(codec, WM8988_RADC, 0x0100, 0x0100);
 831        snd_soc_update_bits(codec, WM8988_RDAC, 0x0100, 0x0100);
 832        snd_soc_update_bits(codec, WM8988_ROUT1V, 0x0100, 0x0100);
 833        snd_soc_update_bits(codec, WM8988_ROUT2V, 0x0100, 0x0100);
 834        snd_soc_update_bits(codec, WM8988_RINVOL, 0x0100, 0x0100);
 835
 836        wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 837
 838        return 0;
 839}
 840
 841static int wm8988_remove(struct snd_soc_codec *codec)
 842{
 843        wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
 844        return 0;
 845}
 846
 847static struct snd_soc_codec_driver soc_codec_dev_wm8988 = {
 848        .probe =        wm8988_probe,
 849        .remove =       wm8988_remove,
 850        .suspend =      wm8988_suspend,
 851        .resume =       wm8988_resume,
 852        .set_bias_level = wm8988_set_bias_level,
 853
 854        .controls = wm8988_snd_controls,
 855        .num_controls = ARRAY_SIZE(wm8988_snd_controls),
 856        .dapm_widgets = wm8988_dapm_widgets,
 857        .num_dapm_widgets = ARRAY_SIZE(wm8988_dapm_widgets),
 858        .dapm_routes = wm8988_dapm_routes,
 859        .num_dapm_routes = ARRAY_SIZE(wm8988_dapm_routes),
 860};
 861
 862static struct regmap_config wm8988_regmap = {
 863        .reg_bits = 7,
 864        .val_bits = 9,
 865
 866        .max_register = WM8988_LPPB,
 867        .writeable_reg = wm8988_writeable,
 868
 869        .cache_type = REGCACHE_RBTREE,
 870        .reg_defaults = wm8988_reg_defaults,
 871        .num_reg_defaults = ARRAY_SIZE(wm8988_reg_defaults),
 872};
 873
 874#if defined(CONFIG_SPI_MASTER)
 875static int wm8988_spi_probe(struct spi_device *spi)
 876{
 877        struct wm8988_priv *wm8988;
 878        int ret;
 879
 880        wm8988 = devm_kzalloc(&spi->dev, sizeof(struct wm8988_priv),
 881                              GFP_KERNEL);
 882        if (wm8988 == NULL)
 883                return -ENOMEM;
 884
 885        wm8988->regmap = devm_regmap_init_spi(spi, &wm8988_regmap);
 886        if (IS_ERR(wm8988->regmap)) {
 887                ret = PTR_ERR(wm8988->regmap);
 888                dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
 889                return ret;
 890        }
 891
 892        spi_set_drvdata(spi, wm8988);
 893
 894        ret = snd_soc_register_codec(&spi->dev,
 895                        &soc_codec_dev_wm8988, &wm8988_dai, 1);
 896        return ret;
 897}
 898
 899static int wm8988_spi_remove(struct spi_device *spi)
 900{
 901        snd_soc_unregister_codec(&spi->dev);
 902        return 0;
 903}
 904
 905static struct spi_driver wm8988_spi_driver = {
 906        .driver = {
 907                .name   = "wm8988",
 908                .owner  = THIS_MODULE,
 909        },
 910        .probe          = wm8988_spi_probe,
 911        .remove         = wm8988_spi_remove,
 912};
 913#endif /* CONFIG_SPI_MASTER */
 914
 915#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 916static int wm8988_i2c_probe(struct i2c_client *i2c,
 917                            const struct i2c_device_id *id)
 918{
 919        struct wm8988_priv *wm8988;
 920        int ret;
 921
 922        wm8988 = devm_kzalloc(&i2c->dev, sizeof(struct wm8988_priv),
 923                              GFP_KERNEL);
 924        if (wm8988 == NULL)
 925                return -ENOMEM;
 926
 927        i2c_set_clientdata(i2c, wm8988);
 928
 929        wm8988->regmap = devm_regmap_init_i2c(i2c, &wm8988_regmap);
 930        if (IS_ERR(wm8988->regmap)) {
 931                ret = PTR_ERR(wm8988->regmap);
 932                dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
 933                return ret;
 934        }
 935
 936        ret =  snd_soc_register_codec(&i2c->dev,
 937                        &soc_codec_dev_wm8988, &wm8988_dai, 1);
 938        return ret;
 939}
 940
 941static int wm8988_i2c_remove(struct i2c_client *client)
 942{
 943        snd_soc_unregister_codec(&client->dev);
 944        return 0;
 945}
 946
 947static const struct i2c_device_id wm8988_i2c_id[] = {
 948        { "wm8988", 0 },
 949        { }
 950};
 951MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
 952
 953static struct i2c_driver wm8988_i2c_driver = {
 954        .driver = {
 955                .name = "wm8988",
 956                .owner = THIS_MODULE,
 957        },
 958        .probe =    wm8988_i2c_probe,
 959        .remove =   wm8988_i2c_remove,
 960        .id_table = wm8988_i2c_id,
 961};
 962#endif
 963
 964static int __init wm8988_modinit(void)
 965{
 966        int ret = 0;
 967#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 968        ret = i2c_add_driver(&wm8988_i2c_driver);
 969        if (ret != 0) {
 970                printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
 971                       ret);
 972        }
 973#endif
 974#if defined(CONFIG_SPI_MASTER)
 975        ret = spi_register_driver(&wm8988_spi_driver);
 976        if (ret != 0) {
 977                printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
 978                       ret);
 979        }
 980#endif
 981        return ret;
 982}
 983module_init(wm8988_modinit);
 984
 985static void __exit wm8988_exit(void)
 986{
 987#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 988        i2c_del_driver(&wm8988_i2c_driver);
 989#endif
 990#if defined(CONFIG_SPI_MASTER)
 991        spi_unregister_driver(&wm8988_spi_driver);
 992#endif
 993}
 994module_exit(wm8988_exit);
 995
 996
 997MODULE_DESCRIPTION("ASoC WM8988 driver");
 998MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 999MODULE_LICENSE("GPL");
1000