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8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/dw_dmac.h>
11#include <linux/fb.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/slab.h>
16#include <linux/gpio.h>
17#include <linux/spi/spi.h>
18#include <linux/usb/atmel_usba_udc.h>
19
20#include <mach/atmel-mci.h>
21#include <linux/atmel-mci.h>
22
23#include <asm/io.h>
24#include <asm/irq.h>
25
26#include <mach/at32ap700x.h>
27#include <mach/board.h>
28#include <mach/hmatrix.h>
29#include <mach/portmux.h>
30#include <mach/sram.h>
31
32#include <sound/atmel-abdac.h>
33#include <sound/atmel-ac97c.h>
34
35#include <video/atmel_lcdc.h>
36
37#include "clock.h"
38#include "pio.h"
39#include "pm.h"
40
41
42#define PBMEM(base) \
43 { \
44 .start = base, \
45 .end = base + 0x3ff, \
46 .flags = IORESOURCE_MEM, \
47 }
48#define IRQ(num) \
49 { \
50 .start = num, \
51 .end = num, \
52 .flags = IORESOURCE_IRQ, \
53 }
54#define NAMED_IRQ(num, _name) \
55 { \
56 .start = num, \
57 .end = num, \
58 .name = _name, \
59 .flags = IORESOURCE_IRQ, \
60 }
61
62
63
64
65#define DEFINE_DEV(_name, _id) \
66static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
67static struct platform_device _name##_id##_device = { \
68 .name = #_name, \
69 .id = _id, \
70 .dev = { \
71 .dma_mask = &_name##_id##_dma_mask, \
72 .coherent_dma_mask = DMA_BIT_MASK(32), \
73 }, \
74 .resource = _name##_id##_resource, \
75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
76}
77#define DEFINE_DEV_DATA(_name, _id) \
78static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
79static struct platform_device _name##_id##_device = { \
80 .name = #_name, \
81 .id = _id, \
82 .dev = { \
83 .dma_mask = &_name##_id##_dma_mask, \
84 .platform_data = &_name##_id##_data, \
85 .coherent_dma_mask = DMA_BIT_MASK(32), \
86 }, \
87 .resource = _name##_id##_resource, \
88 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
89}
90
91#define select_peripheral(port, pin_mask, periph, flags) \
92 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
93 GPIO_##periph, flags)
94
95#define DEV_CLK(_name, devname, bus, _index) \
96static struct clk devname##_##_name = { \
97 .name = #_name, \
98 .dev = &devname##_device.dev, \
99 .parent = &bus##_clk, \
100 .mode = bus##_clk_mode, \
101 .get_rate = bus##_clk_get_rate, \
102 .index = _index, \
103}
104
105static DEFINE_SPINLOCK(pm_lock);
106
107static struct clk osc0;
108static struct clk osc1;
109
110static unsigned long osc_get_rate(struct clk *clk)
111{
112 return at32_board_osc_rates[clk->index];
113}
114
115static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
116{
117 unsigned long div, mul, rate;
118
119 div = PM_BFEXT(PLLDIV, control) + 1;
120 mul = PM_BFEXT(PLLMUL, control) + 1;
121
122 rate = clk->parent->get_rate(clk->parent);
123 rate = (rate + div / 2) / div;
124 rate *= mul;
125
126 return rate;
127}
128
129static long pll_set_rate(struct clk *clk, unsigned long rate,
130 u32 *pll_ctrl)
131{
132 unsigned long mul;
133 unsigned long mul_best_fit = 0;
134 unsigned long div;
135 unsigned long div_min;
136 unsigned long div_max;
137 unsigned long div_best_fit = 0;
138 unsigned long base;
139 unsigned long pll_in;
140 unsigned long actual = 0;
141 unsigned long rate_error;
142 unsigned long rate_error_prev = ~0UL;
143 u32 ctrl;
144
145
146 if (rate < 80000000UL || rate > 200000000UL)
147 return -EINVAL;
148
149 ctrl = PM_BF(PLLOPT, 4);
150 base = clk->parent->get_rate(clk->parent);
151
152
153 div_min = DIV_ROUND_UP(base, 32000000UL);
154 div_max = base / 6000000UL;
155
156 if (div_max < div_min)
157 return -EINVAL;
158
159 for (div = div_min; div <= div_max; div++) {
160 pll_in = (base + div / 2) / div;
161 mul = (rate + pll_in / 2) / pll_in;
162
163 if (mul == 0)
164 continue;
165
166 actual = pll_in * mul;
167 rate_error = abs(actual - rate);
168
169 if (rate_error < rate_error_prev) {
170 mul_best_fit = mul;
171 div_best_fit = div;
172 rate_error_prev = rate_error;
173 }
174
175 if (rate_error == 0)
176 break;
177 }
178
179 if (div_best_fit == 0)
180 return -EINVAL;
181
182 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
183 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
184 ctrl |= PM_BF(PLLCOUNT, 16);
185
186 if (clk->parent == &osc1)
187 ctrl |= PM_BIT(PLLOSC);
188
189 *pll_ctrl = ctrl;
190
191 return actual;
192}
193
194static unsigned long pll0_get_rate(struct clk *clk)
195{
196 u32 control;
197
198 control = pm_readl(PLL0);
199
200 return pll_get_rate(clk, control);
201}
202
203static void pll1_mode(struct clk *clk, int enabled)
204{
205 unsigned long timeout;
206 u32 status;
207 u32 ctrl;
208
209 ctrl = pm_readl(PLL1);
210
211 if (enabled) {
212 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
213 pr_debug("clk %s: failed to enable, rate not set\n",
214 clk->name);
215 return;
216 }
217
218 ctrl |= PM_BIT(PLLEN);
219 pm_writel(PLL1, ctrl);
220
221
222 for (timeout = 10000; timeout; timeout--) {
223 status = pm_readl(ISR);
224 if (status & PM_BIT(LOCK1))
225 break;
226 udelay(10);
227 }
228
229 if (!(status & PM_BIT(LOCK1)))
230 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
231 clk->name);
232 } else {
233 ctrl &= ~PM_BIT(PLLEN);
234 pm_writel(PLL1, ctrl);
235 }
236}
237
238static unsigned long pll1_get_rate(struct clk *clk)
239{
240 u32 control;
241
242 control = pm_readl(PLL1);
243
244 return pll_get_rate(clk, control);
245}
246
247static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
248{
249 u32 ctrl = 0;
250 unsigned long actual_rate;
251
252 actual_rate = pll_set_rate(clk, rate, &ctrl);
253
254 if (apply) {
255 if (actual_rate != rate)
256 return -EINVAL;
257 if (clk->users > 0)
258 return -EBUSY;
259 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
260 clk->name, rate, actual_rate);
261 pm_writel(PLL1, ctrl);
262 }
263
264 return actual_rate;
265}
266
267static int pll1_set_parent(struct clk *clk, struct clk *parent)
268{
269 u32 ctrl;
270
271 if (clk->users > 0)
272 return -EBUSY;
273
274 ctrl = pm_readl(PLL1);
275 WARN_ON(ctrl & PM_BIT(PLLEN));
276
277 if (parent == &osc0)
278 ctrl &= ~PM_BIT(PLLOSC);
279 else if (parent == &osc1)
280 ctrl |= PM_BIT(PLLOSC);
281 else
282 return -EINVAL;
283
284 pm_writel(PLL1, ctrl);
285 clk->parent = parent;
286
287 return 0;
288}
289
290
291
292
293
294static struct clk osc32k = {
295 .name = "osc32k",
296 .get_rate = osc_get_rate,
297 .users = 1,
298 .index = 0,
299};
300static struct clk osc0 = {
301 .name = "osc0",
302 .get_rate = osc_get_rate,
303 .users = 1,
304 .index = 1,
305};
306static struct clk osc1 = {
307 .name = "osc1",
308 .get_rate = osc_get_rate,
309 .index = 2,
310};
311static struct clk pll0 = {
312 .name = "pll0",
313 .get_rate = pll0_get_rate,
314 .parent = &osc0,
315};
316static struct clk pll1 = {
317 .name = "pll1",
318 .mode = pll1_mode,
319 .get_rate = pll1_get_rate,
320 .set_rate = pll1_set_rate,
321 .set_parent = pll1_set_parent,
322 .parent = &osc0,
323};
324
325
326
327
328
329
330static struct clk *main_clock;
331
332
333
334
335
336
337
338static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
339{
340 return main_clock->get_rate(main_clock) >> shift;
341};
342
343static void cpu_clk_mode(struct clk *clk, int enabled)
344{
345 unsigned long flags;
346 u32 mask;
347
348 spin_lock_irqsave(&pm_lock, flags);
349 mask = pm_readl(CPU_MASK);
350 if (enabled)
351 mask |= 1 << clk->index;
352 else
353 mask &= ~(1 << clk->index);
354 pm_writel(CPU_MASK, mask);
355 spin_unlock_irqrestore(&pm_lock, flags);
356}
357
358static unsigned long cpu_clk_get_rate(struct clk *clk)
359{
360 unsigned long cksel, shift = 0;
361
362 cksel = pm_readl(CKSEL);
363 if (cksel & PM_BIT(CPUDIV))
364 shift = PM_BFEXT(CPUSEL, cksel) + 1;
365
366 return bus_clk_get_rate(clk, shift);
367}
368
369static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
370{
371 u32 control;
372 unsigned long parent_rate, child_div, actual_rate, div;
373
374 parent_rate = clk->parent->get_rate(clk->parent);
375 control = pm_readl(CKSEL);
376
377 if (control & PM_BIT(HSBDIV))
378 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
379 else
380 child_div = 1;
381
382 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
383 actual_rate = parent_rate;
384 control &= ~PM_BIT(CPUDIV);
385 } else {
386 unsigned int cpusel;
387 div = (parent_rate + rate / 2) / rate;
388 if (div > child_div)
389 div = child_div;
390 cpusel = (div > 1) ? (fls(div) - 2) : 0;
391 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
392 actual_rate = parent_rate / (1 << (cpusel + 1));
393 }
394
395 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
396 clk->name, rate, actual_rate);
397
398 if (apply)
399 pm_writel(CKSEL, control);
400
401 return actual_rate;
402}
403
404static void hsb_clk_mode(struct clk *clk, int enabled)
405{
406 unsigned long flags;
407 u32 mask;
408
409 spin_lock_irqsave(&pm_lock, flags);
410 mask = pm_readl(HSB_MASK);
411 if (enabled)
412 mask |= 1 << clk->index;
413 else
414 mask &= ~(1 << clk->index);
415 pm_writel(HSB_MASK, mask);
416 spin_unlock_irqrestore(&pm_lock, flags);
417}
418
419static unsigned long hsb_clk_get_rate(struct clk *clk)
420{
421 unsigned long cksel, shift = 0;
422
423 cksel = pm_readl(CKSEL);
424 if (cksel & PM_BIT(HSBDIV))
425 shift = PM_BFEXT(HSBSEL, cksel) + 1;
426
427 return bus_clk_get_rate(clk, shift);
428}
429
430void pba_clk_mode(struct clk *clk, int enabled)
431{
432 unsigned long flags;
433 u32 mask;
434
435 spin_lock_irqsave(&pm_lock, flags);
436 mask = pm_readl(PBA_MASK);
437 if (enabled)
438 mask |= 1 << clk->index;
439 else
440 mask &= ~(1 << clk->index);
441 pm_writel(PBA_MASK, mask);
442 spin_unlock_irqrestore(&pm_lock, flags);
443}
444
445unsigned long pba_clk_get_rate(struct clk *clk)
446{
447 unsigned long cksel, shift = 0;
448
449 cksel = pm_readl(CKSEL);
450 if (cksel & PM_BIT(PBADIV))
451 shift = PM_BFEXT(PBASEL, cksel) + 1;
452
453 return bus_clk_get_rate(clk, shift);
454}
455
456static void pbb_clk_mode(struct clk *clk, int enabled)
457{
458 unsigned long flags;
459 u32 mask;
460
461 spin_lock_irqsave(&pm_lock, flags);
462 mask = pm_readl(PBB_MASK);
463 if (enabled)
464 mask |= 1 << clk->index;
465 else
466 mask &= ~(1 << clk->index);
467 pm_writel(PBB_MASK, mask);
468 spin_unlock_irqrestore(&pm_lock, flags);
469}
470
471static unsigned long pbb_clk_get_rate(struct clk *clk)
472{
473 unsigned long cksel, shift = 0;
474
475 cksel = pm_readl(CKSEL);
476 if (cksel & PM_BIT(PBBDIV))
477 shift = PM_BFEXT(PBBSEL, cksel) + 1;
478
479 return bus_clk_get_rate(clk, shift);
480}
481
482static struct clk cpu_clk = {
483 .name = "cpu",
484 .get_rate = cpu_clk_get_rate,
485 .set_rate = cpu_clk_set_rate,
486 .users = 1,
487};
488static struct clk hsb_clk = {
489 .name = "hsb",
490 .parent = &cpu_clk,
491 .get_rate = hsb_clk_get_rate,
492};
493static struct clk pba_clk = {
494 .name = "pba",
495 .parent = &hsb_clk,
496 .mode = hsb_clk_mode,
497 .get_rate = pba_clk_get_rate,
498 .index = 1,
499};
500static struct clk pbb_clk = {
501 .name = "pbb",
502 .parent = &hsb_clk,
503 .mode = hsb_clk_mode,
504 .get_rate = pbb_clk_get_rate,
505 .users = 1,
506 .index = 2,
507};
508
509
510
511
512
513static void genclk_mode(struct clk *clk, int enabled)
514{
515 u32 control;
516
517 control = pm_readl(GCCTRL(clk->index));
518 if (enabled)
519 control |= PM_BIT(CEN);
520 else
521 control &= ~PM_BIT(CEN);
522 pm_writel(GCCTRL(clk->index), control);
523}
524
525static unsigned long genclk_get_rate(struct clk *clk)
526{
527 u32 control;
528 unsigned long div = 1;
529
530 control = pm_readl(GCCTRL(clk->index));
531 if (control & PM_BIT(DIVEN))
532 div = 2 * (PM_BFEXT(DIV, control) + 1);
533
534 return clk->parent->get_rate(clk->parent) / div;
535}
536
537static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
538{
539 u32 control;
540 unsigned long parent_rate, actual_rate, div;
541
542 parent_rate = clk->parent->get_rate(clk->parent);
543 control = pm_readl(GCCTRL(clk->index));
544
545 if (rate > 3 * parent_rate / 4) {
546 actual_rate = parent_rate;
547 control &= ~PM_BIT(DIVEN);
548 } else {
549 div = (parent_rate + rate) / (2 * rate) - 1;
550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
551 actual_rate = parent_rate / (2 * (div + 1));
552 }
553
554 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
555 clk->name, rate, actual_rate);
556
557 if (apply)
558 pm_writel(GCCTRL(clk->index), control);
559
560 return actual_rate;
561}
562
563int genclk_set_parent(struct clk *clk, struct clk *parent)
564{
565 u32 control;
566
567 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
568 clk->name, parent->name, clk->parent->name);
569
570 control = pm_readl(GCCTRL(clk->index));
571
572 if (parent == &osc1 || parent == &pll1)
573 control |= PM_BIT(OSCSEL);
574 else if (parent == &osc0 || parent == &pll0)
575 control &= ~PM_BIT(OSCSEL);
576 else
577 return -EINVAL;
578
579 if (parent == &pll0 || parent == &pll1)
580 control |= PM_BIT(PLLSEL);
581 else
582 control &= ~PM_BIT(PLLSEL);
583
584 pm_writel(GCCTRL(clk->index), control);
585 clk->parent = parent;
586
587 return 0;
588}
589
590static void __init genclk_init_parent(struct clk *clk)
591{
592 u32 control;
593 struct clk *parent;
594
595 BUG_ON(clk->index > 7);
596
597 control = pm_readl(GCCTRL(clk->index));
598 if (control & PM_BIT(OSCSEL))
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
600 else
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
602
603 clk->parent = parent;
604}
605
606static struct dw_dma_platform_data dw_dmac0_data = {
607 .nr_channels = 3,
608 .block_size = 4095U,
609 .nr_masters = 2,
610 .data_width = { 2, 2, 0, 0 },
611};
612
613static struct resource dw_dmac0_resource[] = {
614 PBMEM(0xff200000),
615 IRQ(2),
616};
617DEFINE_DEV_DATA(dw_dmac, 0);
618DEV_CLK(hclk, dw_dmac0, hsb, 10);
619
620
621
622
623static struct resource at32_pm0_resource[] = {
624 {
625 .start = 0xfff00000,
626 .end = 0xfff0007f,
627 .flags = IORESOURCE_MEM,
628 },
629 IRQ(20),
630};
631
632static struct resource at32ap700x_rtc0_resource[] = {
633 {
634 .start = 0xfff00080,
635 .end = 0xfff000af,
636 .flags = IORESOURCE_MEM,
637 },
638 IRQ(21),
639};
640
641static struct resource at32_wdt0_resource[] = {
642 {
643 .start = 0xfff000b0,
644 .end = 0xfff000cf,
645 .flags = IORESOURCE_MEM,
646 },
647};
648
649static struct resource at32_eic0_resource[] = {
650 {
651 .start = 0xfff00100,
652 .end = 0xfff0013f,
653 .flags = IORESOURCE_MEM,
654 },
655 IRQ(19),
656};
657
658DEFINE_DEV(at32_pm, 0);
659DEFINE_DEV(at32ap700x_rtc, 0);
660DEFINE_DEV(at32_wdt, 0);
661DEFINE_DEV(at32_eic, 0);
662
663
664
665
666
667static struct clk at32_pm_pclk = {
668 .name = "pclk",
669 .dev = &at32_pm0_device.dev,
670 .parent = &pbb_clk,
671 .mode = pbb_clk_mode,
672 .get_rate = pbb_clk_get_rate,
673 .users = 1,
674 .index = 0,
675};
676
677static struct resource intc0_resource[] = {
678 PBMEM(0xfff00400),
679};
680struct platform_device at32_intc0_device = {
681 .name = "intc",
682 .id = 0,
683 .resource = intc0_resource,
684 .num_resources = ARRAY_SIZE(intc0_resource),
685};
686DEV_CLK(pclk, at32_intc0, pbb, 1);
687
688static struct clk ebi_clk = {
689 .name = "ebi",
690 .parent = &hsb_clk,
691 .mode = hsb_clk_mode,
692 .get_rate = hsb_clk_get_rate,
693 .users = 1,
694};
695static struct clk hramc_clk = {
696 .name = "hramc",
697 .parent = &hsb_clk,
698 .mode = hsb_clk_mode,
699 .get_rate = hsb_clk_get_rate,
700 .users = 1,
701 .index = 3,
702};
703static struct clk sdramc_clk = {
704 .name = "sdramc_clk",
705 .parent = &pbb_clk,
706 .mode = pbb_clk_mode,
707 .get_rate = pbb_clk_get_rate,
708 .users = 1,
709 .index = 14,
710};
711
712static struct resource smc0_resource[] = {
713 PBMEM(0xfff03400),
714};
715DEFINE_DEV(smc, 0);
716DEV_CLK(pclk, smc0, pbb, 13);
717DEV_CLK(mck, smc0, hsb, 0);
718
719static struct platform_device pdc_device = {
720 .name = "pdc",
721 .id = 0,
722};
723DEV_CLK(hclk, pdc, hsb, 4);
724DEV_CLK(pclk, pdc, pba, 16);
725
726static struct clk pico_clk = {
727 .name = "pico",
728 .parent = &cpu_clk,
729 .mode = cpu_clk_mode,
730 .get_rate = cpu_clk_get_rate,
731 .users = 1,
732};
733
734
735
736
737
738struct clk at32_hmatrix_clk = {
739 .name = "hmatrix_clk",
740 .parent = &pbb_clk,
741 .mode = pbb_clk_mode,
742 .get_rate = pbb_clk_get_rate,
743 .index = 2,
744 .users = 1,
745};
746
747
748
749
750
751
752
753static inline void set_ebi_sfr_bits(u32 mask)
754{
755 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
756}
757
758
759
760
761
762static struct resource at32_tcb0_resource[] = {
763 PBMEM(0xfff00c00),
764 IRQ(22),
765};
766static struct platform_device at32_tcb0_device = {
767 .name = "atmel_tcb",
768 .id = 0,
769 .resource = at32_tcb0_resource,
770 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
771};
772DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
773
774static struct resource at32_tcb1_resource[] = {
775 PBMEM(0xfff01000),
776 IRQ(23),
777};
778static struct platform_device at32_tcb1_device = {
779 .name = "atmel_tcb",
780 .id = 1,
781 .resource = at32_tcb1_resource,
782 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
783};
784DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
785
786
787
788
789
790static struct resource pio0_resource[] = {
791 PBMEM(0xffe02800),
792 IRQ(13),
793};
794DEFINE_DEV(pio, 0);
795DEV_CLK(mck, pio0, pba, 10);
796
797static struct resource pio1_resource[] = {
798 PBMEM(0xffe02c00),
799 IRQ(14),
800};
801DEFINE_DEV(pio, 1);
802DEV_CLK(mck, pio1, pba, 11);
803
804static struct resource pio2_resource[] = {
805 PBMEM(0xffe03000),
806 IRQ(15),
807};
808DEFINE_DEV(pio, 2);
809DEV_CLK(mck, pio2, pba, 12);
810
811static struct resource pio3_resource[] = {
812 PBMEM(0xffe03400),
813 IRQ(16),
814};
815DEFINE_DEV(pio, 3);
816DEV_CLK(mck, pio3, pba, 13);
817
818static struct resource pio4_resource[] = {
819 PBMEM(0xffe03800),
820 IRQ(17),
821};
822DEFINE_DEV(pio, 4);
823DEV_CLK(mck, pio4, pba, 14);
824
825static int __init system_device_init(void)
826{
827 platform_device_register(&at32_pm0_device);
828 platform_device_register(&at32_intc0_device);
829 platform_device_register(&at32ap700x_rtc0_device);
830 platform_device_register(&at32_wdt0_device);
831 platform_device_register(&at32_eic0_device);
832 platform_device_register(&smc0_device);
833 platform_device_register(&pdc_device);
834 platform_device_register(&dw_dmac0_device);
835
836 platform_device_register(&at32_tcb0_device);
837 platform_device_register(&at32_tcb1_device);
838
839 platform_device_register(&pio0_device);
840 platform_device_register(&pio1_device);
841 platform_device_register(&pio2_device);
842 platform_device_register(&pio3_device);
843 platform_device_register(&pio4_device);
844
845 return 0;
846}
847core_initcall(system_device_init);
848
849
850
851
852static struct resource atmel_psif0_resource[] __initdata = {
853 {
854 .start = 0xffe03c00,
855 .end = 0xffe03cff,
856 .flags = IORESOURCE_MEM,
857 },
858 IRQ(18),
859};
860static struct clk atmel_psif0_pclk = {
861 .name = "pclk",
862 .parent = &pba_clk,
863 .mode = pba_clk_mode,
864 .get_rate = pba_clk_get_rate,
865 .index = 15,
866};
867
868static struct resource atmel_psif1_resource[] __initdata = {
869 {
870 .start = 0xffe03d00,
871 .end = 0xffe03dff,
872 .flags = IORESOURCE_MEM,
873 },
874 IRQ(18),
875};
876static struct clk atmel_psif1_pclk = {
877 .name = "pclk",
878 .parent = &pba_clk,
879 .mode = pba_clk_mode,
880 .get_rate = pba_clk_get_rate,
881 .index = 15,
882};
883
884struct platform_device *__init at32_add_device_psif(unsigned int id)
885{
886 struct platform_device *pdev;
887 u32 pin_mask;
888
889 if (!(id == 0 || id == 1))
890 return NULL;
891
892 pdev = platform_device_alloc("atmel_psif", id);
893 if (!pdev)
894 return NULL;
895
896 switch (id) {
897 case 0:
898 pin_mask = (1 << 8) | (1 << 9);
899
900 if (platform_device_add_resources(pdev, atmel_psif0_resource,
901 ARRAY_SIZE(atmel_psif0_resource)))
902 goto err_add_resources;
903 atmel_psif0_pclk.dev = &pdev->dev;
904 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
905 break;
906 case 1:
907 pin_mask = (1 << 11) | (1 << 12);
908
909 if (platform_device_add_resources(pdev, atmel_psif1_resource,
910 ARRAY_SIZE(atmel_psif1_resource)))
911 goto err_add_resources;
912 atmel_psif1_pclk.dev = &pdev->dev;
913 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
914 break;
915 default:
916 return NULL;
917 }
918
919 platform_device_add(pdev);
920 return pdev;
921
922err_add_resources:
923 platform_device_put(pdev);
924 return NULL;
925}
926
927
928
929
930
931static struct atmel_uart_data atmel_usart0_data = {
932 .use_dma_tx = 1,
933 .use_dma_rx = 1,
934};
935static struct resource atmel_usart0_resource[] = {
936 PBMEM(0xffe00c00),
937 IRQ(6),
938};
939DEFINE_DEV_DATA(atmel_usart, 0);
940DEV_CLK(usart, atmel_usart0, pba, 3);
941
942static struct atmel_uart_data atmel_usart1_data = {
943 .use_dma_tx = 1,
944 .use_dma_rx = 1,
945};
946static struct resource atmel_usart1_resource[] = {
947 PBMEM(0xffe01000),
948 IRQ(7),
949};
950DEFINE_DEV_DATA(atmel_usart, 1);
951DEV_CLK(usart, atmel_usart1, pba, 4);
952
953static struct atmel_uart_data atmel_usart2_data = {
954 .use_dma_tx = 1,
955 .use_dma_rx = 1,
956};
957static struct resource atmel_usart2_resource[] = {
958 PBMEM(0xffe01400),
959 IRQ(8),
960};
961DEFINE_DEV_DATA(atmel_usart, 2);
962DEV_CLK(usart, atmel_usart2, pba, 5);
963
964static struct atmel_uart_data atmel_usart3_data = {
965 .use_dma_tx = 1,
966 .use_dma_rx = 1,
967};
968static struct resource atmel_usart3_resource[] = {
969 PBMEM(0xffe01800),
970 IRQ(9),
971};
972DEFINE_DEV_DATA(atmel_usart, 3);
973DEV_CLK(usart, atmel_usart3, pba, 6);
974
975static inline void configure_usart0_pins(int flags)
976{
977 u32 pin_mask = (1 << 8) | (1 << 9);
978 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
979 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
980 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
981
982 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
983}
984
985static inline void configure_usart1_pins(int flags)
986{
987 u32 pin_mask = (1 << 17) | (1 << 18);
988 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
989 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
990 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
991
992 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
993}
994
995static inline void configure_usart2_pins(int flags)
996{
997 u32 pin_mask = (1 << 26) | (1 << 27);
998 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
999 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
1000 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
1001
1002 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1003}
1004
1005static inline void configure_usart3_pins(int flags)
1006{
1007 u32 pin_mask = (1 << 18) | (1 << 17);
1008 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1009 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1010 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1011
1012 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1013}
1014
1015static struct platform_device *__initdata at32_usarts[4];
1016
1017void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1018{
1019 struct platform_device *pdev;
1020 struct atmel_uart_data *pdata;
1021
1022 switch (hw_id) {
1023 case 0:
1024 pdev = &atmel_usart0_device;
1025 configure_usart0_pins(flags);
1026 break;
1027 case 1:
1028 pdev = &atmel_usart1_device;
1029 configure_usart1_pins(flags);
1030 break;
1031 case 2:
1032 pdev = &atmel_usart2_device;
1033 configure_usart2_pins(flags);
1034 break;
1035 case 3:
1036 pdev = &atmel_usart3_device;
1037 configure_usart3_pins(flags);
1038 break;
1039 default:
1040 return;
1041 }
1042
1043 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1044
1045 struct atmel_uart_data *data = pdev->dev.platform_data;
1046 data->regs = (void __iomem *)pdev->resource[0].start;
1047 }
1048
1049 pdev->id = line;
1050 pdata = pdev->dev.platform_data;
1051 pdata->num = line;
1052 at32_usarts[line] = pdev;
1053}
1054
1055struct platform_device *__init at32_add_device_usart(unsigned int id)
1056{
1057 platform_device_register(at32_usarts[id]);
1058 return at32_usarts[id];
1059}
1060
1061void __init at32_setup_serial_console(unsigned int usart_id)
1062{
1063 atmel_default_console_device = at32_usarts[usart_id];
1064}
1065
1066
1067
1068
1069
1070#ifdef CONFIG_CPU_AT32AP7000
1071static struct macb_platform_data macb0_data;
1072static struct resource macb0_resource[] = {
1073 PBMEM(0xfff01800),
1074 IRQ(25),
1075};
1076DEFINE_DEV_DATA(macb, 0);
1077DEV_CLK(hclk, macb0, hsb, 8);
1078DEV_CLK(pclk, macb0, pbb, 6);
1079
1080static struct macb_platform_data macb1_data;
1081static struct resource macb1_resource[] = {
1082 PBMEM(0xfff01c00),
1083 IRQ(26),
1084};
1085DEFINE_DEV_DATA(macb, 1);
1086DEV_CLK(hclk, macb1, hsb, 9);
1087DEV_CLK(pclk, macb1, pbb, 7);
1088
1089struct platform_device *__init
1090at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1091{
1092 struct platform_device *pdev;
1093 u32 pin_mask;
1094
1095 switch (id) {
1096 case 0:
1097 pdev = &macb0_device;
1098
1099 pin_mask = (1 << 3);
1100 pin_mask |= (1 << 4);
1101 pin_mask |= (1 << 7);
1102 pin_mask |= (1 << 8);
1103 pin_mask |= (1 << 9);
1104 pin_mask |= (1 << 10);
1105 pin_mask |= (1 << 13);
1106 pin_mask |= (1 << 15);
1107 pin_mask |= (1 << 16);
1108 pin_mask |= (1 << 17);
1109
1110 if (!data->is_rmii) {
1111 pin_mask |= (1 << 0);
1112 pin_mask |= (1 << 1);
1113 pin_mask |= (1 << 2);
1114 pin_mask |= (1 << 5);
1115 pin_mask |= (1 << 6);
1116 pin_mask |= (1 << 11);
1117 pin_mask |= (1 << 12);
1118 pin_mask |= (1 << 14);
1119#ifndef CONFIG_BOARD_MIMC200
1120 pin_mask |= (1 << 18);
1121#endif
1122 }
1123
1124 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1125
1126 break;
1127
1128 case 1:
1129 pdev = &macb1_device;
1130
1131 pin_mask = (1 << 13);
1132 pin_mask |= (1 << 14);
1133 pin_mask |= (1 << 11);
1134 pin_mask |= (1 << 12);
1135 pin_mask |= (1 << 10);
1136 pin_mask |= (1 << 6);
1137 pin_mask |= (1 << 5);
1138 pin_mask |= (1 << 4);
1139 pin_mask |= (1 << 3);
1140 pin_mask |= (1 << 2);
1141
1142#ifndef CONFIG_BOARD_MIMC200
1143 if (!data->is_rmii)
1144 pin_mask |= (1 << 15);
1145#endif
1146
1147 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1148
1149 if (!data->is_rmii) {
1150 pin_mask = (1 << 19);
1151 pin_mask |= (1 << 23);
1152 pin_mask |= (1 << 26);
1153 pin_mask |= (1 << 27);
1154 pin_mask |= (1 << 28);
1155 pin_mask |= (1 << 29);
1156 pin_mask |= (1 << 30);
1157 pin_mask |= (1 << 24);
1158
1159 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1160 }
1161 break;
1162
1163 default:
1164 return NULL;
1165 }
1166
1167 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1168 platform_device_register(pdev);
1169
1170 return pdev;
1171}
1172#endif
1173
1174
1175
1176
1177static struct resource atmel_spi0_resource[] = {
1178 PBMEM(0xffe00000),
1179 IRQ(3),
1180};
1181DEFINE_DEV(atmel_spi, 0);
1182DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1183
1184static struct resource atmel_spi1_resource[] = {
1185 PBMEM(0xffe00400),
1186 IRQ(4),
1187};
1188DEFINE_DEV(atmel_spi, 1);
1189DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1190
1191void __init
1192at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1193{
1194
1195
1196
1197
1198 static u8 __initdata spi_pins[][4] = {
1199 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1200 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1201 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1202 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1203 };
1204 unsigned int pin, mode;
1205
1206
1207 if (bus_num > 1)
1208 return;
1209
1210 for (; n; n--, b++) {
1211 b->bus_num = bus_num;
1212 if (b->chip_select >= 4)
1213 continue;
1214 pin = (unsigned)b->controller_data;
1215 if (!pin) {
1216 pin = spi_pins[bus_num][b->chip_select];
1217 b->controller_data = (void *)pin;
1218 }
1219 mode = AT32_GPIOF_OUTPUT;
1220 if (!(b->mode & SPI_CS_HIGH))
1221 mode |= AT32_GPIOF_HIGH;
1222 at32_select_gpio(pin, mode);
1223 }
1224}
1225
1226struct platform_device *__init
1227at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1228{
1229 struct platform_device *pdev;
1230 u32 pin_mask;
1231
1232 switch (id) {
1233 case 0:
1234 pdev = &atmel_spi0_device;
1235 pin_mask = (1 << 1) | (1 << 2);
1236
1237
1238 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1239 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1240
1241 at32_spi_setup_slaves(0, b, n);
1242 break;
1243
1244 case 1:
1245 pdev = &atmel_spi1_device;
1246 pin_mask = (1 << 1) | (1 << 5);
1247
1248
1249 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1250 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1251
1252 at32_spi_setup_slaves(1, b, n);
1253 break;
1254
1255 default:
1256 return NULL;
1257 }
1258
1259 spi_register_board_info(b, n);
1260 platform_device_register(pdev);
1261 return pdev;
1262}
1263
1264
1265
1266
1267static struct resource atmel_twi0_resource[] __initdata = {
1268 PBMEM(0xffe00800),
1269 IRQ(5),
1270};
1271static struct clk atmel_twi0_pclk = {
1272 .name = "twi_pclk",
1273 .parent = &pba_clk,
1274 .mode = pba_clk_mode,
1275 .get_rate = pba_clk_get_rate,
1276 .index = 2,
1277};
1278
1279struct platform_device *__init at32_add_device_twi(unsigned int id,
1280 struct i2c_board_info *b,
1281 unsigned int n)
1282{
1283 struct platform_device *pdev;
1284 u32 pin_mask;
1285
1286 if (id != 0)
1287 return NULL;
1288
1289 pdev = platform_device_alloc("atmel_twi", id);
1290 if (!pdev)
1291 return NULL;
1292
1293 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1294 ARRAY_SIZE(atmel_twi0_resource)))
1295 goto err_add_resources;
1296
1297 pin_mask = (1 << 6) | (1 << 7);
1298
1299 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1300
1301 atmel_twi0_pclk.dev = &pdev->dev;
1302
1303 if (b)
1304 i2c_register_board_info(id, b, n);
1305
1306 platform_device_add(pdev);
1307 return pdev;
1308
1309err_add_resources:
1310 platform_device_put(pdev);
1311 return NULL;
1312}
1313
1314
1315
1316
1317static struct resource atmel_mci0_resource[] __initdata = {
1318 PBMEM(0xfff02400),
1319 IRQ(28),
1320};
1321static struct clk atmel_mci0_pclk = {
1322 .name = "mci_clk",
1323 .parent = &pbb_clk,
1324 .mode = pbb_clk_mode,
1325 .get_rate = pbb_clk_get_rate,
1326 .index = 9,
1327};
1328
1329struct platform_device *__init
1330at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1331{
1332 struct platform_device *pdev;
1333 struct mci_dma_data *slave;
1334 u32 pioa_mask;
1335 u32 piob_mask;
1336
1337 if (id != 0 || !data)
1338 return NULL;
1339
1340
1341 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1342 return NULL;
1343
1344 pdev = platform_device_alloc("atmel_mci", id);
1345 if (!pdev)
1346 goto fail;
1347
1348 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1349 ARRAY_SIZE(atmel_mci0_resource)))
1350 goto fail;
1351
1352 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1353 if (!slave)
1354 goto fail;
1355
1356 slave->sdata.dma_dev = &dw_dmac0_device.dev;
1357 slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1358 | DWC_CFGH_DST_PER(1));
1359 slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1360 | DWC_CFGL_HS_SRC_POL);
1361
1362 data->dma_slave = slave;
1363
1364 if (platform_device_add_data(pdev, data,
1365 sizeof(struct mci_platform_data)))
1366 goto fail_free;
1367
1368
1369 pioa_mask = 1 << 10;
1370
1371 switch (data->slot[0].bus_width) {
1372 case 4:
1373 pioa_mask |= 1 << 13;
1374 pioa_mask |= 1 << 14;
1375 pioa_mask |= 1 << 15;
1376
1377 case 1:
1378 pioa_mask |= 1 << 11;
1379 pioa_mask |= 1 << 12;
1380
1381 if (gpio_is_valid(data->slot[0].detect_pin))
1382 at32_select_gpio(data->slot[0].detect_pin, 0);
1383 if (gpio_is_valid(data->slot[0].wp_pin))
1384 at32_select_gpio(data->slot[0].wp_pin, 0);
1385 break;
1386 case 0:
1387
1388 break;
1389 default:
1390 goto fail_free;
1391 }
1392
1393 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1394 piob_mask = 0;
1395
1396 switch (data->slot[1].bus_width) {
1397 case 4:
1398 piob_mask |= 1 << 8;
1399 piob_mask |= 1 << 9;
1400 piob_mask |= 1 << 10;
1401
1402 case 1:
1403 piob_mask |= 1 << 6;
1404 piob_mask |= 1 << 7;
1405 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1406
1407 if (gpio_is_valid(data->slot[1].detect_pin))
1408 at32_select_gpio(data->slot[1].detect_pin, 0);
1409 if (gpio_is_valid(data->slot[1].wp_pin))
1410 at32_select_gpio(data->slot[1].wp_pin, 0);
1411 break;
1412 case 0:
1413
1414 break;
1415 default:
1416 if (!data->slot[0].bus_width)
1417 goto fail_free;
1418
1419 data->slot[1].bus_width = 0;
1420 break;
1421 }
1422
1423 atmel_mci0_pclk.dev = &pdev->dev;
1424
1425 platform_device_add(pdev);
1426 return pdev;
1427
1428fail_free:
1429 kfree(slave);
1430fail:
1431 data->dma_slave = NULL;
1432 platform_device_put(pdev);
1433 return NULL;
1434}
1435
1436
1437
1438
1439#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1440static struct atmel_lcdfb_info atmel_lcdfb0_data;
1441static struct resource atmel_lcdfb0_resource[] = {
1442 {
1443 .start = 0xff000000,
1444 .end = 0xff000fff,
1445 .flags = IORESOURCE_MEM,
1446 },
1447 IRQ(1),
1448 {
1449
1450 .start = 0x00000000,
1451 .end = 0x00000000,
1452 .flags = 0,
1453 },
1454};
1455DEFINE_DEV_DATA(atmel_lcdfb, 0);
1456DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1457static struct clk atmel_lcdfb0_pixclk = {
1458 .name = "lcdc_clk",
1459 .dev = &atmel_lcdfb0_device.dev,
1460 .mode = genclk_mode,
1461 .get_rate = genclk_get_rate,
1462 .set_rate = genclk_set_rate,
1463 .set_parent = genclk_set_parent,
1464 .index = 7,
1465};
1466
1467struct platform_device *__init
1468at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1469 unsigned long fbmem_start, unsigned long fbmem_len,
1470 u64 pin_mask)
1471{
1472 struct platform_device *pdev;
1473 struct atmel_lcdfb_info *info;
1474 struct fb_monspecs *monspecs;
1475 struct fb_videomode *modedb;
1476 unsigned int modedb_size;
1477 u32 portc_mask, portd_mask, porte_mask;
1478
1479
1480
1481
1482
1483
1484 monspecs = kmemdup(data->default_monspecs,
1485 sizeof(struct fb_monspecs), GFP_KERNEL);
1486 if (!monspecs)
1487 return NULL;
1488
1489 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1490 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1491 if (!modedb)
1492 goto err_dup_modedb;
1493 monspecs->modedb = modedb;
1494
1495 switch (id) {
1496 case 0:
1497 pdev = &atmel_lcdfb0_device;
1498
1499 if (pin_mask == 0ULL)
1500
1501 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1502
1503
1504 portc_mask = pin_mask & 0xfff80000;
1505 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1506
1507
1508 portd_mask = pin_mask & 0x0003ffff;
1509 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1510
1511
1512 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1513 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1514
1515 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1516 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1517 break;
1518
1519 default:
1520 goto err_invalid_id;
1521 }
1522
1523 if (fbmem_len) {
1524 pdev->resource[2].start = fbmem_start;
1525 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1526 pdev->resource[2].flags = IORESOURCE_MEM;
1527 }
1528
1529 info = pdev->dev.platform_data;
1530 memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1531 info->default_monspecs = monspecs;
1532
1533 platform_device_register(pdev);
1534 return pdev;
1535
1536err_invalid_id:
1537 kfree(modedb);
1538err_dup_modedb:
1539 kfree(monspecs);
1540 return NULL;
1541}
1542#endif
1543
1544
1545
1546
1547static struct resource atmel_pwm0_resource[] __initdata = {
1548 PBMEM(0xfff01400),
1549 IRQ(24),
1550};
1551static struct clk atmel_pwm0_mck = {
1552 .name = "pwm_clk",
1553 .parent = &pbb_clk,
1554 .mode = pbb_clk_mode,
1555 .get_rate = pbb_clk_get_rate,
1556 .index = 5,
1557};
1558
1559struct platform_device *__init at32_add_device_pwm(u32 mask)
1560{
1561 struct platform_device *pdev;
1562 u32 pin_mask;
1563
1564 if (!mask)
1565 return NULL;
1566
1567 pdev = platform_device_alloc("atmel_pwm", 0);
1568 if (!pdev)
1569 return NULL;
1570
1571 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1572 ARRAY_SIZE(atmel_pwm0_resource)))
1573 goto out_free_pdev;
1574
1575 if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1576 goto out_free_pdev;
1577
1578 pin_mask = 0;
1579 if (mask & (1 << 0))
1580 pin_mask |= (1 << 28);
1581 if (mask & (1 << 1))
1582 pin_mask |= (1 << 29);
1583 if (pin_mask > 0)
1584 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1585
1586 pin_mask = 0;
1587 if (mask & (1 << 2))
1588 pin_mask |= (1 << 21);
1589 if (mask & (1 << 3))
1590 pin_mask |= (1 << 22);
1591 if (pin_mask > 0)
1592 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1593
1594 atmel_pwm0_mck.dev = &pdev->dev;
1595
1596 platform_device_add(pdev);
1597
1598 return pdev;
1599
1600out_free_pdev:
1601 platform_device_put(pdev);
1602 return NULL;
1603}
1604
1605
1606
1607
1608static struct resource ssc0_resource[] = {
1609 PBMEM(0xffe01c00),
1610 IRQ(10),
1611};
1612DEFINE_DEV(ssc, 0);
1613DEV_CLK(pclk, ssc0, pba, 7);
1614
1615static struct resource ssc1_resource[] = {
1616 PBMEM(0xffe02000),
1617 IRQ(11),
1618};
1619DEFINE_DEV(ssc, 1);
1620DEV_CLK(pclk, ssc1, pba, 8);
1621
1622static struct resource ssc2_resource[] = {
1623 PBMEM(0xffe02400),
1624 IRQ(12),
1625};
1626DEFINE_DEV(ssc, 2);
1627DEV_CLK(pclk, ssc2, pba, 9);
1628
1629struct platform_device *__init
1630at32_add_device_ssc(unsigned int id, unsigned int flags)
1631{
1632 struct platform_device *pdev;
1633 u32 pin_mask = 0;
1634
1635 switch (id) {
1636 case 0:
1637 pdev = &ssc0_device;
1638 if (flags & ATMEL_SSC_RF)
1639 pin_mask |= (1 << 21);
1640 if (flags & ATMEL_SSC_RK)
1641 pin_mask |= (1 << 22);
1642 if (flags & ATMEL_SSC_TK)
1643 pin_mask |= (1 << 23);
1644 if (flags & ATMEL_SSC_TF)
1645 pin_mask |= (1 << 24);
1646 if (flags & ATMEL_SSC_TD)
1647 pin_mask |= (1 << 25);
1648 if (flags & ATMEL_SSC_RD)
1649 pin_mask |= (1 << 26);
1650
1651 if (pin_mask > 0)
1652 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1653
1654 break;
1655 case 1:
1656 pdev = &ssc1_device;
1657 if (flags & ATMEL_SSC_RF)
1658 pin_mask |= (1 << 0);
1659 if (flags & ATMEL_SSC_RK)
1660 pin_mask |= (1 << 1);
1661 if (flags & ATMEL_SSC_TK)
1662 pin_mask |= (1 << 2);
1663 if (flags & ATMEL_SSC_TF)
1664 pin_mask |= (1 << 3);
1665 if (flags & ATMEL_SSC_TD)
1666 pin_mask |= (1 << 4);
1667 if (flags & ATMEL_SSC_RD)
1668 pin_mask |= (1 << 5);
1669
1670 if (pin_mask > 0)
1671 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1672
1673 break;
1674 case 2:
1675 pdev = &ssc2_device;
1676 if (flags & ATMEL_SSC_TD)
1677 pin_mask |= (1 << 13);
1678 if (flags & ATMEL_SSC_RD)
1679 pin_mask |= (1 << 14);
1680 if (flags & ATMEL_SSC_TK)
1681 pin_mask |= (1 << 15);
1682 if (flags & ATMEL_SSC_TF)
1683 pin_mask |= (1 << 16);
1684 if (flags & ATMEL_SSC_RF)
1685 pin_mask |= (1 << 17);
1686 if (flags & ATMEL_SSC_RK)
1687 pin_mask |= (1 << 18);
1688
1689 if (pin_mask > 0)
1690 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1691
1692 break;
1693 default:
1694 return NULL;
1695 }
1696
1697 platform_device_register(pdev);
1698 return pdev;
1699}
1700
1701
1702
1703
1704static struct resource usba0_resource[] __initdata = {
1705 {
1706 .start = 0xff300000,
1707 .end = 0xff3fffff,
1708 .flags = IORESOURCE_MEM,
1709 }, {
1710 .start = 0xfff03000,
1711 .end = 0xfff033ff,
1712 .flags = IORESOURCE_MEM,
1713 },
1714 IRQ(31),
1715};
1716static struct clk usba0_pclk = {
1717 .name = "pclk",
1718 .parent = &pbb_clk,
1719 .mode = pbb_clk_mode,
1720 .get_rate = pbb_clk_get_rate,
1721 .index = 12,
1722};
1723static struct clk usba0_hclk = {
1724 .name = "hclk",
1725 .parent = &hsb_clk,
1726 .mode = hsb_clk_mode,
1727 .get_rate = hsb_clk_get_rate,
1728 .index = 6,
1729};
1730
1731#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1732 [idx] = { \
1733 .name = nam, \
1734 .index = idx, \
1735 .fifo_size = maxpkt, \
1736 .nr_banks = maxbk, \
1737 .can_dma = dma, \
1738 .can_isoc = isoc, \
1739 }
1740
1741static struct usba_ep_data at32_usba_ep[] __initdata = {
1742 EP("ep0", 0, 64, 1, 0, 0),
1743 EP("ep1", 1, 512, 2, 1, 1),
1744 EP("ep2", 2, 512, 2, 1, 1),
1745 EP("ep3-int", 3, 64, 3, 1, 0),
1746 EP("ep4-int", 4, 64, 3, 1, 0),
1747 EP("ep5", 5, 1024, 3, 1, 1),
1748 EP("ep6", 6, 1024, 3, 1, 1),
1749};
1750
1751#undef EP
1752
1753struct platform_device *__init
1754at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1755{
1756
1757
1758
1759
1760 struct {
1761 struct usba_platform_data pdata;
1762 struct usba_ep_data ep[7];
1763 } usba_data;
1764 struct platform_device *pdev;
1765
1766 if (id != 0)
1767 return NULL;
1768
1769 pdev = platform_device_alloc("atmel_usba_udc", 0);
1770 if (!pdev)
1771 return NULL;
1772
1773 if (platform_device_add_resources(pdev, usba0_resource,
1774 ARRAY_SIZE(usba0_resource)))
1775 goto out_free_pdev;
1776
1777 if (data) {
1778 usba_data.pdata.vbus_pin = data->vbus_pin;
1779 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1780 } else {
1781 usba_data.pdata.vbus_pin = -EINVAL;
1782 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1783 }
1784
1785 data = &usba_data.pdata;
1786 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1787 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1788
1789 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1790 goto out_free_pdev;
1791
1792 if (gpio_is_valid(data->vbus_pin))
1793 at32_select_gpio(data->vbus_pin, 0);
1794
1795 usba0_pclk.dev = &pdev->dev;
1796 usba0_hclk.dev = &pdev->dev;
1797
1798 platform_device_add(pdev);
1799
1800 return pdev;
1801
1802out_free_pdev:
1803 platform_device_put(pdev);
1804 return NULL;
1805}
1806
1807
1808
1809
1810#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1811static struct resource at32_smc_cs4_resource[] __initdata = {
1812 {
1813 .start = 0x04000000,
1814 .end = 0x07ffffff,
1815 .flags = IORESOURCE_MEM,
1816 },
1817 IRQ(~0UL),
1818};
1819static struct resource at32_smc_cs5_resource[] __initdata = {
1820 {
1821 .start = 0x20000000,
1822 .end = 0x23ffffff,
1823 .flags = IORESOURCE_MEM,
1824 },
1825 IRQ(~0UL),
1826};
1827
1828static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1829 unsigned int cs, unsigned int extint)
1830{
1831 static unsigned int extint_pin_map[4] __initdata = {
1832 (1 << 25),
1833 (1 << 26),
1834 (1 << 27),
1835 (1 << 28),
1836 };
1837 static bool common_pins_initialized __initdata = false;
1838 unsigned int extint_pin;
1839 int ret;
1840 u32 pin_mask;
1841
1842 if (extint >= ARRAY_SIZE(extint_pin_map))
1843 return -EINVAL;
1844 extint_pin = extint_pin_map[extint];
1845
1846 switch (cs) {
1847 case 4:
1848 ret = platform_device_add_resources(pdev,
1849 at32_smc_cs4_resource,
1850 ARRAY_SIZE(at32_smc_cs4_resource));
1851 if (ret)
1852 return ret;
1853
1854
1855 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1856 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1857 break;
1858 case 5:
1859 ret = platform_device_add_resources(pdev,
1860 at32_smc_cs5_resource,
1861 ARRAY_SIZE(at32_smc_cs5_resource));
1862 if (ret)
1863 return ret;
1864
1865
1866 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1867 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1868 break;
1869 default:
1870 return -EINVAL;
1871 }
1872
1873 if (!common_pins_initialized) {
1874 pin_mask = (1 << 19);
1875 pin_mask |= (1 << 20);
1876 pin_mask |= (1 << 23);
1877 pin_mask |= (1 << 24);
1878
1879 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1880
1881 common_pins_initialized = true;
1882 }
1883
1884 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1885
1886 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1887 pdev->resource[1].end = pdev->resource[1].start;
1888
1889 return 0;
1890}
1891
1892struct platform_device *__init
1893at32_add_device_ide(unsigned int id, unsigned int extint,
1894 struct ide_platform_data *data)
1895{
1896 struct platform_device *pdev;
1897
1898 pdev = platform_device_alloc("at32_ide", id);
1899 if (!pdev)
1900 goto fail;
1901
1902 if (platform_device_add_data(pdev, data,
1903 sizeof(struct ide_platform_data)))
1904 goto fail;
1905
1906 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1907 goto fail;
1908
1909 platform_device_add(pdev);
1910 return pdev;
1911
1912fail:
1913 platform_device_put(pdev);
1914 return NULL;
1915}
1916
1917struct platform_device *__init
1918at32_add_device_cf(unsigned int id, unsigned int extint,
1919 struct cf_platform_data *data)
1920{
1921 struct platform_device *pdev;
1922
1923 pdev = platform_device_alloc("at32_cf", id);
1924 if (!pdev)
1925 goto fail;
1926
1927 if (platform_device_add_data(pdev, data,
1928 sizeof(struct cf_platform_data)))
1929 goto fail;
1930
1931 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1932 goto fail;
1933
1934 if (gpio_is_valid(data->detect_pin))
1935 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1936 if (gpio_is_valid(data->reset_pin))
1937 at32_select_gpio(data->reset_pin, 0);
1938 if (gpio_is_valid(data->vcc_pin))
1939 at32_select_gpio(data->vcc_pin, 0);
1940
1941
1942 platform_device_add(pdev);
1943 return pdev;
1944
1945fail:
1946 platform_device_put(pdev);
1947 return NULL;
1948}
1949#endif
1950
1951
1952
1953
1954static struct resource smc_cs3_resource[] __initdata = {
1955 {
1956 .start = 0x0c000000,
1957 .end = 0x0fffffff,
1958 .flags = IORESOURCE_MEM,
1959 }, {
1960 .start = 0xfff03c00,
1961 .end = 0xfff03fff,
1962 .flags = IORESOURCE_MEM,
1963 },
1964};
1965
1966struct platform_device *__init
1967at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1968{
1969 struct platform_device *pdev;
1970
1971 if (id != 0 || !data)
1972 return NULL;
1973
1974 pdev = platform_device_alloc("atmel_nand", id);
1975 if (!pdev)
1976 goto fail;
1977
1978 if (platform_device_add_resources(pdev, smc_cs3_resource,
1979 ARRAY_SIZE(smc_cs3_resource)))
1980 goto fail;
1981
1982 if (platform_device_add_data(pdev, data,
1983 sizeof(struct atmel_nand_data)))
1984 goto fail;
1985
1986 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1987 if (data->enable_pin)
1988 at32_select_gpio(data->enable_pin,
1989 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1990 if (data->rdy_pin)
1991 at32_select_gpio(data->rdy_pin, 0);
1992 if (data->det_pin)
1993 at32_select_gpio(data->det_pin, 0);
1994
1995 platform_device_add(pdev);
1996 return pdev;
1997
1998fail:
1999 platform_device_put(pdev);
2000 return NULL;
2001}
2002
2003
2004
2005
2006static struct resource atmel_ac97c0_resource[] __initdata = {
2007 PBMEM(0xfff02800),
2008 IRQ(29),
2009};
2010static struct clk atmel_ac97c0_pclk = {
2011 .name = "pclk",
2012 .parent = &pbb_clk,
2013 .mode = pbb_clk_mode,
2014 .get_rate = pbb_clk_get_rate,
2015 .index = 10,
2016};
2017
2018struct platform_device *__init
2019at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2020 unsigned int flags)
2021{
2022 struct platform_device *pdev;
2023 struct dw_dma_slave *rx_dws;
2024 struct dw_dma_slave *tx_dws;
2025 struct ac97c_platform_data _data;
2026 u32 pin_mask;
2027
2028 if (id != 0)
2029 return NULL;
2030
2031 pdev = platform_device_alloc("atmel_ac97c", id);
2032 if (!pdev)
2033 return NULL;
2034
2035 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2036 ARRAY_SIZE(atmel_ac97c0_resource)))
2037 goto out_free_resources;
2038
2039 if (!data) {
2040 data = &_data;
2041 memset(data, 0, sizeof(struct ac97c_platform_data));
2042 data->reset_pin = -ENODEV;
2043 }
2044
2045 rx_dws = &data->rx_dws;
2046 tx_dws = &data->tx_dws;
2047
2048
2049 if (flags & AC97C_CAPTURE) {
2050 rx_dws->dma_dev = &dw_dmac0_device.dev;
2051 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2052 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2053 rx_dws->src_master = 0;
2054 rx_dws->dst_master = 1;
2055 }
2056
2057
2058 if (flags & AC97C_PLAYBACK) {
2059 tx_dws->dma_dev = &dw_dmac0_device.dev;
2060 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2061 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2062 tx_dws->src_master = 0;
2063 tx_dws->dst_master = 1;
2064 }
2065
2066 if (platform_device_add_data(pdev, data,
2067 sizeof(struct ac97c_platform_data)))
2068 goto out_free_resources;
2069
2070
2071 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2072
2073 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2074
2075 if (gpio_is_valid(data->reset_pin))
2076 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2077 | AT32_GPIOF_HIGH);
2078
2079 atmel_ac97c0_pclk.dev = &pdev->dev;
2080
2081 platform_device_add(pdev);
2082 return pdev;
2083
2084out_free_resources:
2085 platform_device_put(pdev);
2086 return NULL;
2087}
2088
2089
2090
2091
2092static struct resource abdac0_resource[] __initdata = {
2093 PBMEM(0xfff02000),
2094 IRQ(27),
2095};
2096static struct clk abdac0_pclk = {
2097 .name = "pclk",
2098 .parent = &pbb_clk,
2099 .mode = pbb_clk_mode,
2100 .get_rate = pbb_clk_get_rate,
2101 .index = 8,
2102};
2103static struct clk abdac0_sample_clk = {
2104 .name = "sample_clk",
2105 .mode = genclk_mode,
2106 .get_rate = genclk_get_rate,
2107 .set_rate = genclk_set_rate,
2108 .set_parent = genclk_set_parent,
2109 .index = 6,
2110};
2111
2112struct platform_device *__init
2113at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2114{
2115 struct platform_device *pdev;
2116 struct dw_dma_slave *dws;
2117 u32 pin_mask;
2118
2119 if (id != 0 || !data)
2120 return NULL;
2121
2122 pdev = platform_device_alloc("atmel_abdac", id);
2123 if (!pdev)
2124 return NULL;
2125
2126 if (platform_device_add_resources(pdev, abdac0_resource,
2127 ARRAY_SIZE(abdac0_resource)))
2128 goto out_free_resources;
2129
2130 dws = &data->dws;
2131
2132 dws->dma_dev = &dw_dmac0_device.dev;
2133 dws->cfg_hi = DWC_CFGH_DST_PER(2);
2134 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2135 dws->src_master = 0;
2136 dws->dst_master = 1;
2137
2138 if (platform_device_add_data(pdev, data,
2139 sizeof(struct atmel_abdac_pdata)))
2140 goto out_free_resources;
2141
2142 pin_mask = (1 << 20) | (1 << 22);
2143 pin_mask |= (1 << 21) | (1 << 23);
2144
2145 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2146
2147 abdac0_pclk.dev = &pdev->dev;
2148 abdac0_sample_clk.dev = &pdev->dev;
2149
2150 platform_device_add(pdev);
2151 return pdev;
2152
2153out_free_resources:
2154 platform_device_put(pdev);
2155 return NULL;
2156}
2157
2158
2159
2160
2161static struct clk gclk0 = {
2162 .name = "gclk0",
2163 .mode = genclk_mode,
2164 .get_rate = genclk_get_rate,
2165 .set_rate = genclk_set_rate,
2166 .set_parent = genclk_set_parent,
2167 .index = 0,
2168};
2169static struct clk gclk1 = {
2170 .name = "gclk1",
2171 .mode = genclk_mode,
2172 .get_rate = genclk_get_rate,
2173 .set_rate = genclk_set_rate,
2174 .set_parent = genclk_set_parent,
2175 .index = 1,
2176};
2177static struct clk gclk2 = {
2178 .name = "gclk2",
2179 .mode = genclk_mode,
2180 .get_rate = genclk_get_rate,
2181 .set_rate = genclk_set_rate,
2182 .set_parent = genclk_set_parent,
2183 .index = 2,
2184};
2185static struct clk gclk3 = {
2186 .name = "gclk3",
2187 .mode = genclk_mode,
2188 .get_rate = genclk_get_rate,
2189 .set_rate = genclk_set_rate,
2190 .set_parent = genclk_set_parent,
2191 .index = 3,
2192};
2193static struct clk gclk4 = {
2194 .name = "gclk4",
2195 .mode = genclk_mode,
2196 .get_rate = genclk_get_rate,
2197 .set_rate = genclk_set_rate,
2198 .set_parent = genclk_set_parent,
2199 .index = 4,
2200};
2201
2202static __initdata struct clk *init_clocks[] = {
2203 &osc32k,
2204 &osc0,
2205 &osc1,
2206 &pll0,
2207 &pll1,
2208 &cpu_clk,
2209 &hsb_clk,
2210 &pba_clk,
2211 &pbb_clk,
2212 &at32_pm_pclk,
2213 &at32_intc0_pclk,
2214 &at32_hmatrix_clk,
2215 &ebi_clk,
2216 &hramc_clk,
2217 &sdramc_clk,
2218 &smc0_pclk,
2219 &smc0_mck,
2220 &pdc_hclk,
2221 &pdc_pclk,
2222 &dw_dmac0_hclk,
2223 &pico_clk,
2224 &pio0_mck,
2225 &pio1_mck,
2226 &pio2_mck,
2227 &pio3_mck,
2228 &pio4_mck,
2229 &at32_tcb0_t0_clk,
2230 &at32_tcb1_t0_clk,
2231 &atmel_psif0_pclk,
2232 &atmel_psif1_pclk,
2233 &atmel_usart0_usart,
2234 &atmel_usart1_usart,
2235 &atmel_usart2_usart,
2236 &atmel_usart3_usart,
2237 &atmel_pwm0_mck,
2238#if defined(CONFIG_CPU_AT32AP7000)
2239 &macb0_hclk,
2240 &macb0_pclk,
2241 &macb1_hclk,
2242 &macb1_pclk,
2243#endif
2244 &atmel_spi0_spi_clk,
2245 &atmel_spi1_spi_clk,
2246 &atmel_twi0_pclk,
2247 &atmel_mci0_pclk,
2248#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2249 &atmel_lcdfb0_hck1,
2250 &atmel_lcdfb0_pixclk,
2251#endif
2252 &ssc0_pclk,
2253 &ssc1_pclk,
2254 &ssc2_pclk,
2255 &usba0_hclk,
2256 &usba0_pclk,
2257 &atmel_ac97c0_pclk,
2258 &abdac0_pclk,
2259 &abdac0_sample_clk,
2260 &gclk0,
2261 &gclk1,
2262 &gclk2,
2263 &gclk3,
2264 &gclk4,
2265};
2266
2267void __init setup_platform(void)
2268{
2269 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2270 int i;
2271
2272 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2273 main_clock = &pll0;
2274 cpu_clk.parent = &pll0;
2275 } else {
2276 main_clock = &osc0;
2277 cpu_clk.parent = &osc0;
2278 }
2279
2280 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2281 pll0.parent = &osc1;
2282 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2283 pll1.parent = &osc1;
2284
2285 genclk_init_parent(&gclk0);
2286 genclk_init_parent(&gclk1);
2287 genclk_init_parent(&gclk2);
2288 genclk_init_parent(&gclk3);
2289 genclk_init_parent(&gclk4);
2290#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2291 genclk_init_parent(&atmel_lcdfb0_pixclk);
2292#endif
2293 genclk_init_parent(&abdac0_sample_clk);
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2305 struct clk *clk = init_clocks[i];
2306
2307
2308 at32_clk_register(clk);
2309
2310 if (clk->users == 0)
2311 continue;
2312
2313 if (clk->mode == &cpu_clk_mode)
2314 cpu_mask |= 1 << clk->index;
2315 else if (clk->mode == &hsb_clk_mode)
2316 hsb_mask |= 1 << clk->index;
2317 else if (clk->mode == &pba_clk_mode)
2318 pba_mask |= 1 << clk->index;
2319 else if (clk->mode == &pbb_clk_mode)
2320 pbb_mask |= 1 << clk->index;
2321 }
2322
2323 pm_writel(CPU_MASK, cpu_mask);
2324 pm_writel(HSB_MASK, hsb_mask);
2325 pm_writel(PBA_MASK, pba_mask);
2326 pm_writel(PBB_MASK, pbb_mask);
2327
2328
2329 at32_init_pio(&pio0_device);
2330 at32_init_pio(&pio1_device);
2331 at32_init_pio(&pio2_device);
2332 at32_init_pio(&pio3_device);
2333 at32_init_pio(&pio4_device);
2334}
2335
2336struct gen_pool *sram_pool;
2337
2338static int __init sram_init(void)
2339{
2340 struct gen_pool *pool;
2341
2342
2343 pool = gen_pool_create(10, -1);
2344 if (!pool)
2345 goto fail;
2346
2347 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2348 goto err_pool_add;
2349
2350 sram_pool = pool;
2351 return 0;
2352
2353err_pool_add:
2354 gen_pool_destroy(pool);
2355fail:
2356 pr_err("Failed to create SRAM pool\n");
2357 return -ENOMEM;
2358}
2359core_initcall(sram_init);
2360