linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
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   1#ifndef BCM63XX_DEV_SPI_H
   2#define BCM63XX_DEV_SPI_H
   3
   4#include <linux/types.h>
   5#include <bcm63xx_io.h>
   6#include <bcm63xx_regs.h>
   7
   8int __init bcm63xx_spi_register(void);
   9
  10struct bcm63xx_spi_pdata {
  11        unsigned int    fifo_size;
  12        unsigned int    msg_type_shift;
  13        unsigned int    msg_ctl_width;
  14        int             bus_num;
  15        int             num_chipselect;
  16        u32             speed_hz;
  17};
  18
  19enum bcm63xx_regs_spi {
  20        SPI_CMD,
  21        SPI_INT_STATUS,
  22        SPI_INT_MASK_ST,
  23        SPI_INT_MASK,
  24        SPI_ST,
  25        SPI_CLK_CFG,
  26        SPI_FILL_BYTE,
  27        SPI_MSG_TAIL,
  28        SPI_RX_TAIL,
  29        SPI_MSG_CTL,
  30        SPI_MSG_DATA,
  31        SPI_RX_DATA,
  32};
  33
  34#define __GEN_SPI_RSET_BASE(__cpu, __rset)                              \
  35        case SPI_## __rset:                                             \
  36                return SPI_## __cpu ##_## __rset;
  37
  38#define __GEN_SPI_RSET(__cpu)                                           \
  39        switch (reg) {                                                  \
  40        __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
  41        __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
  42        __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
  43        __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
  44        __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
  45        __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
  46        __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
  47        __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
  48        __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
  49        __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
  50        __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
  51        __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
  52        }
  53
  54#define __GEN_SPI_REGS_TABLE(__cpu)                                     \
  55        [SPI_CMD]               = SPI_## __cpu ##_CMD,                  \
  56        [SPI_INT_STATUS]        = SPI_## __cpu ##_INT_STATUS,           \
  57        [SPI_INT_MASK_ST]       = SPI_## __cpu ##_INT_MASK_ST,          \
  58        [SPI_INT_MASK]          = SPI_## __cpu ##_INT_MASK,             \
  59        [SPI_ST]                = SPI_## __cpu ##_ST,                   \
  60        [SPI_CLK_CFG]           = SPI_## __cpu ##_CLK_CFG,              \
  61        [SPI_FILL_BYTE]         = SPI_## __cpu ##_FILL_BYTE,            \
  62        [SPI_MSG_TAIL]          = SPI_## __cpu ##_MSG_TAIL,             \
  63        [SPI_RX_TAIL]           = SPI_## __cpu ##_RX_TAIL,              \
  64        [SPI_MSG_CTL]           = SPI_## __cpu ##_MSG_CTL,              \
  65        [SPI_MSG_DATA]          = SPI_## __cpu ##_MSG_DATA,             \
  66        [SPI_RX_DATA]           = SPI_## __cpu ##_RX_DATA,
  67
  68static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
  69{
  70#ifdef BCMCPU_RUNTIME_DETECT
  71        extern const unsigned long *bcm63xx_regs_spi;
  72
  73        return bcm63xx_regs_spi[reg];
  74#else
  75#ifdef CONFIG_BCM63XX_CPU_6338
  76        __GEN_SPI_RSET(6338)
  77#endif
  78#ifdef CONFIG_BCM63XX_CPU_6348
  79        __GEN_SPI_RSET(6348)
  80#endif
  81#ifdef CONFIG_BCM63XX_CPU_6358
  82        __GEN_SPI_RSET(6358)
  83#endif
  84#ifdef CONFIG_BCM63XX_CPU_6368
  85        __GEN_SPI_RSET(6368)
  86#endif
  87#endif
  88        return 0;
  89}
  90
  91#endif /* BCM63XX_DEV_SPI_H */
  92