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12#ifndef __OPAL_H
13#define __OPAL_H
14
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22
23#ifndef __ASSEMBLY__
24
25struct opal_takeover_args {
26 u64 k_image;
27 u64 k_size;
28 u64 k_entry;
29 u64 k_entry2;
30 u64 hal_addr;
31 u64 rd_image;
32 u64 rd_size;
33 u64 rd_loc;
34};
35
36extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
37
38extern long opal_do_takeover(struct opal_takeover_args *args);
39
40struct rtas_args;
41extern int opal_enter_rtas(struct rtas_args *args,
42 unsigned long data,
43 unsigned long entry);
44
45#endif
46
47
48
49
50#define OPAL_SUCCESS 0
51#define OPAL_PARAMETER -1
52#define OPAL_BUSY -2
53#define OPAL_PARTIAL -3
54#define OPAL_CONSTRAINED -4
55#define OPAL_CLOSED -5
56#define OPAL_HARDWARE -6
57#define OPAL_UNSUPPORTED -7
58#define OPAL_PERMISSION -8
59#define OPAL_NO_MEM -9
60#define OPAL_RESOURCE -10
61#define OPAL_INTERNAL_ERROR -11
62#define OPAL_BUSY_EVENT -12
63#define OPAL_HARDWARE_FROZEN -13
64
65
66#define OPAL_CONSOLE_WRITE 1
67#define OPAL_CONSOLE_READ 2
68#define OPAL_RTC_READ 3
69#define OPAL_RTC_WRITE 4
70#define OPAL_CEC_POWER_DOWN 5
71#define OPAL_CEC_REBOOT 6
72#define OPAL_READ_NVRAM 7
73#define OPAL_WRITE_NVRAM 8
74#define OPAL_HANDLE_INTERRUPT 9
75#define OPAL_POLL_EVENTS 10
76#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
77#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
78#define OPAL_PCI_CONFIG_READ_BYTE 13
79#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
80#define OPAL_PCI_CONFIG_READ_WORD 15
81#define OPAL_PCI_CONFIG_WRITE_BYTE 16
82#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
83#define OPAL_PCI_CONFIG_WRITE_WORD 18
84#define OPAL_SET_XIVE 19
85#define OPAL_GET_XIVE 20
86#define OPAL_GET_COMPLETION_TOKEN_STATUS 21
87#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
88#define OPAL_PCI_EEH_FREEZE_STATUS 23
89#define OPAL_PCI_SHPC 24
90#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
91#define OPAL_PCI_EEH_FREEZE_CLEAR 26
92#define OPAL_PCI_PHB_MMIO_ENABLE 27
93#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
94#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
95#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
96#define OPAL_PCI_SET_PE 31
97#define OPAL_PCI_SET_PELTV 32
98#define OPAL_PCI_SET_MVE 33
99#define OPAL_PCI_SET_MVE_ENABLE 34
100#define OPAL_PCI_GET_XIVE_REISSUE 35
101#define OPAL_PCI_SET_XIVE_REISSUE 36
102#define OPAL_PCI_SET_XIVE_PE 37
103#define OPAL_GET_XIVE_SOURCE 38
104#define OPAL_GET_MSI_32 39
105#define OPAL_GET_MSI_64 40
106#define OPAL_START_CPU 41
107#define OPAL_QUERY_CPU_STATUS 42
108#define OPAL_WRITE_OPPANEL 43
109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111#define OPAL_PCI_RESET 49
112#define OPAL_PCI_GET_HUB_DIAG_DATA 50
113#define OPAL_PCI_GET_PHB_DIAG_DATA 51
114#define OPAL_PCI_FENCE_PHB 52
115#define OPAL_PCI_REINIT 53
116#define OPAL_PCI_MASK_PE_ERROR 54
117#define OPAL_SET_SLOT_LED_STATUS 55
118#define OPAL_GET_EPOW_STATUS 56
119#define OPAL_SET_SYSTEM_ATTENTION_LED 57
120
121#ifndef __ASSEMBLY__
122
123
124enum OpalVendorApiTokens {
125 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
126};
127enum OpalFreezeState {
128 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
129 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
130 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
131 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
132 OPAL_EEH_STOPPED_RESET = 4,
133 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
134 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
135};
136enum OpalEehFreezeActionToken {
137 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
138 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
139 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
140};
141enum OpalPciStatusToken {
142 OPAL_EEH_PHB_NO_ERROR = 0,
143 OPAL_EEH_PHB_FATAL = 1,
144 OPAL_EEH_PHB_RECOVERABLE = 2,
145 OPAL_EEH_PHB_BUS_ERROR = 3,
146 OPAL_EEH_PCI_NO_DEVSEL = 4,
147 OPAL_EEH_PCI_TA = 5,
148 OPAL_EEH_PCIEX_UR = 6,
149 OPAL_EEH_PCIEX_CA = 7,
150 OPAL_EEH_PCI_MMIO_ERROR = 8,
151 OPAL_EEH_PCI_DMA_ERROR = 9
152};
153enum OpalShpcAction {
154 OPAL_SHPC_GET_LINK_STATE = 0,
155 OPAL_SHPC_GET_SLOT_STATE = 1
156};
157enum OpalShpcLinkState {
158 OPAL_SHPC_LINK_DOWN = 0,
159 OPAL_SHPC_LINK_UP = 1
160};
161enum OpalMmioWindowType {
162 OPAL_M32_WINDOW_TYPE = 1,
163 OPAL_M64_WINDOW_TYPE = 2,
164 OPAL_IO_WINDOW_TYPE = 3
165};
166enum OpalShpcSlotState {
167 OPAL_SHPC_DEV_NOT_PRESENT = 0,
168 OPAL_SHPC_DEV_PRESENT = 1
169};
170enum OpalExceptionHandler {
171 OPAL_MACHINE_CHECK_HANDLER = 1,
172 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
173 OPAL_SOFTPATCH_HANDLER = 3
174};
175enum OpalPendingState {
176 OPAL_EVENT_OPAL_INTERNAL = 0x1,
177 OPAL_EVENT_NVRAM = 0x2,
178 OPAL_EVENT_RTC = 0x4,
179 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
180 OPAL_EVENT_CONSOLE_INPUT = 0x10,
181 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
182 OPAL_EVENT_ERROR_LOG = 0x40,
183 OPAL_EVENT_EPOW = 0x80,
184 OPAL_EVENT_LED_STATUS = 0x100
185};
186
187
188enum OpalMCE_Version {
189 OpalMCE_V1 = 1,
190};
191
192enum OpalMCE_Severity {
193 OpalMCE_SEV_NO_ERROR = 0,
194 OpalMCE_SEV_WARNING = 1,
195 OpalMCE_SEV_ERROR_SYNC = 2,
196 OpalMCE_SEV_FATAL = 3,
197};
198
199enum OpalMCE_Disposition {
200 OpalMCE_DISPOSITION_RECOVERED = 0,
201 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
202};
203
204enum OpalMCE_Initiator {
205 OpalMCE_INITIATOR_UNKNOWN = 0,
206 OpalMCE_INITIATOR_CPU = 1,
207};
208
209enum OpalMCE_ErrorType {
210 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
211 OpalMCE_ERROR_TYPE_UE = 1,
212 OpalMCE_ERROR_TYPE_SLB = 2,
213 OpalMCE_ERROR_TYPE_ERAT = 3,
214 OpalMCE_ERROR_TYPE_TLB = 4,
215};
216
217enum OpalMCE_UeErrorType {
218 OpalMCE_UE_ERROR_INDETERMINATE = 0,
219 OpalMCE_UE_ERROR_IFETCH = 1,
220 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
221 OpalMCE_UE_ERROR_LOAD_STORE = 3,
222 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
223};
224
225enum OpalMCE_SlbErrorType {
226 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
227 OpalMCE_SLB_ERROR_PARITY = 1,
228 OpalMCE_SLB_ERROR_MULTIHIT = 2,
229};
230
231enum OpalMCE_EratErrorType {
232 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
233 OpalMCE_ERAT_ERROR_PARITY = 1,
234 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
235};
236
237enum OpalMCE_TlbErrorType {
238 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
239 OpalMCE_TLB_ERROR_PARITY = 1,
240 OpalMCE_TLB_ERROR_MULTIHIT = 2,
241};
242
243enum OpalThreadStatus {
244 OPAL_THREAD_INACTIVE = 0x0,
245 OPAL_THREAD_STARTED = 0x1
246};
247
248enum OpalPciBusCompare {
249 OpalPciBusAny = 0,
250 OpalPciBus3Bits = 2,
251 OpalPciBus4Bits = 3,
252 OpalPciBus5Bits = 4,
253 OpalPciBus6Bits = 5,
254 OpalPciBus7Bits = 6,
255 OpalPciBusAll = 7,
256};
257
258enum OpalDeviceCompare {
259 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
260 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
261};
262
263enum OpalFuncCompare {
264 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
265 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
266};
267
268enum OpalPeAction {
269 OPAL_UNMAP_PE = 0,
270 OPAL_MAP_PE = 1
271};
272
273enum OpalPeltvAction {
274 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
275 OPAL_ADD_PE_TO_DOMAIN = 1
276};
277
278enum OpalMveEnableAction {
279 OPAL_DISABLE_MVE = 0,
280 OPAL_ENABLE_MVE = 1
281};
282
283enum OpalPciResetAndReinitScope {
284 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
285 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
286 OPAL_PCI_IODA_TABLE_RESET = 6,
287};
288
289enum OpalPciResetState {
290 OPAL_DEASSERT_RESET = 0,
291 OPAL_ASSERT_RESET = 1
292};
293
294enum OpalPciMaskAction {
295 OPAL_UNMASK_ERROR_TYPE = 0,
296 OPAL_MASK_ERROR_TYPE = 1
297};
298
299enum OpalSlotLedType {
300 OPAL_SLOT_LED_ID_TYPE = 0,
301 OPAL_SLOT_LED_FAULT_TYPE = 1
302};
303
304enum OpalLedAction {
305 OPAL_TURN_OFF_LED = 0,
306 OPAL_TURN_ON_LED = 1,
307 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
308};
309
310enum OpalEpowStatus {
311 OPAL_EPOW_NONE = 0,
312 OPAL_EPOW_UPS = 1,
313 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
314 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
315};
316
317struct opal_machine_check_event {
318 enum OpalMCE_Version version:8;
319 uint8_t in_use;
320 enum OpalMCE_Severity severity:8;
321 enum OpalMCE_Initiator initiator:8;
322 enum OpalMCE_ErrorType error_type:8;
323 enum OpalMCE_Disposition disposition:8;
324 uint8_t reserved_1[2];
325 uint64_t gpr3;
326 uint64_t srr0;
327 uint64_t srr1;
328 union {
329 struct {
330 enum OpalMCE_UeErrorType ue_error_type:8;
331 uint8_t effective_address_provided;
332 uint8_t physical_address_provided;
333 uint8_t reserved_1[5];
334 uint64_t effective_address;
335 uint64_t physical_address;
336 uint8_t reserved_2[8];
337 } ue_error;
338
339 struct {
340 enum OpalMCE_SlbErrorType slb_error_type:8;
341 uint8_t effective_address_provided;
342 uint8_t reserved_1[6];
343 uint64_t effective_address;
344 uint8_t reserved_2[16];
345 } slb_error;
346
347 struct {
348 enum OpalMCE_EratErrorType erat_error_type:8;
349 uint8_t effective_address_provided;
350 uint8_t reserved_1[6];
351 uint64_t effective_address;
352 uint8_t reserved_2[16];
353 } erat_error;
354
355 struct {
356 enum OpalMCE_TlbErrorType tlb_error_type:8;
357 uint8_t effective_address_provided;
358 uint8_t reserved_1[6];
359 uint64_t effective_address;
360 uint8_t reserved_2[16];
361 } tlb_error;
362 } u;
363};
364
365
366
367
368
369enum {
370 OPAL_P7IOC_NUM_PEST_REGS = 128,
371};
372
373struct OpalIoP7IOCPhbErrorData {
374 uint32_t brdgCtl;
375
376
377 uint32_t portStatusReg;
378 uint32_t rootCmplxStatus;
379 uint32_t busAgentStatus;
380
381
382 uint32_t deviceStatus;
383 uint32_t slotStatus;
384 uint32_t linkStatus;
385 uint32_t devCmdStatus;
386 uint32_t devSecStatus;
387
388
389 uint32_t rootErrorStatus;
390 uint32_t uncorrErrorStatus;
391 uint32_t corrErrorStatus;
392 uint32_t tlpHdr1;
393 uint32_t tlpHdr2;
394 uint32_t tlpHdr3;
395 uint32_t tlpHdr4;
396 uint32_t sourceId;
397
398 uint32_t rsv3;
399
400
401 uint64_t errorClass;
402 uint64_t correlator;
403
404
405 uint64_t p7iocPlssr;
406 uint64_t p7iocCsr;
407 uint64_t lemFir;
408 uint64_t lemErrorMask;
409 uint64_t lemWOF;
410 uint64_t phbErrorStatus;
411 uint64_t phbFirstErrorStatus;
412 uint64_t phbErrorLog0;
413 uint64_t phbErrorLog1;
414 uint64_t mmioErrorStatus;
415 uint64_t mmioFirstErrorStatus;
416 uint64_t mmioErrorLog0;
417 uint64_t mmioErrorLog1;
418 uint64_t dma0ErrorStatus;
419 uint64_t dma0FirstErrorStatus;
420 uint64_t dma0ErrorLog0;
421 uint64_t dma0ErrorLog1;
422 uint64_t dma1ErrorStatus;
423 uint64_t dma1FirstErrorStatus;
424 uint64_t dma1ErrorLog0;
425 uint64_t dma1ErrorLog1;
426 uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
427 uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
428};
429
430typedef struct oppanel_line {
431 const char * line;
432 uint64_t line_len;
433} oppanel_line_t;
434
435
436int64_t opal_console_write(int64_t term_number, int64_t *length,
437 const uint8_t *buffer);
438int64_t opal_console_read(int64_t term_number, int64_t *length,
439 uint8_t *buffer);
440int64_t opal_console_write_buffer_space(int64_t term_number,
441 int64_t *length);
442int64_t opal_rtc_read(uint32_t *year_month_day,
443 uint64_t *hour_minute_second_millisecond);
444int64_t opal_rtc_write(uint32_t year_month_day,
445 uint64_t hour_minute_second_millisecond);
446int64_t opal_cec_power_down(uint64_t request);
447int64_t opal_cec_reboot(void);
448int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
449int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
450int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
451int64_t opal_poll_events(uint64_t *outstanding_event_mask);
452int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
453 uint64_t tce_mem_size);
454int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
455 uint64_t tce_mem_size);
456int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
457 uint64_t offset, uint8_t *data);
458int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
459 uint64_t offset, uint16_t *data);
460int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
461 uint64_t offset, uint32_t *data);
462int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
463 uint64_t offset, uint8_t data);
464int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
465 uint64_t offset, uint16_t data);
466int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
467 uint64_t offset, uint32_t data);
468int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
469int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
470int64_t opal_register_exception_handler(uint64_t opal_exception,
471 uint64_t handler_address,
472 uint64_t glue_cache_line);
473int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
474 uint8_t *freeze_state,
475 uint16_t *pci_error_type,
476 uint64_t *phb_status);
477int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
478 uint64_t eeh_action_token);
479int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
480
481
482
483int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
484 uint16_t window_num, uint16_t enable);
485int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
486 uint16_t window_num,
487 uint64_t starting_real_address,
488 uint64_t starting_pci_address,
489 uint16_t segment_size);
490int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
491 uint16_t window_type, uint16_t window_num,
492 uint16_t segment_num);
493int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
494 uint64_t ivt_addr, uint64_t ivt_len,
495 uint64_t reject_array_addr,
496 uint64_t peltv_addr);
497int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
498 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
499 uint8_t pe_action);
500int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
501 uint8_t state);
502int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
503int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
504 uint32_t state);
505int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
506 uint8_t *p_bit, uint8_t *q_bit);
507int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
508 uint8_t p_bit, uint8_t q_bit);
509int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
510 uint32_t xive_num);
511int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
512 int32_t *interrupt_source_number);
513int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
514 uint8_t msi_range, uint32_t *msi_address,
515 uint32_t *message_data);
516int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
517 uint32_t xive_num, uint8_t msi_range,
518 uint64_t *msi_address, uint32_t *message_data);
519int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
520int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
521int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
522int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
523 uint16_t tce_levels, uint64_t tce_table_addr,
524 uint64_t tce_table_size, uint64_t tce_page_size);
525int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
526 uint16_t dma_window_number, uint64_t pci_start_addr,
527 uint64_t pci_mem_size);
528int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
529
530int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
531int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
532int64_t opal_pci_fence_phb(uint64_t phb_id);
533int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
534int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
535int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
536int64_t opal_get_epow_status(uint64_t *status);
537int64_t opal_set_system_attention_led(uint8_t led_action);
538
539
540extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
541
542extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
543extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
544
545extern void hvc_opal_init_early(void);
546
547
548extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
549 int depth, void *data);
550
551extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
552extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
553
554extern void hvc_opal_init_early(void);
555
556struct rtc_time;
557extern int opal_set_rtc_time(struct rtc_time *tm);
558extern void opal_get_rtc_time(struct rtc_time *tm);
559extern unsigned long opal_get_boot_time(void);
560extern void opal_nvram_init(void);
561
562extern int opal_machine_check(struct pt_regs *regs);
563
564#endif
565
566#endif
567
