LXR linux/arch/powerpc/include/asm/processor.h

   1#ifndef _ASM_POWERPC_PROCESSOR_H
   2#define _ASM_POWERPC_PROCESSOR_H
   3
   4/*
   5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version
  10 * 2 of the License, or (at your option) any later version.
  11 */
  12
  13#include <asm/reg.h>
  14
  15#ifdef CONFIG_VSX
  16#define TS_FPRWIDTH 2
  17#else
  18#define TS_FPRWIDTH 1
  19#endif
  20
  21#ifdef CONFIG_PPC64
  22/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
  23#define PPR_PRIORITY 3
  24#ifdef __ASSEMBLY__
  25#define INIT_PPR (PPR_PRIORITY << 50)
  26#else
  27#define INIT_PPR ((u64)PPR_PRIORITY << 50)
  28#endif /* __ASSEMBLY__ */
  29#endif /* CONFIG_PPC64 */
  30
  31#ifndef __ASSEMBLY__
  32#include <linux/compiler.h>
  33#include <linux/cache.h>
  34#include <asm/ptrace.h>
  35#include <asm/types.h>
  36#include <asm/hw_breakpoint.h>
  37
  38/* We do _not_ want to define new machine types at all, those must die
  39 * in favor of using the device-tree
  40 * -- BenH.
  41 */
  42
  43/* PREP sub-platform types see residual.h for these */
  44#define _PREP_Motorola  0x01    /* motorola prep */
  45#define _PREP_Firm      0x02    /* firmworks prep */
  46#define _PREP_IBM       0x00    /* ibm prep */
  47#define _PREP_Bull      0x03    /* bull prep */
  48
  49/* CHRP sub-platform types. These are arbitrary */
  50#define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
  51#define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
  52#define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
  53#define _CHRP_briq      0x07    /* TotalImpact's briQ */
  54
  55#if defined(__KERNEL__) && defined(CONFIG_PPC32)
  56
  57extern int _chrp_type;
  58
  59#ifdef CONFIG_PPC_PREP
  60
  61/* what kind of prep workstation we are */
  62extern int _prep_type;
  63
  64#endif /* CONFIG_PPC_PREP */
  65
  66#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
  67
  68/*
  69 * Default implementation of macro that returns current
  70 * instruction pointer ("program counter").
  71 */
  72#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  73
  74/* Macros for adjusting thread priority (hardware multi-threading) */
  75#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
  76#define HMT_low()        asm volatile("or 1,1,1      # low priority")
  77#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
  78#define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
  79#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
  80#define HMT_high()       asm volatile("or 3,3,3      # high priority")
  81
  82#ifdef __KERNEL__
  83
  84struct task_struct;
  85void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
  86void release_thread(struct task_struct *);
  87
  88/* Lazy FPU handling on uni-processor */
  89extern struct task_struct *last_task_used_math;
  90extern struct task_struct *last_task_used_altivec;
  91extern struct task_struct *last_task_used_vsx;
  92extern struct task_struct *last_task_used_spe;
  93
  94#ifdef CONFIG_PPC32
  95
  96#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
  97#error User TASK_SIZE overlaps with KERNEL_START address
  98#endif
  99#define TASK_SIZE       (CONFIG_TASK_SIZE)
 100
 101/* This decides where the kernel will search for a free chunk of vm
 102 * space during mmap's.
 103 */
 104#define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 105#endif
 106
 107#ifdef CONFIG_PPC64
 108/* 64-bit user address space is 46-bits (64TB user VM) */
 109#define TASK_SIZE_USER64 (0x0000400000000000UL)
 110
 111/* 
 112 * 32-bit user address space is 4GB - 1 page 
 113 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 114 */
 115#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
 116
 117#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
 118                TASK_SIZE_USER32 : TASK_SIZE_USER64)
 119#define TASK_SIZE         TASK_SIZE_OF(current)
 120
 121/* This decides where the kernel will search for a free chunk of vm
 122 * space during mmap's.
 123 */
 124#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
 125#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
 126
 127#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
 128                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 129#endif
 130
 131#ifdef __powerpc64__
 132
 133#define STACK_TOP_USER64 TASK_SIZE_USER64
 134#define STACK_TOP_USER32 TASK_SIZE_USER32
 135
 136#define STACK_TOP (is_32bit_task() ? \
 137                   STACK_TOP_USER32 : STACK_TOP_USER64)
 138
 139#define STACK_TOP_MAX STACK_TOP_USER64
 140
 141#else /* __powerpc64__ */
 142
 143#define STACK_TOP TASK_SIZE
 144#define STACK_TOP_MAX   STACK_TOP
 145
 146#endif /* __powerpc64__ */
 147
 148typedef struct {
 149        unsigned long seg;
 150} mm_segment_t;
 151
 152#define TS_FPROFFSET 0
 153#define TS_VSRLOWOFFSET 1
 154#define TS_FPR(i) fpr[i][TS_FPROFFSET]
 155#define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]
 156
 157struct thread_struct {
 158        unsigned long   ksp;            /* Kernel stack pointer */
 159        unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
 160
 161#ifdef CONFIG_PPC64
 162        unsigned long   ksp_vsid;
 163#endif
 164        struct pt_regs  *regs;          /* Pointer to saved register state */
 165        mm_segment_t    fs;             /* for get_fs() validation */
 166#ifdef CONFIG_BOOKE
 167        /* BookE base exception scratch space; align on cacheline */
 168        unsigned long   normsave[8] ____cacheline_aligned;
 169#endif
 170#ifdef CONFIG_PPC32
 171        void            *pgdir;         /* root of page-table tree */
 172#endif
 173#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 174        /*
 175         * The following help to manage the use of Debug Control Registers
 176         * om the BookE platforms.
 177         */
 178        unsigned long   dbcr0;
 179        unsigned long   dbcr1;
 180#ifdef CONFIG_BOOKE
 181        unsigned long   dbcr2;
 182#endif
 183        /*
 184         * The stored value of the DBSR register will be the value at the
 185         * last debug interrupt. This register can only be read from the
 186         * user (will never be written to) and has value while helping to
 187         * describe the reason for the last debug trap.  Torez
 188         */
 189        unsigned long   dbsr;
 190        /*
 191         * The following will contain addresses used by debug applications
 192         * to help trace and trap on particular address locations.
 193         * The bits in the Debug Control Registers above help define which
 194         * of the following registers will contain valid data and/or addresses.
 195         */
 196        unsigned long   iac1;
 197        unsigned long   iac2;
 198#if CONFIG_PPC_ADV_DEBUG_IACS > 2
 199        unsigned long   iac3;
 200        unsigned long   iac4;
 201#endif
 202        unsigned long   dac1;
 203        unsigned long   dac2;
 204#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 205        unsigned long   dvc1;
 206        unsigned long   dvc2;
 207#endif
 208#endif
 209        /* FP and VSX 0-31 register set */
 210        double          fpr[32][TS_FPRWIDTH];
 211        struct {
 212
 213                unsigned int pad;
 214                unsigned int val;       /* Floating point status */
 215        } fpscr;
 216        int             fpexc_mode;     /* floating-point exception mode */
 217        unsigned int    align_ctl;      /* alignment handling control */
 218#ifdef CONFIG_PPC64
 219        unsigned long   start_tb;       /* Start purr when proc switched in */
 220        unsigned long   accum_tb;       /* Total accumilated purr for process */
 221#ifdef CONFIG_HAVE_HW_BREAKPOINT
 222        struct perf_event *ptrace_bps[HBP_NUM];
 223        /*
 224         * Helps identify source of single-step exception and subsequent
 225         * hw-breakpoint enablement
 226         */
 227        struct perf_event *last_hit_ubp;
 228#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 229#endif
 230        struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
 231        unsigned long   trap_nr;        /* last trap # on this thread */
 232#ifdef CONFIG_ALTIVEC
 233        /* Complete AltiVec register set */
 234        vector128       vr[32] __attribute__((aligned(16)));
 235        /* AltiVec status */
 236        vector128       vscr __attribute__((aligned(16)));
 237        unsigned long   vrsave;
 238        int             used_vr;        /* set if process has used altivec */
 239#endif /* CONFIG_ALTIVEC */
 240#ifdef CONFIG_VSX
 241        /* VSR status */
 242        int             used_vsr;       /* set if process has used altivec */
 243#endif /* CONFIG_VSX */
 244#ifdef CONFIG_SPE
 245        unsigned long   evr[32];        /* upper 32-bits of SPE regs */
 246        u64             acc;            /* Accumulator */
 247        unsigned long   spefscr;        /* SPE & eFP status */
 248        int             used_spe;       /* set if process has used spe */
 249#endif /* CONFIG_SPE */
 250#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 251        u64             tm_tfhar;       /* Transaction fail handler addr */
 252        u64             tm_texasr;      /* Transaction exception & summary */
 253        u64             tm_tfiar;       /* Transaction fail instr address reg */
 254        unsigned long   tm_orig_msr;    /* Thread's MSR on ctx switch */
 255        struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 256
 257        /*
 258         * Transactional FP and VSX 0-31 register set.
 259         * NOTE: the sense of these is the opposite of the integer ckpt_regs!
 260         *
 261         * When a transaction is active/signalled/scheduled etc., *regs is the
 262         * most recent set of/speculated GPRs with ckpt_regs being the older
 263         * checkpointed regs to which we roll back if transaction aborts.
 264         *
 265         * However, fpr[] is the checkpointed 'base state' of FP regs, and
 266         * transact_fpr[] is the new set of transactional values.
 267         * VRs work the same way.
 268         */
 269        double          transact_fpr[32][TS_FPRWIDTH];
 270        struct {
 271                unsigned int pad;
 272                unsigned int val;       /* Floating point status */
 273        } transact_fpscr;
 274        vector128       transact_vr[32] __attribute__((aligned(16)));
 275        vector128       transact_vscr __attribute__((aligned(16)));
 276        unsigned long   transact_vrsave;
 277#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 278#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
 279        void*           kvm_shadow_vcpu; /* KVM internal data */
 280#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
 281#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
 282        struct kvm_vcpu *kvm_vcpu;
 283#endif
 284#ifdef CONFIG_PPC64
 285        unsigned long   dscr;
 286        int             dscr_inherit;
 287        unsigned long   ppr;    /* used to save/restore SMT priority */
 288#endif
 289#ifdef CONFIG_PPC_BOOK3S_64
 290        unsigned long   tar;
 291#endif
 292};
 293
 294#define ARCH_MIN_TASKALIGN 16
 295
 296#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 297#define INIT_SP_LIMIT \
 298        (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
 299
 300#ifdef CONFIG_SPE
 301#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 302#else
 303#define SPEFSCR_INIT
 304#endif
 305
 306#ifdef CONFIG_PPC32
 307#define INIT_THREAD { \
 308        .ksp = INIT_SP, \
 309        .ksp_limit = INIT_SP_LIMIT, \
 310        .fs = KERNEL_DS, \
 311        .pgdir = swapper_pg_dir, \
 312        .fpexc_mode = MSR_FE0 | MSR_FE1, \
 313        SPEFSCR_INIT \
 314}
 315#else
 316#define INIT_THREAD  { \
 317        .ksp = INIT_SP, \
 318        .ksp_limit = INIT_SP_LIMIT, \
 319        .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
 320        .fs = KERNEL_DS, \
 321        .fpr = {{0}}, \
 322        .fpscr = { .val = 0, }, \
 323        .fpexc_mode = 0, \
 324        .ppr = INIT_PPR, \
 325}
 326#endif
 327
 328/*
 329 * Return saved PC of a blocked thread. For now, this is the "user" PC
 330 */
 331#define thread_saved_pc(tsk)    \
 332        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 333
 334#define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.regs)
 335
 336unsigned long get_wchan(struct task_struct *p);
 337
 338#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 339#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 340
 341/* Get/set floating-point exception mode */
 342#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 343#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 344
 345extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 346extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 347
 348#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
 349#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
 350
 351extern int get_endian(struct task_struct *tsk, unsigned long adr);
 352extern int set_endian(struct task_struct *tsk, unsigned int val);
 353
 354#define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
 355#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 356
 357extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 358extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 359
 360static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 361{
 362        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 363}
 364
 365static inline unsigned long __pack_fe01(unsigned int fpmode)
 366{
 367        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 368}
 369
 370#ifdef CONFIG_PPC64
 371#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
 372#else
 373#define cpu_relax()     barrier()
 374#endif
 375
 376/* Check that a certain kernel stack pointer is valid in task_struct p */
 377int validate_sp(unsigned long sp, struct task_struct *p,
 378                       unsigned long nbytes);
 379
 380/*
 381 * Prefetch macros.
 382 */
 383#define ARCH_HAS_PREFETCH
 384#define ARCH_HAS_PREFETCHW
 385#define ARCH_HAS_SPINLOCK_PREFETCH
 386
 387static inline void prefetch(const void *x)
 388{
 389        if (unlikely(!x))
 390                return;
 391
 392        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 393}
 394
 395static inline void prefetchw(const void *x)
 396{
 397        if (unlikely(!x))
 398                return;
 399
 400        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 401}
 402
 403#define spin_lock_prefetch(x)   prefetchw(x)
 404
 405#ifdef CONFIG_PPC64
 406#define HAVE_ARCH_PICK_MMAP_LAYOUT
 407#endif
 408
 409#ifdef CONFIG_PPC64
 410static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
 411{
 412        unsigned long sp;
 413
 414        if (is_32)
 415                sp = regs->gpr[1] & 0x0ffffffffUL;
 416        else
 417                sp = regs->gpr[1];
 418
 419        return sp;
 420}
 421#else
 422static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
 423{
 424        return regs->gpr[1];
 425}
 426#endif
 427
 428extern unsigned long cpuidle_disable;
 429enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 430
 431extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 432extern void power7_nap(void);
 433
 434#ifdef CONFIG_PSERIES_IDLE
 435extern void update_smt_snooze_delay(int cpu, int residency);
 436#else
 437static inline void update_smt_snooze_delay(int cpu, int residency) {}
 438#endif
 439
 440extern void flush_instruction_cache(void);
 441extern void hard_reset_now(void);
 442extern void poweroff_now(void);
 443extern int fix_alignment(struct pt_regs *);
 444extern void cvt_fd(float *from, double *to);
 445extern void cvt_df(double *from, float *to);
 446extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 447
 448#ifdef CONFIG_PPC64
 449/*
 450 * We handle most unaligned accesses in hardware. On the other hand 
 451 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 452 * powers of 2 writes until it reaches sufficient alignment).
 453 *
 454 * Based on this we disable the IP header alignment in network drivers.
 455 */
 456#define NET_IP_ALIGN    0
 457#endif
 458
 459#endif /* __KERNEL__ */
 460#endif /* __ASSEMBLY__ */
 461#endif /* _ASM_POWERPC_PROCESSOR_H */
 462