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15#include <linux/sched.h>
16#include <linux/preempt.h>
17#include <linux/module.h>
18#include <linux/fs.h>
19#include <linux/kprobes.h>
20#include <linux/elfcore.h>
21#include <linux/tick.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/compat.h>
25#include <linux/hardirq.h>
26#include <linux/syscalls.h>
27#include <linux/kernel.h>
28#include <linux/tracehook.h>
29#include <linux/signal.h>
30#include <asm/stack.h>
31#include <asm/switch_to.h>
32#include <asm/homecache.h>
33#include <asm/syscalls.h>
34#include <asm/traps.h>
35#include <asm/setup.h>
36#ifdef CONFIG_HARDWALL
37#include <asm/hardwall.h>
38#endif
39#include <arch/chip.h>
40#include <arch/abi.h>
41#include <arch/sim_def.h>
42
43
44
45
46
47
48
49static int no_idle_nap;
50static int __init idle_setup(char *str)
51{
52 if (!str)
53 return -EINVAL;
54
55 if (!strcmp(str, "poll")) {
56 pr_info("using polling idle threads.\n");
57 no_idle_nap = 1;
58 } else if (!strcmp(str, "halt"))
59 no_idle_nap = 0;
60 else
61 return -1;
62
63 return 0;
64}
65early_param("idle", idle_setup);
66
67
68
69
70
71
72
73void cpu_idle(void)
74{
75 int cpu = smp_processor_id();
76
77
78 current_thread_info()->status |= TS_POLLING;
79
80 if (no_idle_nap) {
81 while (1) {
82 while (!need_resched())
83 cpu_relax();
84 schedule();
85 }
86 }
87
88
89 while (1) {
90 tick_nohz_idle_enter();
91 rcu_idle_enter();
92 while (!need_resched()) {
93 if (cpu_is_offline(cpu))
94 BUG();
95
96 local_irq_disable();
97 __get_cpu_var(irq_stat).idle_timestamp = jiffies;
98 current_thread_info()->status &= ~TS_POLLING;
99
100
101
102
103 smp_mb();
104
105 if (!need_resched())
106 _cpu_idle();
107 else
108 local_irq_enable();
109 current_thread_info()->status |= TS_POLLING;
110 }
111 rcu_idle_exit();
112 tick_nohz_idle_exit();
113 schedule_preempt_disabled();
114 }
115}
116
117
118
119
120void arch_release_thread_info(struct thread_info *info)
121{
122 struct single_step_state *step_state = info->step_state;
123
124#ifdef CONFIG_HARDWALL
125
126
127
128
129
130
131
132
133
134 hardwall_deactivate_all(info->task);
135#endif
136
137 if (step_state) {
138
139
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143
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147
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149
150
151
152
153 kfree(step_state);
154 }
155}
156
157static void save_arch_state(struct thread_struct *t);
158
159int copy_thread(unsigned long clone_flags, unsigned long sp,
160 unsigned long arg, struct task_struct *p)
161{
162 struct pt_regs *childregs = task_pt_regs(p);
163 unsigned long ksp;
164 unsigned long *callee_regs;
165
166
167
168
169
170
171
172
173
174 ksp = (unsigned long) childregs;
175 ksp -= C_ABI_SAVE_AREA_SIZE;
176 ((long *)ksp)[0] = ((long *)ksp)[1] = 0;
177 ksp -= CALLEE_SAVED_REGS_COUNT * sizeof(unsigned long);
178 callee_regs = (unsigned long *)ksp;
179 ksp -= C_ABI_SAVE_AREA_SIZE;
180 ((long *)ksp)[0] = ((long *)ksp)[1] = 0;
181 p->thread.ksp = ksp;
182
183
184 p->thread.creator_pid = current->pid;
185
186 if (unlikely(p->flags & PF_KTHREAD)) {
187
188 memset(childregs, 0, sizeof(struct pt_regs));
189 memset(&callee_regs[2], 0,
190 (CALLEE_SAVED_REGS_COUNT - 2) * sizeof(unsigned long));
191 callee_regs[0] = sp;
192 callee_regs[1] = arg;
193 childregs->ex1 = PL_ICS_EX1(KERNEL_PL, 0);
194 p->thread.pc = (unsigned long) ret_from_kernel_thread;
195 return 0;
196 }
197
198
199
200
201
202 p->thread.pc = (unsigned long) ret_from_fork;
203
204
205
206
207
208 task_thread_info(p)->step_state = NULL;
209
210
211
212
213
214 *childregs = *current_pt_regs();
215 childregs->regs[0] = 0;
216 if (sp)
217 childregs->sp = sp;
218 memcpy(callee_regs, &childregs->regs[CALLEE_SAVED_FIRST_REG],
219 CALLEE_SAVED_REGS_COUNT * sizeof(unsigned long));
220
221
222 p->thread.usp0 = childregs->sp;
223
224
225
226
227
228 if (clone_flags & CLONE_SETTLS)
229 childregs->tp = childregs->regs[4];
230
231
232#if CHIP_HAS_TILE_DMA()
233
234
235
236
237 memset(&p->thread.tile_dma_state, 0, sizeof(struct tile_dma_state));
238 memset(&p->thread.dma_async_tlb, 0, sizeof(struct async_tlb));
239#endif
240
241#if CHIP_HAS_SN_PROC()
242
243 p->thread.sn_proc_running = 0;
244 memset(&p->thread.sn_async_tlb, 0, sizeof(struct async_tlb));
245#endif
246
247#if CHIP_HAS_PROC_STATUS_SPR()
248
249 p->thread.proc_status = 0;
250#endif
251
252#ifdef CONFIG_HARDWALL
253
254 memset(&p->thread.hardwall[0], 0,
255 sizeof(struct hardwall_task) * HARDWALL_TYPES);
256#endif
257
258
259
260
261
262
263 save_arch_state(&p->thread);
264
265 return 0;
266}
267
268
269
270
271
272struct task_struct *validate_current(void)
273{
274 static struct task_struct corrupt = { .comm = "<corrupt>" };
275 struct task_struct *tsk = current;
276 if (unlikely((unsigned long)tsk < PAGE_OFFSET ||
277 (high_memory && (void *)tsk > high_memory) ||
278 ((unsigned long)tsk & (__alignof__(*tsk) - 1)) != 0)) {
279 pr_err("Corrupt 'current' %p (sp %#lx)\n", tsk, stack_pointer);
280 tsk = &corrupt;
281 }
282 return tsk;
283}
284
285
286struct task_struct *sim_notify_fork(struct task_struct *prev)
287{
288 struct task_struct *tsk = current;
289 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_FORK_PARENT |
290 (tsk->thread.creator_pid << _SIM_CONTROL_OPERATOR_BITS));
291 __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_FORK |
292 (tsk->pid << _SIM_CONTROL_OPERATOR_BITS));
293 return prev;
294}
295
296int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
297{
298 struct pt_regs *ptregs = task_pt_regs(tsk);
299 elf_core_copy_regs(regs, ptregs);
300 return 1;
301}
302
303#if CHIP_HAS_TILE_DMA()
304
305
306void grant_dma_mpls(void)
307{
308#if CONFIG_KERNEL_PL == 2
309 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
310 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
311#else
312 __insn_mtspr(SPR_MPL_DMA_CPL_SET_0, 1);
313 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_0, 1);
314#endif
315}
316
317
318void restrict_dma_mpls(void)
319{
320#if CONFIG_KERNEL_PL == 2
321 __insn_mtspr(SPR_MPL_DMA_CPL_SET_2, 1);
322 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_2, 1);
323#else
324 __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
325 __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
326#endif
327}
328
329
330static void save_tile_dma_state(struct tile_dma_state *dma)
331{
332 unsigned long state = __insn_mfspr(SPR_DMA_USER_STATUS);
333 unsigned long post_suspend_state;
334
335
336 if ((state & DMA_STATUS_MASK) == SPR_DMA_STATUS__RUNNING_MASK)
337 __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__SUSPEND_MASK);
338
339
340
341
342
343
344
345
346
347 do {
348 post_suspend_state = __insn_mfspr(SPR_DMA_USER_STATUS);
349 } while (post_suspend_state & SPR_DMA_STATUS__BUSY_MASK);
350
351 dma->src = __insn_mfspr(SPR_DMA_SRC_ADDR);
352 dma->src_chunk = __insn_mfspr(SPR_DMA_SRC_CHUNK_ADDR);
353 dma->dest = __insn_mfspr(SPR_DMA_DST_ADDR);
354 dma->dest_chunk = __insn_mfspr(SPR_DMA_DST_CHUNK_ADDR);
355 dma->strides = __insn_mfspr(SPR_DMA_STRIDE);
356 dma->chunk_size = __insn_mfspr(SPR_DMA_CHUNK_SIZE);
357 dma->byte = __insn_mfspr(SPR_DMA_BYTE);
358 dma->status = (state & SPR_DMA_STATUS__RUNNING_MASK) |
359 (post_suspend_state & SPR_DMA_STATUS__DONE_MASK);
360}
361
362
363static void restore_tile_dma_state(struct thread_struct *t)
364{
365 const struct tile_dma_state *dma = &t->tile_dma_state;
366
367
368
369
370
371 if ((dma->status & SPR_DMA_STATUS__DONE_MASK) &&
372 !(__insn_mfspr(SPR_DMA_USER_STATUS) & SPR_DMA_STATUS__DONE_MASK)) {
373 __insn_mtspr(SPR_DMA_BYTE, 0);
374 __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
375 while (__insn_mfspr(SPR_DMA_USER_STATUS) &
376 SPR_DMA_STATUS__BUSY_MASK)
377 ;
378 }
379
380 __insn_mtspr(SPR_DMA_SRC_ADDR, dma->src);
381 __insn_mtspr(SPR_DMA_SRC_CHUNK_ADDR, dma->src_chunk);
382 __insn_mtspr(SPR_DMA_DST_ADDR, dma->dest);
383 __insn_mtspr(SPR_DMA_DST_CHUNK_ADDR, dma->dest_chunk);
384 __insn_mtspr(SPR_DMA_STRIDE, dma->strides);
385 __insn_mtspr(SPR_DMA_CHUNK_SIZE, dma->chunk_size);
386 __insn_mtspr(SPR_DMA_BYTE, dma->byte);
387
388
389
390
391
392
393
394
395
396 if ((dma->status & DMA_STATUS_MASK) == SPR_DMA_STATUS__RUNNING_MASK) {
397 t->dma_async_tlb.fault_num = 0;
398 __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
399 }
400}
401
402#endif
403
404static void save_arch_state(struct thread_struct *t)
405{
406#if CHIP_HAS_SPLIT_INTR_MASK()
407 t->interrupt_mask = __insn_mfspr(SPR_INTERRUPT_MASK_0_0) |
408 ((u64)__insn_mfspr(SPR_INTERRUPT_MASK_0_1) << 32);
409#else
410 t->interrupt_mask = __insn_mfspr(SPR_INTERRUPT_MASK_0);
411#endif
412 t->ex_context[0] = __insn_mfspr(SPR_EX_CONTEXT_0_0);
413 t->ex_context[1] = __insn_mfspr(SPR_EX_CONTEXT_0_1);
414 t->system_save[0] = __insn_mfspr(SPR_SYSTEM_SAVE_0_0);
415 t->system_save[1] = __insn_mfspr(SPR_SYSTEM_SAVE_0_1);
416 t->system_save[2] = __insn_mfspr(SPR_SYSTEM_SAVE_0_2);
417 t->system_save[3] = __insn_mfspr(SPR_SYSTEM_SAVE_0_3);
418 t->intctrl_0 = __insn_mfspr(SPR_INTCTRL_0_STATUS);
419#if CHIP_HAS_PROC_STATUS_SPR()
420 t->proc_status = __insn_mfspr(SPR_PROC_STATUS);
421#endif
422#if !CHIP_HAS_FIXED_INTVEC_BASE()
423 t->interrupt_vector_base = __insn_mfspr(SPR_INTERRUPT_VECTOR_BASE_0);
424#endif
425#if CHIP_HAS_TILE_RTF_HWM()
426 t->tile_rtf_hwm = __insn_mfspr(SPR_TILE_RTF_HWM);
427#endif
428#if CHIP_HAS_DSTREAM_PF()
429 t->dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
430#endif
431}
432
433static void restore_arch_state(const struct thread_struct *t)
434{
435#if CHIP_HAS_SPLIT_INTR_MASK()
436 __insn_mtspr(SPR_INTERRUPT_MASK_0_0, (u32) t->interrupt_mask);
437 __insn_mtspr(SPR_INTERRUPT_MASK_0_1, t->interrupt_mask >> 32);
438#else
439 __insn_mtspr(SPR_INTERRUPT_MASK_0, t->interrupt_mask);
440#endif
441 __insn_mtspr(SPR_EX_CONTEXT_0_0, t->ex_context[0]);
442 __insn_mtspr(SPR_EX_CONTEXT_0_1, t->ex_context[1]);
443 __insn_mtspr(SPR_SYSTEM_SAVE_0_0, t->system_save[0]);
444 __insn_mtspr(SPR_SYSTEM_SAVE_0_1, t->system_save[1]);
445 __insn_mtspr(SPR_SYSTEM_SAVE_0_2, t->system_save[2]);
446 __insn_mtspr(SPR_SYSTEM_SAVE_0_3, t->system_save[3]);
447 __insn_mtspr(SPR_INTCTRL_0_STATUS, t->intctrl_0);
448#if CHIP_HAS_PROC_STATUS_SPR()
449 __insn_mtspr(SPR_PROC_STATUS, t->proc_status);
450#endif
451#if !CHIP_HAS_FIXED_INTVEC_BASE()
452 __insn_mtspr(SPR_INTERRUPT_VECTOR_BASE_0, t->interrupt_vector_base);
453#endif
454#if CHIP_HAS_TILE_RTF_HWM()
455 __insn_mtspr(SPR_TILE_RTF_HWM, t->tile_rtf_hwm);
456#endif
457#if CHIP_HAS_DSTREAM_PF()
458 __insn_mtspr(SPR_DSTREAM_PF, t->dstream_pf);
459#endif
460}
461
462
463void _prepare_arch_switch(struct task_struct *next)
464{
465#if CHIP_HAS_SN_PROC()
466 int snctl;
467#endif
468#if CHIP_HAS_TILE_DMA()
469 struct tile_dma_state *dma = ¤t->thread.tile_dma_state;
470 if (dma->enabled)
471 save_tile_dma_state(dma);
472#endif
473#if CHIP_HAS_SN_PROC()
474
475
476
477
478
479 snctl = __insn_mfspr(SPR_SNCTL);
480 current->thread.sn_proc_running =
481 (snctl & SPR_SNCTL__FRZPROC_MASK) == 0;
482 if (current->thread.sn_proc_running)
483 __insn_mtspr(SPR_SNCTL, snctl | SPR_SNCTL__FRZPROC_MASK);
484#endif
485}
486
487
488struct task_struct *__sched _switch_to(struct task_struct *prev,
489 struct task_struct *next)
490{
491
492 save_arch_state(&prev->thread);
493
494#if CHIP_HAS_TILE_DMA()
495
496
497
498
499
500
501 if (next->thread.tile_dma_state.enabled) {
502 restore_tile_dma_state(&next->thread);
503 grant_dma_mpls();
504 } else {
505 restrict_dma_mpls();
506 }
507#endif
508
509
510 restore_arch_state(&next->thread);
511
512#if CHIP_HAS_SN_PROC()
513
514
515
516
517 if (next->thread.sn_proc_running) {
518 int snctl = __insn_mfspr(SPR_SNCTL);
519 __insn_mtspr(SPR_SNCTL, snctl & ~SPR_SNCTL__FRZPROC_MASK);
520 }
521#endif
522
523#ifdef CONFIG_HARDWALL
524
525 hardwall_switch_tasks(prev, next);
526#endif
527
528
529
530
531
532
533
534 return __switch_to(prev, next, next_current_ksp0(next));
535}
536
537
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540
541
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548
549
550
551int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
552{
553
554 if (!user_mode(regs))
555 return 0;
556
557
558 local_irq_enable();
559
560 if (thread_info_flags & _TIF_NEED_RESCHED) {
561 schedule();
562 return 1;
563 }
564#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
565 if (thread_info_flags & _TIF_ASYNC_TLB) {
566 do_async_page_fault(regs);
567 return 1;
568 }
569#endif
570 if (thread_info_flags & _TIF_SIGPENDING) {
571 do_signal(regs);
572 return 1;
573 }
574 if (thread_info_flags & _TIF_NOTIFY_RESUME) {
575 clear_thread_flag(TIF_NOTIFY_RESUME);
576 tracehook_notify_resume(regs);
577 return 1;
578 }
579 if (thread_info_flags & _TIF_SINGLESTEP) {
580 single_step_once(regs);
581 return 0;
582 }
583 panic("work_pending: bad flags %#x\n", thread_info_flags);
584}
585
586unsigned long get_wchan(struct task_struct *p)
587{
588 struct KBacktraceIterator kbt;
589
590 if (!p || p == current || p->state == TASK_RUNNING)
591 return 0;
592
593 for (KBacktraceIterator_init(&kbt, p, NULL);
594 !KBacktraceIterator_end(&kbt);
595 KBacktraceIterator_next(&kbt)) {
596 if (!in_sched_functions(kbt.it.pc))
597 return kbt.it.pc;
598 }
599
600 return 0;
601}
602
603
604void flush_thread(void)
605{
606
607}
608
609
610
611
612void exit_thread(void)
613{
614
615}
616
617void show_regs(struct pt_regs *regs)
618{
619 struct task_struct *tsk = validate_current();
620 int i;
621
622 pr_err("\n");
623 pr_err(" Pid: %d, comm: %20s, CPU: %d\n",
624 tsk->pid, tsk->comm, smp_processor_id());
625#ifdef __tilegx__
626 for (i = 0; i < 51; i += 3)
627 pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
628 i, regs->regs[i], i+1, regs->regs[i+1],
629 i+2, regs->regs[i+2]);
630 pr_err(" r51: "REGFMT" r52: "REGFMT" tp : "REGFMT"\n",
631 regs->regs[51], regs->regs[52], regs->tp);
632 pr_err(" sp : "REGFMT" lr : "REGFMT"\n", regs->sp, regs->lr);
633#else
634 for (i = 0; i < 52; i += 4)
635 pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT
636 " r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
637 i, regs->regs[i], i+1, regs->regs[i+1],
638 i+2, regs->regs[i+2], i+3, regs->regs[i+3]);
639 pr_err(" r52: "REGFMT" tp : "REGFMT" sp : "REGFMT" lr : "REGFMT"\n",
640 regs->regs[52], regs->tp, regs->sp, regs->lr);
641#endif
642 pr_err(" pc : "REGFMT" ex1: %ld faultnum: %ld\n",
643 regs->pc, regs->ex1, regs->faultnum);
644
645 dump_stack_regs(regs);
646}
647