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20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/sched.h>
26#include <linux/errno.h>
27#include <linux/bootmem.h>
28
29#include <asm/pci-bridge.h>
30#include <asm/platform.h>
31
32#undef DEBUG
33
34#ifdef DEBUG
35#define DBG(x...) printk(x)
36#else
37#define DBG(x...)
38#endif
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53struct pci_controller* pci_ctrl_head;
54struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;
55
56static int pci_bus_count;
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70
71resource_size_t
72pcibios_align_resource(void *data, const struct resource *res,
73 resource_size_t size, resource_size_t align)
74{
75 struct pci_dev *dev = data;
76 resource_size_t start = res->start;
77
78 if (res->flags & IORESOURCE_IO) {
79 if (size > 0x100) {
80 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
81 " (%ld bytes)\n", pci_name(dev),
82 dev->resource - res, size);
83 }
84
85 if (start & 0x300)
86 start = (start + 0x3ff) & ~0x3ff;
87 }
88
89 return start;
90}
91
92int
93pcibios_enable_resources(struct pci_dev *dev, int mask)
94{
95 u16 cmd, old_cmd;
96 int idx;
97 struct resource *r;
98
99 pci_read_config_word(dev, PCI_COMMAND, &cmd);
100 old_cmd = cmd;
101 for(idx=0; idx<6; idx++) {
102 r = &dev->resource[idx];
103 if (!r->start && r->end) {
104 printk (KERN_ERR "PCI: Device %s not available because "
105 "of resource collisions\n", pci_name(dev));
106 return -EINVAL;
107 }
108 if (r->flags & IORESOURCE_IO)
109 cmd |= PCI_COMMAND_IO;
110 if (r->flags & IORESOURCE_MEM)
111 cmd |= PCI_COMMAND_MEMORY;
112 }
113 if (dev->resource[PCI_ROM_RESOURCE].start)
114 cmd |= PCI_COMMAND_MEMORY;
115 if (cmd != old_cmd) {
116 printk("PCI: Enabling device %s (%04x -> %04x)\n",
117 pci_name(dev), old_cmd, cmd);
118 pci_write_config_word(dev, PCI_COMMAND, cmd);
119 }
120 return 0;
121}
122
123struct pci_controller * __init pcibios_alloc_controller(void)
124{
125 struct pci_controller *pci_ctrl;
126
127 pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl));
128 memset(pci_ctrl, 0, sizeof(struct pci_controller));
129
130 *pci_ctrl_tail = pci_ctrl;
131 pci_ctrl_tail = &pci_ctrl->next;
132
133 return pci_ctrl;
134}
135
136static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
137 struct list_head *resources)
138{
139 struct resource *res;
140 unsigned long io_offset;
141 int i;
142
143 io_offset = (unsigned long)pci_ctrl->io_space.base;
144 res = &pci_ctrl->io_resource;
145 if (!res->flags) {
146 if (io_offset)
147 printk (KERN_ERR "I/O resource not set for host"
148 " bridge %d\n", pci_ctrl->index);
149 res->start = 0;
150 res->end = IO_SPACE_LIMIT;
151 res->flags = IORESOURCE_IO;
152 }
153 res->start += io_offset;
154 res->end += io_offset;
155 pci_add_resource_offset(resources, res, io_offset);
156
157 for (i = 0; i < 3; i++) {
158 res = &pci_ctrl->mem_resources[i];
159 if (!res->flags) {
160 if (i > 0)
161 continue;
162 printk(KERN_ERR "Memory resource not set for "
163 "host bridge %d\n", pci_ctrl->index);
164 res->start = 0;
165 res->end = ~0U;
166 res->flags = IORESOURCE_MEM;
167 }
168 pci_add_resource(resources, res);
169 }
170}
171
172static int __init pcibios_init(void)
173{
174 struct pci_controller *pci_ctrl;
175 struct list_head resources;
176 struct pci_bus *bus;
177 int next_busno = 0, i;
178
179 printk("PCI: Probing PCI hardware\n");
180
181
182 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
183 pci_ctrl->last_busno = 0xff;
184 INIT_LIST_HEAD(&resources);
185 pci_controller_apertures(pci_ctrl, &resources);
186 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
187 pci_ctrl->ops, pci_ctrl, &resources);
188 pci_ctrl->bus = bus;
189 pci_ctrl->last_busno = bus->busn_res.end;
190 if (next_busno <= pci_ctrl->last_busno)
191 next_busno = pci_ctrl->last_busno+1;
192 }
193 pci_bus_count = next_busno;
194
195 return platform_pcibios_fixup();
196}
197
198subsys_initcall(pcibios_init);
199
200void __init pcibios_fixup_bus(struct pci_bus *bus)
201{
202 if (bus->parent) {
203
204 pci_read_bridge_bases(bus);
205 }
206}
207
208void pcibios_set_master(struct pci_dev *dev)
209{
210
211}
212
213int pcibios_enable_device(struct pci_dev *dev, int mask)
214{
215 u16 cmd, old_cmd;
216 int idx;
217 struct resource *r;
218
219 pci_read_config_word(dev, PCI_COMMAND, &cmd);
220 old_cmd = cmd;
221 for (idx=0; idx<6; idx++) {
222 r = &dev->resource[idx];
223 if (!r->start && r->end) {
224 printk(KERN_ERR "PCI: Device %s not available because "
225 "of resource collisions\n", pci_name(dev));
226 return -EINVAL;
227 }
228 if (r->flags & IORESOURCE_IO)
229 cmd |= PCI_COMMAND_IO;
230 if (r->flags & IORESOURCE_MEM)
231 cmd |= PCI_COMMAND_MEMORY;
232 }
233 if (cmd != old_cmd) {
234 printk("PCI: Enabling device %s (%04x -> %04x)\n",
235 pci_name(dev), old_cmd, cmd);
236 pci_write_config_word(dev, PCI_COMMAND, cmd);
237 }
238
239 return 0;
240}
241
242#ifdef CONFIG_PROC_FS
243
244
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246
247
248int
249pci_controller_num(struct pci_dev *dev)
250{
251 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
252 return pci_ctrl->index;
253}
254
255#endif
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273
274static __inline__ int
275__pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
276 enum pci_mmap_state mmap_state)
277{
278 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
279 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
280 unsigned long io_offset = 0;
281 int i, res_bit;
282
283 if (pci_ctrl == 0)
284 return -EINVAL;
285
286
287 if (mmap_state == pci_mmap_mem) {
288 res_bit = IORESOURCE_MEM;
289 } else {
290 io_offset = (unsigned long)pci_ctrl->io_space.base;
291 offset += io_offset;
292 res_bit = IORESOURCE_IO;
293 }
294
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298
299 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
300 struct resource *rp = &dev->resource[i];
301 int flags = rp->flags;
302
303
304 if (i == PCI_ROM_RESOURCE)
305 flags |= IORESOURCE_MEM;
306
307
308 if ((flags & res_bit) == 0)
309 continue;
310
311
312 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
313 continue;
314
315
316 if (mmap_state == pci_mmap_io)
317 offset += pci_ctrl->io_space.start - io_offset;
318 vma->vm_pgoff = offset >> PAGE_SHIFT;
319 return 0;
320 }
321
322 return -EINVAL;
323}
324
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327
328
329static __inline__ void
330__pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
331 enum pci_mmap_state mmap_state, int write_combine)
332{
333 int prot = pgprot_val(vma->vm_page_prot);
334
335
336 prot = (prot & _PAGE_CA_MASK) | _PAGE_CA_WT;
337#if 0
338 if (!write_combine)
339 prot |= _PAGE_WRITETHRU;
340#endif
341 vma->vm_page_prot = __pgprot(prot);
342}
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354int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
355 enum pci_mmap_state mmap_state,
356 int write_combine)
357{
358 int ret;
359
360 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
361 if (ret < 0)
362 return ret;
363
364 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
365
366 ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
367 vma->vm_end - vma->vm_start,vma->vm_page_prot);
368
369 return ret;
370}
371