LXR linux/drivers/clk/mxs/clk-imx28.c

   1/*
   2 * Copyright 2012 Freescale Semiconductor, Inc.
   3 *
   4 * The code contained herein is licensed under the GNU General Public
   5 * License. You may obtain a copy of the GNU General Public License
   6 * Version 2 or later at the following locations:
   7 *
   8 * http://www.opensource.org/licenses/gpl-license.html
   9 * http://www.gnu.org/copyleft/gpl.html
  10 */
  11
  12#include <linux/clk.h>
  13#include <linux/clkdev.h>
  14#include <linux/err.h>
  15#include <linux/init.h>
  16#include <linux/io.h>
  17#include <linux/of.h>
  18#include <mach/common.h>
  19#include <mach/mx28.h>
  20#include "clk.h"
  21
  22#define CLKCTRL                 MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
  23#define PLL0CTRL0               (CLKCTRL + 0x0000)
  24#define PLL1CTRL0               (CLKCTRL + 0x0020)
  25#define PLL2CTRL0               (CLKCTRL + 0x0040)
  26#define CPU                     (CLKCTRL + 0x0050)
  27#define HBUS                    (CLKCTRL + 0x0060)
  28#define XBUS                    (CLKCTRL + 0x0070)
  29#define XTAL                    (CLKCTRL + 0x0080)
  30#define SSP0                    (CLKCTRL + 0x0090)
  31#define SSP1                    (CLKCTRL + 0x00a0)
  32#define SSP2                    (CLKCTRL + 0x00b0)
  33#define SSP3                    (CLKCTRL + 0x00c0)
  34#define GPMI                    (CLKCTRL + 0x00d0)
  35#define SPDIF                   (CLKCTRL + 0x00e0)
  36#define EMI                     (CLKCTRL + 0x00f0)
  37#define SAIF0                   (CLKCTRL + 0x0100)
  38#define SAIF1                   (CLKCTRL + 0x0110)
  39#define LCDIF                   (CLKCTRL + 0x0120)
  40#define ETM                     (CLKCTRL + 0x0130)
  41#define ENET                    (CLKCTRL + 0x0140)
  42#define FLEXCAN                 (CLKCTRL + 0x0160)
  43#define FRAC0                   (CLKCTRL + 0x01b0)
  44#define FRAC1                   (CLKCTRL + 0x01c0)
  45#define CLKSEQ                  (CLKCTRL + 0x01d0)
  46
  47#define BP_CPU_INTERRUPT_WAIT   12
  48#define BP_SAIF_DIV_FRAC_EN     16
  49#define BP_ENET_DIV_TIME        21
  50#define BP_ENET_SLEEP           31
  51#define BP_CLKSEQ_BYPASS_SAIF0  0
  52#define BP_CLKSEQ_BYPASS_SSP0   3
  53#define BP_FRAC0_IO1FRAC        16
  54#define BP_FRAC0_IO0FRAC        24
  55
  56#define DIGCTRL                 MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
  57#define BP_SAIF_CLKMUX          10
  58
  59/*
  60 * HW_SAIF_CLKMUX_SEL:
  61 *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
  62 *              clock pins selected for SAIF1 input clocks.
  63 *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
  64 *              SAIF0 clock inputs selected for SAIF1 input clocks.
  65 *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
  66 *              clocks.
  67 *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
  68 *              clocks.
  69 */
  70int mxs_saif_clkmux_select(unsigned int clkmux)
  71{
  72        if (clkmux > 0x3)
  73                return -EINVAL;
  74
  75        __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
  76        __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
  77
  78        return 0;
  79}
  80
  81static void __init clk_misc_init(void)
  82{
  83        u32 val;
  84
  85        /* Gate off cpu clock in WFI for power saving */
  86        __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
  87
  88        /* 0 is a bad default value for a divider */
  89        __mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
  90
  91        /* Clear BYPASS for SAIF */
  92        __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
  93
  94        /* SAIF has to use frac div for functional operation */
  95        val = readl_relaxed(SAIF0);
  96        val |= 1 << BP_SAIF_DIV_FRAC_EN;
  97        writel_relaxed(val, SAIF0);
  98
  99        val = readl_relaxed(SAIF1);
 100        val |= 1 << BP_SAIF_DIV_FRAC_EN;
 101        writel_relaxed(val, SAIF1);
 102
 103        /* Extra fec clock setting */
 104        val = readl_relaxed(ENET);
 105        val &= ~(1 << BP_ENET_SLEEP);
 106        writel_relaxed(val, ENET);
 107
 108        /*
 109         * Source ssp clock from ref_io than ref_xtal,
 110         * as ref_xtal only provides 24 MHz as maximum.
 111         */
 112        __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
 113
 114        /*
 115         * 480 MHz seems too high to be ssp clock source directly,
 116         * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 117         */
 118        val = readl_relaxed(FRAC0);
 119        val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
 120        val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 121        writel_relaxed(val, FRAC0);
 122}
 123
 124static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 125static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 126static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
 127static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
 128static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
 129static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", };
 130static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
 131static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
 132static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", };
 133
 134enum imx28_clk {
 135        ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
 136        ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
 137        ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
 138        lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
 139        ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
 140        emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
 141        clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
 142        ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
 143        fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
 144        clk_max
 145};
 146
 147static struct clk *clks[clk_max];
 148static struct clk_onecell_data clk_data;
 149
 150static enum imx28_clk clks_init_on[] __initdata = {
 151        cpu, hbus, xbus, emi, uart,
 152};
 153
 154int __init mx28_clocks_init(void)
 155{
 156        struct device_node *np;
 157        u32 i;
 158
 159        clk_misc_init();
 160
 161        clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
 162        clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
 163        clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
 164        clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
 165        clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
 166        clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
 167        clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
 168        clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
 169        clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
 170        clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
 171        clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
 172        clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
 173        clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
 174        clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
 175        clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
 176        clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
 177        clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
 178        clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
 179        clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
 180        clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
 181        clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
 182        clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
 183        clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
 184        clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
 185        clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
 186        clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
 187        clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
 188        clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
 189        clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
 190        clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
 191        clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
 192        clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
 193        clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
 194        clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
 195        clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
 196        clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
 197        clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
 198        clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
 199        clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
 200        clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
 201        clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
 202        clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
 203        clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
 204        clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
 205        clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
 206        clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
 207        clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
 208        clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
 209        clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
 210        clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
 211        clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
 212        clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
 213        clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
 214        clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
 215        clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
 216        clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
 217        clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
 218        clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
 219        clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
 220        clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
 221        clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
 222        clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
 223        clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
 224        clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
 225        clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
 226
 227        for (i = 0; i < ARRAY_SIZE(clks); i++)
 228                if (IS_ERR(clks[i])) {
 229                        pr_err("i.MX28 clk %d: register failed with %ld\n",
 230                                i, PTR_ERR(clks[i]));
 231                        return PTR_ERR(clks[i]);
 232                }
 233
 234        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
 235        if (np) {
 236                clk_data.clks = clks;
 237                clk_data.clk_num = ARRAY_SIZE(clks);
 238                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 239        }
 240
 241        clk_register_clkdev(clks[xbus], NULL, "timrot");
 242        clk_register_clkdev(clks[enet_out], NULL, "enet_out");
 243
 244        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
 245                clk_prepare_enable(clks[clks_init_on[i]]);
 246
 247        mxs_timer_init();
 248
 249        return 0;
 250}
 251