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26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
88
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
90 bool is_tv = false, is_cv = false;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
98 is_tv = true;
99 }
100
101 memset(&args, 0, sizeof(args));
102
103 args.ucScaler = radeon_crtc->crtc_id;
104
105 if (is_tv) {
106 switch (tv_std) {
107 case TV_STD_NTSC:
108 default:
109 args.ucTVStandard = ATOM_TV_NTSC;
110 break;
111 case TV_STD_PAL:
112 args.ucTVStandard = ATOM_TV_PAL;
113 break;
114 case TV_STD_PAL_M:
115 args.ucTVStandard = ATOM_TV_PALM;
116 break;
117 case TV_STD_PAL_60:
118 args.ucTVStandard = ATOM_TV_PAL60;
119 break;
120 case TV_STD_NTSC_J:
121 args.ucTVStandard = ATOM_TV_NTSCJ;
122 break;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL;
125 break;
126 case TV_STD_SECAM:
127 args.ucTVStandard = ATOM_TV_SECAM;
128 break;
129 case TV_STD_PAL_CN:
130 args.ucTVStandard = ATOM_TV_PALCN;
131 break;
132 }
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
134 } else if (is_cv) {
135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
137 } else {
138 switch (radeon_crtc->rmx_type) {
139 case RMX_FULL:
140 args.ucEnable = ATOM_SCALER_EXPANSION;
141 break;
142 case RMX_CENTER:
143 args.ucEnable = ATOM_SCALER_CENTER;
144 break;
145 case RMX_ASPECT:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 default:
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
151 else
152 args.ucEnable = ATOM_SCALER_CENTER;
153 break;
154 }
155 }
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
157 if ((is_tv || is_cv)
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
160 }
161}
162
163static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
164{
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 int index =
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
171
172 memset(&args, 0, sizeof(args));
173
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
176
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
178}
179
180static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
181{
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194}
195
196static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
197{
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210}
211
212static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
213{
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
215 struct drm_device *dev = crtc->dev;
216 struct radeon_device *rdev = dev->dev_private;
217 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
218 BLANK_CRTC_PS_ALLOCATION args;
219
220 memset(&args, 0, sizeof(args));
221
222 args.ucCRTC = radeon_crtc->crtc_id;
223 args.ucBlanking = state;
224
225 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
226}
227
228static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
229{
230 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
231 struct drm_device *dev = crtc->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
234 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
235
236 memset(&args, 0, sizeof(args));
237
238 args.ucDispPipeId = radeon_crtc->crtc_id;
239 args.ucEnable = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
242}
243
244void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
245{
246 struct drm_device *dev = crtc->dev;
247 struct radeon_device *rdev = dev->dev_private;
248 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
249
250 switch (mode) {
251 case DRM_MODE_DPMS_ON:
252 radeon_crtc->enabled = true;
253
254 radeon_pm_compute_clocks(rdev);
255 atombios_enable_crtc(crtc, ATOM_ENABLE);
256 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
257 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
258 atombios_blank_crtc(crtc, ATOM_DISABLE);
259 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
260 radeon_crtc_load_lut(crtc);
261 break;
262 case DRM_MODE_DPMS_STANDBY:
263 case DRM_MODE_DPMS_SUSPEND:
264 case DRM_MODE_DPMS_OFF:
265 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
266 if (radeon_crtc->enabled)
267 atombios_blank_crtc(crtc, ATOM_ENABLE);
268 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
269 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
270 atombios_enable_crtc(crtc, ATOM_DISABLE);
271 radeon_crtc->enabled = false;
272
273 radeon_pm_compute_clocks(rdev);
274 break;
275 }
276}
277
278static void
279atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
280 struct drm_display_mode *mode)
281{
282 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
283 struct drm_device *dev = crtc->dev;
284 struct radeon_device *rdev = dev->dev_private;
285 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
286 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
287 u16 misc = 0;
288
289 memset(&args, 0, sizeof(args));
290 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
291 args.usH_Blanking_Time =
292 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
293 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
294 args.usV_Blanking_Time =
295 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
296 args.usH_SyncOffset =
297 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
298 args.usH_SyncWidth =
299 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
300 args.usV_SyncOffset =
301 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
302 args.usV_SyncWidth =
303 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
304 args.ucH_Border = radeon_crtc->h_border;
305 args.ucV_Border = radeon_crtc->v_border;
306
307 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
308 misc |= ATOM_VSYNC_POLARITY;
309 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
310 misc |= ATOM_HSYNC_POLARITY;
311 if (mode->flags & DRM_MODE_FLAG_CSYNC)
312 misc |= ATOM_COMPOSITESYNC;
313 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
314 misc |= ATOM_INTERLACE;
315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
316 misc |= ATOM_DOUBLE_CLOCK_MODE;
317
318 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
319 args.ucCRTC = radeon_crtc->crtc_id;
320
321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
322}
323
324static void atombios_crtc_set_timing(struct drm_crtc *crtc,
325 struct drm_display_mode *mode)
326{
327 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
328 struct drm_device *dev = crtc->dev;
329 struct radeon_device *rdev = dev->dev_private;
330 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
331 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
332 u16 misc = 0;
333
334 memset(&args, 0, sizeof(args));
335 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
336 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
337 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
338 args.usH_SyncWidth =
339 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
340 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
341 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
342 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
343 args.usV_SyncWidth =
344 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
345
346 args.ucOverscanRight = radeon_crtc->h_border;
347 args.ucOverscanLeft = radeon_crtc->h_border;
348 args.ucOverscanBottom = radeon_crtc->v_border;
349 args.ucOverscanTop = radeon_crtc->v_border;
350
351 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
352 misc |= ATOM_VSYNC_POLARITY;
353 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
354 misc |= ATOM_HSYNC_POLARITY;
355 if (mode->flags & DRM_MODE_FLAG_CSYNC)
356 misc |= ATOM_COMPOSITESYNC;
357 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
358 misc |= ATOM_INTERLACE;
359 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
360 misc |= ATOM_DOUBLE_CLOCK_MODE;
361
362 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
363 args.ucCRTC = radeon_crtc->crtc_id;
364
365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
366}
367
368static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
369{
370 u32 ss_cntl;
371
372 if (ASIC_IS_DCE4(rdev)) {
373 switch (pll_id) {
374 case ATOM_PPLL1:
375 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
376 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
377 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
378 break;
379 case ATOM_PPLL2:
380 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
381 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
382 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
383 break;
384 case ATOM_DCPLL:
385 case ATOM_PPLL_INVALID:
386 return;
387 }
388 } else if (ASIC_IS_AVIVO(rdev)) {
389 switch (pll_id) {
390 case ATOM_PPLL1:
391 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
392 ss_cntl &= ~1;
393 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
394 break;
395 case ATOM_PPLL2:
396 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
397 ss_cntl &= ~1;
398 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
399 break;
400 case ATOM_DCPLL:
401 case ATOM_PPLL_INVALID:
402 return;
403 }
404 }
405}
406
407
408union atom_enable_ss {
409 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
410 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
411 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
412 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
413 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
414};
415
416static void atombios_crtc_program_ss(struct radeon_device *rdev,
417 int enable,
418 int pll_id,
419 int crtc_id,
420 struct radeon_atom_ss *ss)
421{
422 unsigned i;
423 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
424 union atom_enable_ss args;
425
426 if (!enable) {
427 for (i = 0; i < rdev->num_crtc; i++) {
428 if (rdev->mode_info.crtcs[i] &&
429 rdev->mode_info.crtcs[i]->enabled &&
430 i != crtc_id &&
431 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
432
433
434
435
436 return;
437 }
438 }
439 }
440
441 memset(&args, 0, sizeof(args));
442
443 if (ASIC_IS_DCE5(rdev)) {
444 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
445 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
446 switch (pll_id) {
447 case ATOM_PPLL1:
448 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
449 break;
450 case ATOM_PPLL2:
451 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
452 break;
453 case ATOM_DCPLL:
454 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
455 break;
456 case ATOM_PPLL_INVALID:
457 return;
458 }
459 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
460 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
461 args.v3.ucEnable = enable;
462 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
463 args.v3.ucEnable = ATOM_DISABLE;
464 } else if (ASIC_IS_DCE4(rdev)) {
465 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
466 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
467 switch (pll_id) {
468 case ATOM_PPLL1:
469 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
470 break;
471 case ATOM_PPLL2:
472 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
473 break;
474 case ATOM_DCPLL:
475 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
476 break;
477 case ATOM_PPLL_INVALID:
478 return;
479 }
480 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
481 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
482 args.v2.ucEnable = enable;
483 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
484 args.v2.ucEnable = ATOM_DISABLE;
485 } else if (ASIC_IS_DCE3(rdev)) {
486 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
487 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
488 args.v1.ucSpreadSpectrumStep = ss->step;
489 args.v1.ucSpreadSpectrumDelay = ss->delay;
490 args.v1.ucSpreadSpectrumRange = ss->range;
491 args.v1.ucPpll = pll_id;
492 args.v1.ucEnable = enable;
493 } else if (ASIC_IS_AVIVO(rdev)) {
494 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
495 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
496 atombios_disable_ss(rdev, pll_id);
497 return;
498 }
499 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
500 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
501 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
502 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
503 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
504 args.lvds_ss_2.ucEnable = enable;
505 } else {
506 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
507 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
508 atombios_disable_ss(rdev, pll_id);
509 return;
510 }
511 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
512 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
513 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
514 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
515 args.lvds_ss.ucEnable = enable;
516 }
517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
518}
519
520union adjust_pixel_clock {
521 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
522 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
523};
524
525static u32 atombios_adjust_pll(struct drm_crtc *crtc,
526 struct drm_display_mode *mode)
527{
528 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
529 struct drm_device *dev = crtc->dev;
530 struct radeon_device *rdev = dev->dev_private;
531 struct drm_encoder *encoder = radeon_crtc->encoder;
532 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
533 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
534 u32 adjusted_clock = mode->clock;
535 int encoder_mode = atombios_get_encoder_mode(encoder);
536 u32 dp_clock = mode->clock;
537 int bpc = radeon_get_monitor_bpc(connector);
538 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
539
540
541 radeon_crtc->pll_flags = 0;
542
543 if (ASIC_IS_AVIVO(rdev)) {
544 if ((rdev->family == CHIP_RS600) ||
545 (rdev->family == CHIP_RS690) ||
546 (rdev->family == CHIP_RS740))
547 radeon_crtc->pll_flags |= (
548 RADEON_PLL_PREFER_CLOSEST_LOWER);
549
550 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)
551 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
552 else
553 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
554
555 if (rdev->family < CHIP_RV770)
556 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
557
558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
561 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
562 } else {
563 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
564
565 if (mode->clock > 200000)
566 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
567 else
568 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
569 }
570
571 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
572 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
573 if (connector) {
574 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
575 struct radeon_connector_atom_dig *dig_connector =
576 radeon_connector->con_priv;
577
578 dp_clock = dig_connector->dp_clock;
579 }
580 }
581
582
583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
584 if (radeon_crtc->ss_enabled) {
585 if (radeon_crtc->ss.refdiv) {
586 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
587 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
588 if (ASIC_IS_AVIVO(rdev))
589 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
590 }
591 }
592 }
593
594 if (ASIC_IS_AVIVO(rdev)) {
595
596 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
597 adjusted_clock = mode->clock * 2;
598 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
599 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
600 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
601 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
602 } else {
603 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
604 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
605 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
606 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
607 }
608
609
610
611
612
613 if (ASIC_IS_DCE3(rdev)) {
614 union adjust_pixel_clock args;
615 u8 frev, crev;
616 int index;
617
618 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
619 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
620 &crev))
621 return adjusted_clock;
622
623 memset(&args, 0, sizeof(args));
624
625 switch (frev) {
626 case 1:
627 switch (crev) {
628 case 1:
629 case 2:
630 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
631 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
632 args.v1.ucEncodeMode = encoder_mode;
633 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
634 args.v1.ucConfig |=
635 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
636
637 atom_execute_table(rdev->mode_info.atom_context,
638 index, (uint32_t *)&args);
639 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
640 break;
641 case 3:
642 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
643 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
644 args.v3.sInput.ucEncodeMode = encoder_mode;
645 args.v3.sInput.ucDispPllConfig = 0;
646 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
647 args.v3.sInput.ucDispPllConfig |=
648 DISPPLL_CONFIG_SS_ENABLE;
649 if (ENCODER_MODE_IS_DP(encoder_mode)) {
650 args.v3.sInput.ucDispPllConfig |=
651 DISPPLL_CONFIG_COHERENT_MODE;
652
653 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
654 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
655 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
656 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
657
658 args.v3.sInput.usPixelClock =
659 cpu_to_le16((mode->clock * bpc / 8) / 10);
660 if (dig->coherent_mode)
661 args.v3.sInput.ucDispPllConfig |=
662 DISPPLL_CONFIG_COHERENT_MODE;
663 if (is_duallink)
664 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_DUAL_LINK;
666 }
667 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
668 ENCODER_OBJECT_ID_NONE)
669 args.v3.sInput.ucExtTransmitterID =
670 radeon_encoder_get_dp_bridge_encoder_id(encoder);
671 else
672 args.v3.sInput.ucExtTransmitterID = 0;
673
674 atom_execute_table(rdev->mode_info.atom_context,
675 index, (uint32_t *)&args);
676 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
677 if (args.v3.sOutput.ucRefDiv) {
678 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
679 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
680 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
681 }
682 if (args.v3.sOutput.ucPostDiv) {
683 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
684 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
685 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
686 }
687 break;
688 default:
689 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
690 return adjusted_clock;
691 }
692 break;
693 default:
694 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
695 return adjusted_clock;
696 }
697 }
698 return adjusted_clock;
699}
700
701union set_pixel_clock {
702 SET_PIXEL_CLOCK_PS_ALLOCATION base;
703 PIXEL_CLOCK_PARAMETERS v1;
704 PIXEL_CLOCK_PARAMETERS_V2 v2;
705 PIXEL_CLOCK_PARAMETERS_V3 v3;
706 PIXEL_CLOCK_PARAMETERS_V5 v5;
707 PIXEL_CLOCK_PARAMETERS_V6 v6;
708};
709
710
711
712
713static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
714 u32 dispclk)
715{
716 u8 frev, crev;
717 int index;
718 union set_pixel_clock args;
719
720 memset(&args, 0, sizeof(args));
721
722 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
723 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
724 &crev))
725 return;
726
727 switch (frev) {
728 case 1:
729 switch (crev) {
730 case 5:
731
732
733
734 args.v5.ucCRTC = ATOM_CRTC_INVALID;
735 args.v5.usPixelClock = cpu_to_le16(dispclk);
736 args.v5.ucPpll = ATOM_DCPLL;
737 break;
738 case 6:
739
740
741
742 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
743 if (ASIC_IS_DCE61(rdev))
744 args.v6.ucPpll = ATOM_EXT_PLL1;
745 else if (ASIC_IS_DCE6(rdev))
746 args.v6.ucPpll = ATOM_PPLL0;
747 else
748 args.v6.ucPpll = ATOM_DCPLL;
749 break;
750 default:
751 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
752 return;
753 }
754 break;
755 default:
756 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
757 return;
758 }
759 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
760}
761
762static void atombios_crtc_program_pll(struct drm_crtc *crtc,
763 u32 crtc_id,
764 int pll_id,
765 u32 encoder_mode,
766 u32 encoder_id,
767 u32 clock,
768 u32 ref_div,
769 u32 fb_div,
770 u32 frac_fb_div,
771 u32 post_div,
772 int bpc,
773 bool ss_enabled,
774 struct radeon_atom_ss *ss)
775{
776 struct drm_device *dev = crtc->dev;
777 struct radeon_device *rdev = dev->dev_private;
778 u8 frev, crev;
779 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
780 union set_pixel_clock args;
781
782 memset(&args, 0, sizeof(args));
783
784 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
785 &crev))
786 return;
787
788 switch (frev) {
789 case 1:
790 switch (crev) {
791 case 1:
792 if (clock == ATOM_DISABLE)
793 return;
794 args.v1.usPixelClock = cpu_to_le16(clock / 10);
795 args.v1.usRefDiv = cpu_to_le16(ref_div);
796 args.v1.usFbDiv = cpu_to_le16(fb_div);
797 args.v1.ucFracFbDiv = frac_fb_div;
798 args.v1.ucPostDiv = post_div;
799 args.v1.ucPpll = pll_id;
800 args.v1.ucCRTC = crtc_id;
801 args.v1.ucRefDivSrc = 1;
802 break;
803 case 2:
804 args.v2.usPixelClock = cpu_to_le16(clock / 10);
805 args.v2.usRefDiv = cpu_to_le16(ref_div);
806 args.v2.usFbDiv = cpu_to_le16(fb_div);
807 args.v2.ucFracFbDiv = frac_fb_div;
808 args.v2.ucPostDiv = post_div;
809 args.v2.ucPpll = pll_id;
810 args.v2.ucCRTC = crtc_id;
811 args.v2.ucRefDivSrc = 1;
812 break;
813 case 3:
814 args.v3.usPixelClock = cpu_to_le16(clock / 10);
815 args.v3.usRefDiv = cpu_to_le16(ref_div);
816 args.v3.usFbDiv = cpu_to_le16(fb_div);
817 args.v3.ucFracFbDiv = frac_fb_div;
818 args.v3.ucPostDiv = post_div;
819 args.v3.ucPpll = pll_id;
820 if (crtc_id == ATOM_CRTC2)
821 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
822 else
823 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
824 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
825 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
826 args.v3.ucTransmitterId = encoder_id;
827 args.v3.ucEncoderMode = encoder_mode;
828 break;
829 case 5:
830 args.v5.ucCRTC = crtc_id;
831 args.v5.usPixelClock = cpu_to_le16(clock / 10);
832 args.v5.ucRefDiv = ref_div;
833 args.v5.usFbDiv = cpu_to_le16(fb_div);
834 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
835 args.v5.ucPostDiv = post_div;
836 args.v5.ucMiscInfo = 0;
837 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
838 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
839 switch (bpc) {
840 case 8:
841 default:
842 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
843 break;
844 case 10:
845 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
846 break;
847 }
848 args.v5.ucTransmitterID = encoder_id;
849 args.v5.ucEncoderMode = encoder_mode;
850 args.v5.ucPpll = pll_id;
851 break;
852 case 6:
853 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
854 args.v6.ucRefDiv = ref_div;
855 args.v6.usFbDiv = cpu_to_le16(fb_div);
856 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
857 args.v6.ucPostDiv = post_div;
858 args.v6.ucMiscInfo = 0;
859 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
860 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
861 switch (bpc) {
862 case 8:
863 default:
864 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
865 break;
866 case 10:
867 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
868 break;
869 case 12:
870 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
871 break;
872 case 16:
873 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
874 break;
875 }
876 args.v6.ucTransmitterID = encoder_id;
877 args.v6.ucEncoderMode = encoder_mode;
878 args.v6.ucPpll = pll_id;
879 break;
880 default:
881 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
882 return;
883 }
884 break;
885 default:
886 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
887 return;
888 }
889
890 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
891}
892
893static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
894{
895 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
896 struct drm_device *dev = crtc->dev;
897 struct radeon_device *rdev = dev->dev_private;
898 struct radeon_encoder *radeon_encoder =
899 to_radeon_encoder(radeon_crtc->encoder);
900 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
901
902 radeon_crtc->bpc = 8;
903 radeon_crtc->ss_enabled = false;
904
905 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
906 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
907 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
908 struct drm_connector *connector =
909 radeon_get_connector_for_encoder(radeon_crtc->encoder);
910 struct radeon_connector *radeon_connector =
911 to_radeon_connector(connector);
912 struct radeon_connector_atom_dig *dig_connector =
913 radeon_connector->con_priv;
914 int dp_clock;
915 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
916
917 switch (encoder_mode) {
918 case ATOM_ENCODER_MODE_DP_MST:
919 case ATOM_ENCODER_MODE_DP:
920
921 dp_clock = dig_connector->dp_clock / 10;
922 if (ASIC_IS_DCE4(rdev))
923 radeon_crtc->ss_enabled =
924 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
925 ASIC_INTERNAL_SS_ON_DP,
926 dp_clock);
927 else {
928 if (dp_clock == 16200) {
929 radeon_crtc->ss_enabled =
930 radeon_atombios_get_ppll_ss_info(rdev,
931 &radeon_crtc->ss,
932 ATOM_DP_SS_ID2);
933 if (!radeon_crtc->ss_enabled)
934 radeon_crtc->ss_enabled =
935 radeon_atombios_get_ppll_ss_info(rdev,
936 &radeon_crtc->ss,
937 ATOM_DP_SS_ID1);
938 } else
939 radeon_crtc->ss_enabled =
940 radeon_atombios_get_ppll_ss_info(rdev,
941 &radeon_crtc->ss,
942 ATOM_DP_SS_ID1);
943 }
944 break;
945 case ATOM_ENCODER_MODE_LVDS:
946 if (ASIC_IS_DCE4(rdev))
947 radeon_crtc->ss_enabled =
948 radeon_atombios_get_asic_ss_info(rdev,
949 &radeon_crtc->ss,
950 dig->lcd_ss_id,
951 mode->clock / 10);
952 else
953 radeon_crtc->ss_enabled =
954 radeon_atombios_get_ppll_ss_info(rdev,
955 &radeon_crtc->ss,
956 dig->lcd_ss_id);
957 break;
958 case ATOM_ENCODER_MODE_DVI:
959 if (ASIC_IS_DCE4(rdev))
960 radeon_crtc->ss_enabled =
961 radeon_atombios_get_asic_ss_info(rdev,
962 &radeon_crtc->ss,
963 ASIC_INTERNAL_SS_ON_TMDS,
964 mode->clock / 10);
965 break;
966 case ATOM_ENCODER_MODE_HDMI:
967 if (ASIC_IS_DCE4(rdev))
968 radeon_crtc->ss_enabled =
969 radeon_atombios_get_asic_ss_info(rdev,
970 &radeon_crtc->ss,
971 ASIC_INTERNAL_SS_ON_HDMI,
972 mode->clock / 10);
973 break;
974 default:
975 break;
976 }
977 }
978
979
980 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
981
982 return true;
983}
984
985static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
986{
987 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
988 struct drm_device *dev = crtc->dev;
989 struct radeon_device *rdev = dev->dev_private;
990 struct radeon_encoder *radeon_encoder =
991 to_radeon_encoder(radeon_crtc->encoder);
992 u32 pll_clock = mode->clock;
993 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
994 struct radeon_pll *pll;
995 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
996
997 switch (radeon_crtc->pll_id) {
998 case ATOM_PPLL1:
999 pll = &rdev->clock.p1pll;
1000 break;
1001 case ATOM_PPLL2:
1002 pll = &rdev->clock.p2pll;
1003 break;
1004 case ATOM_DCPLL:
1005 case ATOM_PPLL_INVALID:
1006 default:
1007 pll = &rdev->clock.dcpll;
1008 break;
1009 }
1010
1011
1012 pll->flags = radeon_crtc->pll_flags;
1013 pll->reference_div = radeon_crtc->pll_reference_div;
1014 pll->post_div = radeon_crtc->pll_post_div;
1015
1016 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1017
1018 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1019 &fb_div, &frac_fb_div, &ref_div, &post_div);
1020 else if (ASIC_IS_AVIVO(rdev))
1021 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1022 &fb_div, &frac_fb_div, &ref_div, &post_div);
1023 else
1024 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1025 &fb_div, &frac_fb_div, &ref_div, &post_div);
1026
1027 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1028 radeon_crtc->crtc_id, &radeon_crtc->ss);
1029
1030 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1031 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1032 ref_div, fb_div, frac_fb_div, post_div,
1033 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1034
1035 if (radeon_crtc->ss_enabled) {
1036
1037 if (ASIC_IS_DCE4(rdev)) {
1038 u32 step_size;
1039 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;
1040 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1041 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1042 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1043 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1044 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1045 (125 * 25 * pll->reference_freq / 100);
1046 else
1047 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1048 (125 * 25 * pll->reference_freq / 100);
1049 radeon_crtc->ss.step = step_size;
1050 }
1051
1052 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1053 radeon_crtc->crtc_id, &radeon_crtc->ss);
1054 }
1055}
1056
1057static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1058 struct drm_framebuffer *fb,
1059 int x, int y, int atomic)
1060{
1061 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1062 struct drm_device *dev = crtc->dev;
1063 struct radeon_device *rdev = dev->dev_private;
1064 struct radeon_framebuffer *radeon_fb;
1065 struct drm_framebuffer *target_fb;
1066 struct drm_gem_object *obj;
1067 struct radeon_bo *rbo;
1068 uint64_t fb_location;
1069 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1070 unsigned bankw, bankh, mtaspect, tile_split;
1071 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1072 u32 tmp, viewport_w, viewport_h;
1073 int r;
1074
1075
1076 if (!atomic && !crtc->fb) {
1077 DRM_DEBUG_KMS("No FB bound\n");
1078 return 0;
1079 }
1080
1081 if (atomic) {
1082 radeon_fb = to_radeon_framebuffer(fb);
1083 target_fb = fb;
1084 }
1085 else {
1086 radeon_fb = to_radeon_framebuffer(crtc->fb);
1087 target_fb = crtc->fb;
1088 }
1089
1090
1091
1092
1093 obj = radeon_fb->obj;
1094 rbo = gem_to_radeon_bo(obj);
1095 r = radeon_bo_reserve(rbo, false);
1096 if (unlikely(r != 0))
1097 return r;
1098
1099 if (atomic)
1100 fb_location = radeon_bo_gpu_offset(rbo);
1101 else {
1102 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1103 if (unlikely(r != 0)) {
1104 radeon_bo_unreserve(rbo);
1105 return -EINVAL;
1106 }
1107 }
1108
1109 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1110 radeon_bo_unreserve(rbo);
1111
1112 switch (target_fb->bits_per_pixel) {
1113 case 8:
1114 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1115 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1116 break;
1117 case 15:
1118 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1119 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1120 break;
1121 case 16:
1122 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1123 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1124#ifdef __BIG_ENDIAN
1125 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1126#endif
1127 break;
1128 case 24:
1129 case 32:
1130 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1131 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1132#ifdef __BIG_ENDIAN
1133 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1134#endif
1135 break;
1136 default:
1137 DRM_ERROR("Unsupported screen depth %d\n",
1138 target_fb->bits_per_pixel);
1139 return -EINVAL;
1140 }
1141
1142 if (tiling_flags & RADEON_TILING_MACRO) {
1143 if (rdev->family >= CHIP_TAHITI)
1144 tmp = rdev->config.si.tile_config;
1145 else if (rdev->family >= CHIP_CAYMAN)
1146 tmp = rdev->config.cayman.tile_config;
1147 else
1148 tmp = rdev->config.evergreen.tile_config;
1149
1150 switch ((tmp & 0xf0) >> 4) {
1151 case 0:
1152 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1153 break;
1154 case 1:
1155 default:
1156 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1157 break;
1158 case 2:
1159 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1160 break;
1161 }
1162
1163 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1164
1165 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1166 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1167 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1168 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1169 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1170 } else if (tiling_flags & RADEON_TILING_MICRO)
1171 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1172
1173 if ((rdev->family == CHIP_TAHITI) ||
1174 (rdev->family == CHIP_PITCAIRN))
1175 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1176 else if (rdev->family == CHIP_VERDE)
1177 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1178
1179 switch (radeon_crtc->crtc_id) {
1180 case 0:
1181 WREG32(AVIVO_D1VGA_CONTROL, 0);
1182 break;
1183 case 1:
1184 WREG32(AVIVO_D2VGA_CONTROL, 0);
1185 break;
1186 case 2:
1187 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1188 break;
1189 case 3:
1190 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1191 break;
1192 case 4:
1193 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1194 break;
1195 case 5:
1196 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1203 upper_32_bits(fb_location));
1204 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1205 upper_32_bits(fb_location));
1206 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1207 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1208 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1209 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1210 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1211 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1212
1213 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1214 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1215 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1216 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1217 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1218 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1219
1220 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1221 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1222 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1223
1224 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1225 target_fb->height);
1226 x &= ~3;
1227 y &= ~1;
1228 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1229 (x << 16) | y);
1230 viewport_w = crtc->mode.hdisplay;
1231 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1232 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1233 (viewport_w << 16) | viewport_h);
1234
1235
1236
1237 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1238 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1239 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1240
1241
1242 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1243
1244 if (!atomic && fb && fb != crtc->fb) {
1245 radeon_fb = to_radeon_framebuffer(fb);
1246 rbo = gem_to_radeon_bo(radeon_fb->obj);
1247 r = radeon_bo_reserve(rbo, false);
1248 if (unlikely(r != 0))
1249 return r;
1250 radeon_bo_unpin(rbo);
1251 radeon_bo_unreserve(rbo);
1252 }
1253
1254
1255 radeon_bandwidth_update(rdev);
1256
1257 return 0;
1258}
1259
1260static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1261 struct drm_framebuffer *fb,
1262 int x, int y, int atomic)
1263{
1264 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1265 struct drm_device *dev = crtc->dev;
1266 struct radeon_device *rdev = dev->dev_private;
1267 struct radeon_framebuffer *radeon_fb;
1268 struct drm_gem_object *obj;
1269 struct radeon_bo *rbo;
1270 struct drm_framebuffer *target_fb;
1271 uint64_t fb_location;
1272 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1273 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1274 u32 tmp, viewport_w, viewport_h;
1275 int r;
1276
1277
1278 if (!atomic && !crtc->fb) {
1279 DRM_DEBUG_KMS("No FB bound\n");
1280 return 0;
1281 }
1282
1283 if (atomic) {
1284 radeon_fb = to_radeon_framebuffer(fb);
1285 target_fb = fb;
1286 }
1287 else {
1288 radeon_fb = to_radeon_framebuffer(crtc->fb);
1289 target_fb = crtc->fb;
1290 }
1291
1292 obj = radeon_fb->obj;
1293 rbo = gem_to_radeon_bo(obj);
1294 r = radeon_bo_reserve(rbo, false);
1295 if (unlikely(r != 0))
1296 return r;
1297
1298
1299
1300
1301 if (atomic)
1302 fb_location = radeon_bo_gpu_offset(rbo);
1303 else {
1304 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1305 if (unlikely(r != 0)) {
1306 radeon_bo_unreserve(rbo);
1307 return -EINVAL;
1308 }
1309 }
1310 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1311 radeon_bo_unreserve(rbo);
1312
1313 switch (target_fb->bits_per_pixel) {
1314 case 8:
1315 fb_format =
1316 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1317 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1318 break;
1319 case 15:
1320 fb_format =
1321 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1322 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1323 break;
1324 case 16:
1325 fb_format =
1326 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1327 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1328#ifdef __BIG_ENDIAN
1329 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1330#endif
1331 break;
1332 case 24:
1333 case 32:
1334 fb_format =
1335 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1336 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1337#ifdef __BIG_ENDIAN
1338 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1339#endif
1340 break;
1341 default:
1342 DRM_ERROR("Unsupported screen depth %d\n",
1343 target_fb->bits_per_pixel);
1344 return -EINVAL;
1345 }
1346
1347 if (rdev->family >= CHIP_R600) {
1348 if (tiling_flags & RADEON_TILING_MACRO)
1349 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1350 else if (tiling_flags & RADEON_TILING_MICRO)
1351 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1352 } else {
1353 if (tiling_flags & RADEON_TILING_MACRO)
1354 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1355
1356 if (tiling_flags & RADEON_TILING_MICRO)
1357 fb_format |= AVIVO_D1GRPH_TILED;
1358 }
1359
1360 if (radeon_crtc->crtc_id == 0)
1361 WREG32(AVIVO_D1VGA_CONTROL, 0);
1362 else
1363 WREG32(AVIVO_D2VGA_CONTROL, 0);
1364
1365 if (rdev->family >= CHIP_RV770) {
1366 if (radeon_crtc->crtc_id) {
1367 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1368 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1369 } else {
1370 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1371 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1372 }
1373 }
1374 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1375 (u32) fb_location);
1376 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1377 radeon_crtc->crtc_offset, (u32) fb_location);
1378 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1379 if (rdev->family >= CHIP_R600)
1380 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1381
1382 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1383 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1384 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1385 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1386 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1387 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1388
1389 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1390 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1391 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1392
1393 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1394 target_fb->height);
1395 x &= ~3;
1396 y &= ~1;
1397 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1398 (x << 16) | y);
1399 viewport_w = crtc->mode.hdisplay;
1400 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1401 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1402 (viewport_w << 16) | viewport_h);
1403
1404
1405
1406 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1407 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1408 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1409
1410
1411 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1412
1413 if (!atomic && fb && fb != crtc->fb) {
1414 radeon_fb = to_radeon_framebuffer(fb);
1415 rbo = gem_to_radeon_bo(radeon_fb->obj);
1416 r = radeon_bo_reserve(rbo, false);
1417 if (unlikely(r != 0))
1418 return r;
1419 radeon_bo_unpin(rbo);
1420 radeon_bo_unreserve(rbo);
1421 }
1422
1423
1424 radeon_bandwidth_update(rdev);
1425
1426 return 0;
1427}
1428
1429int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1430 struct drm_framebuffer *old_fb)
1431{
1432 struct drm_device *dev = crtc->dev;
1433 struct radeon_device *rdev = dev->dev_private;
1434
1435 if (ASIC_IS_DCE4(rdev))
1436 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1437 else if (ASIC_IS_AVIVO(rdev))
1438 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1439 else
1440 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1441}
1442
1443int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1444 struct drm_framebuffer *fb,
1445 int x, int y, enum mode_set_atomic state)
1446{
1447 struct drm_device *dev = crtc->dev;
1448 struct radeon_device *rdev = dev->dev_private;
1449
1450 if (ASIC_IS_DCE4(rdev))
1451 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1452 else if (ASIC_IS_AVIVO(rdev))
1453 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1454 else
1455 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1456}
1457
1458
1459static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1460{
1461 struct drm_device *dev = crtc->dev;
1462 struct radeon_device *rdev = dev->dev_private;
1463 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1464 u32 disp_merge_cntl;
1465
1466 switch (radeon_crtc->crtc_id) {
1467 case 0:
1468 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1469 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1470 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1471 break;
1472 case 1:
1473 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1474 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1475 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1476 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1477 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1478 break;
1479 }
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1490{
1491 struct drm_device *dev = crtc->dev;
1492 struct drm_crtc *test_crtc;
1493 struct radeon_crtc *test_radeon_crtc;
1494 u32 pll_in_use = 0;
1495
1496 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1497 if (crtc == test_crtc)
1498 continue;
1499
1500 test_radeon_crtc = to_radeon_crtc(test_crtc);
1501 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1502 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1503 }
1504 return pll_in_use;
1505}
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1517{
1518 struct drm_device *dev = crtc->dev;
1519 struct drm_crtc *test_crtc;
1520 struct radeon_crtc *test_radeon_crtc;
1521
1522 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1523 if (crtc == test_crtc)
1524 continue;
1525 test_radeon_crtc = to_radeon_crtc(test_crtc);
1526 if (test_radeon_crtc->encoder &&
1527 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1528
1529 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1530 return test_radeon_crtc->pll_id;
1531 }
1532 }
1533 return ATOM_PPLL_INVALID;
1534}
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1546{
1547 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1548 struct drm_device *dev = crtc->dev;
1549 struct drm_crtc *test_crtc;
1550 struct radeon_crtc *test_radeon_crtc;
1551 u32 adjusted_clock, test_adjusted_clock;
1552
1553 adjusted_clock = radeon_crtc->adjusted_clock;
1554
1555 if (adjusted_clock == 0)
1556 return ATOM_PPLL_INVALID;
1557
1558 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1559 if (crtc == test_crtc)
1560 continue;
1561 test_radeon_crtc = to_radeon_crtc(test_crtc);
1562 if (test_radeon_crtc->encoder &&
1563 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1564
1565 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1566
1567 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1568 return test_radeon_crtc->pll_id;
1569 }
1570
1571 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1572 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1573 (adjusted_clock == test_adjusted_clock) &&
1574 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1575 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1576 return test_radeon_crtc->pll_id;
1577 }
1578 }
1579 return ATOM_PPLL_INVALID;
1580}
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1614{
1615 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1616 struct drm_device *dev = crtc->dev;
1617 struct radeon_device *rdev = dev->dev_private;
1618 struct radeon_encoder *radeon_encoder =
1619 to_radeon_encoder(radeon_crtc->encoder);
1620 u32 pll_in_use;
1621 int pll;
1622
1623 if (ASIC_IS_DCE61(rdev)) {
1624 struct radeon_encoder_atom_dig *dig =
1625 radeon_encoder->enc_priv;
1626
1627 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1628 (dig->linkb == false))
1629
1630 return ATOM_PPLL2;
1631 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1632
1633 if (rdev->clock.dp_extclk)
1634
1635 return ATOM_PPLL_INVALID;
1636 else {
1637
1638 pll = radeon_get_shared_dp_ppll(crtc);
1639 if (pll != ATOM_PPLL_INVALID)
1640 return pll;
1641 }
1642 } else {
1643
1644 pll = radeon_get_shared_nondp_ppll(crtc);
1645 if (pll != ATOM_PPLL_INVALID)
1646 return pll;
1647 }
1648
1649 pll_in_use = radeon_get_pll_use_mask(crtc);
1650 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1651 return ATOM_PPLL0;
1652 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1653 return ATOM_PPLL1;
1654 DRM_ERROR("unable to allocate a PPLL\n");
1655 return ATOM_PPLL_INVALID;
1656 } else if (ASIC_IS_DCE4(rdev)) {
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1668 if (rdev->clock.dp_extclk)
1669
1670 return ATOM_PPLL_INVALID;
1671 else if (ASIC_IS_DCE6(rdev))
1672
1673 return ATOM_PPLL0;
1674 else if (ASIC_IS_DCE5(rdev))
1675
1676 return ATOM_DCPLL;
1677 else {
1678
1679 pll = radeon_get_shared_dp_ppll(crtc);
1680 if (pll != ATOM_PPLL_INVALID)
1681 return pll;
1682 }
1683 } else {
1684
1685 pll = radeon_get_shared_nondp_ppll(crtc);
1686 if (pll != ATOM_PPLL_INVALID)
1687 return pll;
1688 }
1689
1690 pll_in_use = radeon_get_pll_use_mask(crtc);
1691 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1692 return ATOM_PPLL1;
1693 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1694 return ATOM_PPLL2;
1695 DRM_ERROR("unable to allocate a PPLL\n");
1696 return ATOM_PPLL_INVALID;
1697 } else {
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713 return radeon_crtc->crtc_id;
1714 }
1715}
1716
1717void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1718{
1719
1720 if (ASIC_IS_DCE6(rdev))
1721 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1722 else if (ASIC_IS_DCE4(rdev)) {
1723 struct radeon_atom_ss ss;
1724 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1725 ASIC_INTERNAL_SS_ON_DCPLL,
1726 rdev->clock.default_dispclk);
1727 if (ss_enabled)
1728 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1729
1730 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1731 if (ss_enabled)
1732 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1733 }
1734
1735}
1736
1737int atombios_crtc_mode_set(struct drm_crtc *crtc,
1738 struct drm_display_mode *mode,
1739 struct drm_display_mode *adjusted_mode,
1740 int x, int y, struct drm_framebuffer *old_fb)
1741{
1742 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1743 struct drm_device *dev = crtc->dev;
1744 struct radeon_device *rdev = dev->dev_private;
1745 struct radeon_encoder *radeon_encoder =
1746 to_radeon_encoder(radeon_crtc->encoder);
1747 bool is_tvcv = false;
1748
1749 if (radeon_encoder->active_device &
1750 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1751 is_tvcv = true;
1752
1753 atombios_crtc_set_pll(crtc, adjusted_mode);
1754
1755 if (ASIC_IS_DCE4(rdev))
1756 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1757 else if (ASIC_IS_AVIVO(rdev)) {
1758 if (is_tvcv)
1759 atombios_crtc_set_timing(crtc, adjusted_mode);
1760 else
1761 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1762 } else {
1763 atombios_crtc_set_timing(crtc, adjusted_mode);
1764 if (radeon_crtc->crtc_id == 0)
1765 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1766 radeon_legacy_atom_fixup(crtc);
1767 }
1768 atombios_crtc_set_base(crtc, x, y, old_fb);
1769 atombios_overscan_setup(crtc, mode, adjusted_mode);
1770 atombios_scaler_setup(crtc);
1771 return 0;
1772}
1773
1774static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1775 const struct drm_display_mode *mode,
1776 struct drm_display_mode *adjusted_mode)
1777{
1778 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1779 struct drm_device *dev = crtc->dev;
1780 struct drm_encoder *encoder;
1781
1782
1783 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1784 if (encoder->crtc == crtc) {
1785 radeon_crtc->encoder = encoder;
1786 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1787 break;
1788 }
1789 }
1790 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1791 radeon_crtc->encoder = NULL;
1792 radeon_crtc->connector = NULL;
1793 return false;
1794 }
1795 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1796 return false;
1797 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1798 return false;
1799
1800 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1801
1802 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1803 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1804 return false;
1805
1806 return true;
1807}
1808
1809static void atombios_crtc_prepare(struct drm_crtc *crtc)
1810{
1811 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1812 struct drm_device *dev = crtc->dev;
1813 struct radeon_device *rdev = dev->dev_private;
1814
1815 radeon_crtc->in_mode_set = true;
1816
1817
1818 if (ASIC_IS_DCE6(rdev))
1819 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1820
1821 atombios_lock_crtc(crtc, ATOM_ENABLE);
1822 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1823}
1824
1825static void atombios_crtc_commit(struct drm_crtc *crtc)
1826{
1827 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1828
1829 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1830 atombios_lock_crtc(crtc, ATOM_DISABLE);
1831 radeon_crtc->in_mode_set = false;
1832}
1833
1834static void atombios_crtc_disable(struct drm_crtc *crtc)
1835{
1836 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1837 struct drm_device *dev = crtc->dev;
1838 struct radeon_device *rdev = dev->dev_private;
1839 struct radeon_atom_ss ss;
1840 int i;
1841
1842 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1843 if (ASIC_IS_DCE6(rdev))
1844 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1845
1846 for (i = 0; i < rdev->num_crtc; i++) {
1847 if (rdev->mode_info.crtcs[i] &&
1848 rdev->mode_info.crtcs[i]->enabled &&
1849 i != radeon_crtc->crtc_id &&
1850 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1851
1852
1853
1854 goto done;
1855 }
1856 }
1857
1858 switch (radeon_crtc->pll_id) {
1859 case ATOM_PPLL1:
1860 case ATOM_PPLL2:
1861
1862 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1863 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1864 break;
1865 case ATOM_PPLL0:
1866
1867 if (ASIC_IS_DCE61(rdev))
1868 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1869 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1870 break;
1871 default:
1872 break;
1873 }
1874done:
1875 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1876 radeon_crtc->adjusted_clock = 0;
1877 radeon_crtc->encoder = NULL;
1878 radeon_crtc->connector = NULL;
1879}
1880
1881static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1882 .dpms = atombios_crtc_dpms,
1883 .mode_fixup = atombios_crtc_mode_fixup,
1884 .mode_set = atombios_crtc_mode_set,
1885 .mode_set_base = atombios_crtc_set_base,
1886 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1887 .prepare = atombios_crtc_prepare,
1888 .commit = atombios_crtc_commit,
1889 .load_lut = radeon_crtc_load_lut,
1890 .disable = atombios_crtc_disable,
1891};
1892
1893void radeon_atombios_init_crtc(struct drm_device *dev,
1894 struct radeon_crtc *radeon_crtc)
1895{
1896 struct radeon_device *rdev = dev->dev_private;
1897
1898 if (ASIC_IS_DCE4(rdev)) {
1899 switch (radeon_crtc->crtc_id) {
1900 case 0:
1901 default:
1902 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1903 break;
1904 case 1:
1905 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1906 break;
1907 case 2:
1908 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1909 break;
1910 case 3:
1911 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1912 break;
1913 case 4:
1914 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1915 break;
1916 case 5:
1917 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1918 break;
1919 }
1920 } else {
1921 if (radeon_crtc->crtc_id == 1)
1922 radeon_crtc->crtc_offset =
1923 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1924 else
1925 radeon_crtc->crtc_offset = 0;
1926 }
1927 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1928 radeon_crtc->adjusted_clock = 0;
1929 radeon_crtc->encoder = NULL;
1930 radeon_crtc->connector = NULL;
1931 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1932}
1933
