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33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/delay.h>
37#include <linux/string.h>
38#include <linux/slab.h>
39
40#include "dvb_frontend.h"
41#include "mt352_priv.h"
42#include "mt352.h"
43
44struct mt352_state {
45 struct i2c_adapter* i2c;
46 struct dvb_frontend frontend;
47
48
49 struct mt352_config config;
50};
51
52static int debug;
53#define dprintk(args...) \
54 do { \
55 if (debug) printk(KERN_DEBUG "mt352: " args); \
56 } while (0)
57
58static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
59{
60 struct mt352_state* state = fe->demodulator_priv;
61 u8 buf[2] = { reg, val };
62 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
63 .buf = buf, .len = 2 };
64 int err = i2c_transfer(state->i2c, &msg, 1);
65 if (err != 1) {
66 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
67 return err;
68 }
69 return 0;
70}
71
72static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
73{
74 int err,i;
75 for (i=0; i < ilen-1; i++)
76 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
77 return err;
78
79 return 0;
80}
81
82static int mt352_read_register(struct mt352_state* state, u8 reg)
83{
84 int ret;
85 u8 b0 [] = { reg };
86 u8 b1 [] = { 0 };
87 struct i2c_msg msg [] = { { .addr = state->config.demod_address,
88 .flags = 0,
89 .buf = b0, .len = 1 },
90 { .addr = state->config.demod_address,
91 .flags = I2C_M_RD,
92 .buf = b1, .len = 1 } };
93
94 ret = i2c_transfer(state->i2c, msg, 2);
95
96 if (ret != 2) {
97 printk("%s: readreg error (reg=%d, ret==%i)\n",
98 __func__, reg, ret);
99 return ret;
100 }
101
102 return b1[0];
103}
104
105static int mt352_sleep(struct dvb_frontend* fe)
106{
107 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
108
109 _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
110 return 0;
111}
112
113static void mt352_calc_nominal_rate(struct mt352_state* state,
114 u32 bandwidth,
115 unsigned char *buf)
116{
117 u32 adc_clock = 20480;
118 u32 bw,value;
119
120 switch (bandwidth) {
121 case 6000000:
122 bw = 6;
123 break;
124 case 7000000:
125 bw = 7;
126 break;
127 case 8000000:
128 default:
129 bw = 8;
130 break;
131 }
132 if (state->config.adc_clock)
133 adc_clock = state->config.adc_clock;
134
135 value = 64 * bw * (1<<16) / (7 * 8);
136 value = value * 1000 / adc_clock;
137 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
138 __func__, bw, adc_clock, value);
139 buf[0] = msb(value);
140 buf[1] = lsb(value);
141}
142
143static void mt352_calc_input_freq(struct mt352_state* state,
144 unsigned char *buf)
145{
146 int adc_clock = 20480;
147 int if2 = 36167;
148 int ife,value;
149
150 if (state->config.adc_clock)
151 adc_clock = state->config.adc_clock;
152 if (state->config.if2)
153 if2 = state->config.if2;
154
155 if (adc_clock >= if2 * 2)
156 ife = if2;
157 else {
158 ife = adc_clock - (if2 % adc_clock);
159 if (ife > adc_clock / 2)
160 ife = adc_clock - ife;
161 }
162 value = -16374 * ife / adc_clock;
163 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
164 __func__, if2, ife, adc_clock, value, value & 0x3fff);
165 buf[0] = msb(value);
166 buf[1] = lsb(value);
167}
168
169static int mt352_set_parameters(struct dvb_frontend *fe)
170{
171 struct dtv_frontend_properties *op = &fe->dtv_property_cache;
172 struct mt352_state* state = fe->demodulator_priv;
173 unsigned char buf[13];
174 static unsigned char tuner_go[] = { 0x5d, 0x01 };
175 static unsigned char fsm_go[] = { 0x5e, 0x01 };
176 unsigned int tps = 0;
177
178 switch (op->code_rate_HP) {
179 case FEC_2_3:
180 tps |= (1 << 7);
181 break;
182 case FEC_3_4:
183 tps |= (2 << 7);
184 break;
185 case FEC_5_6:
186 tps |= (3 << 7);
187 break;
188 case FEC_7_8:
189 tps |= (4 << 7);
190 break;
191 case FEC_1_2:
192 case FEC_AUTO:
193 break;
194 default:
195 return -EINVAL;
196 }
197
198 switch (op->code_rate_LP) {
199 case FEC_2_3:
200 tps |= (1 << 4);
201 break;
202 case FEC_3_4:
203 tps |= (2 << 4);
204 break;
205 case FEC_5_6:
206 tps |= (3 << 4);
207 break;
208 case FEC_7_8:
209 tps |= (4 << 4);
210 break;
211 case FEC_1_2:
212 case FEC_AUTO:
213 break;
214 case FEC_NONE:
215 if (op->hierarchy == HIERARCHY_AUTO ||
216 op->hierarchy == HIERARCHY_NONE)
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 switch (op->modulation) {
223 case QPSK:
224 break;
225 case QAM_AUTO:
226 case QAM_16:
227 tps |= (1 << 13);
228 break;
229 case QAM_64:
230 tps |= (2 << 13);
231 break;
232 default:
233 return -EINVAL;
234 }
235
236 switch (op->transmission_mode) {
237 case TRANSMISSION_MODE_2K:
238 case TRANSMISSION_MODE_AUTO:
239 break;
240 case TRANSMISSION_MODE_8K:
241 tps |= (1 << 0);
242 break;
243 default:
244 return -EINVAL;
245 }
246
247 switch (op->guard_interval) {
248 case GUARD_INTERVAL_1_32:
249 case GUARD_INTERVAL_AUTO:
250 break;
251 case GUARD_INTERVAL_1_16:
252 tps |= (1 << 2);
253 break;
254 case GUARD_INTERVAL_1_8:
255 tps |= (2 << 2);
256 break;
257 case GUARD_INTERVAL_1_4:
258 tps |= (3 << 2);
259 break;
260 default:
261 return -EINVAL;
262 }
263
264 switch (op->hierarchy) {
265 case HIERARCHY_AUTO:
266 case HIERARCHY_NONE:
267 break;
268 case HIERARCHY_1:
269 tps |= (1 << 10);
270 break;
271 case HIERARCHY_2:
272 tps |= (2 << 10);
273 break;
274 case HIERARCHY_4:
275 tps |= (3 << 10);
276 break;
277 default:
278 return -EINVAL;
279 }
280
281
282 buf[0] = TPS_GIVEN_1;
283
284 buf[1] = msb(tps);
285 buf[2] = lsb(tps);
286
287 buf[3] = 0x50;
288
289
290 mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
291 mt352_calc_input_freq(state, buf+6);
292
293 if (state->config.no_tuner) {
294 if (fe->ops.tuner_ops.set_params) {
295 fe->ops.tuner_ops.set_params(fe);
296 if (fe->ops.i2c_gate_ctrl)
297 fe->ops.i2c_gate_ctrl(fe, 0);
298 }
299
300 _mt352_write(fe, buf, 8);
301 _mt352_write(fe, fsm_go, 2);
302 } else {
303 if (fe->ops.tuner_ops.calc_regs) {
304 fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
305 buf[8] <<= 1;
306 _mt352_write(fe, buf, sizeof(buf));
307 _mt352_write(fe, tuner_go, 2);
308 }
309 }
310
311 return 0;
312}
313
314static int mt352_get_parameters(struct dvb_frontend* fe)
315{
316 struct dtv_frontend_properties *op = &fe->dtv_property_cache;
317 struct mt352_state* state = fe->demodulator_priv;
318 u16 tps;
319 u16 div;
320 u8 trl;
321 static const u8 tps_fec_to_api[8] =
322 {
323 FEC_1_2,
324 FEC_2_3,
325 FEC_3_4,
326 FEC_5_6,
327 FEC_7_8,
328 FEC_AUTO,
329 FEC_AUTO,
330 FEC_AUTO
331 };
332
333 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
334 return -EINVAL;
335
336
337
338
339 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
340 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
341 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
342
343 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
344 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
345
346 switch ( (tps >> 13) & 3)
347 {
348 case 0:
349 op->modulation = QPSK;
350 break;
351 case 1:
352 op->modulation = QAM_16;
353 break;
354 case 2:
355 op->modulation = QAM_64;
356 break;
357 default:
358 op->modulation = QAM_AUTO;
359 break;
360 }
361
362 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
363
364 switch ( (tps >> 2) & 3)
365 {
366 case 0:
367 op->guard_interval = GUARD_INTERVAL_1_32;
368 break;
369 case 1:
370 op->guard_interval = GUARD_INTERVAL_1_16;
371 break;
372 case 2:
373 op->guard_interval = GUARD_INTERVAL_1_8;
374 break;
375 case 3:
376 op->guard_interval = GUARD_INTERVAL_1_4;
377 break;
378 default:
379 op->guard_interval = GUARD_INTERVAL_AUTO;
380 break;
381 }
382
383 switch ( (tps >> 10) & 7)
384 {
385 case 0:
386 op->hierarchy = HIERARCHY_NONE;
387 break;
388 case 1:
389 op->hierarchy = HIERARCHY_1;
390 break;
391 case 2:
392 op->hierarchy = HIERARCHY_2;
393 break;
394 case 3:
395 op->hierarchy = HIERARCHY_4;
396 break;
397 default:
398 op->hierarchy = HIERARCHY_AUTO;
399 break;
400 }
401
402 op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
403
404 if (trl == 0x72)
405 op->bandwidth_hz = 8000000;
406 else if (trl == 0x64)
407 op->bandwidth_hz = 7000000;
408 else
409 op->bandwidth_hz = 6000000;
410
411
412 if (mt352_read_register(state, STATUS_2) & 0x02)
413 op->inversion = INVERSION_OFF;
414 else
415 op->inversion = INVERSION_ON;
416
417 return 0;
418}
419
420static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
421{
422 struct mt352_state* state = fe->demodulator_priv;
423 int s0, s1, s3;
424
425
426
427
428
429
430
431
432
433
434
435
436
437 if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
438 return -EREMOTEIO;
439 if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
440 return -EREMOTEIO;
441 if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
442 return -EREMOTEIO;
443
444 *status = 0;
445 if (s0 & (1 << 4))
446 *status |= FE_HAS_CARRIER;
447 if (s0 & (1 << 1))
448 *status |= FE_HAS_VITERBI;
449 if (s0 & (1 << 5))
450 *status |= FE_HAS_LOCK;
451 if (s1 & (1 << 1))
452 *status |= FE_HAS_SYNC;
453 if (s3 & (1 << 6))
454 *status |= FE_HAS_SIGNAL;
455
456 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
457 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
458 *status &= ~FE_HAS_LOCK;
459
460 return 0;
461}
462
463static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
464{
465 struct mt352_state* state = fe->demodulator_priv;
466
467 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
468 (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
469 (mt352_read_register (state, RS_ERR_CNT_0));
470
471 return 0;
472}
473
474static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
475{
476 struct mt352_state* state = fe->demodulator_priv;
477
478
479 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
480 (mt352_read_register(state, AGC_GAIN_0) << 4);
481
482
483 *strength = ~signal;
484 return 0;
485}
486
487static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
488{
489 struct mt352_state* state = fe->demodulator_priv;
490
491 u8 _snr = mt352_read_register (state, SNR);
492 *snr = (_snr << 8) | _snr;
493
494 return 0;
495}
496
497static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
498{
499 struct mt352_state* state = fe->demodulator_priv;
500
501 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
502 (mt352_read_register (state, RS_UBC_0));
503
504 return 0;
505}
506
507static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
508{
509 fe_tune_settings->min_delay_ms = 800;
510 fe_tune_settings->step_size = 0;
511 fe_tune_settings->max_drift = 0;
512
513 return 0;
514}
515
516static int mt352_init(struct dvb_frontend* fe)
517{
518 struct mt352_state* state = fe->demodulator_priv;
519
520 static u8 mt352_reset_attach [] = { RESET, 0xC0 };
521
522 dprintk("%s: hello\n",__func__);
523
524 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
525 (mt352_read_register(state, CONFIG) & 0x20) == 0) {
526
527
528 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
529 return state->config.demod_init(fe);
530 }
531
532 return 0;
533}
534
535static void mt352_release(struct dvb_frontend* fe)
536{
537 struct mt352_state* state = fe->demodulator_priv;
538 kfree(state);
539}
540
541static struct dvb_frontend_ops mt352_ops;
542
543struct dvb_frontend* mt352_attach(const struct mt352_config* config,
544 struct i2c_adapter* i2c)
545{
546 struct mt352_state* state = NULL;
547
548
549 state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
550 if (state == NULL) goto error;
551
552
553 state->i2c = i2c;
554 memcpy(&state->config,config,sizeof(struct mt352_config));
555
556
557 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
558
559
560 memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
561 state->frontend.demodulator_priv = state;
562 return &state->frontend;
563
564error:
565 kfree(state);
566 return NULL;
567}
568
569static struct dvb_frontend_ops mt352_ops = {
570 .delsys = { SYS_DVBT },
571 .info = {
572 .name = "Zarlink MT352 DVB-T",
573 .frequency_min = 174000000,
574 .frequency_max = 862000000,
575 .frequency_stepsize = 166667,
576 .frequency_tolerance = 0,
577 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
578 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
579 FE_CAN_FEC_AUTO |
580 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
581 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
582 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
583 FE_CAN_MUTE_TS
584 },
585
586 .release = mt352_release,
587
588 .init = mt352_init,
589 .sleep = mt352_sleep,
590 .write = _mt352_write,
591
592 .set_frontend = mt352_set_parameters,
593 .get_frontend = mt352_get_parameters,
594 .get_tune_settings = mt352_get_tune_settings,
595
596 .read_status = mt352_read_status,
597 .read_ber = mt352_read_ber,
598 .read_signal_strength = mt352_read_signal_strength,
599 .read_snr = mt352_read_snr,
600 .read_ucblocks = mt352_read_ucblocks,
601};
602
603module_param(debug, int, 0644);
604MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
605
606MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
607MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
608MODULE_LICENSE("GPL");
609
610EXPORT_SYMBOL(mt352_attach);
611
