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26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <asm/io.h>
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/map.h>
33#include <linux/mtd/concat.h>
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56
57#define REPROGRAM_PAR
58
59
60
61#ifdef REPROGRAM_PAR
62
63
64#define WINDOW_ADDR_0 0x08800000
65#define WINDOW_ADDR_1 0x09000000
66#define WINDOW_ADDR_2 0x09800000
67
68
69#define WINDOW_ADDR_0_BIOS 0x08400000
70#define WINDOW_ADDR_1_BIOS 0x08c00000
71#define WINDOW_ADDR_2_BIOS 0x09400000
72
73#else
74
75#define WINDOW_ADDR_0 0x08400000
76#define WINDOW_ADDR_1 0x08C00000
77#define WINDOW_ADDR_2 0x09400000
78
79#endif
80
81#define WINDOW_SIZE_0 0x00800000
82#define WINDOW_SIZE_1 0x00800000
83#define WINDOW_SIZE_2 0x00080000
84
85
86static struct map_info sc520cdp_map[] = {
87 {
88 .name = "SC520CDP Flash Bank #0",
89 .size = WINDOW_SIZE_0,
90 .bankwidth = 4,
91 .phys = WINDOW_ADDR_0
92 },
93 {
94 .name = "SC520CDP Flash Bank #1",
95 .size = WINDOW_SIZE_1,
96 .bankwidth = 4,
97 .phys = WINDOW_ADDR_1
98 },
99 {
100 .name = "SC520CDP DIL Flash",
101 .size = WINDOW_SIZE_2,
102 .bankwidth = 1,
103 .phys = WINDOW_ADDR_2
104 },
105};
106
107#define NUM_FLASH_BANKS ARRAY_SIZE(sc520cdp_map)
108
109static struct mtd_info *mymtd[NUM_FLASH_BANKS];
110static struct mtd_info *merged_mtd;
111
112#ifdef REPROGRAM_PAR
113
114
115
116
117
118
119#define SC520_MMCR_BASE 0xFFFEF000
120#define SC520_MMCR_EXTENT 0x1000
121#define SC520_PAR(x) ((0x88/sizeof(unsigned long)) + (x))
122#define NUM_SC520_PAR 16
123
124
125
126
127
128
129#define SC520_PAR_BOOTCS (0x4<<29)
130#define SC520_PAR_ROMCS0 (0x5<<29)
131#define SC520_PAR_ROMCS1 (0x6<<29)
132#define SC520_PAR_TRGDEV (0x7<<29)
133
134
135
136
137
138#define SC520_PAR_WRPROT (1<<26)
139#define SC520_PAR_NOCACHE (1<<27)
140#define SC520_PAR_NOEXEC (1<<28)
141
142
143
144
145
146#define SC520_PAR_PG_SIZ4 (0<<25)
147#define SC520_PAR_PG_SIZ64 (1<<25)
148
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150
151
152
153#define SC520_PAR_ENTRY(trgdev, address, size) \
154 ((trgdev) | SC520_PAR_NOCACHE | SC520_PAR_PG_SIZ64 | \
155 (address) >> 16 | (((size) >> 16) - 1) << 14)
156
157struct sc520_par_table
158{
159 unsigned long trgdev;
160 unsigned long new_par;
161 unsigned long default_address;
162};
163
164static const struct sc520_par_table par_table[NUM_FLASH_BANKS] =
165{
166 {
167 SC520_PAR_ROMCS0,
168 SC520_PAR_ENTRY(SC520_PAR_ROMCS0, WINDOW_ADDR_0, WINDOW_SIZE_0),
169 WINDOW_ADDR_0_BIOS
170 },
171 {
172 SC520_PAR_ROMCS1,
173 SC520_PAR_ENTRY(SC520_PAR_ROMCS1, WINDOW_ADDR_1, WINDOW_SIZE_1),
174 WINDOW_ADDR_1_BIOS
175 },
176 {
177 SC520_PAR_BOOTCS,
178 SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2),
179 WINDOW_ADDR_2_BIOS
180 }
181};
182
183
184static void sc520cdp_setup_par(void)
185{
186 volatile unsigned long __iomem *mmcr;
187 unsigned long mmcr_val;
188 int i, j;
189
190
191 mmcr = ioremap_nocache(SC520_MMCR_BASE, SC520_MMCR_EXTENT);
192 if(!mmcr) {
193
194 for(i = 0; i < NUM_FLASH_BANKS; i++)
195 sc520cdp_map[i].phys = par_table[i].default_address;
196 return;
197 }
198
199
200
201
202
203
204 for(i = 0; i < NUM_FLASH_BANKS; i++) {
205 for(j = 0; j < NUM_SC520_PAR; j++) {
206 mmcr_val = mmcr[SC520_PAR(j)];
207
208 if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev)
209 {
210 mmcr[SC520_PAR(j)] = par_table[i].new_par;
211 break;
212 }
213 }
214 if(j == NUM_SC520_PAR)
215 {
216 printk(KERN_NOTICE "Could not find PAR responsible for %s\n",
217 sc520cdp_map[i].name);
218 printk(KERN_NOTICE "Trying default address 0x%lx\n",
219 par_table[i].default_address);
220 sc520cdp_map[i].phys = par_table[i].default_address;
221 }
222 }
223 iounmap(mmcr);
224}
225#endif
226
227
228static int __init init_sc520cdp(void)
229{
230 int i, devices_found = 0;
231
232#ifdef REPROGRAM_PAR
233
234 sc520cdp_setup_par();
235#endif
236
237 for (i = 0; i < NUM_FLASH_BANKS; i++) {
238 printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",
239 (unsigned long long)sc520cdp_map[i].size,
240 (unsigned long long)sc520cdp_map[i].phys);
241
242 sc520cdp_map[i].virt = ioremap_nocache(sc520cdp_map[i].phys, sc520cdp_map[i].size);
243
244 if (!sc520cdp_map[i].virt) {
245 printk("Failed to ioremap_nocache\n");
246 return -EIO;
247 }
248
249 simple_map_init(&sc520cdp_map[i]);
250
251 mymtd[i] = do_map_probe("cfi_probe", &sc520cdp_map[i]);
252 if(!mymtd[i])
253 mymtd[i] = do_map_probe("jedec_probe", &sc520cdp_map[i]);
254 if(!mymtd[i])
255 mymtd[i] = do_map_probe("map_rom", &sc520cdp_map[i]);
256
257 if (mymtd[i]) {
258 mymtd[i]->owner = THIS_MODULE;
259 ++devices_found;
260 }
261 else {
262 iounmap(sc520cdp_map[i].virt);
263 }
264 }
265 if(devices_found >= 2) {
266
267 merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");
268 if(merged_mtd)
269 mtd_device_register(merged_mtd, NULL, 0);
270 }
271 if(devices_found == 3)
272 mtd_device_register(mymtd[2], NULL, 0);
273 return(devices_found ? 0 : -ENXIO);
274}
275
276static void __exit cleanup_sc520cdp(void)
277{
278 int i;
279
280 if (merged_mtd) {
281 mtd_device_unregister(merged_mtd);
282 mtd_concat_destroy(merged_mtd);
283 }
284 if (mymtd[2])
285 mtd_device_unregister(mymtd[2]);
286
287 for (i = 0; i < NUM_FLASH_BANKS; i++) {
288 if (mymtd[i])
289 map_destroy(mymtd[i]);
290 if (sc520cdp_map[i].virt) {
291 iounmap(sc520cdp_map[i].virt);
292 sc520cdp_map[i].virt = NULL;
293 }
294 }
295}
296
297module_init(init_sc520cdp);
298module_exit(cleanup_sc520cdp);
299
300MODULE_LICENSE("GPL");
301MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
302MODULE_DESCRIPTION("MTD map driver for AMD SC520 Customer Development Platform");
303