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17#ifndef BNX2X_LINK_H
18#define BNX2X_LINK_H
19
20
21
22
23
24
25#define DEFAULT_PHY_DEV_ADDR 3
26#define E2_DEFAULT_PHY_DEV_ADDR 5
27
28
29
30#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
31#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
32#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
33#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
34#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
35
36#define NET_SERDES_IF_XFI 1
37#define NET_SERDES_IF_SFI 2
38#define NET_SERDES_IF_KR 3
39#define NET_SERDES_IF_DXGXS 4
40
41#define SPEED_AUTO_NEG 0
42#define SPEED_20000 20000
43
44#define SFP_EEPROM_PAGE_SIZE 16
45#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
46#define SFP_EEPROM_VENDOR_NAME_SIZE 16
47#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
48#define SFP_EEPROM_VENDOR_OUI_SIZE 3
49#define SFP_EEPROM_PART_NO_ADDR 0x28
50#define SFP_EEPROM_PART_NO_SIZE 16
51#define SFP_EEPROM_REVISION_ADDR 0x38
52#define SFP_EEPROM_REVISION_SIZE 4
53#define SFP_EEPROM_SERIAL_ADDR 0x44
54#define SFP_EEPROM_SERIAL_SIZE 16
55#define SFP_EEPROM_DATE_ADDR 0x54
56#define SFP_EEPROM_DATE_SIZE 6
57#define PWR_FLT_ERR_MSG_LEN 250
58
59#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
60 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
61#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
62 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
63 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
64#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
65 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
66
67
68#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
69
70#define SINGLE_MEDIA(params) (params->num_phys == 2)
71
72#define DUAL_MEDIA(params) (params->num_phys == 3)
73
74#define FW_PARAM_PHY_ADDR_MASK 0x000000FF
75#define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
76#define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
77#define FW_PARAM_MDIO_CTRL_OFFSET 16
78#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
79 FW_PARAM_PHY_ADDR_MASK)
80#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
81 FW_PARAM_PHY_TYPE_MASK)
82#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
83 FW_PARAM_MDIO_CTRL_MASK) >> \
84 FW_PARAM_MDIO_CTRL_OFFSET)
85#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
86 (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
87
88
89#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
90#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
91
92#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
93
94#define BMAC_CONTROL_RX_ENABLE 2
95
96
97
98#define INT_PHY 0
99#define EXT_PHY1 1
100#define EXT_PHY2 2
101#define MAX_PHYS 3
102
103
104#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
105#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
106 0 : (_phy_idx - 1))
107
108
109
110
111struct link_vars;
112struct link_params;
113struct bnx2x_phy;
114
115typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
116 struct link_vars *vars);
117typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
118 struct link_vars *vars);
119typedef void (*link_reset_t)(struct bnx2x_phy *phy,
120 struct link_params *params);
121typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
122 struct link_params *params);
123typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
124typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
125typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
126 struct link_params *params, u8 mode);
127typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
128 struct link_params *params, u32 action);
129struct bnx2x_reg_set {
130 u8 devad;
131 u16 reg;
132 u16 val;
133};
134
135struct bnx2x_phy {
136 u32 type;
137
138
139 u8 addr;
140 u8 def_md_devad;
141 u16 flags;
142
143#define FLAGS_NOC (1<<1)
144
145#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
146
147#define FLAGS_INIT_XGXS_FIRST (1<<3)
148#define FLAGS_WC_DUAL_MODE (1<<4)
149#define FLAGS_4_PORT_MODE (1<<5)
150#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
151#define FLAGS_SFP_NOT_APPROVED (1<<7)
152#define FLAGS_MDC_MDIO_WA (1<<8)
153#define FLAGS_DUMMY_READ (1<<9)
154#define FLAGS_MDC_MDIO_WA_B0 (1<<10)
155#define FLAGS_TX_ERROR_CHECK (1<<12)
156#define FLAGS_EEE (1<<13)
157#define FLAGS_MDC_MDIO_WA_G (1<<15)
158
159
160 u16 rx_preemphasis[4];
161
162
163 u16 tx_preemphasis[4];
164
165
166 u32 mdio_ctrl;
167
168 u32 supported;
169
170 u32 media_type;
171#define ETH_PHY_UNSPECIFIED 0x0
172#define ETH_PHY_SFPP_10G_FIBER 0x1
173#define ETH_PHY_XFP_FIBER 0x2
174#define ETH_PHY_DA_TWINAX 0x3
175#define ETH_PHY_BASE_T 0x4
176#define ETH_PHY_SFP_1G_FIBER 0x5
177#define ETH_PHY_KR 0xf0
178#define ETH_PHY_CX4 0xf1
179#define ETH_PHY_NOT_PRESENT 0xff
180
181
182 u32 ver_addr;
183
184 u16 req_flow_ctrl;
185
186 u16 req_line_speed;
187
188 u32 speed_cap_mask;
189
190 u16 req_duplex;
191 u16 rsrv;
192
193
194 config_init_t config_init;
195
196
197 read_status_t read_status;
198
199
200 link_reset_t link_reset;
201
202
203 config_loopback_t config_loopback;
204
205
206 format_fw_ver_t format_fw_ver;
207
208
209 hw_reset_t hw_reset;
210
211
212 set_link_led_t set_link_led;
213
214
215 phy_specific_func_t phy_specific_func;
216#define DISABLE_TX 1
217#define ENABLE_TX 2
218#define PHY_INIT 3
219};
220
221
222struct link_params {
223
224 u8 port;
225
226
227 u8 loopback_mode;
228#define LOOPBACK_NONE 0
229#define LOOPBACK_EMAC 1
230#define LOOPBACK_BMAC 2
231#define LOOPBACK_XGXS 3
232#define LOOPBACK_EXT_PHY 4
233#define LOOPBACK_EXT 5
234#define LOOPBACK_UMAC 6
235#define LOOPBACK_XMAC 7
236
237
238 u8 mac_addr[6];
239
240 u16 req_duplex[LINK_CONFIG_SIZE];
241 u16 req_flow_ctrl[LINK_CONFIG_SIZE];
242
243 u16 req_line_speed[LINK_CONFIG_SIZE];
244
245
246 u32 shmem_base;
247 u32 shmem2_base;
248 u32 speed_cap_mask[LINK_CONFIG_SIZE];
249 u32 switch_cfg;
250#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
251#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
252#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
253
254 u32 lane_config;
255
256
257 u32 chip_id;
258
259
260 u32 feature_config_flags;
261#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
262#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
263#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
264#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
265#define FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
266#define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
267#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
268#define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
269#define FEATURE_CONFIG_MT_SUPPORT (1<<13)
270#define FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
271
272
273 struct bnx2x_phy phy[MAX_PHYS];
274
275
276 u8 num_phys;
277
278 u8 rsrv;
279
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290
291
292 u32 eee_mode;
293#define EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
294#define EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
295#define EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
296#define EEE_MODE_NVRAM_MASK (0x3)
297#define EEE_MODE_TIMER_MASK (0xfffff)
298#define EEE_MODE_OUTPUT_TIME (1<<28)
299#define EEE_MODE_OVERRIDE_NVRAM (1<<29)
300#define EEE_MODE_ENABLE_LPI (1<<30)
301#define EEE_MODE_ADV_LPI (1<<31)
302
303 u16 hw_led_mode;
304 u32 multi_phy_config;
305
306
307 struct bnx2x *bp;
308 u16 req_fc_auto_adv;
309
310 u16 link_flags;
311#define LINK_FLAGS_INT_DISABLED (1<<0)
312#define PHY_INITIALIZED (1<<1)
313 u32 lfa_base;
314};
315
316
317struct link_vars {
318 u8 phy_flags;
319#define PHY_XGXS_FLAG (1<<0)
320#define PHY_SGMII_FLAG (1<<1)
321#define PHY_PHYSICAL_LINK_FLAG (1<<2)
322#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
323#define PHY_OVER_CURRENT_FLAG (1<<4)
324#define PHY_SFP_TX_FAULT_FLAG (1<<5)
325
326 u8 mac_type;
327#define MAC_TYPE_NONE 0
328#define MAC_TYPE_EMAC 1
329#define MAC_TYPE_BMAC 2
330#define MAC_TYPE_UMAC 3
331#define MAC_TYPE_XMAC 4
332
333 u8 phy_link_up;
334 u8 link_up;
335
336 u16 line_speed;
337 u16 duplex;
338
339 u16 flow_ctrl;
340 u16 ieee_fc;
341
342
343 u32 link_status;
344 u32 eee_status;
345 u8 fault_detected;
346 u8 check_kr2_recovery_cnt;
347#define CHECK_KR2_RECOVERY_CNT 5
348 u16 periodic_flags;
349#define PERIODIC_FLAGS_LINK_EVENT 0x0001
350
351 u32 aeu_int_mask;
352 u8 rx_tx_asic_rst;
353 u8 turn_to_run_wc_rt;
354 u16 rsrv2;
355
356 u32 link_attr_sync;
357};
358
359
360
361
362int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
363
364
365
366
367int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
368 u8 reset_ext_phy);
369int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
370
371int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
372
373
374
375
376
377int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
378 u8 devad, u16 reg, u16 *ret_val);
379
380int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
381 u8 devad, u16 reg, u16 val);
382
383
384
385void bnx2x_link_status_update(struct link_params *input,
386 struct link_vars *output);
387
388int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
389 u16 len);
390
391
392
393
394
395int bnx2x_set_led(struct link_params *params,
396 struct link_vars *vars, u8 mode, u32 speed);
397#define LED_MODE_OFF 0
398#define LED_MODE_ON 1
399#define LED_MODE_OPER 2
400#define LED_MODE_FRONT_PANEL_OFF 3
401
402
403
404void bnx2x_handle_module_detect_int(struct link_params *params);
405
406
407
408int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
409 u8 is_serdes);
410
411
412int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
413 u32 shmem2_base_path[], u32 chip_id);
414
415
416void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
417
418
419void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
420
421
422int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
423 struct link_params *params, u16 addr,
424 u8 byte_cnt, u8 *o_buf);
425
426void bnx2x_hw_reset_phy(struct link_params *params);
427
428
429u32 bnx2x_phy_selection(struct link_params *params);
430
431
432int bnx2x_phy_probe(struct link_params *params);
433
434
435u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
436 u32 shmem2_base, u8 port);
437
438
439void bnx2x_set_rx_filter(struct link_params *params, u8 en);
440
441
442
443
444#define DCBX_E2E3_MAX_NUM_COS (2)
445#define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
446#define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
447#define DCBX_E3B0_MAX_NUM_COS ( \
448 MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
449 DCBX_E3B0_MAX_NUM_COS_PORT1))
450
451#define DCBX_MAX_NUM_COS ( \
452 MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
453 DCBX_E2E3_MAX_NUM_COS))
454
455
456struct bnx2x_nig_brb_pfc_port_params {
457
458 u32 pause_enable;
459 u32 llfc_out_en;
460 u32 llfc_enable;
461 u32 pkt_priority_to_cos;
462 u8 num_of_rx_cos_priority_mask;
463 u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
464 u32 llfc_high_priority_classes;
465 u32 llfc_low_priority_classes;
466};
467
468
469
470struct bnx2x_ets_bw_params {
471 u8 bw;
472};
473
474struct bnx2x_ets_sp_params {
475
476
477
478
479 u8 pri;
480};
481
482enum bnx2x_cos_state {
483 bnx2x_cos_state_strict = 0,
484 bnx2x_cos_state_bw = 1,
485};
486
487struct bnx2x_ets_cos_params {
488 enum bnx2x_cos_state state ;
489 union {
490 struct bnx2x_ets_bw_params bw_params;
491 struct bnx2x_ets_sp_params sp_params;
492 } params;
493};
494
495struct bnx2x_ets_params {
496 u8 num_of_cos;
497 struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
498};
499
500
501
502
503int bnx2x_update_pfc(struct link_params *params,
504 struct link_vars *vars,
505 struct bnx2x_nig_brb_pfc_port_params *pfc_params);
506
507
508
509int bnx2x_ets_disabled(struct link_params *params,
510 struct link_vars *vars);
511
512
513void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
514 const u32 cos1_bw);
515
516
517int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
518
519
520
521int bnx2x_ets_e3b0_config(const struct link_params *params,
522 const struct link_vars *vars,
523 struct bnx2x_ets_params *ets_params);
524
525void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
526 u32 pfc_frames_sent[2],
527 u32 pfc_frames_received[2]);
528void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
529 u32 chip_id, u32 shmem_base, u32 shmem2_base,
530 u8 port);
531
532int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
533 struct link_params *params);
534
535void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
536
537int bnx2x_check_half_open_conn(struct link_params *params,
538 struct link_vars *vars, u8 notify);
539#endif
540