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18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/delay.h>
24#include <net/tcp.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27#include <linux/if_vlan.h>
28#include <linux/workqueue.h>
29#include <linux/interrupt.h>
30#include <linux/firmware.h>
31#include <linux/slab.h>
32#include <linux/u64_stats_sync.h>
33
34#include "be_hw.h"
35#include "be_roce.h"
36
37#define DRV_VER "4.6.62.0u"
38#define DRV_NAME "be2net"
39#define BE_NAME "Emulex BladeEngine2"
40#define BE3_NAME "Emulex BladeEngine3"
41#define OC_NAME "Emulex OneConnect"
42#define OC_NAME_BE OC_NAME "(be3)"
43#define OC_NAME_LANCER OC_NAME "(Lancer)"
44#define OC_NAME_SH OC_NAME "(Skyhawk)"
45#define DRV_DESC "Emulex OneConnect 10Gbps NIC Driver"
46
47#define BE_VENDOR_ID 0x19a2
48#define EMULEX_VENDOR_ID 0x10df
49#define BE_DEVICE_ID1 0x211
50#define BE_DEVICE_ID2 0x221
51#define OC_DEVICE_ID1 0x700
52#define OC_DEVICE_ID2 0x710
53#define OC_DEVICE_ID3 0xe220
54#define OC_DEVICE_ID4 0xe228
55#define OC_DEVICE_ID5 0x720
56#define OC_DEVICE_ID6 0x728
57#define OC_SUBSYS_DEVICE_ID1 0xE602
58#define OC_SUBSYS_DEVICE_ID2 0xE642
59#define OC_SUBSYS_DEVICE_ID3 0xE612
60#define OC_SUBSYS_DEVICE_ID4 0xE652
61
62static inline char *nic_name(struct pci_dev *pdev)
63{
64 switch (pdev->device) {
65 case OC_DEVICE_ID1:
66 return OC_NAME;
67 case OC_DEVICE_ID2:
68 return OC_NAME_BE;
69 case OC_DEVICE_ID3:
70 case OC_DEVICE_ID4:
71 return OC_NAME_LANCER;
72 case BE_DEVICE_ID2:
73 return BE3_NAME;
74 case OC_DEVICE_ID5:
75 case OC_DEVICE_ID6:
76 return OC_NAME_SH;
77 default:
78 return BE_NAME;
79 }
80}
81
82
83#define BE_HDR_LEN ((u16) 64)
84
85#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
86
87#define BE_MAX_JUMBO_FRAME_SIZE 9018
88#define BE_MIN_MTU 256
89
90#define BE_NUM_VLANS_SUPPORTED 64
91#define BE_MAX_EQD 96u
92#define BE_MAX_TX_FRAG_COUNT 30
93
94#define EVNT_Q_LEN 1024
95#define TX_Q_LEN 2048
96#define TX_CQ_LEN 1024
97#define RX_Q_LEN 1024
98#define RX_CQ_LEN 1024
99#define MCC_Q_LEN 128
100#define MCC_CQ_LEN 256
101
102#define BE3_MAX_RSS_QS 8
103#define BE2_MAX_RSS_QS 4
104#define MAX_RSS_QS BE3_MAX_RSS_QS
105#define MAX_RX_QS (MAX_RSS_QS + 1)
106
107#define MAX_TX_QS 8
108#define MAX_ROCE_EQS 5
109#define MAX_MSIX_VECTORS (MAX_RSS_QS + MAX_ROCE_EQS)
110#define BE_TX_BUDGET 256
111#define BE_NAPI_WEIGHT 64
112#define MAX_RX_POST BE_NAPI_WEIGHT
113#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
114
115#define MAX_VFS 30
116#define FW_VER_LEN 32
117
118struct be_dma_mem {
119 void *va;
120 dma_addr_t dma;
121 u32 size;
122};
123
124struct be_queue_info {
125 struct be_dma_mem dma_mem;
126 u16 len;
127 u16 entry_size;
128 u16 id;
129 u16 tail, head;
130 bool created;
131 atomic_t used;
132};
133
134static inline u32 MODULO(u16 val, u16 limit)
135{
136 BUG_ON(limit & (limit - 1));
137 return val & (limit - 1);
138}
139
140static inline void index_adv(u16 *index, u16 val, u16 limit)
141{
142 *index = MODULO((*index + val), limit);
143}
144
145static inline void index_inc(u16 *index, u16 limit)
146{
147 *index = MODULO((*index + 1), limit);
148}
149
150static inline void *queue_head_node(struct be_queue_info *q)
151{
152 return q->dma_mem.va + q->head * q->entry_size;
153}
154
155static inline void *queue_tail_node(struct be_queue_info *q)
156{
157 return q->dma_mem.va + q->tail * q->entry_size;
158}
159
160static inline void *queue_index_node(struct be_queue_info *q, u16 index)
161{
162 return q->dma_mem.va + index * q->entry_size;
163}
164
165static inline void queue_head_inc(struct be_queue_info *q)
166{
167 index_inc(&q->head, q->len);
168}
169
170static inline void index_dec(u16 *index, u16 limit)
171{
172 *index = MODULO((*index - 1), limit);
173}
174
175static inline void queue_tail_inc(struct be_queue_info *q)
176{
177 index_inc(&q->tail, q->len);
178}
179
180struct be_eq_obj {
181 struct be_queue_info q;
182 char desc[32];
183
184
185 bool enable_aic;
186 u32 min_eqd;
187 u32 max_eqd;
188 u32 eqd;
189 u32 cur_eqd;
190
191 u8 idx;
192 u16 tx_budget;
193 u16 spurious_intr;
194 struct napi_struct napi;
195 struct be_adapter *adapter;
196} ____cacheline_aligned_in_smp;
197
198struct be_mcc_obj {
199 struct be_queue_info q;
200 struct be_queue_info cq;
201 bool rearm_cq;
202};
203
204struct be_tx_stats {
205 u64 tx_bytes;
206 u64 tx_pkts;
207 u64 tx_reqs;
208 u64 tx_wrbs;
209 u64 tx_compl;
210 ulong tx_jiffies;
211 u32 tx_stops;
212 struct u64_stats_sync sync;
213 struct u64_stats_sync sync_compl;
214};
215
216struct be_tx_obj {
217 struct be_queue_info q;
218 struct be_queue_info cq;
219
220 struct sk_buff *sent_skb_list[TX_Q_LEN];
221 struct be_tx_stats stats;
222} ____cacheline_aligned_in_smp;
223
224
225struct be_rx_page_info {
226 struct page *page;
227 DEFINE_DMA_UNMAP_ADDR(bus);
228 u16 page_offset;
229 bool last_page_user;
230};
231
232struct be_rx_stats {
233 u64 rx_bytes;
234 u64 rx_pkts;
235 u64 rx_pkts_prev;
236 ulong rx_jiffies;
237 u32 rx_drops_no_skbs;
238 u32 rx_drops_no_frags;
239 u32 rx_post_fail;
240 u32 rx_compl;
241 u32 rx_mcast_pkts;
242 u32 rx_compl_err;
243 u32 rx_pps;
244 struct u64_stats_sync sync;
245};
246
247struct be_rx_compl_info {
248 u32 rss_hash;
249 u16 vlan_tag;
250 u16 pkt_size;
251 u16 rxq_idx;
252 u16 port;
253 u8 vlanf;
254 u8 num_rcvd;
255 u8 err;
256 u8 ipf;
257 u8 tcpf;
258 u8 udpf;
259 u8 ip_csum;
260 u8 l4_csum;
261 u8 ipv6;
262 u8 vtm;
263 u8 pkt_type;
264};
265
266struct be_rx_obj {
267 struct be_adapter *adapter;
268 struct be_queue_info q;
269 struct be_queue_info cq;
270 struct be_rx_compl_info rxcp;
271 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
272 struct be_rx_stats stats;
273 u8 rss_id;
274 bool rx_post_starved;
275} ____cacheline_aligned_in_smp;
276
277struct be_drv_stats {
278 u32 be_on_die_temperature;
279 u32 eth_red_drops;
280 u32 rx_drops_no_pbuf;
281 u32 rx_drops_no_txpb;
282 u32 rx_drops_no_erx_descr;
283 u32 rx_drops_no_tpre_descr;
284 u32 rx_drops_too_many_frags;
285 u32 forwarded_packets;
286 u32 rx_drops_mtu;
287 u32 rx_crc_errors;
288 u32 rx_alignment_symbol_errors;
289 u32 rx_pause_frames;
290 u32 rx_priority_pause_frames;
291 u32 rx_control_frames;
292 u32 rx_in_range_errors;
293 u32 rx_out_range_errors;
294 u32 rx_frame_too_long;
295 u32 rx_address_mismatch_drops;
296 u32 rx_dropped_too_small;
297 u32 rx_dropped_too_short;
298 u32 rx_dropped_header_too_small;
299 u32 rx_dropped_tcp_length;
300 u32 rx_dropped_runt;
301 u32 rx_ip_checksum_errs;
302 u32 rx_tcp_checksum_errs;
303 u32 rx_udp_checksum_errs;
304 u32 tx_pauseframes;
305 u32 tx_priority_pauseframes;
306 u32 tx_controlframes;
307 u32 rxpp_fifo_overflow_drop;
308 u32 rx_input_fifo_overflow_drop;
309 u32 pmem_fifo_overflow_drop;
310 u32 jabber_events;
311};
312
313struct be_vf_cfg {
314 unsigned char mac_addr[ETH_ALEN];
315 int if_handle;
316 int pmac_id;
317 u16 def_vid;
318 u16 vlan_tag;
319 u32 tx_rate;
320};
321
322enum vf_state {
323 ENABLED = 0,
324 ASSIGNED = 1
325};
326
327#define BE_FLAGS_LINK_STATUS_INIT 1
328#define BE_FLAGS_WORKER_SCHEDULED (1 << 3)
329#define BE_UC_PMAC_COUNT 30
330#define BE_VF_UC_PMAC_COUNT 2
331
332struct phy_info {
333 u8 transceiver;
334 u8 autoneg;
335 u8 fc_autoneg;
336 u8 port_type;
337 u16 phy_type;
338 u16 interface_type;
339 u32 misc_params;
340 u16 auto_speeds_supported;
341 u16 fixed_speeds_supported;
342 int link_speed;
343 u32 dac_cable_len;
344 u32 advertising;
345 u32 supported;
346};
347
348struct be_adapter {
349 struct pci_dev *pdev;
350 struct net_device *netdev;
351
352 u8 __iomem *csr;
353 u8 __iomem *db;
354
355 struct mutex mbox_lock;
356 struct be_dma_mem mbox_mem;
357
358
359 struct be_dma_mem mbox_mem_alloced;
360
361 struct be_mcc_obj mcc_obj;
362 spinlock_t mcc_lock;
363 spinlock_t mcc_cq_lock;
364
365 u32 num_msix_vec;
366 u32 num_evt_qs;
367 struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
368 struct msix_entry msix_entries[MAX_MSIX_VECTORS];
369 bool isr_registered;
370
371
372 u32 num_tx_qs;
373 struct be_tx_obj tx_obj[MAX_TX_QS];
374
375
376 u32 num_rx_qs;
377 struct be_rx_obj rx_obj[MAX_RX_QS];
378 u32 big_page_size;
379
380 struct be_drv_stats drv_stats;
381 u16 vlans_added;
382 u8 vlan_tag[VLAN_N_VID];
383 u8 vlan_prio_bmap;
384 u16 recommended_prio;
385 struct be_dma_mem rx_filter;
386
387 struct be_dma_mem stats_cmd;
388
389 struct delayed_work work;
390 u16 work_counter;
391
392 struct delayed_work func_recovery_work;
393 u32 flags;
394 u32 cmd_privileges;
395
396 char fw_ver[FW_VER_LEN];
397 int if_handle;
398 u32 *pmac_id;
399 u32 beacon_state;
400
401 bool eeh_error;
402 bool fw_timeout;
403 bool hw_error;
404
405 u32 port_num;
406 bool promiscuous;
407 u32 function_mode;
408 u32 function_caps;
409 u32 rx_fc;
410 u32 tx_fc;
411 bool stats_cmd_sent;
412 u32 if_type;
413 struct {
414 u32 size;
415 u32 total_size;
416 u64 io_addr;
417 } roce_db;
418 u32 num_msix_roce_vec;
419 struct ocrdma_dev *ocrdma_dev;
420 struct list_head entry;
421
422 u32 flash_status;
423 struct completion flash_compl;
424
425 u32 num_vfs;
426 u32 dev_num_vfs;
427 u8 virtfn;
428 struct be_vf_cfg *vf_cfg;
429 bool be3_native;
430 u32 sli_family;
431 u8 hba_port_num;
432 u16 pvid;
433 struct phy_info phy;
434 u8 wol_cap;
435 bool wol;
436 u32 uc_macs;
437 u32 msg_enable;
438 int be_get_temp_freq;
439 u16 max_mcast_mac;
440 u16 max_tx_queues;
441 u16 max_rss_queues;
442 u16 max_rx_queues;
443 u16 max_pmac_cnt;
444 u16 max_vlans;
445 u16 max_event_queues;
446 u32 if_cap_flags;
447 u8 pf_number;
448};
449
450#define be_physfn(adapter) (!adapter->virtfn)
451#define sriov_enabled(adapter) (adapter->num_vfs > 0)
452#define sriov_want(adapter) (adapter->dev_num_vfs && num_vfs && \
453 be_physfn(adapter))
454#define for_all_vfs(adapter, vf_cfg, i) \
455 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
456 i++, vf_cfg++)
457
458#define ON 1
459#define OFF 0
460
461#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \
462 adapter->pdev->device == OC_DEVICE_ID4)
463
464#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \
465 adapter->pdev->device == OC_DEVICE_ID6)
466
467#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \
468 adapter->pdev->device == OC_DEVICE_ID2)
469
470#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \
471 adapter->pdev->device == OC_DEVICE_ID1)
472
473#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter))
474
475#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \
476 (adapter->function_mode & RDMA_ENABLED))
477
478extern const struct ethtool_ops be_ethtool_ops;
479
480#define msix_enabled(adapter) (adapter->num_msix_vec > 0)
481#define num_irqs(adapter) (msix_enabled(adapter) ? \
482 adapter->num_msix_vec : 1)
483#define tx_stats(txo) (&(txo)->stats)
484#define rx_stats(rxo) (&(rxo)->stats)
485
486
487#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1])
488
489#define for_all_rx_queues(adapter, rxo, i) \
490 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
491 i++, rxo++)
492
493
494#define for_all_rss_queues(adapter, rxo, i) \
495 for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
496 i++, rxo++)
497
498#define for_all_tx_queues(adapter, txo, i) \
499 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \
500 i++, txo++)
501
502#define for_all_evt_queues(adapter, eqo, i) \
503 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
504 i++, eqo++)
505
506#define is_mcc_eqo(eqo) (eqo->idx == 0)
507#define mcc_eqo(adapter) (&adapter->eq_obj[0])
508
509#define PAGE_SHIFT_4K 12
510#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
511
512
513#define PAGES_4K_SPANNED(_address, size) \
514 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
515 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
516
517
518#define AMAP_BIT_OFFSET(_struct, field) \
519 (((size_t)&(((_struct *)0)->field))%32)
520
521
522static inline u32 amap_mask(u32 bitsize)
523{
524 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
525}
526
527static inline void
528amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
529{
530 u32 *dw = (u32 *) ptr + dw_offset;
531 *dw &= ~(mask << offset);
532 *dw |= (mask & value) << offset;
533}
534
535#define AMAP_SET_BITS(_struct, field, ptr, val) \
536 amap_set(ptr, \
537 offsetof(_struct, field)/32, \
538 amap_mask(sizeof(((_struct *)0)->field)), \
539 AMAP_BIT_OFFSET(_struct, field), \
540 val)
541
542static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
543{
544 u32 *dw = (u32 *) ptr;
545 return mask & (*(dw + dw_offset) >> offset);
546}
547
548#define AMAP_GET_BITS(_struct, field, ptr) \
549 amap_get(ptr, \
550 offsetof(_struct, field)/32, \
551 amap_mask(sizeof(((_struct *)0)->field)), \
552 AMAP_BIT_OFFSET(_struct, field))
553
554#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
555#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
556static inline void swap_dws(void *wrb, int len)
557{
558#ifdef __BIG_ENDIAN
559 u32 *dw = wrb;
560 BUG_ON(len % 4);
561 do {
562 *dw = cpu_to_le32(*dw);
563 dw++;
564 len -= 4;
565 } while (len);
566#endif
567}
568
569static inline u8 is_tcp_pkt(struct sk_buff *skb)
570{
571 u8 val = 0;
572
573 if (ip_hdr(skb)->version == 4)
574 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
575 else if (ip_hdr(skb)->version == 6)
576 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
577
578 return val;
579}
580
581static inline u8 is_udp_pkt(struct sk_buff *skb)
582{
583 u8 val = 0;
584
585 if (ip_hdr(skb)->version == 4)
586 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
587 else if (ip_hdr(skb)->version == 6)
588 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
589
590 return val;
591}
592
593static inline bool is_ipv4_pkt(struct sk_buff *skb)
594{
595 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
596}
597
598static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
599{
600 u32 addr;
601
602 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
603
604 mac[5] = (u8)(addr & 0xFF);
605 mac[4] = (u8)((addr >> 8) & 0xFF);
606 mac[3] = (u8)((addr >> 16) & 0xFF);
607
608 memcpy(mac, adapter->netdev->dev_addr, 3);
609}
610
611static inline bool be_multi_rxq(const struct be_adapter *adapter)
612{
613 return adapter->num_rx_qs > 1;
614}
615
616static inline bool be_error(struct be_adapter *adapter)
617{
618 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout;
619}
620
621static inline bool be_hw_error(struct be_adapter *adapter)
622{
623 return adapter->eeh_error || adapter->hw_error;
624}
625
626static inline void be_clear_all_error(struct be_adapter *adapter)
627{
628 adapter->eeh_error = false;
629 adapter->hw_error = false;
630 adapter->fw_timeout = false;
631}
632
633static inline bool be_is_wol_excluded(struct be_adapter *adapter)
634{
635 struct pci_dev *pdev = adapter->pdev;
636
637 if (!be_physfn(adapter))
638 return true;
639
640 switch (pdev->subsystem_device) {
641 case OC_SUBSYS_DEVICE_ID1:
642 case OC_SUBSYS_DEVICE_ID2:
643 case OC_SUBSYS_DEVICE_ID3:
644 case OC_SUBSYS_DEVICE_ID4:
645 return true;
646 default:
647 return false;
648 }
649}
650
651extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
652 u16 num_popped);
653extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
654extern void be_parse_stats(struct be_adapter *adapter);
655extern int be_load_fw(struct be_adapter *adapter, u8 *func);
656extern bool be_is_wol_supported(struct be_adapter *adapter);
657extern bool be_pause_supported(struct be_adapter *adapter);
658extern u32 be_get_fw_log_level(struct be_adapter *adapter);
659
660
661
662
663extern void be_roce_dev_add(struct be_adapter *);
664extern void be_roce_dev_remove(struct be_adapter *);
665
666
667
668
669extern void be_roce_dev_open(struct be_adapter *);
670extern void be_roce_dev_close(struct be_adapter *);
671
672#endif
673