1/* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * (C) Copyright 2009-2011 Faraday Technology 5 * Po-Yu Chuang <ratbert@faraday-tech.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22#ifndef __FTGMAC100_H 23#define __FTGMAC100_H 24 25#define FTGMAC100_OFFSET_ISR 0x00 26#define FTGMAC100_OFFSET_IER 0x04 27#define FTGMAC100_OFFSET_MAC_MADR 0x08 28#define FTGMAC100_OFFSET_MAC_LADR 0x0c 29#define FTGMAC100_OFFSET_MAHT0 0x10 30#define FTGMAC100_OFFSET_MAHT1 0x14 31#define FTGMAC100_OFFSET_NPTXPD 0x18 32#define FTGMAC100_OFFSET_RXPD 0x1c 33#define FTGMAC100_OFFSET_NPTXR_BADR 0x20 34#define FTGMAC100_OFFSET_RXR_BADR 0x24 35#define FTGMAC100_OFFSET_HPTXPD 0x28 36#define FTGMAC100_OFFSET_HPTXR_BADR 0x2c 37#define FTGMAC100_OFFSET_ITC 0x30 38#define FTGMAC100_OFFSET_APTC 0x34 39#define FTGMAC100_OFFSET_DBLAC 0x38 40#define FTGMAC100_OFFSET_DMAFIFOS 0x3c 41#define FTGMAC100_OFFSET_REVR 0x40 42#define FTGMAC100_OFFSET_FEAR 0x44 43#define FTGMAC100_OFFSET_TPAFCR 0x48 44#define FTGMAC100_OFFSET_RBSR 0x4c 45#define FTGMAC100_OFFSET_MACCR 0x50 46#define FTGMAC100_OFFSET_MACSR 0x54 47#define FTGMAC100_OFFSET_TM 0x58 48#define FTGMAC100_OFFSET_PHYCR 0x60 49#define FTGMAC100_OFFSET_PHYDATA 0x64 50#define FTGMAC100_OFFSET_FCR 0x68 51#define FTGMAC100_OFFSET_BPR 0x6c 52#define FTGMAC100_OFFSET_WOLCR 0x70 53#define FTGMAC100_OFFSET_WOLSR 0x74 54#define FTGMAC100_OFFSET_WFCRC 0x78 55#define FTGMAC100_OFFSET_WFBM1 0x80 56#define FTGMAC100_OFFSET_WFBM2 0x84 57#define FTGMAC100_OFFSET_WFBM3 0x88 58#define FTGMAC100_OFFSET_WFBM4 0x8c 59#define FTGMAC100_OFFSET_NPTXR_PTR 0x90 60#define FTGMAC100_OFFSET_HPTXR_PTR 0x94 61#define FTGMAC100_OFFSET_RXR_PTR 0x98 62#define FTGMAC100_OFFSET_TX 0xa0 63#define FTGMAC100_OFFSET_TX_MCOL_SCOL 0xa4 64#define FTGMAC100_OFFSET_TX_ECOL_FAIL 0xa8 65#define FTGMAC100_OFFSET_TX_LCOL_UND 0xac 66#define FTGMAC100_OFFSET_RX 0xb0 67#define FTGMAC100_OFFSET_RX_BC 0xb4 68#define FTGMAC100_OFFSET_RX_MC 0xb8 69#define FTGMAC100_OFFSET_RX_PF_AEP 0xbc 70#define FTGMAC100_OFFSET_RX_RUNT 0xc0 71#define FTGMAC100_OFFSET_RX_CRCER_FTL 0xc4 72#define FTGMAC100_OFFSET_RX_COL_LOST 0xc8 73 74/* 75 * Interrupt status register & interrupt enable register 76 */ 77#define FTGMAC100_INT_RPKT_BUF (1 << 0) 78#define FTGMAC100_INT_RPKT_FIFO (1 << 1) 79#define FTGMAC100_INT_NO_RXBUF (1 << 2) 80#define FTGMAC100_INT_RPKT_LOST (1 << 3) 81#define FTGMAC100_INT_XPKT_ETH (1 << 4) 82#define FTGMAC100_INT_XPKT_FIFO (1 << 5) 83#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) 84#define FTGMAC100_INT_XPKT_LOST (1 << 7) 85#define FTGMAC100_INT_AHB_ERR (1 << 8) 86#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) 87#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) 88 89/* 90 * Interrupt timer control register 91 */ 92#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) 93#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) 94#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) 95#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) 96#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) 97#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) 98 99/* 100 * Automatic polling timer control register 101 */ 102#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 103#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 104#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 105#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 106 107/* 108 * DMA burst length and arbitration control register 109 */ 110#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) 111#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) 112#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) 113#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) 114#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) 115#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) 116#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) 117#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) 118#define FTGMAC100_DBLAC_IFG_INC (1 << 23) 119 120/* 121 * DMA FIFO status register 122 */ 123#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) 124#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) 125#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) 126#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) 127#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) 128#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) 129#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) 130#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) 131#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) 132#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) 133#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) 134#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) 135 136/* 137 * Receive buffer size register 138 */ 139#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) 140 141/* 142 * MAC control register 143 */ 144#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) 145#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) 146#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) 147#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) 148#define FTGMAC100_MACCR_RM_VLAN (1 << 4) 149#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) 150#define FTGMAC100_MACCR_LOOP_EN (1 << 6) 151#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) 152#define FTGMAC100_MACCR_FULLDUP (1 << 8) 153#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) 154#define FTGMAC100_MACCR_CRC_APD (1 << 10) 155#define FTGMAC100_MACCR_RX_RUNT (1 << 12) 156#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) 157#define FTGMAC100_MACCR_RX_ALL (1 << 14) 158#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) 159#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) 160#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) 161#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) 162#define FTGMAC100_MACCR_FAST_MODE (1 << 19) 163#define FTGMAC100_MACCR_SW_RST (1 << 31) 164 165/* 166 * PHY control register 167 */ 168#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f 169#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) 170#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) 171#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) 172#define FTGMAC100_PHYCR_MIIRD (1 << 26) 173#define FTGMAC100_PHYCR_MIIWR (1 << 27) 174 175/* 176 * PHY data register 177 */ 178#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) 179#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) 180 181/* 182 * Transmit descriptor, aligned to 16 bytes 183 */ 184struct ftgmac100_txdes { 185 unsigned int txdes0; 186 unsigned int txdes1; 187 unsigned int txdes2; /* not used by HW */ 188 unsigned int txdes3; /* TXBUF_BADR */ 189} __attribute__ ((aligned(16))); 190 191#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) 192#define FTGMAC100_TXDES0_EDOTR (1 << 15) 193#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) 194#define FTGMAC100_TXDES0_LTS (1 << 28) 195#define FTGMAC100_TXDES0_FTS (1 << 29) 196#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) 197 198#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) 199#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) 200#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) 201#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) 202#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) 203#define FTGMAC100_TXDES1_LLC (1 << 22) 204#define FTGMAC100_TXDES1_TX2FIC (1 << 30) 205#define FTGMAC100_TXDES1_TXIC (1 << 31) 206 207/* 208 * Receive descriptor, aligned to 16 bytes 209 */ 210struct ftgmac100_rxdes { 211 unsigned int rxdes0; 212 unsigned int rxdes1; 213 unsigned int rxdes2; /* not used by HW */ 214 unsigned int rxdes3; /* RXBUF_BADR */ 215} __attribute__ ((aligned(16))); 216 217#define FTGMAC100_RXDES0_VDBC 0x3fff 218#define FTGMAC100_RXDES0_EDORR (1 << 15) 219#define FTGMAC100_RXDES0_MULTICAST (1 << 16) 220#define FTGMAC100_RXDES0_BROADCAST (1 << 17) 221#define FTGMAC100_RXDES0_RX_ERR (1 << 18) 222#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) 223#define FTGMAC100_RXDES0_FTL (1 << 20) 224#define FTGMAC100_RXDES0_RUNT (1 << 21) 225#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) 226#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) 227#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) 228#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) 229#define FTGMAC100_RXDES0_LRS (1 << 28) 230#define FTGMAC100_RXDES0_FRS (1 << 29) 231#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) 232 233#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff 234#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) 235#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) 236#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) 237#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) 238#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) 239#define FTGMAC100_RXDES1_LLC (1 << 22) 240#define FTGMAC100_RXDES1_DF (1 << 23) 241#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) 242#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) 243#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) 244#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) 245 246#endif /* __FTGMAC100_H */ 247