linux/drivers/net/ethernet/intel/igb/e1000_mac.c
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   1/*******************************************************************************
   2
   3  Intel(R) Gigabit Ethernet Linux driver
   4  Copyright(c) 2007-2013 Intel Corporation.
   5
   6  This program is free software; you can redistribute it and/or modify it
   7  under the terms and conditions of the GNU General Public License,
   8  version 2, as published by the Free Software Foundation.
   9
  10  This program is distributed in the hope it will be useful, but WITHOUT
  11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  more details.
  14
  15  You should have received a copy of the GNU General Public License along with
  16  this program; if not, write to the Free Software Foundation, Inc.,
  17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19  The full GNU General Public License is included in this distribution in
  20  the file called "COPYING".
  21
  22  Contact Information:
  23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26*******************************************************************************/
  27
  28#include <linux/if_ether.h>
  29#include <linux/delay.h>
  30#include <linux/pci.h>
  31#include <linux/netdevice.h>
  32#include <linux/etherdevice.h>
  33
  34#include "e1000_mac.h"
  35
  36#include "igb.h"
  37
  38static s32 igb_set_default_fc(struct e1000_hw *hw);
  39static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
  40
  41/**
  42 *  igb_get_bus_info_pcie - Get PCIe bus information
  43 *  @hw: pointer to the HW structure
  44 *
  45 *  Determines and stores the system bus information for a particular
  46 *  network interface.  The following bus information is determined and stored:
  47 *  bus speed, bus width, type (PCIe), and PCIe function.
  48 **/
  49s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
  50{
  51        struct e1000_bus_info *bus = &hw->bus;
  52        s32 ret_val;
  53        u32 reg;
  54        u16 pcie_link_status;
  55
  56        bus->type = e1000_bus_type_pci_express;
  57
  58        ret_val = igb_read_pcie_cap_reg(hw,
  59                                        PCI_EXP_LNKSTA,
  60                                        &pcie_link_status);
  61        if (ret_val) {
  62                bus->width = e1000_bus_width_unknown;
  63                bus->speed = e1000_bus_speed_unknown;
  64        } else {
  65                switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
  66                case PCI_EXP_LNKSTA_CLS_2_5GB:
  67                        bus->speed = e1000_bus_speed_2500;
  68                        break;
  69                case PCI_EXP_LNKSTA_CLS_5_0GB:
  70                        bus->speed = e1000_bus_speed_5000;
  71                        break;
  72                default:
  73                        bus->speed = e1000_bus_speed_unknown;
  74                        break;
  75                }
  76
  77                bus->width = (enum e1000_bus_width)((pcie_link_status &
  78                                                     PCI_EXP_LNKSTA_NLW) >>
  79                                                     PCI_EXP_LNKSTA_NLW_SHIFT);
  80        }
  81
  82        reg = rd32(E1000_STATUS);
  83        bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
  84
  85        return 0;
  86}
  87
  88/**
  89 *  igb_clear_vfta - Clear VLAN filter table
  90 *  @hw: pointer to the HW structure
  91 *
  92 *  Clears the register array which contains the VLAN filter table by
  93 *  setting all the values to 0.
  94 **/
  95void igb_clear_vfta(struct e1000_hw *hw)
  96{
  97        u32 offset;
  98
  99        for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
 100                array_wr32(E1000_VFTA, offset, 0);
 101                wrfl();
 102        }
 103}
 104
 105/**
 106 *  igb_write_vfta - Write value to VLAN filter table
 107 *  @hw: pointer to the HW structure
 108 *  @offset: register offset in VLAN filter table
 109 *  @value: register value written to VLAN filter table
 110 *
 111 *  Writes value at the given offset in the register array which stores
 112 *  the VLAN filter table.
 113 **/
 114static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
 115{
 116        array_wr32(E1000_VFTA, offset, value);
 117        wrfl();
 118}
 119
 120/* Due to a hw errata, if the host tries to  configure the VFTA register
 121 * while performing queries from the BMC or DMA, then the VFTA in some
 122 * cases won't be written.
 123 */
 124
 125/**
 126 *  igb_clear_vfta_i350 - Clear VLAN filter table
 127 *  @hw: pointer to the HW structure
 128 *
 129 *  Clears the register array which contains the VLAN filter table by
 130 *  setting all the values to 0.
 131 **/
 132void igb_clear_vfta_i350(struct e1000_hw *hw)
 133{
 134        u32 offset;
 135        int i;
 136
 137        for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
 138                for (i = 0; i < 10; i++)
 139                        array_wr32(E1000_VFTA, offset, 0);
 140
 141                wrfl();
 142        }
 143}
 144
 145/**
 146 *  igb_write_vfta_i350 - Write value to VLAN filter table
 147 *  @hw: pointer to the HW structure
 148 *  @offset: register offset in VLAN filter table
 149 *  @value: register value written to VLAN filter table
 150 *
 151 *  Writes value at the given offset in the register array which stores
 152 *  the VLAN filter table.
 153 **/
 154static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
 155{
 156        int i;
 157
 158        for (i = 0; i < 10; i++)
 159                array_wr32(E1000_VFTA, offset, value);
 160
 161        wrfl();
 162}
 163
 164/**
 165 *  igb_init_rx_addrs - Initialize receive address's
 166 *  @hw: pointer to the HW structure
 167 *  @rar_count: receive address registers
 168 *
 169 *  Setups the receive address registers by setting the base receive address
 170 *  register to the devices MAC address and clearing all the other receive
 171 *  address registers to 0.
 172 **/
 173void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
 174{
 175        u32 i;
 176        u8 mac_addr[ETH_ALEN] = {0};
 177
 178        /* Setup the receive address */
 179        hw_dbg("Programming MAC Address into RAR[0]\n");
 180
 181        hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
 182
 183        /* Zero out the other (rar_entry_count - 1) receive addresses */
 184        hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
 185        for (i = 1; i < rar_count; i++)
 186                hw->mac.ops.rar_set(hw, mac_addr, i);
 187}
 188
 189/**
 190 *  igb_vfta_set - enable or disable vlan in VLAN filter table
 191 *  @hw: pointer to the HW structure
 192 *  @vid: VLAN id to add or remove
 193 *  @add: if true add filter, if false remove
 194 *
 195 *  Sets or clears a bit in the VLAN filter table array based on VLAN id
 196 *  and if we are adding or removing the filter
 197 **/
 198s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add)
 199{
 200        u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
 201        u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
 202        u32 vfta;
 203        struct igb_adapter *adapter = hw->back;
 204        s32 ret_val = 0;
 205
 206        vfta = adapter->shadow_vfta[index];
 207
 208        /* bit was set/cleared before we started */
 209        if ((!!(vfta & mask)) == add) {
 210                ret_val = -E1000_ERR_CONFIG;
 211        } else {
 212                if (add)
 213                        vfta |= mask;
 214                else
 215                        vfta &= ~mask;
 216        }
 217        if (hw->mac.type == e1000_i350)
 218                igb_write_vfta_i350(hw, index, vfta);
 219        else
 220                igb_write_vfta(hw, index, vfta);
 221        adapter->shadow_vfta[index] = vfta;
 222
 223        return ret_val;
 224}
 225
 226/**
 227 *  igb_check_alt_mac_addr - Check for alternate MAC addr
 228 *  @hw: pointer to the HW structure
 229 *
 230 *  Checks the nvm for an alternate MAC address.  An alternate MAC address
 231 *  can be setup by pre-boot software and must be treated like a permanent
 232 *  address and must override the actual permanent MAC address.  If an
 233 *  alternate MAC address is fopund it is saved in the hw struct and
 234 *  prgrammed into RAR0 and the cuntion returns success, otherwise the
 235 *  function returns an error.
 236 **/
 237s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
 238{
 239        u32 i;
 240        s32 ret_val = 0;
 241        u16 offset, nvm_alt_mac_addr_offset, nvm_data;
 242        u8 alt_mac_addr[ETH_ALEN];
 243
 244        /*
 245         * Alternate MAC address is handled by the option ROM for 82580
 246         * and newer. SW support not required.
 247         */
 248        if (hw->mac.type >= e1000_82580)
 249                goto out;
 250
 251        ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
 252                                 &nvm_alt_mac_addr_offset);
 253        if (ret_val) {
 254                hw_dbg("NVM Read Error\n");
 255                goto out;
 256        }
 257
 258        if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
 259            (nvm_alt_mac_addr_offset == 0x0000))
 260                /* There is no Alternate MAC Address */
 261                goto out;
 262
 263        if (hw->bus.func == E1000_FUNC_1)
 264                nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
 265        if (hw->bus.func == E1000_FUNC_2)
 266                nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
 267
 268        if (hw->bus.func == E1000_FUNC_3)
 269                nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
 270        for (i = 0; i < ETH_ALEN; i += 2) {
 271                offset = nvm_alt_mac_addr_offset + (i >> 1);
 272                ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 273                if (ret_val) {
 274                        hw_dbg("NVM Read Error\n");
 275                        goto out;
 276                }
 277
 278                alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
 279                alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
 280        }
 281
 282        /* if multicast bit is set, the alternate address will not be used */
 283        if (is_multicast_ether_addr(alt_mac_addr)) {
 284                hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
 285                goto out;
 286        }
 287
 288        /*
 289         * We have a valid alternate MAC address, and we want to treat it the
 290         * same as the normal permanent MAC address stored by the HW into the
 291         * RAR. Do this by mapping this address into RAR0.
 292         */
 293        hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
 294
 295out:
 296        return ret_val;
 297}
 298
 299/**
 300 *  igb_rar_set - Set receive address register
 301 *  @hw: pointer to the HW structure
 302 *  @addr: pointer to the receive address
 303 *  @index: receive address array register
 304 *
 305 *  Sets the receive address array register at index to the address passed
 306 *  in by addr.
 307 **/
 308void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
 309{
 310        u32 rar_low, rar_high;
 311
 312        /*
 313         * HW expects these in little endian so we reverse the byte order
 314         * from network order (big endian) to little endian
 315         */
 316        rar_low = ((u32) addr[0] |
 317                   ((u32) addr[1] << 8) |
 318                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 319
 320        rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 321
 322        /* If MAC address zero, no need to set the AV bit */
 323        if (rar_low || rar_high)
 324                rar_high |= E1000_RAH_AV;
 325
 326        /*
 327         * Some bridges will combine consecutive 32-bit writes into
 328         * a single burst write, which will malfunction on some parts.
 329         * The flushes avoid this.
 330         */
 331        wr32(E1000_RAL(index), rar_low);
 332        wrfl();
 333        wr32(E1000_RAH(index), rar_high);
 334        wrfl();
 335}
 336
 337/**
 338 *  igb_mta_set - Set multicast filter table address
 339 *  @hw: pointer to the HW structure
 340 *  @hash_value: determines the MTA register and bit to set
 341 *
 342 *  The multicast table address is a register array of 32-bit registers.
 343 *  The hash_value is used to determine what register the bit is in, the
 344 *  current value is read, the new bit is OR'd in and the new value is
 345 *  written back into the register.
 346 **/
 347void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
 348{
 349        u32 hash_bit, hash_reg, mta;
 350
 351        /*
 352         * The MTA is a register array of 32-bit registers. It is
 353         * treated like an array of (32*mta_reg_count) bits.  We want to
 354         * set bit BitArray[hash_value]. So we figure out what register
 355         * the bit is in, read it, OR in the new bit, then write
 356         * back the new value.  The (hw->mac.mta_reg_count - 1) serves as a
 357         * mask to bits 31:5 of the hash value which gives us the
 358         * register we're modifying.  The hash bit within that register
 359         * is determined by the lower 5 bits of the hash value.
 360         */
 361        hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
 362        hash_bit = hash_value & 0x1F;
 363
 364        mta = array_rd32(E1000_MTA, hash_reg);
 365
 366        mta |= (1 << hash_bit);
 367
 368        array_wr32(E1000_MTA, hash_reg, mta);
 369        wrfl();
 370}
 371
 372/**
 373 *  igb_hash_mc_addr - Generate a multicast hash value
 374 *  @hw: pointer to the HW structure
 375 *  @mc_addr: pointer to a multicast address
 376 *
 377 *  Generates a multicast address hash value which is used to determine
 378 *  the multicast filter table array address and new table value.  See
 379 *  igb_mta_set()
 380 **/
 381static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
 382{
 383        u32 hash_value, hash_mask;
 384        u8 bit_shift = 0;
 385
 386        /* Register count multiplied by bits per register */
 387        hash_mask = (hw->mac.mta_reg_count * 32) - 1;
 388
 389        /*
 390         * For a mc_filter_type of 0, bit_shift is the number of left-shifts
 391         * where 0xFF would still fall within the hash mask.
 392         */
 393        while (hash_mask >> bit_shift != 0xFF)
 394                bit_shift++;
 395
 396        /*
 397         * The portion of the address that is used for the hash table
 398         * is determined by the mc_filter_type setting.
 399         * The algorithm is such that there is a total of 8 bits of shifting.
 400         * The bit_shift for a mc_filter_type of 0 represents the number of
 401         * left-shifts where the MSB of mc_addr[5] would still fall within
 402         * the hash_mask.  Case 0 does this exactly.  Since there are a total
 403         * of 8 bits of shifting, then mc_addr[4] will shift right the
 404         * remaining number of bits. Thus 8 - bit_shift.  The rest of the
 405         * cases are a variation of this algorithm...essentially raising the
 406         * number of bits to shift mc_addr[5] left, while still keeping the
 407         * 8-bit shifting total.
 408         *
 409         * For example, given the following Destination MAC Address and an
 410         * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
 411         * we can see that the bit_shift for case 0 is 4.  These are the hash
 412         * values resulting from each mc_filter_type...
 413         * [0] [1] [2] [3] [4] [5]
 414         * 01  AA  00  12  34  56
 415         * LSB                 MSB
 416         *
 417         * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
 418         * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
 419         * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
 420         * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
 421         */
 422        switch (hw->mac.mc_filter_type) {
 423        default:
 424        case 0:
 425                break;
 426        case 1:
 427                bit_shift += 1;
 428                break;
 429        case 2:
 430                bit_shift += 2;
 431                break;
 432        case 3:
 433                bit_shift += 4;
 434                break;
 435        }
 436
 437        hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
 438                                  (((u16) mc_addr[5]) << bit_shift)));
 439
 440        return hash_value;
 441}
 442
 443/**
 444 *  igb_update_mc_addr_list - Update Multicast addresses
 445 *  @hw: pointer to the HW structure
 446 *  @mc_addr_list: array of multicast addresses to program
 447 *  @mc_addr_count: number of multicast addresses to program
 448 *
 449 *  Updates entire Multicast Table Array.
 450 *  The caller must have a packed mc_addr_list of multicast addresses.
 451 **/
 452void igb_update_mc_addr_list(struct e1000_hw *hw,
 453                             u8 *mc_addr_list, u32 mc_addr_count)
 454{
 455        u32 hash_value, hash_bit, hash_reg;
 456        int i;
 457
 458        /* clear mta_shadow */
 459        memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
 460
 461        /* update mta_shadow from mc_addr_list */
 462        for (i = 0; (u32) i < mc_addr_count; i++) {
 463                hash_value = igb_hash_mc_addr(hw, mc_addr_list);
 464
 465                hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
 466                hash_bit = hash_value & 0x1F;
 467
 468                hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
 469                mc_addr_list += (ETH_ALEN);
 470        }
 471
 472        /* replace the entire MTA table */
 473        for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
 474                array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
 475        wrfl();
 476}
 477
 478/**
 479 *  igb_clear_hw_cntrs_base - Clear base hardware counters
 480 *  @hw: pointer to the HW structure
 481 *
 482 *  Clears the base hardware counters by reading the counter registers.
 483 **/
 484void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
 485{
 486        rd32(E1000_CRCERRS);
 487        rd32(E1000_SYMERRS);
 488        rd32(E1000_MPC);
 489        rd32(E1000_SCC);
 490        rd32(E1000_ECOL);
 491        rd32(E1000_MCC);
 492        rd32(E1000_LATECOL);
 493        rd32(E1000_COLC);
 494        rd32(E1000_DC);
 495        rd32(E1000_SEC);
 496        rd32(E1000_RLEC);
 497        rd32(E1000_XONRXC);
 498        rd32(E1000_XONTXC);
 499        rd32(E1000_XOFFRXC);
 500        rd32(E1000_XOFFTXC);
 501        rd32(E1000_FCRUC);
 502        rd32(E1000_GPRC);
 503        rd32(E1000_BPRC);
 504        rd32(E1000_MPRC);
 505        rd32(E1000_GPTC);
 506        rd32(E1000_GORCL);
 507        rd32(E1000_GORCH);
 508        rd32(E1000_GOTCL);
 509        rd32(E1000_GOTCH);
 510        rd32(E1000_RNBC);
 511        rd32(E1000_RUC);
 512        rd32(E1000_RFC);
 513        rd32(E1000_ROC);
 514        rd32(E1000_RJC);
 515        rd32(E1000_TORL);
 516        rd32(E1000_TORH);
 517        rd32(E1000_TOTL);
 518        rd32(E1000_TOTH);
 519        rd32(E1000_TPR);
 520        rd32(E1000_TPT);
 521        rd32(E1000_MPTC);
 522        rd32(E1000_BPTC);
 523}
 524
 525/**
 526 *  igb_check_for_copper_link - Check for link (Copper)
 527 *  @hw: pointer to the HW structure
 528 *
 529 *  Checks to see of the link status of the hardware has changed.  If a
 530 *  change in link status has been detected, then we read the PHY registers
 531 *  to get the current speed/duplex if link exists.
 532 **/
 533s32 igb_check_for_copper_link(struct e1000_hw *hw)
 534{
 535        struct e1000_mac_info *mac = &hw->mac;
 536        s32 ret_val;
 537        bool link;
 538
 539        /*
 540         * We only want to go out to the PHY registers to see if Auto-Neg
 541         * has completed and/or if our link status has changed.  The
 542         * get_link_status flag is set upon receiving a Link Status
 543         * Change or Rx Sequence Error interrupt.
 544         */
 545        if (!mac->get_link_status) {
 546                ret_val = 0;
 547                goto out;
 548        }
 549
 550        /*
 551         * First we want to see if the MII Status Register reports
 552         * link.  If so, then we want to get the current speed/duplex
 553         * of the PHY.
 554         */
 555        ret_val = igb_phy_has_link(hw, 1, 0, &link);
 556        if (ret_val)
 557                goto out;
 558
 559        if (!link)
 560                goto out; /* No link detected */
 561
 562        mac->get_link_status = false;
 563
 564        /*
 565         * Check if there was DownShift, must be checked
 566         * immediately after link-up
 567         */
 568        igb_check_downshift(hw);
 569
 570        /*
 571         * If we are forcing speed/duplex, then we simply return since
 572         * we have already determined whether we have link or not.
 573         */
 574        if (!mac->autoneg) {
 575                ret_val = -E1000_ERR_CONFIG;
 576                goto out;
 577        }
 578
 579        /*
 580         * Auto-Neg is enabled.  Auto Speed Detection takes care
 581         * of MAC speed/duplex configuration.  So we only need to
 582         * configure Collision Distance in the MAC.
 583         */
 584        igb_config_collision_dist(hw);
 585
 586        /*
 587         * Configure Flow Control now that Auto-Neg has completed.
 588         * First, we need to restore the desired flow control
 589         * settings because we may have had to re-autoneg with a
 590         * different link partner.
 591         */
 592        ret_val = igb_config_fc_after_link_up(hw);
 593        if (ret_val)
 594                hw_dbg("Error configuring flow control\n");
 595
 596out:
 597        return ret_val;
 598}
 599
 600/**
 601 *  igb_setup_link - Setup flow control and link settings
 602 *  @hw: pointer to the HW structure
 603 *
 604 *  Determines which flow control settings to use, then configures flow
 605 *  control.  Calls the appropriate media-specific link configuration
 606 *  function.  Assuming the adapter has a valid link partner, a valid link
 607 *  should be established.  Assumes the hardware has previously been reset
 608 *  and the transmitter and receiver are not enabled.
 609 **/
 610s32 igb_setup_link(struct e1000_hw *hw)
 611{
 612        s32 ret_val = 0;
 613
 614        /*
 615         * In the case of the phy reset being blocked, we already have a link.
 616         * We do not need to set it up again.
 617         */
 618        if (igb_check_reset_block(hw))
 619                goto out;
 620
 621        /*
 622         * If requested flow control is set to default, set flow control
 623         * based on the EEPROM flow control settings.
 624         */
 625        if (hw->fc.requested_mode == e1000_fc_default) {
 626                ret_val = igb_set_default_fc(hw);
 627                if (ret_val)
 628                        goto out;
 629        }
 630
 631        /*
 632         * We want to save off the original Flow Control configuration just
 633         * in case we get disconnected and then reconnected into a different
 634         * hub or switch with different Flow Control capabilities.
 635         */
 636        hw->fc.current_mode = hw->fc.requested_mode;
 637
 638        hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
 639
 640        /* Call the necessary media_type subroutine to configure the link. */
 641        ret_val = hw->mac.ops.setup_physical_interface(hw);
 642        if (ret_val)
 643                goto out;
 644
 645        /*
 646         * Initialize the flow control address, type, and PAUSE timer
 647         * registers to their default values.  This is done even if flow
 648         * control is disabled, because it does not hurt anything to
 649         * initialize these registers.
 650         */
 651        hw_dbg("Initializing the Flow Control address, type and timer regs\n");
 652        wr32(E1000_FCT, FLOW_CONTROL_TYPE);
 653        wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 654        wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 655
 656        wr32(E1000_FCTTV, hw->fc.pause_time);
 657
 658        ret_val = igb_set_fc_watermarks(hw);
 659
 660out:
 661
 662        return ret_val;
 663}
 664
 665/**
 666 *  igb_config_collision_dist - Configure collision distance
 667 *  @hw: pointer to the HW structure
 668 *
 669 *  Configures the collision distance to the default value and is used
 670 *  during link setup. Currently no func pointer exists and all
 671 *  implementations are handled in the generic version of this function.
 672 **/
 673void igb_config_collision_dist(struct e1000_hw *hw)
 674{
 675        u32 tctl;
 676
 677        tctl = rd32(E1000_TCTL);
 678
 679        tctl &= ~E1000_TCTL_COLD;
 680        tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
 681
 682        wr32(E1000_TCTL, tctl);
 683        wrfl();
 684}
 685
 686/**
 687 *  igb_set_fc_watermarks - Set flow control high/low watermarks
 688 *  @hw: pointer to the HW structure
 689 *
 690 *  Sets the flow control high/low threshold (watermark) registers.  If
 691 *  flow control XON frame transmission is enabled, then set XON frame
 692 *  tansmission as well.
 693 **/
 694static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
 695{
 696        s32 ret_val = 0;
 697        u32 fcrtl = 0, fcrth = 0;
 698
 699        /*
 700         * Set the flow control receive threshold registers.  Normally,
 701         * these registers will be set to a default threshold that may be
 702         * adjusted later by the driver's runtime code.  However, if the
 703         * ability to transmit pause frames is not enabled, then these
 704         * registers will be set to 0.
 705         */
 706        if (hw->fc.current_mode & e1000_fc_tx_pause) {
 707                /*
 708                 * We need to set up the Receive Threshold high and low water
 709                 * marks as well as (optionally) enabling the transmission of
 710                 * XON frames.
 711                 */
 712                fcrtl = hw->fc.low_water;
 713                if (hw->fc.send_xon)
 714                        fcrtl |= E1000_FCRTL_XONE;
 715
 716                fcrth = hw->fc.high_water;
 717        }
 718        wr32(E1000_FCRTL, fcrtl);
 719        wr32(E1000_FCRTH, fcrth);
 720
 721        return ret_val;
 722}
 723
 724/**
 725 *  igb_set_default_fc - Set flow control default values
 726 *  @hw: pointer to the HW structure
 727 *
 728 *  Read the EEPROM for the default values for flow control and store the
 729 *  values.
 730 **/
 731static s32 igb_set_default_fc(struct e1000_hw *hw)
 732{
 733        s32 ret_val = 0;
 734        u16 nvm_data;
 735
 736        /*
 737         * Read and store word 0x0F of the EEPROM. This word contains bits
 738         * that determine the hardware's default PAUSE (flow control) mode,
 739         * a bit that determines whether the HW defaults to enabling or
 740         * disabling auto-negotiation, and the direction of the
 741         * SW defined pins. If there is no SW over-ride of the flow
 742         * control setting, then the variable hw->fc will
 743         * be initialized based on a value in the EEPROM.
 744         */
 745        ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
 746
 747        if (ret_val) {
 748                hw_dbg("NVM Read Error\n");
 749                goto out;
 750        }
 751
 752        if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
 753                hw->fc.requested_mode = e1000_fc_none;
 754        else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
 755                 NVM_WORD0F_ASM_DIR)
 756                hw->fc.requested_mode = e1000_fc_tx_pause;
 757        else
 758                hw->fc.requested_mode = e1000_fc_full;
 759
 760out:
 761        return ret_val;
 762}
 763
 764/**
 765 *  igb_force_mac_fc - Force the MAC's flow control settings
 766 *  @hw: pointer to the HW structure
 767 *
 768 *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
 769 *  device control register to reflect the adapter settings.  TFCE and RFCE
 770 *  need to be explicitly set by software when a copper PHY is used because
 771 *  autonegotiation is managed by the PHY rather than the MAC.  Software must
 772 *  also configure these bits when link is forced on a fiber connection.
 773 **/
 774s32 igb_force_mac_fc(struct e1000_hw *hw)
 775{
 776        u32 ctrl;
 777        s32 ret_val = 0;
 778
 779        ctrl = rd32(E1000_CTRL);
 780
 781        /*
 782         * Because we didn't get link via the internal auto-negotiation
 783         * mechanism (we either forced link or we got link via PHY
 784         * auto-neg), we have to manually enable/disable transmit an
 785         * receive flow control.
 786         *
 787         * The "Case" statement below enables/disable flow control
 788         * according to the "hw->fc.current_mode" parameter.
 789         *
 790         * The possible values of the "fc" parameter are:
 791         *      0:  Flow control is completely disabled
 792         *      1:  Rx flow control is enabled (we can receive pause
 793         *          frames but not send pause frames).
 794         *      2:  Tx flow control is enabled (we can send pause frames
 795         *          frames but we do not receive pause frames).
 796         *      3:  Both Rx and TX flow control (symmetric) is enabled.
 797         *  other:  No other values should be possible at this point.
 798         */
 799        hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
 800
 801        switch (hw->fc.current_mode) {
 802        case e1000_fc_none:
 803                ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
 804                break;
 805        case e1000_fc_rx_pause:
 806                ctrl &= (~E1000_CTRL_TFCE);
 807                ctrl |= E1000_CTRL_RFCE;
 808                break;
 809        case e1000_fc_tx_pause:
 810                ctrl &= (~E1000_CTRL_RFCE);
 811                ctrl |= E1000_CTRL_TFCE;
 812                break;
 813        case e1000_fc_full:
 814                ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
 815                break;
 816        default:
 817                hw_dbg("Flow control param set incorrectly\n");
 818                ret_val = -E1000_ERR_CONFIG;
 819                goto out;
 820        }
 821
 822        wr32(E1000_CTRL, ctrl);
 823
 824out:
 825        return ret_val;
 826}
 827
 828/**
 829 *  igb_config_fc_after_link_up - Configures flow control after link
 830 *  @hw: pointer to the HW structure
 831 *
 832 *  Checks the status of auto-negotiation after link up to ensure that the
 833 *  speed and duplex were not forced.  If the link needed to be forced, then
 834 *  flow control needs to be forced also.  If auto-negotiation is enabled
 835 *  and did not fail, then we configure flow control based on our link
 836 *  partner.
 837 **/
 838s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
 839{
 840        struct e1000_mac_info *mac = &hw->mac;
 841        s32 ret_val = 0;
 842        u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
 843        u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
 844        u16 speed, duplex;
 845
 846        /*
 847         * Check for the case where we have fiber media and auto-neg failed
 848         * so we had to force link.  In this case, we need to force the
 849         * configuration of the MAC to match the "fc" parameter.
 850         */
 851        if (mac->autoneg_failed) {
 852                if (hw->phy.media_type == e1000_media_type_internal_serdes)
 853                        ret_val = igb_force_mac_fc(hw);
 854        } else {
 855                if (hw->phy.media_type == e1000_media_type_copper)
 856                        ret_val = igb_force_mac_fc(hw);
 857        }
 858
 859        if (ret_val) {
 860                hw_dbg("Error forcing flow control settings\n");
 861                goto out;
 862        }
 863
 864        /*
 865         * Check for the case where we have copper media and auto-neg is
 866         * enabled.  In this case, we need to check and see if Auto-Neg
 867         * has completed, and if so, how the PHY and link partner has
 868         * flow control configured.
 869         */
 870        if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
 871                /*
 872                 * Read the MII Status Register and check to see if AutoNeg
 873                 * has completed.  We read this twice because this reg has
 874                 * some "sticky" (latched) bits.
 875                 */
 876                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
 877                                                   &mii_status_reg);
 878                if (ret_val)
 879                        goto out;
 880                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
 881                                                   &mii_status_reg);
 882                if (ret_val)
 883                        goto out;
 884
 885                if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
 886                        hw_dbg("Copper PHY and Auto Neg "
 887                                 "has not completed.\n");
 888                        goto out;
 889                }
 890
 891                /*
 892                 * The AutoNeg process has completed, so we now need to
 893                 * read both the Auto Negotiation Advertisement
 894                 * Register (Address 4) and the Auto_Negotiation Base
 895                 * Page Ability Register (Address 5) to determine how
 896                 * flow control was negotiated.
 897                 */
 898                ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
 899                                            &mii_nway_adv_reg);
 900                if (ret_val)
 901                        goto out;
 902                ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
 903                                            &mii_nway_lp_ability_reg);
 904                if (ret_val)
 905                        goto out;
 906
 907                /*
 908                 * Two bits in the Auto Negotiation Advertisement Register
 909                 * (Address 4) and two bits in the Auto Negotiation Base
 910                 * Page Ability Register (Address 5) determine flow control
 911                 * for both the PHY and the link partner.  The following
 912                 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
 913                 * 1999, describes these PAUSE resolution bits and how flow
 914                 * control is determined based upon these settings.
 915                 * NOTE:  DC = Don't Care
 916                 *
 917                 *   LOCAL DEVICE  |   LINK PARTNER
 918                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
 919                 *-------|---------|-------|---------|--------------------
 920                 *   0   |    0    |  DC   |   DC    | e1000_fc_none
 921                 *   0   |    1    |   0   |   DC    | e1000_fc_none
 922                 *   0   |    1    |   1   |    0    | e1000_fc_none
 923                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 924                 *   1   |    0    |   0   |   DC    | e1000_fc_none
 925                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
 926                 *   1   |    1    |   0   |    0    | e1000_fc_none
 927                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 928                 *
 929                 * Are both PAUSE bits set to 1?  If so, this implies
 930                 * Symmetric Flow Control is enabled at both ends.  The
 931                 * ASM_DIR bits are irrelevant per the spec.
 932                 *
 933                 * For Symmetric Flow Control:
 934                 *
 935                 *   LOCAL DEVICE  |   LINK PARTNER
 936                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 937                 *-------|---------|-------|---------|--------------------
 938                 *   1   |   DC    |   1   |   DC    | E1000_fc_full
 939                 *
 940                 */
 941                if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 942                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
 943                        /*
 944                         * Now we need to check if the user selected RX ONLY
 945                         * of pause frames.  In this case, we had to advertise
 946                         * FULL flow control because we could not advertise RX
 947                         * ONLY. Hence, we must now check to see if we need to
 948                         * turn OFF  the TRANSMISSION of PAUSE frames.
 949                         */
 950                        if (hw->fc.requested_mode == e1000_fc_full) {
 951                                hw->fc.current_mode = e1000_fc_full;
 952                                hw_dbg("Flow Control = FULL.\r\n");
 953                        } else {
 954                                hw->fc.current_mode = e1000_fc_rx_pause;
 955                                hw_dbg("Flow Control = "
 956                                       "RX PAUSE frames only.\r\n");
 957                        }
 958                }
 959                /*
 960                 * For receiving PAUSE frames ONLY.
 961                 *
 962                 *   LOCAL DEVICE  |   LINK PARTNER
 963                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 964                 *-------|---------|-------|---------|--------------------
 965                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 966                 */
 967                else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 968                          (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
 969                          (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
 970                          (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 971                        hw->fc.current_mode = e1000_fc_tx_pause;
 972                        hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
 973                }
 974                /*
 975                 * For transmitting PAUSE frames ONLY.
 976                 *
 977                 *   LOCAL DEVICE  |   LINK PARTNER
 978                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 979                 *-------|---------|-------|---------|--------------------
 980                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 981                 */
 982                else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 983                         (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
 984                         !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
 985                         (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 986                        hw->fc.current_mode = e1000_fc_rx_pause;
 987                        hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
 988                }
 989                /*
 990                 * Per the IEEE spec, at this point flow control should be
 991                 * disabled.  However, we want to consider that we could
 992                 * be connected to a legacy switch that doesn't advertise
 993                 * desired flow control, but can be forced on the link
 994                 * partner.  So if we advertised no flow control, that is
 995                 * what we will resolve to.  If we advertised some kind of
 996                 * receive capability (Rx Pause Only or Full Flow Control)
 997                 * and the link partner advertised none, we will configure
 998                 * ourselves to enable Rx Flow Control only.  We can do
 999                 * this safely for two reasons:  If the link partner really
1000                 * didn't want flow control enabled, and we enable Rx, no
1001                 * harm done since we won't be receiving any PAUSE frames
1002                 * anyway.  If the intent on the link partner was to have
1003                 * flow control enabled, then by us enabling RX only, we
1004                 * can at least receive pause frames and process them.
1005                 * This is a good idea because in most cases, since we are
1006                 * predominantly a server NIC, more times than not we will
1007                 * be asked to delay transmission of packets than asking
1008                 * our link partner to pause transmission of frames.
1009                 */
1010                else if ((hw->fc.requested_mode == e1000_fc_none ||
1011                          hw->fc.requested_mode == e1000_fc_tx_pause) ||
1012                         hw->fc.strict_ieee) {
1013                        hw->fc.current_mode = e1000_fc_none;
1014                        hw_dbg("Flow Control = NONE.\r\n");
1015                } else {
1016                        hw->fc.current_mode = e1000_fc_rx_pause;
1017                        hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
1018                }
1019
1020                /*
1021                 * Now we need to do one last check...  If we auto-
1022                 * negotiated to HALF DUPLEX, flow control should not be
1023                 * enabled per IEEE 802.3 spec.
1024                 */
1025                ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
1026                if (ret_val) {
1027                        hw_dbg("Error getting link speed and duplex\n");
1028                        goto out;
1029                }
1030
1031                if (duplex == HALF_DUPLEX)
1032                        hw->fc.current_mode = e1000_fc_none;
1033
1034                /*
1035                 * Now we call a subroutine to actually force the MAC
1036                 * controller to use the correct flow control settings.
1037                 */
1038                ret_val = igb_force_mac_fc(hw);
1039                if (ret_val) {
1040                        hw_dbg("Error forcing flow control settings\n");
1041                        goto out;
1042                }
1043        }
1044        /* Check for the case where we have SerDes media and auto-neg is
1045         * enabled.  In this case, we need to check and see if Auto-Neg
1046         * has completed, and if so, how the PHY and link partner has
1047         * flow control configured.
1048         */
1049        if ((hw->phy.media_type == e1000_media_type_internal_serdes)
1050                && mac->autoneg) {
1051                /* Read the PCS_LSTS and check to see if AutoNeg
1052                 * has completed.
1053                 */
1054                pcs_status_reg = rd32(E1000_PCS_LSTAT);
1055
1056                if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1057                        hw_dbg("PCS Auto Neg has not completed.\n");
1058                        return ret_val;
1059                }
1060
1061                /* The AutoNeg process has completed, so we now need to
1062                 * read both the Auto Negotiation Advertisement
1063                 * Register (PCS_ANADV) and the Auto_Negotiation Base
1064                 * Page Ability Register (PCS_LPAB) to determine how
1065                 * flow control was negotiated.
1066                 */
1067                pcs_adv_reg = rd32(E1000_PCS_ANADV);
1068                pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
1069
1070                /* Two bits in the Auto Negotiation Advertisement Register
1071                 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1072                 * Page Ability Register (PCS_LPAB) determine flow control
1073                 * for both the PHY and the link partner.  The following
1074                 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1075                 * 1999, describes these PAUSE resolution bits and how flow
1076                 * control is determined based upon these settings.
1077                 * NOTE:  DC = Don't Care
1078                 *
1079                 *   LOCAL DEVICE  |   LINK PARTNER
1080                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1081                 *-------|---------|-------|---------|--------------------
1082                 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1083                 *   0   |    1    |   0   |   DC    | e1000_fc_none
1084                 *   0   |    1    |   1   |    0    | e1000_fc_none
1085                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1086                 *   1   |    0    |   0   |   DC    | e1000_fc_none
1087                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1088                 *   1   |    1    |   0   |    0    | e1000_fc_none
1089                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1090                 *
1091                 * Are both PAUSE bits set to 1?  If so, this implies
1092                 * Symmetric Flow Control is enabled at both ends.  The
1093                 * ASM_DIR bits are irrelevant per the spec.
1094                 *
1095                 * For Symmetric Flow Control:
1096                 *
1097                 *   LOCAL DEVICE  |   LINK PARTNER
1098                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1099                 *-------|---------|-------|---------|--------------------
1100                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1101                 *
1102                 */
1103                if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1104                    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1105                        /* Now we need to check if the user selected Rx ONLY
1106                         * of pause frames.  In this case, we had to advertise
1107                         * FULL flow control because we could not advertise Rx
1108                         * ONLY. Hence, we must now check to see if we need to
1109                         * turn OFF the TRANSMISSION of PAUSE frames.
1110                         */
1111                        if (hw->fc.requested_mode == e1000_fc_full) {
1112                                hw->fc.current_mode = e1000_fc_full;
1113                                hw_dbg("Flow Control = FULL.\n");
1114                        } else {
1115                                hw->fc.current_mode = e1000_fc_rx_pause;
1116                                hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1117                        }
1118                }
1119                /* For receiving PAUSE frames ONLY.
1120                 *
1121                 *   LOCAL DEVICE  |   LINK PARTNER
1122                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1123                 *-------|---------|-------|---------|--------------------
1124                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1125                 */
1126                else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1127                          (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1128                          (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1129                          (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1130                        hw->fc.current_mode = e1000_fc_tx_pause;
1131                        hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1132                }
1133                /* For transmitting PAUSE frames ONLY.
1134                 *
1135                 *   LOCAL DEVICE  |   LINK PARTNER
1136                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1137                 *-------|---------|-------|---------|--------------------
1138                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1139                 */
1140                else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1141                         (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1142                         !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1143                         (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1144                        hw->fc.current_mode = e1000_fc_rx_pause;
1145                        hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1146                } else {
1147                        /* Per the IEEE spec, at this point flow control
1148                         * should be disabled.
1149                         */
1150                        hw->fc.current_mode = e1000_fc_none;
1151                        hw_dbg("Flow Control = NONE.\n");
1152                }
1153
1154                /* Now we call a subroutine to actually force the MAC
1155                 * controller to use the correct flow control settings.
1156                 */
1157                pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
1158                pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1159                wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
1160
1161                ret_val = igb_force_mac_fc(hw);
1162                if (ret_val) {
1163                        hw_dbg("Error forcing flow control settings\n");
1164                        return ret_val;
1165                }
1166        }
1167
1168out:
1169        return ret_val;
1170}
1171
1172/**
1173 *  igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1174 *  @hw: pointer to the HW structure
1175 *  @speed: stores the current speed
1176 *  @duplex: stores the current duplex
1177 *
1178 *  Read the status register for the current speed/duplex and store the current
1179 *  speed and duplex for copper connections.
1180 **/
1181s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1182                                      u16 *duplex)
1183{
1184        u32 status;
1185
1186        status = rd32(E1000_STATUS);
1187        if (status & E1000_STATUS_SPEED_1000) {
1188                *speed = SPEED_1000;
1189                hw_dbg("1000 Mbs, ");
1190        } else if (status & E1000_STATUS_SPEED_100) {
1191                *speed = SPEED_100;
1192                hw_dbg("100 Mbs, ");
1193        } else {
1194                *speed = SPEED_10;
1195                hw_dbg("10 Mbs, ");
1196        }
1197
1198        if (status & E1000_STATUS_FD) {
1199                *duplex = FULL_DUPLEX;
1200                hw_dbg("Full Duplex\n");
1201        } else {
1202                *duplex = HALF_DUPLEX;
1203                hw_dbg("Half Duplex\n");
1204        }
1205
1206        return 0;
1207}
1208
1209/**
1210 *  igb_get_hw_semaphore - Acquire hardware semaphore
1211 *  @hw: pointer to the HW structure
1212 *
1213 *  Acquire the HW semaphore to access the PHY or NVM
1214 **/
1215s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1216{
1217        u32 swsm;
1218        s32 ret_val = 0;
1219        s32 timeout = hw->nvm.word_size + 1;
1220        s32 i = 0;
1221
1222        /* Get the SW semaphore */
1223        while (i < timeout) {
1224                swsm = rd32(E1000_SWSM);
1225                if (!(swsm & E1000_SWSM_SMBI))
1226                        break;
1227
1228                udelay(50);
1229                i++;
1230        }
1231
1232        if (i == timeout) {
1233                hw_dbg("Driver can't access device - SMBI bit is set.\n");
1234                ret_val = -E1000_ERR_NVM;
1235                goto out;
1236        }
1237
1238        /* Get the FW semaphore. */
1239        for (i = 0; i < timeout; i++) {
1240                swsm = rd32(E1000_SWSM);
1241                wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1242
1243                /* Semaphore acquired if bit latched */
1244                if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
1245                        break;
1246
1247                udelay(50);
1248        }
1249
1250        if (i == timeout) {
1251                /* Release semaphores */
1252                igb_put_hw_semaphore(hw);
1253                hw_dbg("Driver can't access the NVM\n");
1254                ret_val = -E1000_ERR_NVM;
1255                goto out;
1256        }
1257
1258out:
1259        return ret_val;
1260}
1261
1262/**
1263 *  igb_put_hw_semaphore - Release hardware semaphore
1264 *  @hw: pointer to the HW structure
1265 *
1266 *  Release hardware semaphore used to access the PHY or NVM
1267 **/
1268void igb_put_hw_semaphore(struct e1000_hw *hw)
1269{
1270        u32 swsm;
1271
1272        swsm = rd32(E1000_SWSM);
1273
1274        swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1275
1276        wr32(E1000_SWSM, swsm);
1277}
1278
1279/**
1280 *  igb_get_auto_rd_done - Check for auto read completion
1281 *  @hw: pointer to the HW structure
1282 *
1283 *  Check EEPROM for Auto Read done bit.
1284 **/
1285s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1286{
1287        s32 i = 0;
1288        s32 ret_val = 0;
1289
1290
1291        while (i < AUTO_READ_DONE_TIMEOUT) {
1292                if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
1293                        break;
1294                msleep(1);
1295                i++;
1296        }
1297
1298        if (i == AUTO_READ_DONE_TIMEOUT) {
1299                hw_dbg("Auto read by HW from NVM has not completed.\n");
1300                ret_val = -E1000_ERR_RESET;
1301                goto out;
1302        }
1303
1304out:
1305        return ret_val;
1306}
1307
1308/**
1309 *  igb_valid_led_default - Verify a valid default LED config
1310 *  @hw: pointer to the HW structure
1311 *  @data: pointer to the NVM (EEPROM)
1312 *
1313 *  Read the EEPROM for the current default LED configuration.  If the
1314 *  LED configuration is not valid, set to a valid LED configuration.
1315 **/
1316static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1317{
1318        s32 ret_val;
1319
1320        ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1321        if (ret_val) {
1322                hw_dbg("NVM Read Error\n");
1323                goto out;
1324        }
1325
1326        if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1327                switch(hw->phy.media_type) {
1328                case e1000_media_type_internal_serdes:
1329                        *data = ID_LED_DEFAULT_82575_SERDES;
1330                        break;
1331                case e1000_media_type_copper:
1332                default:
1333                        *data = ID_LED_DEFAULT;
1334                        break;
1335                }
1336        }
1337out:
1338        return ret_val;
1339}
1340
1341/**
1342 *  igb_id_led_init -
1343 *  @hw: pointer to the HW structure
1344 *
1345 **/
1346s32 igb_id_led_init(struct e1000_hw *hw)
1347{
1348        struct e1000_mac_info *mac = &hw->mac;
1349        s32 ret_val;
1350        const u32 ledctl_mask = 0x000000FF;
1351        const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1352        const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1353        u16 data, i, temp;
1354        const u16 led_mask = 0x0F;
1355
1356        ret_val = igb_valid_led_default(hw, &data);
1357        if (ret_val)
1358                goto out;
1359
1360        mac->ledctl_default = rd32(E1000_LEDCTL);
1361        mac->ledctl_mode1 = mac->ledctl_default;
1362        mac->ledctl_mode2 = mac->ledctl_default;
1363
1364        for (i = 0; i < 4; i++) {
1365                temp = (data >> (i << 2)) & led_mask;
1366                switch (temp) {
1367                case ID_LED_ON1_DEF2:
1368                case ID_LED_ON1_ON2:
1369                case ID_LED_ON1_OFF2:
1370                        mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1371                        mac->ledctl_mode1 |= ledctl_on << (i << 3);
1372                        break;
1373                case ID_LED_OFF1_DEF2:
1374                case ID_LED_OFF1_ON2:
1375                case ID_LED_OFF1_OFF2:
1376                        mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1377                        mac->ledctl_mode1 |= ledctl_off << (i << 3);
1378                        break;
1379                default:
1380                        /* Do nothing */
1381                        break;
1382                }
1383                switch (temp) {
1384                case ID_LED_DEF1_ON2:
1385                case ID_LED_ON1_ON2:
1386                case ID_LED_OFF1_ON2:
1387                        mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1388                        mac->ledctl_mode2 |= ledctl_on << (i << 3);
1389                        break;
1390                case ID_LED_DEF1_OFF2:
1391                case ID_LED_ON1_OFF2:
1392                case ID_LED_OFF1_OFF2:
1393                        mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1394                        mac->ledctl_mode2 |= ledctl_off << (i << 3);
1395                        break;
1396                default:
1397                        /* Do nothing */
1398                        break;
1399                }
1400        }
1401
1402out:
1403        return ret_val;
1404}
1405
1406/**
1407 *  igb_cleanup_led - Set LED config to default operation
1408 *  @hw: pointer to the HW structure
1409 *
1410 *  Remove the current LED configuration and set the LED configuration
1411 *  to the default value, saved from the EEPROM.
1412 **/
1413s32 igb_cleanup_led(struct e1000_hw *hw)
1414{
1415        wr32(E1000_LEDCTL, hw->mac.ledctl_default);
1416        return 0;
1417}
1418
1419/**
1420 *  igb_blink_led - Blink LED
1421 *  @hw: pointer to the HW structure
1422 *
1423 *  Blink the led's which are set to be on.
1424 **/
1425s32 igb_blink_led(struct e1000_hw *hw)
1426{
1427        u32 ledctl_blink = 0;
1428        u32 i;
1429
1430        /*
1431         * set the blink bit for each LED that's "on" (0x0E)
1432         * in ledctl_mode2
1433         */
1434        ledctl_blink = hw->mac.ledctl_mode2;
1435        for (i = 0; i < 4; i++)
1436                if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1437                    E1000_LEDCTL_MODE_LED_ON)
1438                        ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1439                                         (i * 8));
1440
1441        wr32(E1000_LEDCTL, ledctl_blink);
1442
1443        return 0;
1444}
1445
1446/**
1447 *  igb_led_off - Turn LED off
1448 *  @hw: pointer to the HW structure
1449 *
1450 *  Turn LED off.
1451 **/
1452s32 igb_led_off(struct e1000_hw *hw)
1453{
1454        switch (hw->phy.media_type) {
1455        case e1000_media_type_copper:
1456                wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1457                break;
1458        default:
1459                break;
1460        }
1461
1462        return 0;
1463}
1464
1465/**
1466 *  igb_disable_pcie_master - Disables PCI-express master access
1467 *  @hw: pointer to the HW structure
1468 *
1469 *  Returns 0 (0) if successful, else returns -10
1470 *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1471 *  the master requests to be disabled.
1472 *
1473 *  Disables PCI-Express master access and verifies there are no pending
1474 *  requests.
1475 **/
1476s32 igb_disable_pcie_master(struct e1000_hw *hw)
1477{
1478        u32 ctrl;
1479        s32 timeout = MASTER_DISABLE_TIMEOUT;
1480        s32 ret_val = 0;
1481
1482        if (hw->bus.type != e1000_bus_type_pci_express)
1483                goto out;
1484
1485        ctrl = rd32(E1000_CTRL);
1486        ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1487        wr32(E1000_CTRL, ctrl);
1488
1489        while (timeout) {
1490                if (!(rd32(E1000_STATUS) &
1491                      E1000_STATUS_GIO_MASTER_ENABLE))
1492                        break;
1493                udelay(100);
1494                timeout--;
1495        }
1496
1497        if (!timeout) {
1498                hw_dbg("Master requests are pending.\n");
1499                ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1500                goto out;
1501        }
1502
1503out:
1504        return ret_val;
1505}
1506
1507/**
1508 *  igb_validate_mdi_setting - Verify MDI/MDIx settings
1509 *  @hw: pointer to the HW structure
1510 *
1511 *  Verify that when not using auto-negotitation that MDI/MDIx is correctly
1512 *  set, which is forced to MDI mode only.
1513 **/
1514s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1515{
1516        s32 ret_val = 0;
1517
1518        /* All MDI settings are supported on 82580 and newer. */
1519        if (hw->mac.type >= e1000_82580)
1520                goto out;
1521
1522        if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1523                hw_dbg("Invalid MDI setting detected\n");
1524                hw->phy.mdix = 1;
1525                ret_val = -E1000_ERR_CONFIG;
1526                goto out;
1527        }
1528
1529out:
1530        return ret_val;
1531}
1532
1533/**
1534 *  igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1535 *  @hw: pointer to the HW structure
1536 *  @reg: 32bit register offset such as E1000_SCTL
1537 *  @offset: register offset to write to
1538 *  @data: data to write at register offset
1539 *
1540 *  Writes an address/data control type register.  There are several of these
1541 *  and they all have the format address << 8 | data and bit 31 is polled for
1542 *  completion.
1543 **/
1544s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1545                              u32 offset, u8 data)
1546{
1547        u32 i, regvalue = 0;
1548        s32 ret_val = 0;
1549
1550        /* Set up the address and data */
1551        regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1552        wr32(reg, regvalue);
1553
1554        /* Poll the ready bit to see if the MDI read completed */
1555        for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1556                udelay(5);
1557                regvalue = rd32(reg);
1558                if (regvalue & E1000_GEN_CTL_READY)
1559                        break;
1560        }
1561        if (!(regvalue & E1000_GEN_CTL_READY)) {
1562                hw_dbg("Reg %08x did not indicate ready\n", reg);
1563                ret_val = -E1000_ERR_PHY;
1564                goto out;
1565        }
1566
1567out:
1568        return ret_val;
1569}
1570
1571/**
1572 *  igb_enable_mng_pass_thru - Enable processing of ARP's
1573 *  @hw: pointer to the HW structure
1574 *
1575 *  Verifies the hardware needs to leave interface enabled so that frames can
1576 *  be directed to and from the management interface.
1577 **/
1578bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
1579{
1580        u32 manc;
1581        u32 fwsm, factps;
1582        bool ret_val = false;
1583
1584        if (!hw->mac.asf_firmware_present)
1585                goto out;
1586
1587        manc = rd32(E1000_MANC);
1588
1589        if (!(manc & E1000_MANC_RCV_TCO_EN))
1590                goto out;
1591
1592        if (hw->mac.arc_subsystem_valid) {
1593                fwsm = rd32(E1000_FWSM);
1594                factps = rd32(E1000_FACTPS);
1595
1596                if (!(factps & E1000_FACTPS_MNGCG) &&
1597                    ((fwsm & E1000_FWSM_MODE_MASK) ==
1598                     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
1599                        ret_val = true;
1600                        goto out;
1601                }
1602        } else {
1603                if ((manc & E1000_MANC_SMBUS_EN) &&
1604                    !(manc & E1000_MANC_ASF_EN)) {
1605                        ret_val = true;
1606                        goto out;
1607                }
1608        }
1609
1610out:
1611        return ret_val;
1612}
1613