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39
40#ifndef _CASSINI_H
41#define _CASSINI_H
42
43
44
45
46
47
48#define CAS_ID_REV2 0x02
49#define CAS_ID_REVPLUS 0x10
50#define CAS_ID_REVPLUS02u 0x11
51#define CAS_ID_REVSATURNB2 0x30
52
53
54
55
56
57
58
59
60
61#define REG_CAWR 0x0004
62#define CAWR_RX_DMA_WEIGHT_SHIFT 0
63#define CAWR_RX_DMA_WEIGHT_MASK 0x03
64#define CAWR_TX_DMA_WEIGHT_SHIFT 2
65#define CAWR_TX_DMA_WEIGHT_MASK 0x0C
66#define CAWR_RR_DIS 0x10
67
68
69
70
71
72
73#define REG_INF_BURST 0x0008
74#define INF_BURST_EN 0x1
75
76
77
78
79
80
81#define REG_INTR_STATUS 0x000C
82#define INTR_TX_INTME 0x00000001
83
84
85#define INTR_TX_ALL 0x00000002
86
87
88
89
90#define INTR_TX_DONE 0x00000004
91
92#define INTR_TX_TAG_ERROR 0x00000008
93
94#define INTR_RX_DONE 0x00000010
95
96
97
98
99#define INTR_RX_BUF_UNAVAIL 0x00000020
100
101#define INTR_RX_TAG_ERROR 0x00000040
102
103#define INTR_RX_COMP_FULL 0x00000080
104
105
106
107
108#define INTR_RX_BUF_AE 0x00000100
109
110
111
112#define INTR_RX_COMP_AF 0x00000200
113
114
115
116
117#define INTR_RX_LEN_MISMATCH 0x00000400
118
119
120
121
122
123
124#define INTR_SUMMARY 0x00001000
125
126
127
128
129#define INTR_PCS_STATUS 0x00002000
130#define INTR_TX_MAC_STATUS 0x00004000
131
132#define INTR_RX_MAC_STATUS 0x00008000
133
134#define INTR_MAC_CTRL_STATUS 0x00010000
135
136
137#define INTR_MIF_STATUS 0x00020000
138
139#define INTR_PCI_ERROR_STATUS 0x00040000
140
141
142#define INTR_TX_COMP_3_MASK 0xFFF80000
143
144#define INTR_TX_COMP_3_SHIFT 19
145#define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
146 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
147 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
148 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
149 INTR_MAC_CTRL_STATUS)
150
151
152
153
154
155#define REG_INTR_MASK 0x0010
156
157
158
159
160
161#define REG_ALIAS_CLEAR 0x0014
162
163
164
165
166
167#define REG_INTR_STATUS_ALIAS 0x001C
168
169
170
171#define REG_PCI_ERR_STATUS 0x1000
172#define PCI_ERR_BADACK 0x01
173
174
175#define PCI_ERR_DTRTO 0x02
176
177#define PCI_ERR_OTHER 0x04
178#define PCI_ERR_BIM_DMA_WRITE 0x08
179
180#define PCI_ERR_BIM_DMA_READ 0x10
181
182#define PCI_ERR_BIM_DMA_TIMEOUT 0x20
183
184
185
186
187
188
189#define REG_PCI_ERR_STATUS_MASK 0x1004
190
191
192
193
194#define REG_BIM_CFG 0x1008
195#define BIM_CFG_RESERVED0 0x001
196#define BIM_CFG_RESERVED1 0x002
197#define BIM_CFG_64BIT_DISABLE 0x004
198#define BIM_CFG_66MHZ 0x008
199#define BIM_CFG_32BIT 0x010
200#define BIM_CFG_DPAR_INTR_ENABLE 0x020
201#define BIM_CFG_RMA_INTR_ENABLE 0x040
202#define BIM_CFG_RTA_INTR_ENABLE 0x080
203#define BIM_CFG_RESERVED2 0x100
204#define BIM_CFG_BIM_DISABLE 0x200
205
206#define BIM_CFG_BIM_STATUS 0x400
207
208#define BIM_CFG_PERROR_BLOCK 0x800
209
210
211
212#define REG_BIM_DIAG 0x100C
213#define BIM_DIAG_MSTR_SM_MASK 0x3FFFFF00
214
215#define BIM_DIAG_BRST_SM_MASK 0x7F
216
217
218
219
220
221#define REG_SW_RESET 0x1010
222#define SW_RESET_TX 0x00000001
223
224#define SW_RESET_RX 0x00000002
225
226#define SW_RESET_RSTOUT 0x00000004
227
228
229
230
231
232#define SW_RESET_BLOCK_PCS_SLINK 0x00000008
233
234
235
236#define SW_RESET_BREQ_SM_MASK 0x00007F00
237#define SW_RESET_PCIARB_SM_MASK 0x00070000
238
239
240
241
242
243
244
245
246#define SW_RESET_RDPCI_SM_MASK 0x00300000
247
248
249
250#define SW_RESET_RDARB_SM_MASK 0x00C00000
251
252
253
254
255#define SW_RESET_WRPCI_SM_MASK 0x06000000
256
257
258
259#define SW_RESET_WRARB_SM_MASK 0x38000000
260
261
262
263
264
265
266
267
268
269
270
271#define REG_MINUS_BIM_DATAPATH_TEST 0x1018
272
273
274
275
276
277
278
279#define REG_BIM_LOCAL_DEV_EN 0x1020
280
281#define BIM_LOCAL_DEV_PAD 0x01
282
283
284
285
286#define BIM_LOCAL_DEV_PROM 0x02
287#define BIM_LOCAL_DEV_EXT 0x04
288
289#define BIM_LOCAL_DEV_SOFT_0 0x08
290#define BIM_LOCAL_DEV_SOFT_1 0x10
291#define BIM_LOCAL_DEV_HW_RESET 0x20
292
293
294
295
296
297
298#define REG_BIM_BUFFER_ADDR 0x1024
299
300#define BIM_BUFFER_ADDR_MASK 0x3F
301#define BIM_BUFFER_WR_SELECT 0x40
302
303
304#define REG_BIM_BUFFER_DATA_LOW 0x1028
305#define REG_BIM_BUFFER_DATA_HI 0x102C
306
307
308
309
310#define REG_BIM_RAM_BIST 0x102C
311
312#define BIM_RAM_BIST_RD_START 0x01
313#define BIM_RAM_BIST_WR_START 0x02
314
315
316#define BIM_RAM_BIST_RD_PASS 0x04
317
318#define BIM_RAM_BIST_WR_PASS 0x08
319
320
321#define BIM_RAM_BIST_RD_LOW_PASS 0x10
322#define BIM_RAM_BIST_RD_HI_PASS 0x20
323#define BIM_RAM_BIST_WR_LOW_PASS 0x40
324
325
326#define BIM_RAM_BIST_WR_HI_PASS 0x80
327
328
329
330
331
332
333#define REG_BIM_DIAG_MUX 0x1030
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355#define REG_PLUS_PROBE_MUX_SELECT 0x1034
356#define PROBE_MUX_EN 0x80000000
357
358
359#define PROBE_MUX_SUB_MUX_MASK 0x0000FF00
360
361
362
363
364#define PROBE_MUX_SEL_HI_MASK 0x000000F0
365
366
367#define PROBE_MUX_SEL_LOW_MASK 0x0000000F
368
369
370
371
372
373#define REG_PLUS_INTR_MASK_1 0x1038
374
375#define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
376
377
378
379
380
381#define INTR_RX_DONE_ALT 0x01
382#define INTR_RX_COMP_FULL_ALT 0x02
383#define INTR_RX_COMP_AF_ALT 0x04
384#define INTR_RX_BUF_UNAVAIL_1 0x08
385#define INTR_RX_BUF_AE_1 0x10
386#define INTRN_MASK_RX_EN 0x80
387#define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
388 INTR_RX_COMP_FULL_ALT | \
389 INTR_RX_COMP_AF_ALT | \
390 INTR_RX_BUF_UNAVAIL_1 | \
391 INTR_RX_BUF_AE_1)
392#define REG_PLUS_INTR_STATUS_1 0x103C
393
394#define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
395#define INTR_STATUS_ALT_INTX_EN 0x80
396
397
398#define REG_PLUS_ALIAS_CLEAR_1 0x1040
399
400#define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
401
402#define REG_PLUS_INTR_STATUS_ALIAS_1 0x1044
403
404#define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
405
406#define REG_SATURN_PCFG 0x106c
407
408
409#define SATURN_PCFG_TLA 0x00000001
410#define SATURN_PCFG_FLA 0x00000002
411#define SATURN_PCFG_CLA 0x00000004
412#define SATURN_PCFG_LLA 0x00000008
413#define SATURN_PCFG_RLA 0x00000010
414#define SATURN_PCFG_PDS 0x00000020
415
416#define SATURN_PCFG_MTP 0x00000080
417#define SATURN_PCFG_GMO 0x00000100
418
419
420#define SATURN_PCFG_FSI 0x00000200
421
422
423
424#define SATURN_PCFG_LAD 0x00000800
425
426
427
428
429
430
431
432#define MAX_TX_RINGS_SHIFT 2
433#define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
434#define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
435
436
437
438
439
440#define REG_TX_CFG 0x2004
441#define TX_CFG_DMA_EN 0x00000001
442
443
444#define TX_CFG_FIFO_PIO_SEL 0x00000002
445
446
447
448
449#define TX_CFG_DESC_RING0_MASK 0x0000003C
450
451#define TX_CFG_DESC_RING0_SHIFT 2
452#define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
453#define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
454#define TX_CFG_PACED_MODE 0x00100000
455
456
457
458#define TX_CFG_DMA_RDPIPE_DIS 0x01000000
459#define TX_CFG_COMPWB_Q1 0x02000000
460
461
462#define TX_CFG_COMPWB_Q2 0x04000000
463
464
465#define TX_CFG_COMPWB_Q3 0x08000000
466
467
468#define TX_CFG_COMPWB_Q4 0x10000000
469
470
471#define TX_CFG_INTR_COMPWB_DIS 0x20000000
472
473#define TX_CFG_CTX_SEL_MASK 0xC0000000
474
475
476
477
478
479
480
481
482
483
484
485
486#define TX_CFG_CTX_SEL_SHIFT 30
487
488
489
490
491#define REG_TX_FIFO_WRITE_PTR 0x2014
492#define REG_TX_FIFO_SHADOW_WRITE_PTR 0x2018
493
494
495#define REG_TX_FIFO_READ_PTR 0x201C
496#define REG_TX_FIFO_SHADOW_READ_PTR 0x2020
497
498
499
500#define REG_TX_FIFO_PKT_CNT 0x2024
501
502
503#define REG_TX_SM_1 0x2028
504#define TX_SM_1_CHAIN_MASK 0x000003FF
505#define TX_SM_1_CSUM_MASK 0x00000C00
506#define TX_SM_1_FIFO_LOAD_MASK 0x0003F000
507
508#define TX_SM_1_FIFO_UNLOAD_MASK 0x003C0000
509#define TX_SM_1_CACHE_MASK 0x03C00000
510
511#define TX_SM_1_CBQ_ARB_MASK 0xF8000000
512
513#define REG_TX_SM_2 0x202C
514#define TX_SM_2_COMP_WB_MASK 0x07
515#define TX_SM_2_SUB_LOAD_MASK 0x38
516#define TX_SM_2_KICK_MASK 0xC0
517
518
519
520
521#define REG_TX_DATA_PTR_LOW 0x2030
522#define REG_TX_DATA_PTR_HI 0x2034
523
524
525
526
527
528
529
530#define REG_TX_KICK0 0x2038
531#define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
532#define REG_TX_COMP0 0x2048
533#define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551#define TX_COMPWB_SIZE 8
552#define REG_TX_COMPWB_DB_LOW 0x2058
553
554#define REG_TX_COMPWB_DB_HI 0x205C
555
556#define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
557#define TX_COMPWB_MSB_SHIFT 0
558#define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
559#define TX_COMPWB_LSB_SHIFT 8
560#define TX_COMPWB_NEXT(x) ((x) >> 16)
561
562
563
564#define REG_TX_DB0_LOW 0x2060
565#define REG_TX_DB0_HI 0x2064
566#define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
567#define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
568
569
570
571
572
573
574
575
576
577
578#define REG_TX_MAXBURST_0 0x2080
579#define REG_TX_MAXBURST_1 0x2084
580#define REG_TX_MAXBURST_2 0x2088
581#define REG_TX_MAXBURST_3 0x208C
582
583
584
585
586
587
588
589
590#define REG_TX_FIFO_ADDR 0x2104
591#define REG_TX_FIFO_TAG 0x2108
592#define REG_TX_FIFO_DATA_LOW 0x210C
593#define REG_TX_FIFO_DATA_HI_T1 0x2110
594#define REG_TX_FIFO_DATA_HI_T0 0x2114
595#define REG_TX_FIFO_SIZE 0x2118
596
597
598
599
600#define REG_TX_RAMBIST 0x211C
601#define TX_RAMBIST_STATE 0x01C0
602
603#define TX_RAMBIST_RAM33A_PASS 0x0020
604#define TX_RAMBIST_RAM32A_PASS 0x0010
605#define TX_RAMBIST_RAM33B_PASS 0x0008
606#define TX_RAMBIST_RAM32B_PASS 0x0004
607#define TX_RAMBIST_SUMMARY 0x0002
608#define TX_RAMBIST_START 0x0001
609
610
611
612#define MAX_RX_DESC_RINGS 2
613#define MAX_RX_COMP_RINGS 4
614
615
616
617
618
619
620#define REG_RX_CFG 0x4000
621#define RX_CFG_DMA_EN 0x00000001
622
623
624
625
626
627#define RX_CFG_DESC_RING_MASK 0x0000001E
628
629
630#define RX_CFG_DESC_RING_SHIFT 1
631#define RX_CFG_COMP_RING_MASK 0x000001E0
632
633#define RX_CFG_COMP_RING_SHIFT 5
634#define RX_CFG_BATCH_DIS 0x00000200
635
636
637#define RX_CFG_SWIVEL_MASK 0x00001C00
638
639
640
641
642
643
644
645
646#define RX_CFG_SWIVEL_SHIFT 10
647
648
649#define RX_CFG_DESC_RING1_MASK 0x000F0000
650
651
652#define RX_CFG_DESC_RING1_SHIFT 16
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667#define REG_RX_PAGE_SIZE 0x4004
668#define RX_PAGE_SIZE_MASK 0x00000003
669
670
671
672
673
674
675
676#define RX_PAGE_SIZE_SHIFT 0
677#define RX_PAGE_SIZE_MTU_COUNT_MASK 0x00007800
678
679
680#define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
681#define RX_PAGE_SIZE_MTU_STRIDE_MASK 0x18000000
682
683
684
685
686
687
688#define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
689#define RX_PAGE_SIZE_MTU_OFF_MASK 0xC0000000
690
691
692
693
694
695
696#define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
697
698
699
700
701
702#define REG_RX_FIFO_WRITE_PTR 0x4008
703#define REG_RX_FIFO_READ_PTR 0x400C
704#define REG_RX_IPP_FIFO_SHADOW_WRITE_PTR 0x4010
705
706#define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014
707
708#define REG_RX_IPP_FIFO_READ_PTR 0x400C
709
710
711
712
713
714#define REG_RX_DEBUG 0x401C
715#define RX_DEBUG_LOAD_STATE_MASK 0x0000000F
716
717
718
719
720
721
722
723
724
725#define RX_DEBUG_LM_STATE_MASK 0x00000070
726
727
728
729
730
731
732
733
734#define RX_DEBUG_FC_STATE_MASK 0x000000180
735
736
737
738
739
740#define RX_DEBUG_DATA_STATE_MASK 0x000001E00
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758#define RX_DEBUG_DESC_STATE_MASK 0x0001E000
759
760
761
762
763
764
765
766
767
768
769
770#define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000
771
772#define RX_DEBUG_INTR_WRITE_PTR_MASK 0xC0000000
773
774
775
776
777
778
779
780
781
782
783
784#define REG_RX_PAUSE_THRESH 0x4020
785#define RX_PAUSE_THRESH_QUANTUM 64
786#define RX_PAUSE_THRESH_OFF_MASK 0x000001FF
787
788
789#define RX_PAUSE_THRESH_OFF_SHIFT 0
790#define RX_PAUSE_THRESH_ON_MASK 0x001FF000
791
792
793
794
795
796
797#define RX_PAUSE_THRESH_ON_SHIFT 12
798
799
800
801
802
803
804
805#define REG_RX_KICK 0x4024
806
807
808
809
810#define REG_RX_DB_LOW 0x4028
811
812#define REG_RX_DB_HI 0x402C
813
814#define REG_RX_CB_LOW 0x4030
815
816#define REG_RX_CB_HI 0x4034
817
818
819
820
821
822#define REG_RX_COMP 0x4038
823
824
825
826
827
828
829
830
831
832
833
834#define REG_RX_COMP_HEAD 0x403C
835#define REG_RX_COMP_TAIL 0x4040
836
837
838
839
840#define REG_RX_BLANK 0x4044
841
842#define RX_BLANK_INTR_PKT_MASK 0x000001FF
843
844
845
846
847
848#define RX_BLANK_INTR_PKT_SHIFT 0
849#define RX_BLANK_INTR_TIME_MASK 0x3FFFF000
850
851
852
853
854
855
856#define RX_BLANK_INTR_TIME_SHIFT 12
857
858
859
860
861
862#define REG_RX_AE_THRESH 0x4048
863
864#define RX_AE_THRESH_FREE_MASK 0x00001FFF
865
866
867
868#define RX_AE_THRESH_FREE_SHIFT 0
869#define RX_AE_THRESH_COMP_MASK 0x0FFFE000
870
871
872
873
874#define RX_AE_THRESH_COMP_SHIFT 13
875
876
877
878
879
880
881
882#define REG_RX_RED 0x404C
883#define RX_RED_4K_6K_FIFO_MASK 0x000000FF
884#define RX_RED_6K_8K_FIFO_MASK 0x0000FF00
885#define RX_RED_8K_10K_FIFO_MASK 0x00FF0000
886#define RX_RED_10K_12K_FIFO_MASK 0xFF000000
887
888
889
890
891
892#define REG_RX_FIFO_FULLNESS 0x4050
893#define RX_FIFO_FULLNESS_RX_FIFO_MASK 0x3FF80000
894#define RX_FIFO_FULLNESS_IPP_FIFO_MASK 0x0007FF00
895#define RX_FIFO_FULLNESS_RX_PKT_MASK 0x000000FF
896#define REG_RX_IPP_PACKET_COUNT 0x4054
897#define REG_RX_WORK_DMA_PTR_LOW 0x4058
898#define REG_RX_WORK_DMA_PTR_HI 0x405C
899
900
901
902
903
904
905
906#define REG_RX_BIST 0x4060
907#define RX_BIST_32A_PASS 0x80000000
908#define RX_BIST_33A_PASS 0x40000000
909#define RX_BIST_32B_PASS 0x20000000
910#define RX_BIST_33B_PASS 0x10000000
911#define RX_BIST_32C_PASS 0x08000000
912#define RX_BIST_33C_PASS 0x04000000
913#define RX_BIST_IPP_32A_PASS 0x02000000
914#define RX_BIST_IPP_33A_PASS 0x01000000
915#define RX_BIST_IPP_32B_PASS 0x00800000
916#define RX_BIST_IPP_33B_PASS 0x00400000
917#define RX_BIST_IPP_32C_PASS 0x00200000
918#define RX_BIST_IPP_33C_PASS 0x00100000
919#define RX_BIST_CTRL_32_PASS 0x00800000
920#define RX_BIST_CTRL_33_PASS 0x00400000
921#define RX_BIST_REAS_26A_PASS 0x00200000
922#define RX_BIST_REAS_26B_PASS 0x00100000
923#define RX_BIST_REAS_27_PASS 0x00080000
924#define RX_BIST_STATE_MASK 0x00078000
925#define RX_BIST_SUMMARY 0x00000002
926
927
928
929
930#define RX_BIST_START 0x00000001
931
932
933
934
935
936
937
938#define REG_RX_CTRL_FIFO_WRITE_PTR 0x4064
939
940#define REG_RX_CTRL_FIFO_READ_PTR 0x4068
941
942
943
944
945
946
947#define REG_RX_BLANK_ALIAS_READ 0x406C
948
949#define RX_BAR_INTR_PACKET_MASK 0x000001FF
950
951
952
953
954
955
956#define RX_BAR_INTR_TIME_MASK 0x3FFFF000
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971#define REG_RX_FIFO_ADDR 0x4080
972#define REG_RX_FIFO_TAG 0x4084
973#define REG_RX_FIFO_DATA_LOW 0x4088
974#define REG_RX_FIFO_DATA_HI_T0 0x408C
975#define REG_RX_FIFO_DATA_HI_T1 0x4090
976
977
978
979
980
981
982
983
984#define REG_RX_CTRL_FIFO_ADDR 0x4094
985
986#define REG_RX_CTRL_FIFO_DATA_LOW 0x4098
987
988#define REG_RX_CTRL_FIFO_DATA_MID 0x409C
989
990#define REG_RX_CTRL_FIFO_DATA_HI 0x4100
991
992#define RX_CTRL_FIFO_DATA_HI_CTRL 0x0001
993#define RX_CTRL_FIFO_DATA_HI_FLOW_MASK 0x007E
994
995
996
997
998#define REG_RX_IPP_FIFO_ADDR 0x4104
999#define REG_RX_IPP_FIFO_TAG 0x4108
1000#define REG_RX_IPP_FIFO_DATA_LOW 0x410C
1001#define REG_RX_IPP_FIFO_DATA_HI_T0 0x4110
1002
1003#define REG_RX_IPP_FIFO_DATA_HI_T1 0x4114
1004
1005
1006
1007
1008
1009
1010
1011
1012#define REG_RX_HEADER_PAGE_PTR_LOW 0x4118
1013
1014#define REG_RX_HEADER_PAGE_PTR_HI 0x411C
1015
1016#define REG_RX_MTU_PAGE_PTR_LOW 0x4120
1017
1018#define REG_RX_MTU_PAGE_PTR_HI 0x4124
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030#define REG_RX_TABLE_ADDR 0x4128
1031
1032#define RX_TABLE_ADDR_MASK 0x0000003F
1033
1034#define REG_RX_TABLE_DATA_LOW 0x412C
1035
1036#define REG_RX_TABLE_DATA_MID 0x4130
1037
1038#define REG_RX_TABLE_DATA_HI 0x4134
1039
1040
1041
1042
1043
1044
1045#define REG_PLUS_RX_DB1_LOW 0x4200
1046
1047#define REG_PLUS_RX_DB1_HI 0x4204
1048
1049#define REG_PLUS_RX_CB1_LOW 0x4208
1050
1051#define REG_PLUS_RX_CB1_HI 0x420C
1052
1053#define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1054#define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1055#define REG_PLUS_RX_KICK1 0x4220
1056#define REG_PLUS_RX_COMP1 0x4224
1057
1058#define REG_PLUS_RX_COMP1_HEAD 0x4228
1059
1060#define REG_PLUS_RX_COMP1_TAIL 0x422C
1061
1062#define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1063#define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1064#define REG_PLUS_RX_AE1_THRESH 0x4240
1065
1066#define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1067#define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1068
1069
1070
1071
1072
1073
1074#define REG_HP_CFG 0x4140
1075
1076#define HP_CFG_PARSE_EN 0x00000001
1077#define HP_CFG_NUM_CPU_MASK 0x000000FC
1078
1079#define HP_CFG_NUM_CPU_SHIFT 2
1080#define HP_CFG_SYN_INC_MASK 0x00000100
1081
1082
1083#define HP_CFG_TCP_THRESH_MASK 0x000FFE00
1084
1085
1086#define HP_CFG_TCP_THRESH_SHIFT 9
1087
1088
1089
1090
1091
1092
1093
1094#define REG_HP_INSTR_RAM_ADDR 0x4144
1095
1096#define HP_INSTR_RAM_ADDR_MASK 0x01F
1097#define REG_HP_INSTR_RAM_DATA_LOW 0x4148
1098
1099#define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1100#define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1101#define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1102#define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1103#define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1104#define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1105#define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1106#define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1107#define REG_HP_INSTR_RAM_DATA_MID 0x414C
1108
1109#define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1110#define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1111#define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1112#define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1113#define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1114#define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1115#define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1116#define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1117#define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1118#define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1119#define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1120#define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1121#define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1122#define HP_INSTR_RAM_MID_OP_SHIFT 30
1123#define REG_HP_INSTR_RAM_DATA_HI 0x4150
1124
1125#define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1126#define HP_INSTR_RAM_HI_VAL_SHIFT 0
1127#define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1128#define HP_INSTR_RAM_HI_MASK_SHIFT 16
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140#define REG_HP_DATA_RAM_FDB_ADDR 0x4154
1141
1142#define HP_DATA_RAM_FDB_DATA_MASK 0x001F
1143
1144
1145
1146#define HP_DATA_RAM_FDB_FDB_MASK 0x3F00
1147
1148#define REG_HP_DATA_RAM_DATA 0x4158
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159#define REG_HP_FLOW_DB0 0x415C
1160#define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1161
1162
1163
1164
1165
1166#define REG_HP_STATE_MACHINE 0x418C
1167#define REG_HP_STATUS0 0x4190
1168#define HP_STATUS0_SAP_MASK 0xFFFF0000
1169#define HP_STATUS0_L3_OFF_MASK 0x0000FE00
1170#define HP_STATUS0_LB_CPUNUM_MASK 0x000001F8
1171
1172#define HP_STATUS0_HRP_OPCODE_MASK 0x00000007
1173
1174#define REG_HP_STATUS1 0x4194
1175#define HP_STATUS1_ACCUR2_MASK 0xE0000000
1176#define HP_STATUS1_FLOWID_MASK 0x1F800000
1177#define HP_STATUS1_TCP_OFF_MASK 0x007F0000
1178#define HP_STATUS1_TCP_SIZE_MASK 0x0000FFFF
1179
1180#define REG_HP_STATUS2 0x4198
1181#define HP_STATUS2_ACCUR2_MASK 0xF0000000
1182#define HP_STATUS2_CSUM_OFF_MASK 0x07F00000
1183
1184#define HP_STATUS2_ACCUR1_MASK 0x000FE000
1185#define HP_STATUS2_FORCE_DROP 0x00001000
1186#define HP_STATUS2_BWO_REASSM 0x00000800
1187
1188#define HP_STATUS2_JH_SPLIT_EN 0x00000400
1189
1190#define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200
1191
1192#define HP_STATUS2_DATA_MASK_ZERO 0x00000100
1193
1194#define HP_STATUS2_FORCE_TCP_CHECK 0x00000080
1195
1196#define HP_STATUS2_MASK_TCP_THRESH 0x00000040
1197
1198#define HP_STATUS2_NO_ASSIST 0x00000020
1199#define HP_STATUS2_CTRL_PACKET_FLAG 0x00000010
1200#define HP_STATUS2_TCP_FLAG_CHECK 0x00000008
1201#define HP_STATUS2_SYN_FLAG 0x00000004
1202#define HP_STATUS2_TCP_CHECK 0x00000002
1203#define HP_STATUS2_TCP_NOCHECK 0x00000001
1204
1205
1206
1207
1208
1209
1210#define REG_HP_RAM_BIST 0x419C
1211#define HP_RAM_BIST_HP_DATA_PASS 0x80000000
1212#define HP_RAM_BIST_HP_INSTR0_PASS 0x40000000
1213#define HP_RAM_BIST_HP_INSTR1_PASS 0x20000000
1214#define HP_RAM_BIST_HP_INSTR2_PASS 0x10000000
1215#define HP_RAM_BIST_FDBM_AGE0_PASS 0x08000000
1216#define HP_RAM_BIST_FDBM_AGE1_PASS 0x04000000
1217#define HP_RAM_BIST_FDBM_FLOWID00_PASS 0x02000000
1218
1219#define HP_RAM_BIST_FDBM_FLOWID10_PASS 0x01000000
1220
1221#define HP_RAM_BIST_FDBM_FLOWID20_PASS 0x00800000
1222
1223#define HP_RAM_BIST_FDBM_FLOWID30_PASS 0x00400000
1224
1225#define HP_RAM_BIST_FDBM_FLOWID01_PASS 0x00200000
1226
1227#define HP_RAM_BIST_FDBM_FLOWID11_PASS 0x00100000
1228
1229#define HP_RAM_BIST_FDBM_FLOWID21_PASS 0x00080000
1230
1231#define HP_RAM_BIST_FDBM_FLOWID31_PASS 0x00040000
1232
1233#define HP_RAM_BIST_FDBM_TCPSEQ_PASS 0x00020000
1234
1235#define HP_RAM_BIST_SUMMARY 0x00000002
1236#define HP_RAM_BIST_START 0x00000001
1237
1238
1239
1240
1241
1242
1243#define REG_MAC_TX_RESET 0x6000
1244
1245#define REG_MAC_RX_RESET 0x6004
1246
1247
1248
1249#define REG_MAC_SEND_PAUSE 0x6008
1250#define MAC_SEND_PAUSE_TIME_MASK 0x0000FFFF
1251
1252
1253
1254#define MAC_SEND_PAUSE_SEND 0x00010000
1255
1256
1257
1258
1259
1260
1261
1262
1263#define REG_MAC_TX_STATUS 0x6010
1264#define MAC_TX_FRAME_XMIT 0x0001
1265
1266#define MAC_TX_UNDERRUN 0x0002
1267
1268
1269
1270#define MAC_TX_MAX_PACKET_ERR 0x0004
1271
1272
1273#define MAC_TX_COLL_NORMAL 0x0008
1274
1275#define MAC_TX_COLL_EXCESS 0x0010
1276
1277#define MAC_TX_COLL_LATE 0x0020
1278
1279#define MAC_TX_COLL_FIRST 0x0040
1280
1281#define MAC_TX_DEFER_TIMER 0x0080
1282
1283#define MAC_TX_PEAK_ATTEMPTS 0x0100
1284
1285
1286#define REG_MAC_RX_STATUS 0x6014
1287#define MAC_RX_FRAME_RECV 0x0001
1288
1289#define MAC_RX_OVERFLOW 0x0002
1290
1291#define MAC_RX_FRAME_COUNT 0x0004
1292
1293#define MAC_RX_ALIGN_ERR 0x0008
1294
1295#define MAC_RX_CRC_ERR 0x0010
1296
1297#define MAC_RX_LEN_ERR 0x0020
1298
1299#define MAC_RX_VIOL_ERR 0x0040
1300
1301
1302
1303#define REG_MAC_CTRL_STATUS 0x6018
1304#define MAC_CTRL_PAUSE_RECEIVED 0x00000001
1305
1306
1307
1308#define MAC_CTRL_PAUSE_STATE 0x00000002
1309
1310
1311
1312#define MAC_CTRL_NOPAUSE_STATE 0x00000004
1313
1314
1315
1316#define MAC_CTRL_PAUSE_TIME_MASK 0xFFFF0000
1317
1318
1319
1320
1321
1322
1323#define REG_MAC_TX_MASK 0x6020
1324
1325#define REG_MAC_RX_MASK 0x6024
1326
1327#define REG_MAC_CTRL_MASK 0x6028
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339#define REG_MAC_TX_CFG 0x6030
1340#define MAC_TX_CFG_EN 0x0001
1341
1342
1343
1344
1345
1346
1347#define MAC_TX_CFG_IGNORE_CARRIER 0x0002
1348
1349
1350
1351#define MAC_TX_CFG_IGNORE_COLL 0x0004
1352
1353
1354
1355#define MAC_TX_CFG_IPG_EN 0x0008
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371#define MAC_TX_CFG_NEVER_GIVE_UP_EN 0x0010
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383#define MAC_TX_CFG_NEVER_GIVE_UP_LIM 0x0020
1384
1385
1386
1387
1388
1389
1390
1391#define MAC_TX_CFG_NO_BACKOFF 0x0040
1392
1393
1394
1395
1396
1397#define MAC_TX_CFG_SLOW_DOWN 0x0080
1398
1399
1400
1401
1402
1403
1404
1405
1406#define MAC_TX_CFG_NO_FCS 0x0100
1407
1408
1409
1410
1411
1412
1413#define MAC_TX_CFG_CARRIER_EXTEND 0x0200
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434#define REG_MAC_RX_CFG 0x6034
1435#define MAC_RX_CFG_EN 0x0001
1436#define MAC_RX_CFG_STRIP_PAD 0x0002
1437
1438#define MAC_RX_CFG_STRIP_FCS 0x0004
1439
1440
1441#define MAC_RX_CFG_PROMISC_EN 0x0008
1442#define MAC_RX_CFG_PROMISC_GROUP_EN 0x0010
1443
1444
1445#define MAC_RX_CFG_HASH_FILTER_EN 0x0020
1446
1447#define MAC_RX_CFG_ADDR_FILTER_EN 0x0040
1448
1449
1450
1451
1452#define MAC_RX_CFG_DISABLE_DISCARD 0x0080
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462#define MAC_RX_CFG_CARRIER_EXTEND 0x0100
1463
1464
1465
1466
1467
1468
1469
1470#define REG_MAC_CTRL_CFG 0x6038
1471#define MAC_CTRL_CFG_SEND_PAUSE_EN 0x0001
1472
1473
1474#define MAC_CTRL_CFG_RECV_PAUSE_EN 0x0002
1475
1476#define MAC_CTRL_CFG_PASS_CTRL 0x0004
1477
1478
1479
1480
1481
1482
1483
1484
1485#define REG_MAC_XIF_CFG 0x603C
1486#define MAC_XIF_TX_MII_OUTPUT_EN 0x0001
1487
1488#define MAC_XIF_MII_INT_LOOPBACK 0x0002
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498#define MAC_XIF_DISABLE_ECHO 0x0004
1499
1500
1501
1502
1503
1504
1505
1506
1507#define MAC_XIF_GMII_MODE 0x0008
1508
1509#define MAC_XIF_MII_BUFFER_OUTPUT_EN 0x0010
1510
1511
1512
1513#define MAC_XIF_LINK_LED 0x0020
1514#define MAC_XIF_FDPLX_LED 0x0040
1515
1516#define REG_MAC_IPG0 0x6040
1517
1518#define REG_MAC_IPG1 0x6044
1519
1520#define REG_MAC_IPG2 0x6048
1521
1522#define REG_MAC_SLOT_TIME 0x604C
1523
1524#define REG_MAC_FRAMESIZE_MIN 0x6050
1525
1526
1527
1528
1529
1530#define REG_MAC_FRAMESIZE_MAX 0x6054
1531#define MAC_FRAMESIZE_MAX_BURST_MASK 0x3FFF0000
1532#define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1533#define MAC_FRAMESIZE_MAX_FRAME_MASK 0x00007FFF
1534#define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1535#define REG_MAC_PA_SIZE 0x6058
1536
1537
1538
1539
1540
1541
1542#define REG_MAC_JAM_SIZE 0x605C
1543
1544
1545
1546#define REG_MAC_ATTEMPT_LIMIT 0x6060
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558#define REG_MAC_CTRL_TYPE 0x6064
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585#define REG_MAC_ADDR0 0x6080
1586#define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1587#define REG_MAC_ADDR_FILTER0 0x614C
1588
1589#define REG_MAC_ADDR_FILTER1 0x6150
1590
1591#define REG_MAC_ADDR_FILTER2 0x6154
1592
1593#define REG_MAC_ADDR_FILTER2_1_MASK 0x6158
1594
1595
1596
1597#define REG_MAC_ADDR_FILTER0_MASK 0x615C
1598
1599
1600
1601
1602
1603
1604
1605#define REG_MAC_HASH_TABLE0 0x6160
1606#define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1607
1608
1609
1610
1611
1612#define REG_MAC_COLL_NORMAL 0x61A0
1613
1614#define REG_MAC_COLL_FIRST 0x61A4
1615
1616
1617#define REG_MAC_COLL_EXCESS 0x61A8
1618
1619#define REG_MAC_COLL_LATE 0x61AC
1620#define REG_MAC_TIMER_DEFER 0x61B0
1621
1622
1623#define REG_MAC_ATTEMPTS_PEAK 0x61B4
1624#define REG_MAC_RECV_FRAME 0x61B8
1625#define REG_MAC_LEN_ERR 0x61BC
1626#define REG_MAC_ALIGN_ERR 0x61C0
1627#define REG_MAC_FCS_ERR 0x61C4
1628#define REG_MAC_RX_CODE_ERR 0x61C8
1629
1630
1631
1632#define REG_MAC_RANDOM_SEED 0x61CC
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651#define REG_MAC_STATE_MACHINE 0x61D0
1652#define MAC_SM_RLM_MASK 0x07800000
1653#define MAC_SM_RLM_SHIFT 23
1654#define MAC_SM_RX_FC_MASK 0x00700000
1655#define MAC_SM_RX_FC_SHIFT 20
1656#define MAC_SM_TLM_MASK 0x000F0000
1657#define MAC_SM_TLM_SHIFT 16
1658#define MAC_SM_ENCAP_SM_MASK 0x0000F000
1659#define MAC_SM_ENCAP_SM_SHIFT 12
1660#define MAC_SM_TX_REQ_MASK 0x00000C00
1661#define MAC_SM_TX_REQ_SHIFT 10
1662#define MAC_SM_TX_FC_MASK 0x000003C0
1663#define MAC_SM_TX_FC_SHIFT 6
1664#define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1665#define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1666#define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1667#define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1668
1669
1670
1671
1672#define REG_MIF_BIT_BANG_CLOCK 0x6200
1673
1674
1675
1676#define REG_MIF_BIT_BANG_DATA 0x6204
1677
1678#define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691#define REG_MIF_FRAME 0x620C
1692#define MIF_FRAME_START_MASK 0xC0000000
1693
1694
1695#define MIF_FRAME_ST 0x40000000
1696#define MIF_FRAME_OPCODE_MASK 0x30000000
1697
1698
1699#define MIF_FRAME_OP_READ 0x20000000
1700#define MIF_FRAME_OP_WRITE 0x10000000
1701#define MIF_FRAME_PHY_ADDR_MASK 0x0F800000
1702
1703
1704
1705
1706#define MIF_FRAME_PHY_ADDR_SHIFT 23
1707#define MIF_FRAME_REG_ADDR_MASK 0x007C0000
1708
1709
1710
1711#define MIF_FRAME_REG_ADDR_SHIFT 18
1712#define MIF_FRAME_TURN_AROUND_MSB 0x00020000
1713
1714
1715#define MIF_FRAME_TURN_AROUND_LSB 0x00010000
1716
1717
1718
1719
1720
1721
1722#define MIF_FRAME_DATA_MASK 0x0000FFFF
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736#define REG_MIF_CFG 0x6210
1737#define MIF_CFG_PHY_SELECT 0x0001
1738
1739#define MIF_CFG_POLL_EN 0x0002
1740
1741
1742#define MIF_CFG_BB_MODE 0x0004
1743
1744#define MIF_CFG_POLL_REG_MASK 0x00F8
1745
1746
1747
1748#define MIF_CFG_POLL_REG_SHIFT 3
1749#define MIF_CFG_MDIO_0 0x0100
1750
1751
1752
1753
1754
1755
1756
1757
1758#define MIF_CFG_MDIO_1 0x0200
1759
1760
1761
1762
1763
1764
1765
1766
1767#define MIF_CFG_POLL_PHY_MASK 0x7C00
1768
1769#define MIF_CFG_POLL_PHY_SHIFT 10
1770
1771
1772
1773
1774
1775
1776#define REG_MIF_MASK 0x6214
1777
1778
1779#define REG_MIF_STATUS 0x6218
1780#define MIF_STATUS_POLL_DATA_MASK 0xFFFF0000
1781
1782
1783
1784#define MIF_STATUS_POLL_DATA_SHIFT 16
1785#define MIF_STATUS_POLL_STATUS_MASK 0x0000FFFF
1786
1787
1788
1789
1790
1791#define MIF_STATUS_POLL_STATUS_SHIFT 0
1792
1793
1794#define REG_MIF_STATE_MACHINE 0x621C
1795#define MIF_SM_CONTROL_MASK 0x07
1796
1797#define MIF_SM_EXECUTION_MASK 0x60
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811#define REG_PCS_MII_CTRL 0x9000
1812#define PCS_MII_CTRL_1000_SEL 0x0040
1813
1814#define PCS_MII_CTRL_COLLISION_TEST 0x0080
1815
1816
1817
1818#define PCS_MII_CTRL_DUPLEX 0x0100
1819
1820
1821#define PCS_MII_RESTART_AUTONEG 0x0200
1822
1823
1824#define PCS_MII_ISOLATE 0x0400
1825
1826#define PCS_MII_POWER_DOWN 0x0800
1827
1828#define PCS_MII_AUTONEG_EN 0x1000
1829
1830
1831
1832
1833
1834
1835#define PCS_MII_10_100_SEL 0x2000
1836
1837#define PCS_MII_RESET 0x8000
1838
1839
1840
1841#define REG_PCS_MII_STATUS 0x9004
1842#define PCS_MII_STATUS_EXTEND_CAP 0x0001
1843#define PCS_MII_STATUS_JABBER_DETECT 0x0002
1844#define PCS_MII_STATUS_LINK_STATUS 0x0004
1845
1846
1847
1848
1849
1850#define PCS_MII_STATUS_AUTONEG_ABLE 0x0008
1851
1852#define PCS_MII_STATUS_REMOTE_FAULT 0x0010
1853
1854
1855
1856#define PCS_MII_STATUS_AUTONEG_COMP 0x0020
1857
1858
1859
1860#define PCS_MII_STATUS_EXTEND_STATUS 0x0100
1861
1862
1863
1864
1865
1866
1867
1868#define REG_PCS_MII_ADVERT 0x9008
1869
1870#define PCS_MII_ADVERT_FD 0x0020
1871
1872#define PCS_MII_ADVERT_HD 0x0040
1873
1874#define PCS_MII_ADVERT_SYM_PAUSE 0x0080
1875
1876#define PCS_MII_ADVERT_ASYM_PAUSE 0x0100
1877
1878#define PCS_MII_ADVERT_RF_MASK 0x3000
1879
1880
1881
1882
1883
1884
1885
1886#define PCS_MII_ADVERT_ACK 0x4000
1887#define PCS_MII_ADVERT_NEXT_PAGE 0x8000
1888
1889
1890
1891
1892#define REG_PCS_MII_LPA 0x900C
1893
1894#define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1895#define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1896#define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1897#define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1898#define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1899#define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1900#define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1901
1902
1903#define REG_PCS_CFG 0x9010
1904#define PCS_CFG_EN 0x01
1905
1906
1907#define PCS_CFG_SD_OVERRIDE 0x02
1908
1909
1910#define PCS_CFG_SD_ACTIVE_LOW 0x04
1911
1912
1913
1914#define PCS_CFG_JITTER_STUDY_MASK 0x18
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924#define PCS_CFG_10MS_TIMER_OVERRIDE 0x20
1925
1926
1927
1928
1929
1930#define REG_PCS_STATE_MACHINE 0x9014
1931
1932#define PCS_SM_TX_STATE_MASK 0x0000000F
1933
1934
1935
1936#define PCS_SM_RX_STATE_MASK 0x000000F0
1937
1938
1939#define PCS_SM_WORD_SYNC_STATE_MASK 0x00000700
1940
1941#define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800
1942
1943
1944
1945
1946#define PCS_SM_LINK_STATE_MASK 0x0001E000
1947#define SM_LINK_STATE_UP 0x00016000
1948
1949#define PCS_SM_LOSS_LINK_C 0x00100000
1950
1951
1952#define PCS_SM_LOSS_LINK_SYNC 0x00200000
1953
1954#define PCS_SM_LOSS_SIGNAL_DETECT 0x00400000
1955
1956
1957
1958#define PCS_SM_NO_LINK_BREAKLINK 0x01000000
1959
1960
1961
1962
1963
1964
1965
1966
1967#define PCS_SM_NO_LINK_SERDES 0x02000000
1968
1969
1970#define PCS_SM_NO_LINK_C 0x04000000
1971
1972#define PCS_SM_NO_LINK_SYNC 0x08000000
1973
1974#define PCS_SM_NO_LINK_WAIT_C 0x10000000
1975
1976#define PCS_SM_NO_LINK_NO_IDLE 0x20000000
1977
1978
1979
1980
1981
1982
1983
1984
1985#define REG_PCS_INTR_STATUS 0x9018
1986#define PCS_INTR_STATUS_LINK_CHANGE 0x04
1987
1988
1989
1990
1991
1992
1993#define REG_PCS_DATAPATH_MODE 0x9050
1994#define PCS_DATAPATH_MODE_MII 0x00
1995
1996
1997
1998
1999#define PCS_DATAPATH_MODE_SERDES 0x02
2000
2001
2002
2003#define REG_PCS_SERDES_CTRL 0x9054
2004#define PCS_SERDES_CTRL_LOOPBACK 0x01
2005
2006#define PCS_SERDES_CTRL_SYNCD_EN 0x02
2007
2008
2009
2010#define PCS_SERDES_CTRL_LOCKREF 0x04
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026#define REG_PCS_SHARED_OUTPUT_SEL 0x9058
2027#define PCS_SOS_PROM_ADDR_MASK 0x0007
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037#define REG_PCS_SERDES_STATE 0x905C
2038#define PCS_SERDES_STATE_MASK 0x03
2039
2040
2041
2042
2043
2044#define REG_PCS_PACKET_COUNT 0x9060
2045#define PCS_PACKET_COUNT_TX 0x000007FF
2046#define PCS_PACKET_COUNT_RX 0x07FF0000
2047
2048
2049
2050
2051
2052
2053
2054#define REG_EXPANSION_ROM_RUN_START 0x100000
2055
2056#define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2057
2058#define REG_SECOND_LOCALBUS_START 0x180000
2059
2060#define REG_SECOND_LOCALBUS_END 0x1FFFFF
2061
2062
2063#define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2064#define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2065#define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2066#define ENTROPY_STATUS_DRDY 0x01
2067#define ENTROPY_STATUS_BUSY 0x02
2068#define ENTROPY_STATUS_CIPHER 0x04
2069#define ENTROPY_STATUS_BYPASS_MASK 0x18
2070#define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2071#define ENTROPY_MODE_KEY_MASK 0x07
2072#define ENTROPY_MODE_ENCRYPT 0x40
2073#define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2074#define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2075#define ENTROPY_RESET_DES_IO 0x01
2076#define ENTROPY_RESET_STC_MODE 0x02
2077#define ENTROPY_RESET_KEY_CACHE 0x04
2078#define ENTROPY_RESET_IV 0x08
2079#define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2080#define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2081#define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2082
2083
2084#define PHY_LUCENT_B0 0x00437421
2085#define LUCENT_MII_REG 0x1F
2086
2087#define PHY_NS_DP83065 0x20005c78
2088#define DP83065_MII_MEM 0x16
2089#define DP83065_MII_REGD 0x1D
2090#define DP83065_MII_REGE 0x1E
2091
2092#define PHY_BROADCOM_5411 0x00206071
2093#define PHY_BROADCOM_B0 0x00206050
2094#define BROADCOM_MII_REG4 0x14
2095#define BROADCOM_MII_REG5 0x15
2096#define BROADCOM_MII_REG7 0x17
2097#define BROADCOM_MII_REG8 0x18
2098
2099#define CAS_MII_ANNPTR 0x07
2100#define CAS_MII_ANNPRR 0x08
2101#define CAS_MII_1000_CTRL 0x09
2102#define CAS_MII_1000_STATUS 0x0A
2103#define CAS_MII_1000_EXTEND 0x0F
2104
2105#define CAS_BMSR_1000_EXTEND 0x0100
2106
2107
2108
2109
2110
2111
2112#define CAS_BMCR_SPEED1000 0x0040
2113
2114#define CAS_ADVERTISE_1000HALF 0x0100
2115#define CAS_ADVERTISE_1000FULL 0x0200
2116#define CAS_ADVERTISE_PAUSE 0x0400
2117#define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2118
2119
2120#define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2121#define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2122
2123
2124#define CAS_LPA_1000HALF 0x0400
2125#define CAS_LPA_1000FULL 0x0800
2126
2127#define CAS_EXTEND_1000XFULL 0x8000
2128#define CAS_EXTEND_1000XHALF 0x4000
2129#define CAS_EXTEND_1000TFULL 0x2000
2130#define CAS_EXTEND_1000THALF 0x1000
2131
2132
2133typedef struct cas_hp_inst {
2134 const char *note;
2135
2136 u16 mask, val;
2137
2138 u8 op;
2139 u8 soff, snext;
2140 u8 foff, fnext;
2141
2142 u8 outop;
2143
2144 u16 outarg;
2145 u8 outenab;
2146
2147 u8 outshift;
2148 u16 outmask;
2149} cas_hp_inst_t;
2150
2151
2152#define OP_EQ 0
2153#define OP_LT 1
2154#define OP_GT 2
2155#define OP_NP 3
2156
2157
2158#define CL_REG 0
2159#define LD_FID 1
2160#define LD_SEQ 2
2161#define LD_CTL 3
2162#define LD_SAP 4
2163#define LD_R1 5
2164#define LD_L3 6
2165#define LD_SUM 7
2166#define LD_HDR 8
2167#define IM_FID 9
2168#define IM_SEQ 10
2169#define IM_SAP 11
2170#define IM_R1 12
2171#define IM_CTL 13
2172#define LD_LEN 14
2173#define ST_FLG 15
2174
2175
2176#define S1_PCKT 0
2177#define S1_VLAN 1
2178#define S1_CFI 2
2179#define S1_8023 3
2180#define S1_LLC 4
2181#define S1_LLCc 5
2182#define S1_IPV4 6
2183#define S1_IPV4c 7
2184#define S1_IPV4F 8
2185#define S1_TCP44 9
2186#define S1_IPV6 10
2187#define S1_IPV6L 11
2188#define S1_IPV6c 12
2189#define S1_TCP64 13
2190#define S1_TCPSQ 14
2191#define S1_TCPFG 15
2192#define S1_TCPHL 16
2193#define S1_TCPHc 17
2194#define S1_CLNP 18
2195#define S1_CLNP2 19
2196#define S1_DROP 20
2197#define S2_HTTP 21
2198#define S1_ESP4 22
2199#define S1_AH4 23
2200#define S1_ESP6 24
2201#define S1_AH6 25
2202
2203#define CAS_PROG_IP46TCP4_PREAMBLE \
2204{ "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT, \
2205 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2206{ "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023, \
2207 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2208{ "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, \
2209 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2210{ "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4, \
2211 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2212{ "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP, \
2213 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2214{ "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2215 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2216{ "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6, \
2217 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2218{ "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP, \
2219 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2220{ "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP, \
2221 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2222{ "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP, \
2223 LD_FID, 0x182, 1, 0x0, 0xffff}, \
2224{ "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP, \
2225 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2226{ "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP, \
2227 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2228{ "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP, \
2229 LD_FID, 0x484, 1, 0x0, 0xffff}, \
2230{ "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP, \
2231 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2232
2233#ifdef USE_HP_IP46TCP4
2234static cas_hp_inst_t cas_prog_ip46tcp4tab[] = {
2235 CAS_PROG_IP46TCP4_PREAMBLE,
2236 { "TCP seq",
2237 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2238 0x081, 3, 0x0, 0xffff},
2239 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2240 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f},
2241 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2242 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2243 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2244 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2245 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2246 IM_CTL, 0x001, 3, 0x0, 0x0001},
2247 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2248 IM_CTL, 0x000, 0, 0x0, 0x0000},
2249 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2250 IM_CTL, 0x080, 3, 0x0, 0xffff},
2251 { NULL },
2252};
2253#ifdef HP_IP46TCP4_DEFAULT
2254#define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2255#endif
2256#endif
2257
2258
2259
2260
2261
2262#ifdef USE_HP_IP46TCP4NOHTTP
2263static cas_hp_inst_t cas_prog_ip46tcp4nohttptab[] = {
2264 CAS_PROG_IP46TCP4_PREAMBLE,
2265 { "TCP seq",
2266 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2267 0x081, 3, 0x0, 0xffff} ,
2268 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2269 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f, },
2270 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2271 LD_R1, 0x205, 3, 0xB, 0xf000},
2272 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2273 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2274 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2275 IM_CTL, 0x001, 3, 0x0, 0x0001},
2276 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2277 CL_REG, 0x002, 3, 0x0, 0x0000},
2278 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2279 IM_CTL, 0x080, 3, 0x0, 0xffff},
2280 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2281 IM_CTL, 0x044, 3, 0x0, 0xffff},
2282 { NULL },
2283};
2284#ifdef HP_IP46TCP4NOHTTP_DEFAULT
2285#define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2286#endif
2287#endif
2288
2289
2290#define S3_IPV6c 11
2291#define S3_TCP64 12
2292#define S3_TCPSQ 13
2293#define S3_TCPFG 14
2294#define S3_TCPHL 15
2295#define S3_TCPHc 16
2296#define S3_FRAG 17
2297#define S3_FOFF 18
2298#define S3_CLNP 19
2299
2300#ifdef USE_HP_IP4FRAG
2301static cas_hp_inst_t cas_prog_ip4fragtab[] = {
2302 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0, S1_PCKT,
2303 CL_REG, 0x3ff, 1, 0x0, 0x0000},
2304 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2305 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2306 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S3_CLNP, 1, S1_8023,
2307 CL_REG, 0x000, 0, 0x0, 0x0000},
2308 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2309 CL_REG, 0x000, 0, 0x0, 0x0000},
2310 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S3_CLNP,
2311 CL_REG, 0x000, 0, 0x0, 0x0000},
2312 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2313 CL_REG, 0x000, 0, 0x0, 0x0000},
2314 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2315 LD_SAP, 0x100, 3, 0x0, 0xffff},
2316 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S3_CLNP,
2317 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2318 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S3_FRAG,
2319 LD_LEN, 0x03e, 3, 0x0, 0xffff},
2320 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S3_TCPSQ, 0, S3_CLNP,
2321 LD_FID, 0x182, 3, 0x0, 0xffff},
2322 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S3_IPV6c, 0, S3_CLNP,
2323 LD_SUM, 0x015, 1, 0x0, 0x0000},
2324 { "IPV6 cont?", 0xf000, 0x6000, OP_EQ, 3, S3_TCP64, 0, S3_CLNP,
2325 LD_FID, 0x484, 1, 0x0, 0xffff},
2326 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S3_TCPSQ, 0, S3_CLNP,
2327 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2328 { "TCP seq",
2329 0x0000, 0x0000, OP_EQ, 0, S3_TCPFG, 4, S3_TCPFG, LD_SEQ,
2330 0x081, 3, 0x0, 0xffff},
2331 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHL, 0,
2332 S3_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f},
2333 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S3_TCPHc, 0, S3_TCPHc,
2334 LD_R1, 0x205, 3, 0xB, 0xf000},
2335 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2336 LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2337 { "IP4 Fragment", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2338 LD_FID, 0x103, 3, 0x0, 0xffff},
2339 { "IP4 frag offset", 0x0000, 0x0000, OP_EQ, 0, S3_FOFF, 0, S3_FOFF,
2340 LD_SEQ, 0x040, 1, 0xD, 0xfff8},
2341 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2342 IM_CTL, 0x001, 3, 0x0, 0x0001},
2343 { NULL },
2344};
2345#ifdef HP_IP4FRAG_DEFAULT
2346#define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2347#endif
2348#endif
2349
2350
2351
2352
2353#ifdef USE_HP_IP46TCP4BATCH
2354static cas_hp_inst_t cas_prog_ip46tcp4batchtab[] = {
2355 CAS_PROG_IP46TCP4_PREAMBLE,
2356 { "TCP seq",
2357 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 0, S1_TCPFG, LD_SEQ,
2358 0x081, 3, 0x0, 0xffff},
2359 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2360 S1_TCPHL, ST_FLG, 0x000, 3, 0x0, 0x0000},
2361 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0,
2362 S1_TCPHc, LD_R1, 0x205, 3, 0xB, 0xf000},
2363 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2364 S1_PCKT, IM_CTL, 0x040, 3, 0x0, 0xffff},
2365 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2366 IM_CTL, 0x001, 3, 0x0, 0x0001},
2367 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2368 S1_PCKT, IM_CTL, 0x080, 3, 0x0, 0xffff},
2369 { NULL },
2370};
2371#ifdef HP_IP46TCP4BATCH_DEFAULT
2372#define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2373#endif
2374#endif
2375
2376
2377
2378
2379
2380#ifdef USE_HP_WORKAROUND
2381static cas_hp_inst_t cas_prog_workaroundtab[] = {
2382 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2383 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000} ,
2384 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2385 IM_CTL, 0x04a, 3, 0x0, 0xffff},
2386 { "CFI?", 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2387 CL_REG, 0x000, 0, 0x0, 0x0000},
2388 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2389 CL_REG, 0x000, 0, 0x0, 0x0000},
2390 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2391 CL_REG, 0x000, 0, 0x0, 0x0000},
2392 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2393 CL_REG, 0x000, 0, 0x0, 0x0000},
2394 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2395 IM_SAP, 0x6AE, 3, 0x0, 0xffff},
2396 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2397 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2398 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2399 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2400 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_CLNP,
2401 LD_FID, 0x182, 3, 0x0, 0xffff},
2402 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2403 LD_SUM, 0x015, 1, 0x0, 0x0000},
2404 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2405 IM_R1, 0x128, 1, 0x0, 0xffff},
2406 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2407 LD_FID, 0x484, 1, 0x0, 0xffff},
2408 { "TCP64?", 0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_CLNP,
2409 LD_LEN, 0x03f, 1, 0x0, 0xffff},
2410 { "TCP seq",
2411 0x0000, 0x0000, OP_EQ, 0, S1_TCPFG, 4, S1_TCPFG, LD_SEQ,
2412 0x081, 3, 0x0, 0xffff},
2413 { "TCP control flags", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHL, 0,
2414 S1_TCPHL, ST_FLG, 0x045, 3, 0x0, 0x002f},
2415 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2416 LD_R1, 0x205, 3, 0xB, 0xf000},
2417 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2418 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2419 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2420 IM_SAP, 0x6AE, 3, 0x0, 0xffff} ,
2421 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2422 IM_CTL, 0x001, 3, 0x0, 0x0001},
2423 { NULL },
2424};
2425#ifdef HP_WORKAROUND_DEFAULT
2426#define CAS_HP_FIRMWARE cas_prog_workaroundtab
2427#endif
2428#endif
2429
2430#ifdef USE_HP_ENCRYPT
2431static cas_hp_inst_t cas_prog_encryptiontab[] = {
2432 { "packet arrival?", 0xffff, 0x0000, OP_NP, 6, S1_VLAN, 0,
2433 S1_PCKT, CL_REG, 0x3ff, 1, 0x0, 0x0000},
2434 { "VLAN?", 0xffff, 0x8100, OP_EQ, 1, S1_CFI, 0, S1_8023,
2435 IM_CTL, 0x00a, 3, 0x0, 0xffff},
2436#if 0
2437
2438
2439 00,
2440#endif
2441 { "CFI?",
2442 0x1000, 0x1000, OP_EQ, 0, S1_CLNP, 1, S1_8023,
2443 CL_REG, 0x000, 0, 0x0, 0x0000},
2444 { "8023?", 0xffff, 0x0600, OP_LT, 1, S1_LLC, 0, S1_IPV4,
2445 CL_REG, 0x000, 0, 0x0, 0x0000},
2446 { "LLC?", 0xffff, 0xaaaa, OP_EQ, 1, S1_LLCc, 0, S1_CLNP,
2447 CL_REG, 0x000, 0, 0x0, 0x0000},
2448 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2449 CL_REG, 0x000, 0, 0x0, 0x0000},
2450 { "IPV4?", 0xffff, 0x0800, OP_EQ, 1, S1_IPV4c, 0, S1_IPV6,
2451 LD_SAP, 0x100, 3, 0x0, 0xffff},
2452 { "IPV4 cont?", 0xff00, 0x4500, OP_EQ, 3, S1_IPV4F, 0, S1_CLNP,
2453 LD_SUM, 0x00a, 1, 0x0, 0x0000},
2454 { "IPV4 frag?", 0x3fff, 0x0000, OP_EQ, 1, S1_TCP44, 0, S1_CLNP,
2455 LD_LEN, 0x03e, 1, 0x0, 0xffff},
2456 { "TCP44?", 0x00ff, 0x0006, OP_EQ, 7, S1_TCPSQ, 0, S1_ESP4,
2457 LD_FID, 0x182, 1, 0x0, 0xffff},
2458 { "IPV6?", 0xffff, 0x86dd, OP_EQ, 1, S1_IPV6L, 0, S1_CLNP,
2459 LD_SUM, 0x015, 1, 0x0, 0x0000},
2460 { "IPV6 len", 0xf000, 0x6000, OP_EQ, 0, S1_IPV6c, 0, S1_CLNP,
2461 IM_R1, 0x128, 1, 0x0, 0xffff},
2462 { "IPV6 cont?", 0x0000, 0x0000, OP_EQ, 3, S1_TCP64, 0, S1_CLNP,
2463 LD_FID, 0x484, 1, 0x0, 0xffff},
2464 { "TCP64?",
2465#if 0
2466
2467#endif
2468 0xff00, 0x0600, OP_EQ, 12, S1_TCPSQ, 0, S1_ESP6, LD_LEN,
2469 0x03f, 1, 0x0, 0xffff},
2470 { "TCP seq",
2471 0xFFFF, 0x0080, OP_EQ, 0, S2_HTTP, 0, S1_TCPFG, LD_SEQ,
2472 0x081, 3, 0x0, 0xffff},
2473 { "TCP control flags", 0xFFFF, 0x8080, OP_EQ, 0, S2_HTTP, 0,
2474 S1_TCPHL, ST_FLG, 0x145, 2, 0x0, 0x002f},
2475 { "TCP length", 0x0000, 0x0000, OP_EQ, 0, S1_TCPHc, 0, S1_TCPHc,
2476 LD_R1, 0x205, 3, 0xB, 0xf000} ,
2477 { "TCP length cont", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0,
2478 S1_PCKT, LD_HDR, 0x0ff, 3, 0x0, 0xffff},
2479 { "Cleanup", 0x0000, 0x0000, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP2,
2480 IM_CTL, 0x001, 3, 0x0, 0x0001},
2481 { "Cleanup 2", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2482 CL_REG, 0x002, 3, 0x0, 0x0000},
2483 { "Drop packet", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2484 IM_CTL, 0x080, 3, 0x0, 0xffff},
2485 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2486 IM_CTL, 0x044, 3, 0x0, 0xffff},
2487 { "IPV4 ESP encrypted?",
2488 0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH4, IM_CTL,
2489 0x021, 1, 0x0, 0xffff},
2490 { "IPV4 AH encrypted?",
2491 0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2492 0x021, 1, 0x0, 0xffff},
2493 { "IPV6 ESP encrypted?",
2494#if 0
2495
2496#endif
2497 0xff00, 0x3200, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL,
2498 0x021, 1, 0x0, 0xffff},
2499 { "IPV6 AH encrypted?",
2500#if 0
2501
2502#endif
2503 0xff00, 0x3300, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL,
2504 0x021, 1, 0x0, 0xffff},
2505 { NULL },
2506};
2507#ifdef HP_ENCRYPT_DEFAULT
2508#define CAS_HP_FIRMWARE cas_prog_encryptiontab
2509#endif
2510#endif
2511
2512static cas_hp_inst_t cas_prog_null[] = { {NULL} };
2513#ifdef HP_NULL_DEFAULT
2514#define CAS_HP_FIRMWARE cas_prog_null
2515#endif
2516
2517
2518#define CAS_PHY_UNKNOWN 0x00
2519#define CAS_PHY_SERDES 0x01
2520#define CAS_PHY_MII_MDIO0 0x02
2521#define CAS_PHY_MII_MDIO1 0x04
2522#define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535#define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2536#define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2537#define TX_DESC_RING_INDEX 4
2538#define RX_DESC_RING_INDEX 4
2539#define RX_COMP_RING_INDEX 4
2540
2541#if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2542#error TX_DESC_RING_INDEX must be between 0 and 8
2543#endif
2544
2545#if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2546#error RX_DESC_RING_INDEX must be between 0 and 8
2547#endif
2548
2549#if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2550#error RX_COMP_RING_INDEX must be between 0 and 8
2551#endif
2552
2553#define N_TX_RINGS MAX_TX_RINGS
2554#define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2555#define N_RX_DESC_RINGS MAX_RX_DESC_RINGS
2556#define N_RX_COMP_RINGS 0x1
2557
2558
2559#define N_RX_FLOWS 64
2560
2561#define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2562#define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2563#define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2564#define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2565#define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2566#define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2567#define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2568#define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2569#define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2570
2571
2572#define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2573#define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2574#define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2575 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2576 TX_CFG_DESC_RINGN_MASK(y))
2577
2578
2579#define CAS_MIN_PAGE_SHIFT 11
2580#define CAS_JUMBO_PAGE_SHIFT 13
2581#define CAS_MAX_PAGE_SHIFT 14
2582
2583#define TX_DESC_BUFLEN_MASK 0x0000000000003FFFULL
2584
2585#define TX_DESC_BUFLEN_SHIFT 0
2586#define TX_DESC_CSUM_START_MASK 0x00000000001F8000ULL
2587
2588
2589
2590
2591
2592#define TX_DESC_CSUM_START_SHIFT 15
2593#define TX_DESC_CSUM_STUFF_MASK 0x000000001FE00000ULL
2594
2595
2596
2597
2598#define TX_DESC_CSUM_STUFF_SHIFT 21
2599#define TX_DESC_CSUM_EN 0x0000000020000000ULL
2600#define TX_DESC_EOF 0x0000000040000000ULL
2601#define TX_DESC_SOF 0x0000000080000000ULL
2602#define TX_DESC_INTME 0x0000000100000000ULL
2603#define TX_DESC_NO_CRC 0x0000000200000000ULL
2604
2605
2606
2607struct cas_tx_desc {
2608 __le64 control;
2609 __le64 buffer;
2610};
2611
2612
2613
2614
2615
2616struct cas_rx_desc {
2617 __le64 index;
2618 __le64 buffer;
2619};
2620
2621
2622
2623#define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2624#define RX_COMP1_DATA_SIZE_SHIFT 13
2625#define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2626#define RX_COMP1_DATA_OFF_SHIFT 27
2627#define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2628#define RX_COMP1_DATA_INDEX_SHIFT 41
2629#define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2630#define RX_COMP1_SKIP_SHIFT 55
2631#define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2632#define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2633#define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2634#define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2635#define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2636#define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2637#define RX_COMP1_TYPE_SHIFT 62
2638
2639
2640#define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2641#define RX_COMP2_NEXT_INDEX_SHIFT 21
2642#define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2643#define RX_COMP2_HDR_SIZE_SHIFT 35
2644#define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2645#define RX_COMP2_HDR_OFF_SHIFT 44
2646#define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2647#define RX_COMP2_HDR_INDEX_SHIFT 50
2648
2649
2650#define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2651#define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2652#define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2653#define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2654#define RX_COMP3_CSUM_START_SHIFT 12
2655#define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2656#define RX_COMP3_FLOWID_SHIFT 19
2657#define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2658#define RX_COMP3_OPCODE_SHIFT 25
2659#define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2660#define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2661#define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2662#define RX_COMP3_LOAD_BAL_SHIFT 35
2663#define RX_PLUS_COMP3_ENC_PKT 0x0000020000000000ULL
2664#define RX_COMP3_L3_HEAD_OFF_MASK 0x0000FE0000000000ULL
2665#define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2666#define RX_PLUS_COMP_L3_HEAD_OFF_MASK 0x0000FC0000000000ULL
2667#define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2668#define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2669#define RX_COMP3_SAP_SHIFT 48
2670
2671
2672#define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2673#define RX_COMP4_TCP_CSUM_SHIFT 0
2674#define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2675#define RX_COMP4_PKT_LEN_SHIFT 16
2676#define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2677#define RX_COMP4_PERFECT_MATCH_SHIFT 30
2678#define RX_COMP4_ZERO 0x0000080000000000ULL
2679#define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2680#define RX_COMP4_HASH_VAL_SHIFT 44
2681#define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2682#define RX_COMP4_BAD 0x4000000000000000ULL
2683#define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2684
2685
2686
2687
2688
2689#define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2690#define RX_INDEX_NUM_SHIFT 0
2691#define RX_INDEX_RING_MASK 0x0000000000001000ULL
2692#define RX_INDEX_RING_SHIFT 12
2693#define RX_INDEX_RELEASE 0x0000000000002000ULL
2694
2695struct cas_rx_comp {
2696 __le64 word1;
2697 __le64 word2;
2698 __le64 word3;
2699 __le64 word4;
2700};
2701
2702enum link_state {
2703 link_down = 0,
2704 link_aneg,
2705 link_force_try,
2706 link_force_ret,
2707 link_force_ok,
2708 link_up
2709};
2710
2711typedef struct cas_page {
2712 struct list_head list;
2713 struct page *buffer;
2714 dma_addr_t dma_addr;
2715 int used;
2716} cas_page_t;
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730#define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2731#define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2732#define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2733
2734struct cas_init_block {
2735 struct cas_rx_comp rxcs[N_RX_COMP_RINGS][INIT_BLOCK_RX_COMP];
2736 struct cas_rx_desc rxds[N_RX_DESC_RINGS][INIT_BLOCK_RX_DESC];
2737 struct cas_tx_desc txds[N_TX_RINGS][INIT_BLOCK_TX];
2738 __le64 tx_compwb;
2739};
2740
2741
2742
2743
2744
2745#define TX_TINY_BUF_LEN 0x100
2746#define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2747
2748struct cas_tiny_count {
2749 int nbufs;
2750 int used;
2751};
2752
2753struct cas {
2754 spinlock_t lock;
2755 spinlock_t tx_lock[N_TX_RINGS];
2756 spinlock_t stat_lock[N_TX_RINGS + 1];
2757 spinlock_t rx_inuse_lock;
2758 spinlock_t rx_spare_lock;
2759
2760 void __iomem *regs;
2761 int tx_new[N_TX_RINGS], tx_old[N_TX_RINGS];
2762 int rx_old[N_RX_DESC_RINGS];
2763 int rx_cur[N_RX_COMP_RINGS], rx_new[N_RX_COMP_RINGS];
2764 int rx_last[N_RX_DESC_RINGS];
2765
2766 struct napi_struct napi;
2767
2768
2769
2770 int hw_running;
2771 int opened;
2772 struct mutex pm_mutex;
2773
2774 struct cas_init_block *init_block;
2775 struct cas_tx_desc *init_txds[MAX_TX_RINGS];
2776 struct cas_rx_desc *init_rxds[MAX_RX_DESC_RINGS];
2777 struct cas_rx_comp *init_rxcs[MAX_RX_COMP_RINGS];
2778
2779
2780
2781 struct sk_buff *tx_skbs[N_TX_RINGS][TX_DESC_RING_SIZE];
2782 struct sk_buff_head rx_flows[N_RX_FLOWS];
2783 cas_page_t *rx_pages[N_RX_DESC_RINGS][RX_DESC_RING_SIZE];
2784 struct list_head rx_spare_list, rx_inuse_list;
2785 int rx_spares_needed;
2786
2787
2788
2789 struct cas_tiny_count tx_tiny_use[N_TX_RINGS][TX_DESC_RING_SIZE];
2790 u8 *tx_tiny_bufs[N_TX_RINGS];
2791
2792 u32 msg_enable;
2793
2794
2795 struct net_device_stats net_stats[N_TX_RINGS + 1];
2796
2797 u32 pci_cfg[64 >> 2];
2798 u8 pci_revision;
2799
2800 int phy_type;
2801 int phy_addr;
2802 u32 phy_id;
2803#define CAS_FLAG_1000MB_CAP 0x00000001
2804#define CAS_FLAG_REG_PLUS 0x00000002
2805#define CAS_FLAG_TARGET_ABORT 0x00000004
2806#define CAS_FLAG_SATURN 0x00000008
2807#define CAS_FLAG_RXD_POST_MASK 0x000000F0
2808#define CAS_FLAG_RXD_POST_SHIFT 4
2809#define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2810 CAS_FLAG_RXD_POST_MASK)
2811#define CAS_FLAG_ENTROPY_DEV 0x00000100
2812#define CAS_FLAG_NO_HW_CSUM 0x00000200
2813 u32 cas_flags;
2814 int packet_min;
2815 int tx_fifo_size;
2816 int rx_fifo_size;
2817 int rx_pause_off;
2818 int rx_pause_on;
2819 int crc_size;
2820
2821 int pci_irq_INTC;
2822 int min_frame_size;
2823
2824
2825 int page_size;
2826 int page_order;
2827 int mtu_stride;
2828
2829 u32 mac_rx_cfg;
2830
2831
2832 int link_cntl;
2833 int link_fcntl;
2834 enum link_state lstate;
2835 struct timer_list link_timer;
2836 int timer_ticks;
2837 struct work_struct reset_task;
2838#if 0
2839 atomic_t reset_task_pending;
2840#else
2841 atomic_t reset_task_pending;
2842 atomic_t reset_task_pending_mtu;
2843 atomic_t reset_task_pending_spare;
2844 atomic_t reset_task_pending_all;
2845#endif
2846
2847
2848#define LINK_TRANSITION_UNKNOWN 0
2849#define LINK_TRANSITION_ON_FAILURE 1
2850#define LINK_TRANSITION_STILL_FAILED 2
2851#define LINK_TRANSITION_LINK_UP 3
2852#define LINK_TRANSITION_LINK_CONFIG 4
2853#define LINK_TRANSITION_LINK_DOWN 5
2854#define LINK_TRANSITION_REQUESTED_RESET 6
2855 int link_transition;
2856 int link_transition_jiffies_valid;
2857 unsigned long link_transition_jiffies;
2858
2859
2860 u8 orig_cacheline_size;
2861#define CAS_PREF_CACHELINE_SIZE 0x20
2862
2863
2864 int casreg_len;
2865 u64 pause_entered;
2866 u16 pause_last_time_recvd;
2867
2868 dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
2869 struct pci_dev *pdev;
2870 struct net_device *dev;
2871#if defined(CONFIG_OF)
2872 struct device_node *of_node;
2873#endif
2874
2875
2876 u16 fw_load_addr;
2877 u32 fw_size;
2878 u8 *fw_data;
2879};
2880
2881#define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2882#define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2883#define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2884
2885#define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2886 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2887
2888#define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2889 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2890 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2891
2892#define CAS_ALIGN(addr, align) \
2893 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2894
2895#define RX_FIFO_SIZE 16384
2896#define EXPANSION_ROM_SIZE 65536
2897
2898#define CAS_MC_EXACT_MATCH_SIZE 15
2899#define CAS_MC_HASH_SIZE 256
2900#define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2901 CAS_MC_HASH_SIZE)
2902
2903#define TX_TARGET_ABORT_LEN 0x20
2904#define RX_SWIVEL_OFF_VAL 0x2
2905#define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2906#define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2907#define RX_BLANK_INTR_PKT_VAL 0x05
2908#define RX_BLANK_INTR_TIME_VAL 0x0F
2909#define HP_TCP_THRESH_VAL 1530
2910
2911#define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2912#define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)
2913
2914#endif
2915