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25#ifndef W83977AF_IR_H
26#define W83977AF_IR_H
27
28#include <asm/io.h>
29#include <linux/types.h>
30
31
32#define ENBNKSEL 0x01
33#define APEDCRC 0x02
34#define TXW4C 0x04
35#define RXW4C 0x08
36
37
38#define RBR 0x00
39#define TBR 0x00
40
41#define ICR 0x01
42#define ICR_ERBRI 0x01
43#define ICR_ETBREI 0x02
44#define ICR_EUSRI 0x04
45#define ICR_EHSRI 0x04
46#define ICR_ETXURI 0x04
47#define ICR_EDMAI 0x10
48#define ICR_ETXTHI 0x20
49#define ICR_EFSFI 0x40
50#define ICR_ETMRI 0x80
51
52#define UFR 0x02
53#define UFR_EN_FIFO 0x01
54#define UFR_RXF_RST 0x02
55#define UFR_TXF_RST 0x04
56#define UFR_RXTL 0x80
57#define UFR_TXTL 0x20
58
59#define ISR 0x02
60#define ISR_RXTH_I 0x01
61#define ISR_TXEMP_I 0x02
62#define ISR_FEND_I 0x04
63#define ISR_DMA_I 0x10
64#define ISR_TXTH_I 0x20
65#define ISR_FSF_I 0x40
66#define ISR_TMR_I 0x80
67
68#define UCR 0x03
69#define UCR_DLS8 0x03
70
71#define SSR 0x03
72#define SET0 UCR_DLS8
73#define SET1 (0x80|UCR_DLS8)
74#define SET2 0xE0
75#define SET3 0xE4
76#define SET4 0xE8
77#define SET5 0xEC
78#define SET6 0xF0
79#define SET7 0xF4
80
81#define HCR 0x04
82#define HCR_MODE_MASK ~(0xD0)
83#define HCR_SIR 0x60
84#define HCR_MIR_576 0x20
85#define HCR_MIR_1152 0x80
86#define HCR_FIR 0xA0
87#define HCR_EN_DMA 0x04
88#define HCR_EN_IRQ 0x08
89#define HCR_TX_WT 0x08
90
91#define USR 0x05
92#define USR_RDR 0x01
93#define USR_TSRE 0x40
94
95#define AUDR 0x07
96#define AUDR_SFEND 0x08
97#define AUDR_RXBSY 0x20
98#define AUDR_UNDR 0x40
99
100
101#define ABLL 0x00
102#define ABHL 0x01
103
104#define ADCR1 0x02
105#define ADCR1_ADV_SL 0x01
106#define ADCR1_D_CHSW 0x08
107#define ADCR1_DMA_F 0x02
108
109#define ADCR2 0x04
110#define ADCR2_TXFS32 0x01
111#define ADCR2_RXFS32 0x04
112
113#define RXFDTH 0x07
114
115
116#define AUID 0x00
117
118
119#define TMRL 0x00
120#define TMRH 0x01
121
122#define IR_MSL 0x02
123#define IR_MSL_EN_TMR 0x01
124
125#define TFRLL 0x04
126#define TFRLH 0x05
127#define RFRLL 0x06
128#define RFRLH 0x07
129
130
131
132#define FS_FO 0x05
133#define FS_FO_FSFDR 0x80
134#define FS_FO_LST_FR 0x40
135#define FS_FO_MX_LEX 0x10
136#define FS_FO_PHY_ERR 0x08
137#define FS_FO_CRC_ERR 0x04
138#define FS_FO_RX_OV 0x02
139#define FS_FO_FSF_OV 0x01
140#define FS_FO_ERR_MSK 0x5f
141
142#define RFLFL 0x06
143#define RFLFH 0x07
144
145
146#define IR_CFG2 0x00
147#define IR_CFG2_DIS_CRC 0x02
148
149
150#define IRM_CR 0x07
151#define IRM_CR_IRX_MSL 0x40
152#define IRM_CR_AF_MNT 0x80
153
154
155struct st_fifo_entry {
156 int status;
157 int len;
158};
159
160struct st_fifo {
161 struct st_fifo_entry entries[10];
162 int head;
163 int tail;
164 int len;
165};
166
167
168struct w83977af_ir {
169 struct st_fifo st_fifo;
170
171 int tx_buff_offsets[10];
172 int tx_len;
173
174 struct net_device *netdev;
175
176 struct irlap_cb *irlap;
177 struct qos_info qos;
178
179 chipio_t io;
180 iobuff_t tx_buff;
181 iobuff_t rx_buff;
182 dma_addr_t tx_buff_dma;
183 dma_addr_t rx_buff_dma;
184
185
186
187
188 spinlock_t lock;
189
190 __u32 new_speed;
191};
192
193static inline void switch_bank( int iobase, int set)
194{
195 outb(set, iobase+SSR);
196}
197
198#endif
199