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17#include <linux/dma-mapping.h>
18#include "ath9k.h"
19#include "ar9003_mac.h"
20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2)
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)
32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38static u16 bits_per_symbol[][2] = {
39
40 { 26, 54 },
41 { 52, 108 },
42 { 78, 162 },
43 { 104, 216 },
44 { 156, 324 },
45 { 208, 432 },
46 { 234, 486 },
47 { 260, 540 },
48};
49
50#define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
52static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
53 struct ath_atx_tid *tid, struct sk_buff *skb);
54static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
56static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
57 struct ath_txq *txq, struct list_head *bf_q,
58 struct ath_tx_status *ts, int txok);
59static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
66static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70
71enum {
72 MCS_HT20,
73 MCS_HT20_SGI,
74 MCS_HT40,
75 MCS_HT40_SGI,
76};
77
78
79
80
81
82void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
83 __acquires(&txq->axq_lock)
84{
85 spin_lock_bh(&txq->axq_lock);
86}
87
88void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
89 __releases(&txq->axq_lock)
90{
91 spin_unlock_bh(&txq->axq_lock);
92}
93
94void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
95 __releases(&txq->axq_lock)
96{
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106}
107
108static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109{
110 struct ath_atx_ac *ac = tid->ac;
111
112 if (tid->paused)
113 return;
114
115 if (tid->sched)
116 return;
117
118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
120
121 if (ac->sched)
122 return;
123
124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126}
127
128static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129{
130 struct ath_txq *txq = tid->ac->txq;
131
132 WARN_ON(!tid->paused);
133
134 ath_txq_lock(sc, txq);
135 tid->paused = false;
136
137 if (skb_queue_empty(&tid->buf_q))
138 goto unlock;
139
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
142unlock:
143 ath_txq_unlock_complete(sc, txq);
144}
145
146static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
147{
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
152}
153
154static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
155{
156 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
157 seqno << IEEE80211_SEQ_SEQ_SHIFT);
158}
159
160static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
161{
162 struct ath_txq *txq = tid->ac->txq;
163 struct sk_buff *skb;
164 struct ath_buf *bf;
165 struct list_head bf_head;
166 struct ath_tx_status ts;
167 struct ath_frame_info *fi;
168 bool sendbar = false;
169
170 INIT_LIST_HEAD(&bf_head);
171
172 memset(&ts, 0, sizeof(ts));
173
174 while ((skb = __skb_dequeue(&tid->buf_q))) {
175 fi = get_frame_info(skb);
176 bf = fi->bf;
177
178 if (!bf) {
179 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
180 if (!bf) {
181 ieee80211_free_txskb(sc->hw, skb);
182 continue;
183 }
184 }
185
186 if (fi->retries) {
187 list_add_tail(&bf->list, &bf_head);
188 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
189 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
190 sendbar = true;
191 } else {
192 ath_tx_send_normal(sc, txq, NULL, skb);
193 }
194 }
195
196 if (tid->baw_head == tid->baw_tail) {
197 tid->state &= ~AGGR_ADDBA_COMPLETE;
198 tid->state &= ~AGGR_CLEANUP;
199 }
200
201 if (sendbar) {
202 ath_txq_unlock(sc, txq);
203 ath_send_bar(tid, tid->seq_start);
204 ath_txq_lock(sc, txq);
205 }
206}
207
208static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
209 int seqno)
210{
211 int index, cindex;
212
213 index = ATH_BA_INDEX(tid->seq_start, seqno);
214 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
215
216 __clear_bit(cindex, tid->tx_buf);
217
218 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
219 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
220 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
221 if (tid->bar_index >= 0)
222 tid->bar_index--;
223 }
224}
225
226static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
227 u16 seqno)
228{
229 int index, cindex;
230
231 index = ATH_BA_INDEX(tid->seq_start, seqno);
232 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
233 __set_bit(cindex, tid->tx_buf);
234
235 if (index >= ((tid->baw_tail - tid->baw_head) &
236 (ATH_TID_MAX_BUFS - 1))) {
237 tid->baw_tail = cindex;
238 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
239 }
240}
241
242
243
244
245
246
247
248static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
249 struct ath_atx_tid *tid)
250
251{
252 struct sk_buff *skb;
253 struct ath_buf *bf;
254 struct list_head bf_head;
255 struct ath_tx_status ts;
256 struct ath_frame_info *fi;
257
258 memset(&ts, 0, sizeof(ts));
259 INIT_LIST_HEAD(&bf_head);
260
261 while ((skb = __skb_dequeue(&tid->buf_q))) {
262 fi = get_frame_info(skb);
263 bf = fi->bf;
264
265 if (!bf) {
266 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
267 continue;
268 }
269
270 list_add_tail(&bf->list, &bf_head);
271
272 if (fi->retries)
273 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
274
275 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
276 }
277
278 tid->seq_next = tid->seq_start;
279 tid->baw_tail = tid->baw_head;
280 tid->bar_index = -1;
281}
282
283static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
284 struct sk_buff *skb, int count)
285{
286 struct ath_frame_info *fi = get_frame_info(skb);
287 struct ath_buf *bf = fi->bf;
288 struct ieee80211_hdr *hdr;
289 int prev = fi->retries;
290
291 TX_STAT_INC(txq->axq_qnum, a_retries);
292 fi->retries += count;
293
294 if (prev > 0)
295 return;
296
297 hdr = (struct ieee80211_hdr *)skb->data;
298 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
299 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
300 sizeof(*hdr), DMA_TO_DEVICE);
301}
302
303static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
304{
305 struct ath_buf *bf = NULL;
306
307 spin_lock_bh(&sc->tx.txbuflock);
308
309 if (unlikely(list_empty(&sc->tx.txbuf))) {
310 spin_unlock_bh(&sc->tx.txbuflock);
311 return NULL;
312 }
313
314 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
315 list_del(&bf->list);
316
317 spin_unlock_bh(&sc->tx.txbuflock);
318
319 return bf;
320}
321
322static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
323{
324 spin_lock_bh(&sc->tx.txbuflock);
325 list_add_tail(&bf->list, &sc->tx.txbuf);
326 spin_unlock_bh(&sc->tx.txbuflock);
327}
328
329static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
330{
331 struct ath_buf *tbf;
332
333 tbf = ath_tx_get_buffer(sc);
334 if (WARN_ON(!tbf))
335 return NULL;
336
337 ATH_TXBUF_RESET(tbf);
338
339 tbf->bf_mpdu = bf->bf_mpdu;
340 tbf->bf_buf_addr = bf->bf_buf_addr;
341 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
342 tbf->bf_state = bf->bf_state;
343
344 return tbf;
345}
346
347static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
348 struct ath_tx_status *ts, int txok,
349 int *nframes, int *nbad)
350{
351 struct ath_frame_info *fi;
352 u16 seq_st = 0;
353 u32 ba[WME_BA_BMP_SIZE >> 5];
354 int ba_index;
355 int isaggr = 0;
356
357 *nbad = 0;
358 *nframes = 0;
359
360 isaggr = bf_isaggr(bf);
361 if (isaggr) {
362 seq_st = ts->ts_seqnum;
363 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
364 }
365
366 while (bf) {
367 fi = get_frame_info(bf->bf_mpdu);
368 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
369
370 (*nframes)++;
371 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
372 (*nbad)++;
373
374 bf = bf->bf_next;
375 }
376}
377
378
379static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
380 struct ath_buf *bf, struct list_head *bf_q,
381 struct ath_tx_status *ts, int txok)
382{
383 struct ath_node *an = NULL;
384 struct sk_buff *skb;
385 struct ieee80211_sta *sta;
386 struct ieee80211_hw *hw = sc->hw;
387 struct ieee80211_hdr *hdr;
388 struct ieee80211_tx_info *tx_info;
389 struct ath_atx_tid *tid = NULL;
390 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
391 struct list_head bf_head;
392 struct sk_buff_head bf_pending;
393 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
394 u32 ba[WME_BA_BMP_SIZE >> 5];
395 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
396 bool rc_update = true, isba;
397 struct ieee80211_tx_rate rates[4];
398 struct ath_frame_info *fi;
399 int nframes;
400 u8 tidno;
401 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
402 int i, retries;
403 int bar_index = -1;
404
405 skb = bf->bf_mpdu;
406 hdr = (struct ieee80211_hdr *)skb->data;
407
408 tx_info = IEEE80211_SKB_CB(skb);
409
410 memcpy(rates, tx_info->control.rates, sizeof(rates));
411
412 retries = ts->ts_longretry + 1;
413 for (i = 0; i < ts->ts_rateindex; i++)
414 retries += rates[i].count;
415
416 rcu_read_lock();
417
418 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
419 if (!sta) {
420 rcu_read_unlock();
421
422 INIT_LIST_HEAD(&bf_head);
423 while (bf) {
424 bf_next = bf->bf_next;
425
426 if (!bf->bf_stale || bf_next != NULL)
427 list_move_tail(&bf->list, &bf_head);
428
429 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
430
431 bf = bf_next;
432 }
433 return;
434 }
435
436 an = (struct ath_node *)sta->drv_priv;
437 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
438 tid = ATH_AN_2_TID(an, tidno);
439 seq_first = tid->seq_start;
440 isba = ts->ts_flags & ATH9K_TX_BA;
441
442
443
444
445
446
447
448
449
450 if (isba && tidno != ts->tid)
451 txok = false;
452
453 isaggr = bf_isaggr(bf);
454 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
455
456 if (isaggr && txok) {
457 if (ts->ts_flags & ATH9K_TX_BA) {
458 seq_st = ts->ts_seqnum;
459 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
460 } else {
461
462
463
464
465
466
467
468 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
469 needreset = 1;
470 }
471 }
472
473 __skb_queue_head_init(&bf_pending);
474
475 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
476 while (bf) {
477 u16 seqno = bf->bf_state.seqno;
478
479 txfail = txpending = sendbar = 0;
480 bf_next = bf->bf_next;
481
482 skb = bf->bf_mpdu;
483 tx_info = IEEE80211_SKB_CB(skb);
484 fi = get_frame_info(skb);
485
486 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
487
488
489 acked_cnt++;
490 } else if (!isaggr && txok) {
491
492 acked_cnt++;
493 } else if (tid->state & AGGR_CLEANUP) {
494
495
496
497
498 txfail = 1;
499 } else if (flush) {
500 txpending = 1;
501 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
502 if (txok || !an->sleeping)
503 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
504 retries);
505
506 txpending = 1;
507 } else {
508 txfail = 1;
509 txfail_cnt++;
510 bar_index = max_t(int, bar_index,
511 ATH_BA_INDEX(seq_first, seqno));
512 }
513
514
515
516
517
518 INIT_LIST_HEAD(&bf_head);
519 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
520 bf_next != NULL || !bf_last->bf_stale)
521 list_move_tail(&bf->list, &bf_head);
522
523 if (!txpending || (tid->state & AGGR_CLEANUP)) {
524
525
526
527
528 ath_tx_update_baw(sc, tid, seqno);
529
530 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
531 memcpy(tx_info->control.rates, rates, sizeof(rates));
532 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
533 rc_update = false;
534 }
535
536 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
537 !txfail);
538 } else {
539
540 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
541 bf->bf_next == NULL && bf_last->bf_stale) {
542 struct ath_buf *tbf;
543
544 tbf = ath_clone_txbuf(sc, bf_last);
545
546
547
548
549
550 if (!tbf) {
551 ath_tx_update_baw(sc, tid, seqno);
552
553 ath_tx_complete_buf(sc, bf, txq,
554 &bf_head, ts, 0);
555 bar_index = max_t(int, bar_index,
556 ATH_BA_INDEX(seq_first, seqno));
557 break;
558 }
559
560 fi->bf = tbf;
561 }
562
563
564
565
566
567 __skb_queue_tail(&bf_pending, skb);
568 }
569
570 bf = bf_next;
571 }
572
573
574 if (!skb_queue_empty(&bf_pending)) {
575 if (an->sleeping)
576 ieee80211_sta_set_buffered(sta, tid->tidno, true);
577
578 skb_queue_splice(&bf_pending, &tid->buf_q);
579 if (!an->sleeping) {
580 ath_tx_queue_tid(txq, tid);
581
582 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
583 tid->ac->clear_ps_filter = true;
584 }
585 }
586
587 if (bar_index >= 0) {
588 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
589
590 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
591 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
592
593 ath_txq_unlock(sc, txq);
594 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
595 ath_txq_lock(sc, txq);
596 }
597
598 if (tid->state & AGGR_CLEANUP)
599 ath_tx_flush_tid(sc, tid);
600
601 rcu_read_unlock();
602
603 if (needreset)
604 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
605}
606
607static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
608{
609 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
610 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
611}
612
613static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
614 struct ath_tx_status *ts, struct ath_buf *bf,
615 struct list_head *bf_head)
616{
617 bool txok, flush;
618
619 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
620 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
621 txq->axq_tx_inprogress = false;
622
623 txq->axq_depth--;
624 if (bf_is_ampdu_not_probing(bf))
625 txq->axq_ampdu_depth--;
626
627 if (!bf_isampdu(bf)) {
628 if (!flush)
629 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
630 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
631 } else
632 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
633
634 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !flush)
635 ath_txq_schedule(sc, txq);
636}
637
638static bool ath_lookup_legacy(struct ath_buf *bf)
639{
640 struct sk_buff *skb;
641 struct ieee80211_tx_info *tx_info;
642 struct ieee80211_tx_rate *rates;
643 int i;
644
645 skb = bf->bf_mpdu;
646 tx_info = IEEE80211_SKB_CB(skb);
647 rates = tx_info->control.rates;
648
649 for (i = 0; i < 4; i++) {
650 if (!rates[i].count || rates[i].idx < 0)
651 break;
652
653 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
654 return true;
655 }
656
657 return false;
658}
659
660static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
661 struct ath_atx_tid *tid)
662{
663 struct sk_buff *skb;
664 struct ieee80211_tx_info *tx_info;
665 struct ieee80211_tx_rate *rates;
666 u32 max_4ms_framelen, frmlen;
667 u16 aggr_limit, bt_aggr_limit, legacy = 0;
668 int q = tid->ac->txq->mac80211_qnum;
669 int i;
670
671 skb = bf->bf_mpdu;
672 tx_info = IEEE80211_SKB_CB(skb);
673 rates = tx_info->control.rates;
674
675
676
677
678
679 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
680
681 for (i = 0; i < 4; i++) {
682 int modeidx;
683
684 if (!rates[i].count)
685 continue;
686
687 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
688 legacy = 1;
689 break;
690 }
691
692 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
693 modeidx = MCS_HT40;
694 else
695 modeidx = MCS_HT20;
696
697 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
698 modeidx++;
699
700 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
701 max_4ms_framelen = min(max_4ms_framelen, frmlen);
702 }
703
704
705
706
707
708
709 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
710 return 0;
711
712 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
713
714
715
716
717 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
718 if (bt_aggr_limit)
719 aggr_limit = bt_aggr_limit;
720
721
722
723
724
725
726 if (tid->an->maxampdu)
727 aggr_limit = min(aggr_limit, tid->an->maxampdu);
728
729 return aggr_limit;
730}
731
732
733
734
735
736static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
737 struct ath_buf *bf, u16 frmlen,
738 bool first_subfrm)
739{
740#define FIRST_DESC_NDELIMS 60
741 struct sk_buff *skb = bf->bf_mpdu;
742 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
743 u32 nsymbits, nsymbols;
744 u16 minlen;
745 u8 flags, rix;
746 int width, streams, half_gi, ndelim, mindelim;
747 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
748
749
750 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
751
752
753
754
755
756
757
758 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
759 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
760 ndelim += ATH_AGGR_ENCRYPTDELIM;
761
762
763
764
765
766 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
767 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
768 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
769
770
771
772
773
774
775
776
777
778
779
780 if (tid->an->mpdudensity == 0)
781 return ndelim;
782
783 rix = tx_info->control.rates[0].idx;
784 flags = tx_info->control.rates[0].flags;
785 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
786 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
787
788 if (half_gi)
789 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
790 else
791 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
792
793 if (nsymbols == 0)
794 nsymbols = 1;
795
796 streams = HT_RC_2_STREAMS(rix);
797 nsymbits = bits_per_symbol[rix % 8][width] * streams;
798 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
799
800 if (frmlen < minlen) {
801 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
802 ndelim = max(mindelim, ndelim);
803 }
804
805 return ndelim;
806}
807
808static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
809 struct ath_txq *txq,
810 struct ath_atx_tid *tid,
811 struct list_head *bf_q,
812 int *aggr_len)
813{
814#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
815 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
816 int rl = 0, nframes = 0, ndelim, prev_al = 0;
817 u16 aggr_limit = 0, al = 0, bpad = 0,
818 al_delta, h_baw = tid->baw_size / 2;
819 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
820 struct ieee80211_tx_info *tx_info;
821 struct ath_frame_info *fi;
822 struct sk_buff *skb;
823 u16 seqno;
824
825 do {
826 skb = skb_peek(&tid->buf_q);
827 fi = get_frame_info(skb);
828 bf = fi->bf;
829 if (!fi->bf)
830 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
831
832 if (!bf) {
833 __skb_unlink(skb, &tid->buf_q);
834 ieee80211_free_txskb(sc->hw, skb);
835 continue;
836 }
837
838 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
839 seqno = bf->bf_state.seqno;
840
841
842 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
843 status = ATH_AGGR_BAW_CLOSED;
844 break;
845 }
846
847 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
848 struct ath_tx_status ts = {};
849 struct list_head bf_head;
850
851 INIT_LIST_HEAD(&bf_head);
852 list_add(&bf->list, &bf_head);
853 __skb_unlink(skb, &tid->buf_q);
854 ath_tx_update_baw(sc, tid, seqno);
855 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
856 continue;
857 }
858
859 if (!bf_first)
860 bf_first = bf;
861
862 if (!rl) {
863 aggr_limit = ath_lookup_rate(sc, bf, tid);
864 rl = 1;
865 }
866
867
868 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
869
870 if (nframes &&
871 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
872 ath_lookup_legacy(bf))) {
873 status = ATH_AGGR_LIMITED;
874 break;
875 }
876
877 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
878 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
879 break;
880
881
882 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
883 status = ATH_AGGR_LIMITED;
884 break;
885 }
886
887
888 al += bpad + al_delta;
889
890
891
892
893
894 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
895 !nframes);
896 bpad = PADBYTES(al_delta) + (ndelim << 2);
897
898 nframes++;
899 bf->bf_next = NULL;
900
901
902 if (!fi->retries)
903 ath_tx_addto_baw(sc, tid, seqno);
904 bf->bf_state.ndelim = ndelim;
905
906 __skb_unlink(skb, &tid->buf_q);
907 list_add_tail(&bf->list, bf_q);
908 if (bf_prev)
909 bf_prev->bf_next = bf;
910
911 bf_prev = bf;
912
913 } while (!skb_queue_empty(&tid->buf_q));
914
915 *aggr_len = al;
916
917 return status;
918#undef PADBYTES
919}
920
921
922
923
924
925
926
927static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
928 int width, int half_gi, bool shortPreamble)
929{
930 u32 nbits, nsymbits, duration, nsymbols;
931 int streams;
932
933
934 streams = HT_RC_2_STREAMS(rix);
935 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
936 nsymbits = bits_per_symbol[rix % 8][width] * streams;
937 nsymbols = (nbits + nsymbits - 1) / nsymbits;
938
939 if (!half_gi)
940 duration = SYMBOL_TIME(nsymbols);
941 else
942 duration = SYMBOL_TIME_HALFGI(nsymbols);
943
944
945 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
946
947 return duration;
948}
949
950static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
951{
952 int streams = HT_RC_2_STREAMS(mcs);
953 int symbols, bits;
954 int bytes = 0;
955
956 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
957 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
958 bits -= OFDM_PLCP_BITS;
959 bytes = bits / 8;
960 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
961 if (bytes > 65532)
962 bytes = 65532;
963
964 return bytes;
965}
966
967void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
968{
969 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
970 int mcs;
971
972
973 if (!txop || txop > 4096)
974 txop = 4096;
975
976 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
977 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
978 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
979 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
980 for (mcs = 0; mcs < 32; mcs++) {
981 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
982 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
983 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
984 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
985 }
986}
987
988static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
989 struct ath_tx_info *info, int len)
990{
991 struct ath_hw *ah = sc->sc_ah;
992 struct sk_buff *skb;
993 struct ieee80211_tx_info *tx_info;
994 struct ieee80211_tx_rate *rates;
995 const struct ieee80211_rate *rate;
996 struct ieee80211_hdr *hdr;
997 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
998 int i;
999 u8 rix = 0;
1000
1001 skb = bf->bf_mpdu;
1002 tx_info = IEEE80211_SKB_CB(skb);
1003 rates = tx_info->control.rates;
1004 hdr = (struct ieee80211_hdr *)skb->data;
1005
1006
1007 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1008 info->rtscts_rate = fi->rtscts_rate;
1009
1010 for (i = 0; i < 4; i++) {
1011 bool is_40, is_sgi, is_sp;
1012 int phy;
1013
1014 if (!rates[i].count || (rates[i].idx < 0))
1015 continue;
1016
1017 rix = rates[i].idx;
1018 info->rates[i].Tries = rates[i].count;
1019
1020 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1021 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1022 info->flags |= ATH9K_TXDESC_RTSENA;
1023 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1024 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1025 info->flags |= ATH9K_TXDESC_CTSENA;
1026 }
1027
1028 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1029 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1030 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1031 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1032
1033 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1034 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1035 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1036
1037 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1038
1039 info->rates[i].Rate = rix | 0x80;
1040 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1041 ah->txchainmask, info->rates[i].Rate);
1042 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1043 is_40, is_sgi, is_sp);
1044 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1045 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1046 continue;
1047 }
1048
1049
1050 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1051 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1052 !(rate->flags & IEEE80211_RATE_ERP_G))
1053 phy = WLAN_RC_PHY_CCK;
1054 else
1055 phy = WLAN_RC_PHY_OFDM;
1056
1057 info->rates[i].Rate = rate->hw_value;
1058 if (rate->hw_value_short) {
1059 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1060 info->rates[i].Rate |= rate->hw_value_short;
1061 } else {
1062 is_sp = false;
1063 }
1064
1065 if (bf->bf_state.bfs_paprd)
1066 info->rates[i].ChSel = ah->txchainmask;
1067 else
1068 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1069 ah->txchainmask, info->rates[i].Rate);
1070
1071 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1072 phy, rate->bitrate * 100, len, rix, is_sp);
1073 }
1074
1075
1076 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1077 info->flags &= ~ATH9K_TXDESC_RTSENA;
1078
1079
1080 if (info->flags & ATH9K_TXDESC_RTSENA)
1081 info->flags &= ~ATH9K_TXDESC_CTSENA;
1082}
1083
1084static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1085{
1086 struct ieee80211_hdr *hdr;
1087 enum ath9k_pkt_type htype;
1088 __le16 fc;
1089
1090 hdr = (struct ieee80211_hdr *)skb->data;
1091 fc = hdr->frame_control;
1092
1093 if (ieee80211_is_beacon(fc))
1094 htype = ATH9K_PKT_TYPE_BEACON;
1095 else if (ieee80211_is_probe_resp(fc))
1096 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1097 else if (ieee80211_is_atim(fc))
1098 htype = ATH9K_PKT_TYPE_ATIM;
1099 else if (ieee80211_is_pspoll(fc))
1100 htype = ATH9K_PKT_TYPE_PSPOLL;
1101 else
1102 htype = ATH9K_PKT_TYPE_NORMAL;
1103
1104 return htype;
1105}
1106
1107static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1108 struct ath_txq *txq, int len)
1109{
1110 struct ath_hw *ah = sc->sc_ah;
1111 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1112 struct ath_buf *bf_first = bf;
1113 struct ath_tx_info info;
1114 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1115
1116 memset(&info, 0, sizeof(info));
1117 info.is_first = true;
1118 info.is_last = true;
1119 info.txpower = MAX_RATE_POWER;
1120 info.qcu = txq->axq_qnum;
1121
1122 info.flags = ATH9K_TXDESC_INTREQ;
1123 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1124 info.flags |= ATH9K_TXDESC_NOACK;
1125 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1126 info.flags |= ATH9K_TXDESC_LDPC;
1127
1128 ath_buf_set_rate(sc, bf, &info, len);
1129
1130 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1131 info.flags |= ATH9K_TXDESC_CLRDMASK;
1132
1133 if (bf->bf_state.bfs_paprd)
1134 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1135
1136
1137 while (bf) {
1138 struct sk_buff *skb = bf->bf_mpdu;
1139 struct ath_frame_info *fi = get_frame_info(skb);
1140
1141 info.type = get_hw_packet_type(skb);
1142 if (bf->bf_next)
1143 info.link = bf->bf_next->bf_daddr;
1144 else
1145 info.link = 0;
1146
1147 info.buf_addr[0] = bf->bf_buf_addr;
1148 info.buf_len[0] = skb->len;
1149 info.pkt_len = fi->framelen;
1150 info.keyix = fi->keyix;
1151 info.keytype = fi->keytype;
1152
1153 if (aggr) {
1154 if (bf == bf_first)
1155 info.aggr = AGGR_BUF_FIRST;
1156 else if (!bf->bf_next)
1157 info.aggr = AGGR_BUF_LAST;
1158 else
1159 info.aggr = AGGR_BUF_MIDDLE;
1160
1161 info.ndelim = bf->bf_state.ndelim;
1162 info.aggr_len = len;
1163 }
1164
1165 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1166 bf = bf->bf_next;
1167 }
1168}
1169
1170static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1171 struct ath_atx_tid *tid)
1172{
1173 struct ath_buf *bf;
1174 enum ATH_AGGR_STATUS status;
1175 struct ieee80211_tx_info *tx_info;
1176 struct list_head bf_q;
1177 int aggr_len;
1178
1179 do {
1180 if (skb_queue_empty(&tid->buf_q))
1181 return;
1182
1183 INIT_LIST_HEAD(&bf_q);
1184
1185 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1186
1187
1188
1189
1190
1191 if (list_empty(&bf_q))
1192 break;
1193
1194 bf = list_first_entry(&bf_q, struct ath_buf, list);
1195 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1196 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1197
1198 if (tid->ac->clear_ps_filter) {
1199 tid->ac->clear_ps_filter = false;
1200 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1201 } else {
1202 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1203 }
1204
1205
1206 if (bf == bf->bf_lastbf) {
1207 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1208 bf->bf_state.bf_type = BUF_AMPDU;
1209 } else {
1210 TX_STAT_INC(txq->axq_qnum, a_aggr);
1211 }
1212
1213 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1214 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1215 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1216 status != ATH_AGGR_BAW_CLOSED);
1217}
1218
1219int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1220 u16 tid, u16 *ssn)
1221{
1222 struct ath_atx_tid *txtid;
1223 struct ath_node *an;
1224 u8 density;
1225
1226 an = (struct ath_node *)sta->drv_priv;
1227 txtid = ATH_AN_2_TID(an, tid);
1228
1229 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1230 return -EAGAIN;
1231
1232
1233
1234
1235
1236 if (sta->ht_cap.ht_supported) {
1237 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1238 sta->ht_cap.ampdu_factor);
1239 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1240 an->mpdudensity = density;
1241 }
1242
1243 txtid->state |= AGGR_ADDBA_PROGRESS;
1244 txtid->paused = true;
1245 *ssn = txtid->seq_start = txtid->seq_next;
1246 txtid->bar_index = -1;
1247
1248 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1249 txtid->baw_head = txtid->baw_tail = 0;
1250
1251 return 0;
1252}
1253
1254void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1255{
1256 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1257 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1258 struct ath_txq *txq = txtid->ac->txq;
1259
1260 if (txtid->state & AGGR_CLEANUP)
1261 return;
1262
1263 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1264 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1265 return;
1266 }
1267
1268 ath_txq_lock(sc, txq);
1269 txtid->paused = true;
1270
1271
1272
1273
1274
1275
1276
1277 if (txtid->baw_head != txtid->baw_tail)
1278 txtid->state |= AGGR_CLEANUP;
1279 else
1280 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1281
1282 ath_tx_flush_tid(sc, txtid);
1283 ath_txq_unlock_complete(sc, txq);
1284}
1285
1286void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1287 struct ath_node *an)
1288{
1289 struct ath_atx_tid *tid;
1290 struct ath_atx_ac *ac;
1291 struct ath_txq *txq;
1292 bool buffered;
1293 int tidno;
1294
1295 for (tidno = 0, tid = &an->tid[tidno];
1296 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1297
1298 if (!tid->sched)
1299 continue;
1300
1301 ac = tid->ac;
1302 txq = ac->txq;
1303
1304 ath_txq_lock(sc, txq);
1305
1306 buffered = !skb_queue_empty(&tid->buf_q);
1307
1308 tid->sched = false;
1309 list_del(&tid->list);
1310
1311 if (ac->sched) {
1312 ac->sched = false;
1313 list_del(&ac->list);
1314 }
1315
1316 ath_txq_unlock(sc, txq);
1317
1318 ieee80211_sta_set_buffered(sta, tidno, buffered);
1319 }
1320}
1321
1322void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1323{
1324 struct ath_atx_tid *tid;
1325 struct ath_atx_ac *ac;
1326 struct ath_txq *txq;
1327 int tidno;
1328
1329 for (tidno = 0, tid = &an->tid[tidno];
1330 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1331
1332 ac = tid->ac;
1333 txq = ac->txq;
1334
1335 ath_txq_lock(sc, txq);
1336 ac->clear_ps_filter = true;
1337
1338 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1339 ath_tx_queue_tid(txq, tid);
1340 ath_txq_schedule(sc, txq);
1341 }
1342
1343 ath_txq_unlock_complete(sc, txq);
1344 }
1345}
1346
1347void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1348{
1349 struct ath_atx_tid *txtid;
1350 struct ath_node *an;
1351
1352 an = (struct ath_node *)sta->drv_priv;
1353
1354 txtid = ATH_AN_2_TID(an, tid);
1355 txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1356 txtid->state |= AGGR_ADDBA_COMPLETE;
1357 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1358 ath_tx_resume_tid(sc, txtid);
1359}
1360
1361
1362
1363
1364
1365struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1366{
1367 struct ath_hw *ah = sc->sc_ah;
1368 struct ath9k_tx_queue_info qi;
1369 static const int subtype_txq_to_hwq[] = {
1370 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1371 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1372 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1373 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1374 };
1375 int axq_qnum, i;
1376
1377 memset(&qi, 0, sizeof(qi));
1378 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1379 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1380 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1381 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1382 qi.tqi_physCompBuf = 0;
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1400 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1401 } else {
1402 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1403 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1404 else
1405 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1406 TXQ_FLAG_TXDESCINT_ENABLE;
1407 }
1408 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1409 if (axq_qnum == -1) {
1410
1411
1412
1413
1414 return NULL;
1415 }
1416 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1417 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1418
1419 txq->axq_qnum = axq_qnum;
1420 txq->mac80211_qnum = -1;
1421 txq->axq_link = NULL;
1422 __skb_queue_head_init(&txq->complete_q);
1423 INIT_LIST_HEAD(&txq->axq_q);
1424 INIT_LIST_HEAD(&txq->axq_acq);
1425 spin_lock_init(&txq->axq_lock);
1426 txq->axq_depth = 0;
1427 txq->axq_ampdu_depth = 0;
1428 txq->axq_tx_inprogress = false;
1429 sc->tx.txqsetup |= 1<<axq_qnum;
1430
1431 txq->txq_headidx = txq->txq_tailidx = 0;
1432 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1433 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1434 }
1435 return &sc->tx.txq[axq_qnum];
1436}
1437
1438int ath_txq_update(struct ath_softc *sc, int qnum,
1439 struct ath9k_tx_queue_info *qinfo)
1440{
1441 struct ath_hw *ah = sc->sc_ah;
1442 int error = 0;
1443 struct ath9k_tx_queue_info qi;
1444
1445 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1446
1447 ath9k_hw_get_txq_props(ah, qnum, &qi);
1448 qi.tqi_aifs = qinfo->tqi_aifs;
1449 qi.tqi_cwmin = qinfo->tqi_cwmin;
1450 qi.tqi_cwmax = qinfo->tqi_cwmax;
1451 qi.tqi_burstTime = qinfo->tqi_burstTime;
1452 qi.tqi_readyTime = qinfo->tqi_readyTime;
1453
1454 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1455 ath_err(ath9k_hw_common(sc->sc_ah),
1456 "Unable to update hardware queue %u!\n", qnum);
1457 error = -EIO;
1458 } else {
1459 ath9k_hw_resettxqueue(ah, qnum);
1460 }
1461
1462 return error;
1463}
1464
1465int ath_cabq_update(struct ath_softc *sc)
1466{
1467 struct ath9k_tx_queue_info qi;
1468 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1469 int qnum = sc->beacon.cabq->axq_qnum;
1470
1471 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1472
1473
1474
1475 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1476 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1477 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1478 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1479
1480 qi.tqi_readyTime = (cur_conf->beacon_interval *
1481 sc->config.cabqReadytime) / 100;
1482 ath_txq_update(sc, qnum, &qi);
1483
1484 return 0;
1485}
1486
1487static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1488 struct list_head *list)
1489{
1490 struct ath_buf *bf, *lastbf;
1491 struct list_head bf_head;
1492 struct ath_tx_status ts;
1493
1494 memset(&ts, 0, sizeof(ts));
1495 ts.ts_status = ATH9K_TX_FLUSH;
1496 INIT_LIST_HEAD(&bf_head);
1497
1498 while (!list_empty(list)) {
1499 bf = list_first_entry(list, struct ath_buf, list);
1500
1501 if (bf->bf_stale) {
1502 list_del(&bf->list);
1503
1504 ath_tx_return_buffer(sc, bf);
1505 continue;
1506 }
1507
1508 lastbf = bf->bf_lastbf;
1509 list_cut_position(&bf_head, list, &lastbf->list);
1510 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1511 }
1512}
1513
1514
1515
1516
1517
1518
1519
1520void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1521{
1522 ath_txq_lock(sc, txq);
1523
1524 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1525 int idx = txq->txq_tailidx;
1526
1527 while (!list_empty(&txq->txq_fifo[idx])) {
1528 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1529
1530 INCR(idx, ATH_TXFIFO_DEPTH);
1531 }
1532 txq->txq_tailidx = idx;
1533 }
1534
1535 txq->axq_link = NULL;
1536 txq->axq_tx_inprogress = false;
1537 ath_drain_txq_list(sc, txq, &txq->axq_q);
1538
1539 ath_txq_unlock_complete(sc, txq);
1540}
1541
1542bool ath_drain_all_txq(struct ath_softc *sc)
1543{
1544 struct ath_hw *ah = sc->sc_ah;
1545 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1546 struct ath_txq *txq;
1547 int i;
1548 u32 npend = 0;
1549
1550 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1551 return true;
1552
1553 ath9k_hw_abort_tx_dma(ah);
1554
1555
1556 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1557 if (!ATH_TXQ_SETUP(sc, i))
1558 continue;
1559
1560 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1561 npend |= BIT(i);
1562 }
1563
1564 if (npend)
1565 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1566
1567 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1568 if (!ATH_TXQ_SETUP(sc, i))
1569 continue;
1570
1571
1572
1573
1574
1575
1576 txq = &sc->tx.txq[i];
1577 txq->stopped = false;
1578 ath_draintxq(sc, txq);
1579 }
1580
1581 return !npend;
1582}
1583
1584void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1585{
1586 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1587 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1588}
1589
1590
1591
1592
1593void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1594{
1595 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1596 struct ath_atx_tid *tid, *last_tid;
1597
1598 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
1599 list_empty(&txq->axq_acq) ||
1600 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1601 return;
1602
1603 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1604 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1605
1606 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1607 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1608 list_del(&ac->list);
1609 ac->sched = false;
1610
1611 while (!list_empty(&ac->tid_q)) {
1612 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1613 list);
1614 list_del(&tid->list);
1615 tid->sched = false;
1616
1617 if (tid->paused)
1618 continue;
1619
1620 ath_tx_sched_aggr(sc, txq, tid);
1621
1622
1623
1624
1625
1626 if (!skb_queue_empty(&tid->buf_q))
1627 ath_tx_queue_tid(txq, tid);
1628
1629 if (tid == last_tid ||
1630 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1631 break;
1632 }
1633
1634 if (!list_empty(&ac->tid_q) && !ac->sched) {
1635 ac->sched = true;
1636 list_add_tail(&ac->list, &txq->axq_acq);
1637 }
1638
1639 if (ac == last_ac ||
1640 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1641 return;
1642 }
1643}
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1654 struct list_head *head, bool internal)
1655{
1656 struct ath_hw *ah = sc->sc_ah;
1657 struct ath_common *common = ath9k_hw_common(ah);
1658 struct ath_buf *bf, *bf_last;
1659 bool puttxbuf = false;
1660 bool edma;
1661
1662
1663
1664
1665
1666
1667 if (list_empty(head))
1668 return;
1669
1670 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1671 bf = list_first_entry(head, struct ath_buf, list);
1672 bf_last = list_entry(head->prev, struct ath_buf, list);
1673
1674 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1675 txq->axq_qnum, txq->axq_depth);
1676
1677 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1678 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1679 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1680 puttxbuf = true;
1681 } else {
1682 list_splice_tail_init(head, &txq->axq_q);
1683
1684 if (txq->axq_link) {
1685 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1686 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1687 txq->axq_qnum, txq->axq_link,
1688 ito64(bf->bf_daddr), bf->bf_desc);
1689 } else if (!edma)
1690 puttxbuf = true;
1691
1692 txq->axq_link = bf_last->bf_desc;
1693 }
1694
1695 if (puttxbuf) {
1696 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1697 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1698 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1699 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1700 }
1701
1702 if (!edma) {
1703 TX_STAT_INC(txq->axq_qnum, txstart);
1704 ath9k_hw_txstart(ah, txq->axq_qnum);
1705 }
1706
1707 if (!internal) {
1708 txq->axq_depth++;
1709 if (bf_is_ampdu_not_probing(bf))
1710 txq->axq_ampdu_depth++;
1711 }
1712}
1713
1714static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1715 struct sk_buff *skb, struct ath_tx_control *txctl)
1716{
1717 struct ath_frame_info *fi = get_frame_info(skb);
1718 struct list_head bf_head;
1719 struct ath_buf *bf;
1720
1721
1722
1723
1724
1725
1726
1727
1728 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1729 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1730 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1731
1732
1733
1734
1735 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1736 __skb_queue_tail(&tid->buf_q, skb);
1737 if (!txctl->an || !txctl->an->sleeping)
1738 ath_tx_queue_tid(txctl->txq, tid);
1739 return;
1740 }
1741
1742 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1743 if (!bf) {
1744 ieee80211_free_txskb(sc->hw, skb);
1745 return;
1746 }
1747
1748 bf->bf_state.bf_type = BUF_AMPDU;
1749 INIT_LIST_HEAD(&bf_head);
1750 list_add(&bf->list, &bf_head);
1751
1752
1753 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1754
1755
1756 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1757 bf->bf_lastbf = bf;
1758 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1759 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1760}
1761
1762static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1763 struct ath_atx_tid *tid, struct sk_buff *skb)
1764{
1765 struct ath_frame_info *fi = get_frame_info(skb);
1766 struct list_head bf_head;
1767 struct ath_buf *bf;
1768
1769 bf = fi->bf;
1770
1771 INIT_LIST_HEAD(&bf_head);
1772 list_add_tail(&bf->list, &bf_head);
1773 bf->bf_state.bf_type = 0;
1774
1775 bf->bf_next = NULL;
1776 bf->bf_lastbf = bf;
1777 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1778 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1779 TX_STAT_INC(txq->axq_qnum, queued);
1780}
1781
1782static void setup_frame_info(struct ieee80211_hw *hw,
1783 struct ieee80211_sta *sta,
1784 struct sk_buff *skb,
1785 int framelen)
1786{
1787 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1788 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1789 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1790 const struct ieee80211_rate *rate;
1791 struct ath_frame_info *fi = get_frame_info(skb);
1792 struct ath_node *an = NULL;
1793 enum ath9k_key_type keytype;
1794 bool short_preamble = false;
1795
1796
1797
1798
1799
1800
1801 if (tx_info->control.vif &&
1802 tx_info->control.vif->bss_conf.use_short_preamble)
1803 short_preamble = true;
1804
1805 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
1806 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1807
1808 if (sta)
1809 an = (struct ath_node *) sta->drv_priv;
1810
1811 memset(fi, 0, sizeof(*fi));
1812 if (hw_key)
1813 fi->keyix = hw_key->hw_key_idx;
1814 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1815 fi->keyix = an->ps_key;
1816 else
1817 fi->keyix = ATH9K_TXKEYIX_INVALID;
1818 fi->keytype = keytype;
1819 fi->framelen = framelen;
1820 fi->rtscts_rate = rate->hw_value;
1821 if (short_preamble)
1822 fi->rtscts_rate |= rate->hw_value_short;
1823}
1824
1825u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1826{
1827 struct ath_hw *ah = sc->sc_ah;
1828 struct ath9k_channel *curchan = ah->curchan;
1829
1830 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1831 (curchan->channelFlags & CHANNEL_5GHZ) &&
1832 (chainmask == 0x7) && (rate < 0x90))
1833 return 0x3;
1834 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
1835 IS_CCK_RATE(rate))
1836 return 0x2;
1837 else
1838 return chainmask;
1839}
1840
1841
1842
1843
1844
1845static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1846 struct ath_txq *txq,
1847 struct ath_atx_tid *tid,
1848 struct sk_buff *skb)
1849{
1850 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1851 struct ath_frame_info *fi = get_frame_info(skb);
1852 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1853 struct ath_buf *bf;
1854 int fragno;
1855 u16 seqno;
1856
1857 bf = ath_tx_get_buffer(sc);
1858 if (!bf) {
1859 ath_dbg(common, XMIT, "TX buffers are full\n");
1860 return NULL;
1861 }
1862
1863 ATH_TXBUF_RESET(bf);
1864
1865 if (tid) {
1866 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
1867 seqno = tid->seq_next;
1868 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1869
1870 if (fragno)
1871 hdr->seq_ctrl |= cpu_to_le16(fragno);
1872
1873 if (!ieee80211_has_morefrags(hdr->frame_control))
1874 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1875
1876 bf->bf_state.seqno = seqno;
1877 }
1878
1879 bf->bf_mpdu = skb;
1880
1881 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1882 skb->len, DMA_TO_DEVICE);
1883 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1884 bf->bf_mpdu = NULL;
1885 bf->bf_buf_addr = 0;
1886 ath_err(ath9k_hw_common(sc->sc_ah),
1887 "dma_mapping_error() on TX\n");
1888 ath_tx_return_buffer(sc, bf);
1889 return NULL;
1890 }
1891
1892 fi->bf = bf;
1893
1894 return bf;
1895}
1896
1897
1898static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1899 struct ath_tx_control *txctl)
1900{
1901 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1902 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1903 struct ath_atx_tid *tid = NULL;
1904 struct ath_buf *bf;
1905 u8 tidno;
1906
1907 if (txctl->an && ieee80211_is_data_qos(hdr->frame_control)) {
1908 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1909 IEEE80211_QOS_CTL_TID_MASK;
1910 tid = ATH_AN_2_TID(txctl->an, tidno);
1911
1912 WARN_ON(tid->ac->txq != txctl->txq);
1913 }
1914
1915 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1916
1917
1918
1919
1920 ath_tx_send_ampdu(sc, tid, skb, txctl);
1921 } else {
1922 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1923 if (!bf) {
1924 if (txctl->paprd)
1925 dev_kfree_skb_any(skb);
1926 else
1927 ieee80211_free_txskb(sc->hw, skb);
1928 return;
1929 }
1930
1931 bf->bf_state.bfs_paprd = txctl->paprd;
1932
1933 if (txctl->paprd)
1934 bf->bf_state.bfs_paprd_timestamp = jiffies;
1935
1936 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1937 }
1938}
1939
1940
1941int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1942 struct ath_tx_control *txctl)
1943{
1944 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1945 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1946 struct ieee80211_sta *sta = txctl->sta;
1947 struct ieee80211_vif *vif = info->control.vif;
1948 struct ath_softc *sc = hw->priv;
1949 struct ath_txq *txq = txctl->txq;
1950 int padpos, padsize;
1951 int frmlen = skb->len + FCS_LEN;
1952 int q;
1953
1954
1955 if (sta)
1956 txctl->an = (struct ath_node *)sta->drv_priv;
1957
1958 if (info->control.hw_key)
1959 frmlen += info->control.hw_key->icv_len;
1960
1961
1962
1963
1964
1965
1966 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1967 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1968 sc->tx.seq_no += 0x10;
1969 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1970 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1971 }
1972
1973
1974 padpos = ath9k_cmn_padpos(hdr->frame_control);
1975 padsize = padpos & 3;
1976 if (padsize && skb->len > padpos) {
1977 if (skb_headroom(skb) < padsize)
1978 return -ENOMEM;
1979
1980 skb_push(skb, padsize);
1981 memmove(skb->data, skb->data + padsize, padpos);
1982 hdr = (struct ieee80211_hdr *) skb->data;
1983 }
1984
1985 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1986 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1987 !ieee80211_is_data(hdr->frame_control))
1988 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1989
1990 setup_frame_info(hw, sta, skb, frmlen);
1991
1992
1993
1994
1995
1996
1997 q = skb_get_queue_mapping(skb);
1998
1999 ath_txq_lock(sc, txq);
2000 if (txq == sc->tx.txq_map[q] &&
2001 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2002 !txq->stopped) {
2003 ieee80211_stop_queue(sc->hw, q);
2004 txq->stopped = true;
2005 }
2006
2007 ath_tx_start_dma(sc, skb, txctl);
2008
2009 ath_txq_unlock(sc, txq);
2010
2011 return 0;
2012}
2013
2014
2015
2016
2017
2018static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2019 int tx_flags, struct ath_txq *txq)
2020{
2021 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2022 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2023 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2024 int q, padpos, padsize;
2025 unsigned long flags;
2026
2027 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2028
2029 if (sc->sc_ah->caldata)
2030 sc->sc_ah->caldata->paprd_packet_sent = true;
2031
2032 if (!(tx_flags & ATH_TX_ERROR))
2033
2034 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2035
2036 padpos = ath9k_cmn_padpos(hdr->frame_control);
2037 padsize = padpos & 3;
2038 if (padsize && skb->len>padpos+padsize) {
2039
2040
2041
2042
2043 memmove(skb->data + padsize, skb->data, padpos);
2044 skb_pull(skb, padsize);
2045 }
2046
2047 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2048 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2049 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2050 ath_dbg(common, PS,
2051 "Going back to sleep after having received TX status (0x%lx)\n",
2052 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2053 PS_WAIT_FOR_CAB |
2054 PS_WAIT_FOR_PSPOLL_DATA |
2055 PS_WAIT_FOR_TX_ACK));
2056 }
2057 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2058
2059 q = skb_get_queue_mapping(skb);
2060 if (txq == sc->tx.txq_map[q]) {
2061 if (WARN_ON(--txq->pending_frames < 0))
2062 txq->pending_frames = 0;
2063
2064 if (txq->stopped &&
2065 txq->pending_frames < sc->tx.txq_max_pending[q]) {
2066 ieee80211_wake_queue(sc->hw, q);
2067 txq->stopped = false;
2068 }
2069 }
2070
2071 __skb_queue_tail(&txq->complete_q, skb);
2072}
2073
2074static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2075 struct ath_txq *txq, struct list_head *bf_q,
2076 struct ath_tx_status *ts, int txok)
2077{
2078 struct sk_buff *skb = bf->bf_mpdu;
2079 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2080 unsigned long flags;
2081 int tx_flags = 0;
2082
2083 if (!txok)
2084 tx_flags |= ATH_TX_ERROR;
2085
2086 if (ts->ts_status & ATH9K_TXERR_FILT)
2087 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2088
2089 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2090 bf->bf_buf_addr = 0;
2091
2092 if (bf->bf_state.bfs_paprd) {
2093 if (time_after(jiffies,
2094 bf->bf_state.bfs_paprd_timestamp +
2095 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2096 dev_kfree_skb_any(skb);
2097 else
2098 complete(&sc->paprd_complete);
2099 } else {
2100 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2101 ath_tx_complete(sc, skb, tx_flags, txq);
2102 }
2103
2104
2105
2106 bf->bf_mpdu = NULL;
2107
2108
2109
2110
2111 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2112 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2113 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2114}
2115
2116static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2117 struct ath_tx_status *ts, int nframes, int nbad,
2118 int txok)
2119{
2120 struct sk_buff *skb = bf->bf_mpdu;
2121 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2122 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2123 struct ieee80211_hw *hw = sc->hw;
2124 struct ath_hw *ah = sc->sc_ah;
2125 u8 i, tx_rateindex;
2126
2127 if (txok)
2128 tx_info->status.ack_signal = ts->ts_rssi;
2129
2130 tx_rateindex = ts->ts_rateindex;
2131 WARN_ON(tx_rateindex >= hw->max_rates);
2132
2133 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2134 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2135
2136 BUG_ON(nbad > nframes);
2137 }
2138 tx_info->status.ampdu_len = nframes;
2139 tx_info->status.ampdu_ack_len = nframes - nbad;
2140
2141 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2142 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2156 ATH9K_TX_DELIM_UNDERRUN)) &&
2157 ieee80211_is_data(hdr->frame_control) &&
2158 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2159 tx_info->status.rates[tx_rateindex].count =
2160 hw->max_rate_tries;
2161 }
2162
2163 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2164 tx_info->status.rates[i].count = 0;
2165 tx_info->status.rates[i].idx = -1;
2166 }
2167
2168 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2169}
2170
2171static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2172{
2173 struct ath_hw *ah = sc->sc_ah;
2174 struct ath_common *common = ath9k_hw_common(ah);
2175 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2176 struct list_head bf_head;
2177 struct ath_desc *ds;
2178 struct ath_tx_status ts;
2179 int status;
2180
2181 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2182 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2183 txq->axq_link);
2184
2185 ath_txq_lock(sc, txq);
2186 for (;;) {
2187 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2188 break;
2189
2190 if (list_empty(&txq->axq_q)) {
2191 txq->axq_link = NULL;
2192 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2193 ath_txq_schedule(sc, txq);
2194 break;
2195 }
2196 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206 bf_held = NULL;
2207 if (bf->bf_stale) {
2208 bf_held = bf;
2209 if (list_is_last(&bf_held->list, &txq->axq_q))
2210 break;
2211
2212 bf = list_entry(bf_held->list.next, struct ath_buf,
2213 list);
2214 }
2215
2216 lastbf = bf->bf_lastbf;
2217 ds = lastbf->bf_desc;
2218
2219 memset(&ts, 0, sizeof(ts));
2220 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2221 if (status == -EINPROGRESS)
2222 break;
2223
2224 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2225
2226
2227
2228
2229
2230
2231 lastbf->bf_stale = true;
2232 INIT_LIST_HEAD(&bf_head);
2233 if (!list_is_singular(&lastbf->list))
2234 list_cut_position(&bf_head,
2235 &txq->axq_q, lastbf->list.prev);
2236
2237 if (bf_held) {
2238 list_del(&bf_held->list);
2239 ath_tx_return_buffer(sc, bf_held);
2240 }
2241
2242 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2243 }
2244 ath_txq_unlock_complete(sc, txq);
2245}
2246
2247void ath_tx_tasklet(struct ath_softc *sc)
2248{
2249 struct ath_hw *ah = sc->sc_ah;
2250 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2251 int i;
2252
2253 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2254 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2255 ath_tx_processq(sc, &sc->tx.txq[i]);
2256 }
2257}
2258
2259void ath_tx_edma_tasklet(struct ath_softc *sc)
2260{
2261 struct ath_tx_status ts;
2262 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2263 struct ath_hw *ah = sc->sc_ah;
2264 struct ath_txq *txq;
2265 struct ath_buf *bf, *lastbf;
2266 struct list_head bf_head;
2267 int status;
2268
2269 for (;;) {
2270 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
2271 break;
2272
2273 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2274 if (status == -EINPROGRESS)
2275 break;
2276 if (status == -EIO) {
2277 ath_dbg(common, XMIT, "Error processing tx status\n");
2278 break;
2279 }
2280
2281
2282 if (ts.qid == sc->beacon.beaconq) {
2283 sc->beacon.tx_processed = true;
2284 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2285 continue;
2286 }
2287
2288 txq = &sc->tx.txq[ts.qid];
2289
2290 ath_txq_lock(sc, txq);
2291
2292 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2293
2294 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2295 ath_txq_unlock(sc, txq);
2296 return;
2297 }
2298
2299 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2300 struct ath_buf, list);
2301 lastbf = bf->bf_lastbf;
2302
2303 INIT_LIST_HEAD(&bf_head);
2304 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2305 &lastbf->list);
2306
2307 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2308 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2309
2310 if (!list_empty(&txq->axq_q)) {
2311 struct list_head bf_q;
2312
2313 INIT_LIST_HEAD(&bf_q);
2314 txq->axq_link = NULL;
2315 list_splice_tail_init(&txq->axq_q, &bf_q);
2316 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2317 }
2318 }
2319
2320 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2321 ath_txq_unlock_complete(sc, txq);
2322 }
2323}
2324
2325
2326
2327
2328
2329static int ath_txstatus_setup(struct ath_softc *sc, int size)
2330{
2331 struct ath_descdma *dd = &sc->txsdma;
2332 u8 txs_len = sc->sc_ah->caps.txs_len;
2333
2334 dd->dd_desc_len = size * txs_len;
2335 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2336 &dd->dd_desc_paddr, GFP_KERNEL);
2337 if (!dd->dd_desc)
2338 return -ENOMEM;
2339
2340 return 0;
2341}
2342
2343static int ath_tx_edma_init(struct ath_softc *sc)
2344{
2345 int err;
2346
2347 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2348 if (!err)
2349 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2350 sc->txsdma.dd_desc_paddr,
2351 ATH_TXSTATUS_RING_SIZE);
2352
2353 return err;
2354}
2355
2356int ath_tx_init(struct ath_softc *sc, int nbufs)
2357{
2358 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2359 int error = 0;
2360
2361 spin_lock_init(&sc->tx.txbuflock);
2362
2363 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2364 "tx", nbufs, 1, 1);
2365 if (error != 0) {
2366 ath_err(common,
2367 "Failed to allocate tx descriptors: %d\n", error);
2368 return error;
2369 }
2370
2371 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2372 "beacon", ATH_BCBUF, 1, 1);
2373 if (error != 0) {
2374 ath_err(common,
2375 "Failed to allocate beacon descriptors: %d\n", error);
2376 return error;
2377 }
2378
2379 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2380
2381 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2382 error = ath_tx_edma_init(sc);
2383
2384 return error;
2385}
2386
2387void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2388{
2389 struct ath_atx_tid *tid;
2390 struct ath_atx_ac *ac;
2391 int tidno, acno;
2392
2393 for (tidno = 0, tid = &an->tid[tidno];
2394 tidno < IEEE80211_NUM_TIDS;
2395 tidno++, tid++) {
2396 tid->an = an;
2397 tid->tidno = tidno;
2398 tid->seq_start = tid->seq_next = 0;
2399 tid->baw_size = WME_MAX_BA;
2400 tid->baw_head = tid->baw_tail = 0;
2401 tid->sched = false;
2402 tid->paused = false;
2403 tid->state &= ~AGGR_CLEANUP;
2404 __skb_queue_head_init(&tid->buf_q);
2405 acno = TID_TO_WME_AC(tidno);
2406 tid->ac = &an->ac[acno];
2407 tid->state &= ~AGGR_ADDBA_COMPLETE;
2408 tid->state &= ~AGGR_ADDBA_PROGRESS;
2409 }
2410
2411 for (acno = 0, ac = &an->ac[acno];
2412 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2413 ac->sched = false;
2414 ac->txq = sc->tx.txq_map[acno];
2415 INIT_LIST_HEAD(&ac->tid_q);
2416 }
2417}
2418
2419void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2420{
2421 struct ath_atx_ac *ac;
2422 struct ath_atx_tid *tid;
2423 struct ath_txq *txq;
2424 int tidno;
2425
2426 for (tidno = 0, tid = &an->tid[tidno];
2427 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2428
2429 ac = tid->ac;
2430 txq = ac->txq;
2431
2432 ath_txq_lock(sc, txq);
2433
2434 if (tid->sched) {
2435 list_del(&tid->list);
2436 tid->sched = false;
2437 }
2438
2439 if (ac->sched) {
2440 list_del(&ac->list);
2441 tid->ac->sched = false;
2442 }
2443
2444 ath_tid_drain(sc, txq, tid);
2445 tid->state &= ~AGGR_ADDBA_COMPLETE;
2446 tid->state &= ~AGGR_CLEANUP;
2447
2448 ath_txq_unlock(sc, txq);
2449 }
2450}
2451