linux/drivers/net/wireless/iwlegacy/common.h
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 *  Intel Linux Wireless <ilw@linux.intel.com>
  23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24 *
  25 *****************************************************************************/
  26#ifndef __il_core_h__
  27#define __il_core_h__
  28
  29#include <linux/interrupt.h>
  30#include <linux/pci.h>          /* for struct pci_device_id */
  31#include <linux/kernel.h>
  32#include <linux/leds.h>
  33#include <linux/wait.h>
  34#include <linux/io.h>
  35#include <net/mac80211.h>
  36#include <net/ieee80211_radiotap.h>
  37
  38#include "commands.h"
  39#include "csr.h"
  40#include "prph.h"
  41
  42struct il_host_cmd;
  43struct il_cmd;
  44struct il_tx_queue;
  45
  46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
  47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
  48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
  49
  50#define RX_QUEUE_SIZE                         256
  51#define RX_QUEUE_MASK                         255
  52#define RX_QUEUE_SIZE_LOG                     8
  53
  54/*
  55 * RX related structures and functions
  56 */
  57#define RX_FREE_BUFFERS 64
  58#define RX_LOW_WATERMARK 8
  59
  60#define U32_PAD(n)              ((4-(n))&0x3)
  61
  62/* CT-KILL constants */
  63#define CT_KILL_THRESHOLD_LEGACY   110  /* in Celsius */
  64
  65/* Default noise level to report when noise measurement is not available.
  66 *   This may be because we're:
  67 *   1)  Not associated (4965, no beacon stats being sent to driver)
  68 *   2)  Scanning (noise measurement does not apply to associated channel)
  69 *   3)  Receiving CCK (3945 delivers noise info only for OFDM frames)
  70 * Use default noise value of -127 ... this is below the range of measurable
  71 *   Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
  72 *   Also, -127 works better than 0 when averaging frames with/without
  73 *   noise info (e.g. averaging might be done in app); measured dBm values are
  74 *   always negative ... using a negative value as the default keeps all
  75 *   averages within an s8's (used in some apps) range of negative values. */
  76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
  77
  78/*
  79 * RTS threshold here is total size [2347] minus 4 FCS bytes
  80 * Per spec:
  81 *   a value of 0 means RTS on all data/management packets
  82 *   a value > max MSDU size means no RTS
  83 * else RTS for data/management frames where MPDU is larger
  84 *   than RTS value.
  85 */
  86#define DEFAULT_RTS_THRESHOLD     2347U
  87#define MIN_RTS_THRESHOLD         0U
  88#define MAX_RTS_THRESHOLD         2347U
  89#define MAX_MSDU_SIZE             2304U
  90#define MAX_MPDU_SIZE             2346U
  91#define DEFAULT_BEACON_INTERVAL   100U
  92#define DEFAULT_SHORT_RETRY_LIMIT 7U
  93#define DEFAULT_LONG_RETRY_LIMIT  4U
  94
  95struct il_rx_buf {
  96        dma_addr_t page_dma;
  97        struct page *page;
  98        struct list_head list;
  99};
 100
 101#define rxb_addr(r) page_address(r->page)
 102
 103/* defined below */
 104struct il_device_cmd;
 105
 106struct il_cmd_meta {
 107        /* only for SYNC commands, iff the reply skb is wanted */
 108        struct il_host_cmd *source;
 109        /*
 110         * only for ASYNC commands
 111         * (which is somewhat stupid -- look at common.c for instance
 112         * which duplicates a bunch of code because the callback isn't
 113         * invoked for SYNC commands, if it were and its result passed
 114         * through it would be simpler...)
 115         */
 116        void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
 117                          struct il_rx_pkt *pkt);
 118
 119        /* The CMD_SIZE_HUGE flag bit indicates that the command
 120         * structure is stored at the end of the shared queue memory. */
 121        u32 flags;
 122
 123         DEFINE_DMA_UNMAP_ADDR(mapping);
 124         DEFINE_DMA_UNMAP_LEN(len);
 125};
 126
 127/*
 128 * Generic queue structure
 129 *
 130 * Contains common data for Rx and Tx queues
 131 */
 132struct il_queue {
 133        int n_bd;               /* number of BDs in this queue */
 134        int write_ptr;          /* 1-st empty entry (idx) host_w */
 135        int read_ptr;           /* last used entry (idx) host_r */
 136        /* use for monitoring and recovering the stuck queue */
 137        dma_addr_t dma_addr;    /* physical addr for BD's */
 138        int n_win;              /* safe queue win */
 139        u32 id;
 140        int low_mark;           /* low watermark, resume queue if free
 141                                 * space more than this */
 142        int high_mark;          /* high watermark, stop queue if free
 143                                 * space less than this */
 144};
 145
 146/**
 147 * struct il_tx_queue - Tx Queue for DMA
 148 * @q: generic Rx/Tx queue descriptor
 149 * @bd: base of circular buffer of TFDs
 150 * @cmd: array of command/TX buffer pointers
 151 * @meta: array of meta data for each command/tx buffer
 152 * @dma_addr_cmd: physical address of cmd/tx buffer array
 153 * @skbs: array of per-TFD socket buffer pointers
 154 * @time_stamp: time (in jiffies) of last read_ptr change
 155 * @need_update: indicates need to update read/write idx
 156 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
 157 *
 158 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
 159 * descriptors) and required locking structures.
 160 */
 161#define TFD_TX_CMD_SLOTS 256
 162#define TFD_CMD_SLOTS 32
 163
 164struct il_tx_queue {
 165        struct il_queue q;
 166        void *tfds;
 167        struct il_device_cmd **cmd;
 168        struct il_cmd_meta *meta;
 169        struct sk_buff **skbs;
 170        unsigned long time_stamp;
 171        u8 need_update;
 172        u8 sched_retry;
 173        u8 active;
 174        u8 swq_id;
 175};
 176
 177/*
 178 * EEPROM access time values:
 179 *
 180 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
 181 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
 182 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
 183 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
 184 */
 185#define IL_EEPROM_ACCESS_TIMEOUT        5000    /* uSec */
 186
 187#define IL_EEPROM_SEM_TIMEOUT           10      /* microseconds */
 188#define IL_EEPROM_SEM_RETRY_LIMIT       1000    /* number of attempts (not time) */
 189
 190/*
 191 * Regulatory channel usage flags in EEPROM struct il4965_eeprom_channel.flags.
 192 *
 193 * IBSS and/or AP operation is allowed *only* on those channels with
 194 * (VALID && IBSS && ACTIVE && !RADAR).  This restriction is in place because
 195 * RADAR detection is not supported by the 4965 driver, but is a
 196 * requirement for establishing a new network for legal operation on channels
 197 * requiring RADAR detection or restricting ACTIVE scanning.
 198 *
 199 * NOTE:  "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
 200 *        It only indicates that 20 MHz channel use is supported; HT40 channel
 201 *        usage is indicated by a separate set of regulatory flags for each
 202 *        HT40 channel pair.
 203 *
 204 * NOTE:  Using a channel inappropriately will result in a uCode error!
 205 */
 206#define IL_NUM_TX_CALIB_GROUPS 5
 207enum {
 208        EEPROM_CHANNEL_VALID = (1 << 0),        /* usable for this SKU/geo */
 209        EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
 210        /* Bit 2 Reserved */
 211        EEPROM_CHANNEL_ACTIVE = (1 << 3),       /* active scanning allowed */
 212        EEPROM_CHANNEL_RADAR = (1 << 4),        /* radar detection required */
 213        EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
 214        /* Bit 6 Reserved (was Narrow Channel) */
 215        EEPROM_CHANNEL_DFS = (1 << 7),  /* dynamic freq selection candidate */
 216};
 217
 218/* SKU Capabilities */
 219/* 3945 only */
 220#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
 221#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
 222
 223/* *regulatory* channel data format in eeprom, one for each channel.
 224 * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
 225struct il_eeprom_channel {
 226        u8 flags;               /* EEPROM_CHANNEL_* flags copied from EEPROM */
 227        s8 max_power_avg;       /* max power (dBm) on this chnl, limit 31 */
 228} __packed;
 229
 230/* 3945 Specific */
 231#define EEPROM_3945_EEPROM_VERSION      (0x2f)
 232
 233/* 4965 has two radio transmitters (and 3 radio receivers) */
 234#define EEPROM_TX_POWER_TX_CHAINS      (2)
 235
 236/* 4965 has room for up to 8 sets of txpower calibration data */
 237#define EEPROM_TX_POWER_BANDS          (8)
 238
 239/* 4965 factory calibration measures txpower gain settings for
 240 * each of 3 target output levels */
 241#define EEPROM_TX_POWER_MEASUREMENTS   (3)
 242
 243/* 4965 Specific */
 244/* 4965 driver does not work with txpower calibration version < 5 */
 245#define EEPROM_4965_TX_POWER_VERSION    (5)
 246#define EEPROM_4965_EEPROM_VERSION      (0x2f)
 247#define EEPROM_4965_CALIB_VERSION_OFFSET       (2*0xB6) /* 2 bytes */
 248#define EEPROM_4965_CALIB_TXPOWER_OFFSET       (2*0xE8) /* 48  bytes */
 249#define EEPROM_4965_BOARD_REVISION             (2*0x4F) /* 2 bytes */
 250#define EEPROM_4965_BOARD_PBA                  (2*0x56+1)       /* 9 bytes */
 251
 252/* 2.4 GHz */
 253extern const u8 il_eeprom_band_1[14];
 254
 255/*
 256 * factory calibration data for one txpower level, on one channel,
 257 * measured on one of the 2 tx chains (radio transmitter and associated
 258 * antenna).  EEPROM contains:
 259 *
 260 * 1)  Temperature (degrees Celsius) of device when measurement was made.
 261 *
 262 * 2)  Gain table idx used to achieve the target measurement power.
 263 *     This refers to the "well-known" gain tables (see 4965.h).
 264 *
 265 * 3)  Actual measured output power, in half-dBm ("34" = 17 dBm).
 266 *
 267 * 4)  RF power amplifier detector level measurement (not used).
 268 */
 269struct il_eeprom_calib_measure {
 270        u8 temperature;         /* Device temperature (Celsius) */
 271        u8 gain_idx;            /* Index into gain table */
 272        u8 actual_pow;          /* Measured RF output power, half-dBm */
 273        s8 pa_det;              /* Power amp detector level (not used) */
 274} __packed;
 275
 276/*
 277 * measurement set for one channel.  EEPROM contains:
 278 *
 279 * 1)  Channel number measured
 280 *
 281 * 2)  Measurements for each of 3 power levels for each of 2 radio transmitters
 282 *     (a.k.a. "tx chains") (6 measurements altogether)
 283 */
 284struct il_eeprom_calib_ch_info {
 285        u8 ch_num;
 286        struct il_eeprom_calib_measure
 287            measurements[EEPROM_TX_POWER_TX_CHAINS]
 288            [EEPROM_TX_POWER_MEASUREMENTS];
 289} __packed;
 290
 291/*
 292 * txpower subband info.
 293 *
 294 * For each frequency subband, EEPROM contains the following:
 295 *
 296 * 1)  First and last channels within range of the subband.  "0" values
 297 *     indicate that this sample set is not being used.
 298 *
 299 * 2)  Sample measurement sets for 2 channels close to the range endpoints.
 300 */
 301struct il_eeprom_calib_subband_info {
 302        u8 ch_from;             /* channel number of lowest channel in subband */
 303        u8 ch_to;               /* channel number of highest channel in subband */
 304        struct il_eeprom_calib_ch_info ch1;
 305        struct il_eeprom_calib_ch_info ch2;
 306} __packed;
 307
 308/*
 309 * txpower calibration info.  EEPROM contains:
 310 *
 311 * 1)  Factory-measured saturation power levels (maximum levels at which
 312 *     tx power amplifier can output a signal without too much distortion).
 313 *     There is one level for 2.4 GHz band and one for 5 GHz band.  These
 314 *     values apply to all channels within each of the bands.
 315 *
 316 * 2)  Factory-measured power supply voltage level.  This is assumed to be
 317 *     constant (i.e. same value applies to all channels/bands) while the
 318 *     factory measurements are being made.
 319 *
 320 * 3)  Up to 8 sets of factory-measured txpower calibration values.
 321 *     These are for different frequency ranges, since txpower gain
 322 *     characteristics of the analog radio circuitry vary with frequency.
 323 *
 324 *     Not all sets need to be filled with data;
 325 *     struct il_eeprom_calib_subband_info contains range of channels
 326 *     (0 if unused) for each set of data.
 327 */
 328struct il_eeprom_calib_info {
 329        u8 saturation_power24;  /* half-dBm (e.g. "34" = 17 dBm) */
 330        u8 saturation_power52;  /* half-dBm */
 331        __le16 voltage;         /* signed */
 332        struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
 333} __packed;
 334
 335/* General */
 336#define EEPROM_DEVICE_ID                    (2*0x08)    /* 2 bytes */
 337#define EEPROM_MAC_ADDRESS                  (2*0x15)    /* 6  bytes */
 338#define EEPROM_BOARD_REVISION               (2*0x35)    /* 2  bytes */
 339#define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)  /* 9  bytes */
 340#define EEPROM_VERSION                      (2*0x44)    /* 2  bytes */
 341#define EEPROM_SKU_CAP                      (2*0x45)    /* 2  bytes */
 342#define EEPROM_OEM_MODE                     (2*0x46)    /* 2  bytes */
 343#define EEPROM_WOWLAN_MODE                  (2*0x47)    /* 2  bytes */
 344#define EEPROM_RADIO_CONFIG                 (2*0x48)    /* 2  bytes */
 345#define EEPROM_NUM_MAC_ADDRESS              (2*0x4C)    /* 2  bytes */
 346
 347/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
 348#define EEPROM_RF_CFG_TYPE_MSK(x)   (x & 0x3)   /* bits 0-1   */
 349#define EEPROM_RF_CFG_STEP_MSK(x)   ((x >> 2)  & 0x3)   /* bits 2-3   */
 350#define EEPROM_RF_CFG_DASH_MSK(x)   ((x >> 4)  & 0x3)   /* bits 4-5   */
 351#define EEPROM_RF_CFG_PNUM_MSK(x)   ((x >> 6)  & 0x3)   /* bits 6-7   */
 352#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8)  & 0xF)   /* bits 8-11  */
 353#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)   /* bits 12-15 */
 354
 355#define EEPROM_3945_RF_CFG_TYPE_MAX  0x0
 356#define EEPROM_4965_RF_CFG_TYPE_MAX  0x1
 357
 358/*
 359 * Per-channel regulatory data.
 360 *
 361 * Each channel that *might* be supported by iwl has a fixed location
 362 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 363 * txpower (MSB).
 364 *
 365 * Entries immediately below are for 20 MHz channel width.  HT40 (40 MHz)
 366 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
 367 *
 368 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 369 */
 370#define EEPROM_REGULATORY_SKU_ID            (2*0x60)    /* 4  bytes */
 371#define EEPROM_REGULATORY_BAND_1            (2*0x62)    /* 2  bytes */
 372#define EEPROM_REGULATORY_BAND_1_CHANNELS   (2*0x63)    /* 28 bytes */
 373
 374/*
 375 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 376 * 5.0 GHz channels 7, 8, 11, 12, 16
 377 * (4915-5080MHz) (none of these is ever supported)
 378 */
 379#define EEPROM_REGULATORY_BAND_2            (2*0x71)    /* 2  bytes */
 380#define EEPROM_REGULATORY_BAND_2_CHANNELS   (2*0x72)    /* 26 bytes */
 381
 382/*
 383 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 384 * (5170-5320MHz)
 385 */
 386#define EEPROM_REGULATORY_BAND_3            (2*0x7F)    /* 2  bytes */
 387#define EEPROM_REGULATORY_BAND_3_CHANNELS   (2*0x80)    /* 24 bytes */
 388
 389/*
 390 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 391 * (5500-5700MHz)
 392 */
 393#define EEPROM_REGULATORY_BAND_4            (2*0x8C)    /* 2  bytes */
 394#define EEPROM_REGULATORY_BAND_4_CHANNELS   (2*0x8D)    /* 22 bytes */
 395
 396/*
 397 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 398 * (5725-5825MHz)
 399 */
 400#define EEPROM_REGULATORY_BAND_5            (2*0x98)    /* 2  bytes */
 401#define EEPROM_REGULATORY_BAND_5_CHANNELS   (2*0x99)    /* 12 bytes */
 402
 403/*
 404 * 2.4 GHz HT40 channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11)
 405 *
 406 * The channel listed is the center of the lower 20 MHz half of the channel.
 407 * The overall center frequency is actually 2 channels (10 MHz) above that,
 408 * and the upper half of each HT40 channel is centered 4 channels (20 MHz) away
 409 * from the lower half; e.g. the upper half of HT40 channel 1 is channel 5,
 410 * and the overall HT40 channel width centers on channel 3.
 411 *
 412 * NOTE:  The RXON command uses 20 MHz channel numbers to specify the
 413 *        control channel to which to tune.  RXON also specifies whether the
 414 *        control channel is the upper or lower half of a HT40 channel.
 415 *
 416 * NOTE:  4965 does not support HT40 channels on 2.4 GHz.
 417 */
 418#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)   /* 14 bytes */
 419
 420/*
 421 * 5.2 GHz HT40 channels 36 (40), 44 (48), 52 (56), 60 (64),
 422 * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161)
 423 */
 424#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)   /* 22 bytes */
 425
 426#define EEPROM_REGULATORY_BAND_NO_HT40                  (0)
 427
 428int il_eeprom_init(struct il_priv *il);
 429void il_eeprom_free(struct il_priv *il);
 430const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
 431u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
 432int il_init_channel_map(struct il_priv *il);
 433void il_free_channel_map(struct il_priv *il);
 434const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
 435                                                  enum ieee80211_band band,
 436                                                  u16 channel);
 437
 438#define IL_NUM_SCAN_RATES         (2)
 439
 440struct il4965_channel_tgd_info {
 441        u8 type;
 442        s8 max_power;
 443};
 444
 445struct il4965_channel_tgh_info {
 446        s64 last_radar_time;
 447};
 448
 449#define IL4965_MAX_RATE (33)
 450
 451struct il3945_clip_group {
 452        /* maximum power level to prevent clipping for each rate, derived by
 453         *   us from this band's saturation power in EEPROM */
 454        const s8 clip_powers[IL_MAX_RATES];
 455};
 456
 457/* current Tx power values to use, one for each rate for each channel.
 458 * requested power is limited by:
 459 * -- regulatory EEPROM limits for this channel
 460 * -- hardware capabilities (clip-powers)
 461 * -- spectrum management
 462 * -- user preference (e.g. iwconfig)
 463 * when requested power is set, base power idx must also be set. */
 464struct il3945_channel_power_info {
 465        struct il3945_tx_power tpc;     /* actual radio and DSP gain settings */
 466        s8 power_table_idx;     /* actual (compenst'd) idx into gain table */
 467        s8 base_power_idx;      /* gain idx for power at factory temp. */
 468        s8 requested_power;     /* power (dBm) requested for this chnl/rate */
 469};
 470
 471/* current scan Tx power values to use, one for each scan rate for each
 472 * channel. */
 473struct il3945_scan_power_info {
 474        struct il3945_tx_power tpc;     /* actual radio and DSP gain settings */
 475        s8 power_table_idx;     /* actual (compenst'd) idx into gain table */
 476        s8 requested_power;     /* scan pwr (dBm) requested for chnl/rate */
 477};
 478
 479/*
 480 * One for each channel, holds all channel setup data
 481 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
 482 *     with one another!
 483 */
 484struct il_channel_info {
 485        struct il4965_channel_tgd_info tgd;
 486        struct il4965_channel_tgh_info tgh;
 487        struct il_eeprom_channel eeprom;        /* EEPROM regulatory limit */
 488        struct il_eeprom_channel ht40_eeprom;   /* EEPROM regulatory limit for
 489                                                 * HT40 channel */
 490
 491        u8 channel;             /* channel number */
 492        u8 flags;               /* flags copied from EEPROM */
 493        s8 max_power_avg;       /* (dBm) regul. eeprom, normal Tx, any rate */
 494        s8 curr_txpow;          /* (dBm) regulatory/spectrum/user (not h/w) limit */
 495        s8 min_power;           /* always 0 */
 496        s8 scan_power;          /* (dBm) regul. eeprom, direct scans, any rate */
 497
 498        u8 group_idx;           /* 0-4, maps channel to group1/2/3/4/5 */
 499        u8 band_idx;            /* 0-4, maps channel to band1/2/3/4/5 */
 500        enum ieee80211_band band;
 501
 502        /* HT40 channel info */
 503        s8 ht40_max_power_avg;  /* (dBm) regul. eeprom, normal Tx, any rate */
 504        u8 ht40_flags;          /* flags copied from EEPROM */
 505        u8 ht40_extension_channel;      /* HT_IE_EXT_CHANNEL_* */
 506
 507        /* Radio/DSP gain settings for each "normal" data Tx rate.
 508         * These include, in addition to RF and DSP gain, a few fields for
 509         *   remembering/modifying gain settings (idxes). */
 510        struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
 511
 512        /* Radio/DSP gain settings for each scan rate, for directed scans. */
 513        struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
 514};
 515
 516#define IL_TX_FIFO_BK           0       /* shared */
 517#define IL_TX_FIFO_BE           1
 518#define IL_TX_FIFO_VI           2       /* shared */
 519#define IL_TX_FIFO_VO           3
 520#define IL_TX_FIFO_UNUSED       -1
 521
 522/* Minimum number of queues. MAX_NUM is defined in hw specific files.
 523 * Set the minimum to accommodate the 4 standard TX queues, 1 command
 524 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
 525#define IL_MIN_NUM_QUEUES       10
 526
 527#define IL_DEFAULT_CMD_QUEUE_NUM        4
 528
 529#define IEEE80211_DATA_LEN              2304
 530#define IEEE80211_4ADDR_LEN             30
 531#define IEEE80211_HLEN                  (IEEE80211_4ADDR_LEN)
 532#define IEEE80211_FRAME_LEN             (IEEE80211_DATA_LEN + IEEE80211_HLEN)
 533
 534struct il_frame {
 535        union {
 536                struct ieee80211_hdr frame;
 537                struct il_tx_beacon_cmd beacon;
 538                u8 raw[IEEE80211_FRAME_LEN];
 539                u8 cmd[360];
 540        } u;
 541        struct list_head list;
 542};
 543
 544#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
 545#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
 546#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
 547
 548enum {
 549        CMD_SYNC = 0,
 550        CMD_SIZE_NORMAL = 0,
 551        CMD_NO_SKB = 0,
 552        CMD_SIZE_HUGE = (1 << 0),
 553        CMD_ASYNC = (1 << 1),
 554        CMD_WANT_SKB = (1 << 2),
 555        CMD_MAPPED = (1 << 3),
 556};
 557
 558#define DEF_CMD_PAYLOAD_SIZE 320
 559
 560/**
 561 * struct il_device_cmd
 562 *
 563 * For allocation of the command and tx queues, this establishes the overall
 564 * size of the largest command we send to uCode, except for a scan command
 565 * (which is relatively huge; space is allocated separately).
 566 */
 567struct il_device_cmd {
 568        struct il_cmd_header hdr;       /* uCode API */
 569        union {
 570                u32 flags;
 571                u8 val8;
 572                u16 val16;
 573                u32 val32;
 574                struct il_tx_cmd tx;
 575                u8 payload[DEF_CMD_PAYLOAD_SIZE];
 576        } __packed cmd;
 577} __packed;
 578
 579#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
 580
 581struct il_host_cmd {
 582        const void *data;
 583        unsigned long reply_page;
 584        void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
 585                          struct il_rx_pkt *pkt);
 586        u32 flags;
 587        u16 len;
 588        u8 id;
 589};
 590
 591#define SUP_RATE_11A_MAX_NUM_CHANNELS  8
 592#define SUP_RATE_11B_MAX_NUM_CHANNELS  4
 593#define SUP_RATE_11G_MAX_NUM_CHANNELS  12
 594
 595/**
 596 * struct il_rx_queue - Rx queue
 597 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
 598 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
 599 * @read: Shared idx to newest available Rx buffer
 600 * @write: Shared idx to oldest written Rx packet
 601 * @free_count: Number of pre-allocated buffers in rx_free
 602 * @rx_free: list of free SKBs for use
 603 * @rx_used: List of Rx buffers with no SKB
 604 * @need_update: flag to indicate we need to update read/write idx
 605 * @rb_stts: driver's pointer to receive buffer status
 606 * @rb_stts_dma: bus address of receive buffer status
 607 *
 608 * NOTE:  rx_free and rx_used are used as a FIFO for il_rx_bufs
 609 */
 610struct il_rx_queue {
 611        __le32 *bd;
 612        dma_addr_t bd_dma;
 613        struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
 614        struct il_rx_buf *queue[RX_QUEUE_SIZE];
 615        u32 read;
 616        u32 write;
 617        u32 free_count;
 618        u32 write_actual;
 619        struct list_head rx_free;
 620        struct list_head rx_used;
 621        int need_update;
 622        struct il_rb_status *rb_stts;
 623        dma_addr_t rb_stts_dma;
 624        spinlock_t lock;
 625};
 626
 627#define IL_SUPPORTED_RATES_IE_LEN         8
 628
 629#define MAX_TID_COUNT        9
 630
 631#define IL_INVALID_RATE     0xFF
 632#define IL_INVALID_VALUE    -1
 633
 634/**
 635 * struct il_ht_agg -- aggregation status while waiting for block-ack
 636 * @txq_id: Tx queue used for Tx attempt
 637 * @frame_count: # frames attempted by Tx command
 638 * @wait_for_ba: Expect block-ack before next Tx reply
 639 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx win
 640 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx win
 641 * @bitmap1: High order, one bit for each frame pending ACK in Tx win
 642 * @rate_n_flags: Rate at which Tx was attempted
 643 *
 644 * If C_TX indicates that aggregation was attempted, driver must wait
 645 * for block ack (N_COMPRESSED_BA).  This struct stores tx reply info
 646 * until block ack arrives.
 647 */
 648struct il_ht_agg {
 649        u16 txq_id;
 650        u16 frame_count;
 651        u16 wait_for_ba;
 652        u16 start_idx;
 653        u64 bitmap;
 654        u32 rate_n_flags;
 655#define IL_AGG_OFF 0
 656#define IL_AGG_ON 1
 657#define IL_EMPTYING_HW_QUEUE_ADDBA 2
 658#define IL_EMPTYING_HW_QUEUE_DELBA 3
 659        u8 state;
 660};
 661
 662struct il_tid_data {
 663        u16 seq_number;         /* 4965 only */
 664        u16 tfds_in_queue;
 665        struct il_ht_agg agg;
 666};
 667
 668struct il_hw_key {
 669        u32 cipher;
 670        int keylen;
 671        u8 keyidx;
 672        u8 key[32];
 673};
 674
 675union il_ht_rate_supp {
 676        u16 rates;
 677        struct {
 678                u8 siso_rate;
 679                u8 mimo_rate;
 680        };
 681};
 682
 683#define CFG_HT_RX_AMPDU_FACTOR_8K   (0x0)
 684#define CFG_HT_RX_AMPDU_FACTOR_16K  (0x1)
 685#define CFG_HT_RX_AMPDU_FACTOR_32K  (0x2)
 686#define CFG_HT_RX_AMPDU_FACTOR_64K  (0x3)
 687#define CFG_HT_RX_AMPDU_FACTOR_DEF  CFG_HT_RX_AMPDU_FACTOR_64K
 688#define CFG_HT_RX_AMPDU_FACTOR_MAX  CFG_HT_RX_AMPDU_FACTOR_64K
 689#define CFG_HT_RX_AMPDU_FACTOR_MIN  CFG_HT_RX_AMPDU_FACTOR_8K
 690
 691/*
 692 * Maximal MPDU density for TX aggregation
 693 * 4 - 2us density
 694 * 5 - 4us density
 695 * 6 - 8us density
 696 * 7 - 16us density
 697 */
 698#define CFG_HT_MPDU_DENSITY_2USEC   (0x4)
 699#define CFG_HT_MPDU_DENSITY_4USEC   (0x5)
 700#define CFG_HT_MPDU_DENSITY_8USEC   (0x6)
 701#define CFG_HT_MPDU_DENSITY_16USEC  (0x7)
 702#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
 703#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
 704#define CFG_HT_MPDU_DENSITY_MIN     (0x1)
 705
 706struct il_ht_config {
 707        bool single_chain_sufficient;
 708        enum ieee80211_smps_mode smps;  /* current smps mode */
 709};
 710
 711/* QoS structures */
 712struct il_qos_info {
 713        int qos_active;
 714        struct il_qosparam_cmd def_qos_parm;
 715};
 716
 717/*
 718 * Structure should be accessed with sta_lock held. When station addition
 719 * is in progress (IL_STA_UCODE_INPROGRESS) it is possible to access only
 720 * the commands (il_addsta_cmd and il_link_quality_cmd) without
 721 * sta_lock held.
 722 */
 723struct il_station_entry {
 724        struct il_addsta_cmd sta;
 725        struct il_tid_data tid[MAX_TID_COUNT];
 726        u8 used;
 727        struct il_hw_key keyinfo;
 728        struct il_link_quality_cmd *lq;
 729};
 730
 731struct il_station_priv_common {
 732        u8 sta_id;
 733};
 734
 735/**
 736 * struct il_vif_priv - driver's ilate per-interface information
 737 *
 738 * When mac80211 allocates a virtual interface, it can allocate
 739 * space for us to put data into.
 740 */
 741struct il_vif_priv {
 742        u8 ibss_bssid_sta_id;
 743};
 744
 745/* one for each uCode image (inst/data, boot/init/runtime) */
 746struct fw_desc {
 747        void *v_addr;           /* access by driver */
 748        dma_addr_t p_addr;      /* access by card's busmaster DMA */
 749        u32 len;                /* bytes */
 750};
 751
 752/* uCode file layout */
 753struct il_ucode_header {
 754        __le32 ver;             /* major/minor/API/serial */
 755        struct {
 756                __le32 inst_size;       /* bytes of runtime code */
 757                __le32 data_size;       /* bytes of runtime data */
 758                __le32 init_size;       /* bytes of init code */
 759                __le32 init_data_size;  /* bytes of init data */
 760                __le32 boot_size;       /* bytes of bootstrap code */
 761                u8 data[0];     /* in same order as sizes */
 762        } v1;
 763};
 764
 765struct il4965_ibss_seq {
 766        u8 mac[ETH_ALEN];
 767        u16 seq_num;
 768        u16 frag_num;
 769        unsigned long packet_time;
 770        struct list_head list;
 771};
 772
 773struct il_sensitivity_ranges {
 774        u16 min_nrg_cck;
 775        u16 max_nrg_cck;
 776
 777        u16 nrg_th_cck;
 778        u16 nrg_th_ofdm;
 779
 780        u16 auto_corr_min_ofdm;
 781        u16 auto_corr_min_ofdm_mrc;
 782        u16 auto_corr_min_ofdm_x1;
 783        u16 auto_corr_min_ofdm_mrc_x1;
 784
 785        u16 auto_corr_max_ofdm;
 786        u16 auto_corr_max_ofdm_mrc;
 787        u16 auto_corr_max_ofdm_x1;
 788        u16 auto_corr_max_ofdm_mrc_x1;
 789
 790        u16 auto_corr_max_cck;
 791        u16 auto_corr_max_cck_mrc;
 792        u16 auto_corr_min_cck;
 793        u16 auto_corr_min_cck_mrc;
 794
 795        u16 barker_corr_th_min;
 796        u16 barker_corr_th_min_mrc;
 797        u16 nrg_th_cca;
 798};
 799
 800#define KELVIN_TO_CELSIUS(x) ((x)-273)
 801#define CELSIUS_TO_KELVIN(x) ((x)+273)
 802
 803/**
 804 * struct il_hw_params
 805 * @bcast_id: f/w broadcast station ID
 806 * @max_txq_num: Max # Tx queues supported
 807 * @dma_chnl_num: Number of Tx DMA/FIFO channels
 808 * @scd_bc_tbls_size: size of scheduler byte count tables
 809 * @tfd_size: TFD size
 810 * @tx/rx_chains_num: Number of TX/RX chains
 811 * @valid_tx/rx_ant: usable antennas
 812 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
 813 * @max_rxq_log: Log-base-2 of max_rxq_size
 814 * @rx_page_order: Rx buffer page order
 815 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
 816 * @max_stations:
 817 * @ht40_channel: is 40MHz width possible in band 2.4
 818 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
 819 * @sw_crypto: 0 for hw, 1 for sw
 820 * @max_xxx_size: for ucode uses
 821 * @ct_kill_threshold: temperature threshold
 822 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
 823 * @struct il_sensitivity_ranges: range of sensitivity values
 824 */
 825struct il_hw_params {
 826        u8 bcast_id;
 827        u8 max_txq_num;
 828        u8 dma_chnl_num;
 829        u16 scd_bc_tbls_size;
 830        u32 tfd_size;
 831        u8 tx_chains_num;
 832        u8 rx_chains_num;
 833        u8 valid_tx_ant;
 834        u8 valid_rx_ant;
 835        u16 max_rxq_size;
 836        u16 max_rxq_log;
 837        u32 rx_page_order;
 838        u32 rx_wrt_ptr_reg;
 839        u8 max_stations;
 840        u8 ht40_channel;
 841        u8 max_beacon_itrvl;    /* in 1024 ms */
 842        u32 max_inst_size;
 843        u32 max_data_size;
 844        u32 max_bsm_size;
 845        u32 ct_kill_threshold;  /* value in hw-dependent units */
 846        u16 beacon_time_tsf_bits;
 847        const struct il_sensitivity_ranges *sens;
 848};
 849
 850/******************************************************************************
 851 *
 852 * Functions implemented in core module which are forward declared here
 853 * for use by iwl-[4-5].c
 854 *
 855 * NOTE:  The implementation of these functions are not hardware specific
 856 * which is why they are in the core module files.
 857 *
 858 * Naming convention --
 859 * il_         <-- Is part of iwlwifi
 860 * iwlXXXX_     <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
 861 * il4965_bg_      <-- Called from work queue context
 862 * il4965_mac_     <-- mac80211 callback
 863 *
 864 ****************************************************************************/
 865extern void il4965_update_chain_flags(struct il_priv *il);
 866extern const u8 il_bcast_addr[ETH_ALEN];
 867extern int il_queue_space(const struct il_queue *q);
 868static inline int
 869il_queue_used(const struct il_queue *q, int i)
 870{
 871        return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
 872                                              i < q->write_ptr) : !(i <
 873                                                                    q->read_ptr
 874                                                                    && i >=
 875                                                                    q->
 876                                                                    write_ptr);
 877}
 878
 879static inline u8
 880il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
 881{
 882        /*
 883         * This is for init calibration result and scan command which
 884         * required buffer > TFD_MAX_PAYLOAD_SIZE,
 885         * the big buffer at end of command array
 886         */
 887        if (is_huge)
 888                return q->n_win;        /* must be power of 2 */
 889
 890        /* Otherwise, use normal size buffers */
 891        return idx & (q->n_win - 1);
 892}
 893
 894struct il_dma_ptr {
 895        dma_addr_t dma;
 896        void *addr;
 897        size_t size;
 898};
 899
 900#define IL_OPERATION_MODE_AUTO     0
 901#define IL_OPERATION_MODE_HT_ONLY  1
 902#define IL_OPERATION_MODE_MIXED    2
 903#define IL_OPERATION_MODE_20MHZ    3
 904
 905#define IL_TX_CRC_SIZE 4
 906#define IL_TX_DELIMITER_SIZE 4
 907
 908#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
 909
 910/* Sensitivity and chain noise calibration */
 911#define INITIALIZATION_VALUE            0xFFFF
 912#define IL4965_CAL_NUM_BEACONS          20
 913#define IL_CAL_NUM_BEACONS              16
 914#define MAXIMUM_ALLOWED_PATHLOSS        15
 915
 916#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
 917
 918#define MAX_FA_OFDM  50
 919#define MIN_FA_OFDM  5
 920#define MAX_FA_CCK   50
 921#define MIN_FA_CCK   5
 922
 923#define AUTO_CORR_STEP_OFDM       1
 924
 925#define AUTO_CORR_STEP_CCK     3
 926#define AUTO_CORR_MAX_TH_CCK   160
 927
 928#define NRG_DIFF               2
 929#define NRG_STEP_CCK           2
 930#define NRG_MARGIN             8
 931#define MAX_NUMBER_CCK_NO_FA 100
 932
 933#define AUTO_CORR_CCK_MIN_VAL_DEF    (125)
 934
 935#define CHAIN_A             0
 936#define CHAIN_B             1
 937#define CHAIN_C             2
 938#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
 939#define ALL_BAND_FILTER                 0xFF00
 940#define IN_BAND_FILTER                  0xFF
 941#define MIN_AVERAGE_NOISE_MAX_VALUE     0xFFFFFFFF
 942
 943#define NRG_NUM_PREV_STAT_L     20
 944#define NUM_RX_CHAINS           3
 945
 946enum il4965_false_alarm_state {
 947        IL_FA_TOO_MANY = 0,
 948        IL_FA_TOO_FEW = 1,
 949        IL_FA_GOOD_RANGE = 2,
 950};
 951
 952enum il4965_chain_noise_state {
 953        IL_CHAIN_NOISE_ALIVE = 0,       /* must be 0 */
 954        IL_CHAIN_NOISE_ACCUMULATE,
 955        IL_CHAIN_NOISE_CALIBRATED,
 956        IL_CHAIN_NOISE_DONE,
 957};
 958
 959enum ucode_type {
 960        UCODE_NONE = 0,
 961        UCODE_INIT,
 962        UCODE_RT
 963};
 964
 965/* Sensitivity calib data */
 966struct il_sensitivity_data {
 967        u32 auto_corr_ofdm;
 968        u32 auto_corr_ofdm_mrc;
 969        u32 auto_corr_ofdm_x1;
 970        u32 auto_corr_ofdm_mrc_x1;
 971        u32 auto_corr_cck;
 972        u32 auto_corr_cck_mrc;
 973
 974        u32 last_bad_plcp_cnt_ofdm;
 975        u32 last_fa_cnt_ofdm;
 976        u32 last_bad_plcp_cnt_cck;
 977        u32 last_fa_cnt_cck;
 978
 979        u32 nrg_curr_state;
 980        u32 nrg_prev_state;
 981        u32 nrg_value[10];
 982        u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
 983        u32 nrg_silence_ref;
 984        u32 nrg_energy_idx;
 985        u32 nrg_silence_idx;
 986        u32 nrg_th_cck;
 987        s32 nrg_auto_corr_silence_diff;
 988        u32 num_in_cck_no_fa;
 989        u32 nrg_th_ofdm;
 990
 991        u16 barker_corr_th_min;
 992        u16 barker_corr_th_min_mrc;
 993        u16 nrg_th_cca;
 994};
 995
 996/* Chain noise (differential Rx gain) calib data */
 997struct il_chain_noise_data {
 998        u32 active_chains;
 999        u32 chain_noise_a;
1000        u32 chain_noise_b;
1001        u32 chain_noise_c;
1002        u32 chain_signal_a;
1003        u32 chain_signal_b;
1004        u32 chain_signal_c;
1005        u16 beacon_count;
1006        u8 disconn_array[NUM_RX_CHAINS];
1007        u8 delta_gain_code[NUM_RX_CHAINS];
1008        u8 radio_write;
1009        u8 state;
1010};
1011
1012#define EEPROM_SEM_TIMEOUT 10   /* milliseconds */
1013#define EEPROM_SEM_RETRY_LIMIT 1000     /* number of attempts (not time) */
1014
1015#define IL_TRAFFIC_ENTRIES      (256)
1016#define IL_TRAFFIC_ENTRY_SIZE  (64)
1017
1018enum {
1019        MEASUREMENT_READY = (1 << 0),
1020        MEASUREMENT_ACTIVE = (1 << 1),
1021};
1022
1023/* interrupt stats */
1024struct isr_stats {
1025        u32 hw;
1026        u32 sw;
1027        u32 err_code;
1028        u32 sch;
1029        u32 alive;
1030        u32 rfkill;
1031        u32 ctkill;
1032        u32 wakeup;
1033        u32 rx;
1034        u32 handlers[IL_CN_MAX];
1035        u32 tx;
1036        u32 unhandled;
1037};
1038
1039/* management stats */
1040enum il_mgmt_stats {
1041        MANAGEMENT_ASSOC_REQ = 0,
1042        MANAGEMENT_ASSOC_RESP,
1043        MANAGEMENT_REASSOC_REQ,
1044        MANAGEMENT_REASSOC_RESP,
1045        MANAGEMENT_PROBE_REQ,
1046        MANAGEMENT_PROBE_RESP,
1047        MANAGEMENT_BEACON,
1048        MANAGEMENT_ATIM,
1049        MANAGEMENT_DISASSOC,
1050        MANAGEMENT_AUTH,
1051        MANAGEMENT_DEAUTH,
1052        MANAGEMENT_ACTION,
1053        MANAGEMENT_MAX,
1054};
1055/* control stats */
1056enum il_ctrl_stats {
1057        CONTROL_BACK_REQ = 0,
1058        CONTROL_BACK,
1059        CONTROL_PSPOLL,
1060        CONTROL_RTS,
1061        CONTROL_CTS,
1062        CONTROL_ACK,
1063        CONTROL_CFEND,
1064        CONTROL_CFENDACK,
1065        CONTROL_MAX,
1066};
1067
1068struct traffic_stats {
1069#ifdef CONFIG_IWLEGACY_DEBUGFS
1070        u32 mgmt[MANAGEMENT_MAX];
1071        u32 ctrl[CONTROL_MAX];
1072        u32 data_cnt;
1073        u64 data_bytes;
1074#endif
1075};
1076
1077/*
1078 * host interrupt timeout value
1079 * used with setting interrupt coalescing timer
1080 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1081 *
1082 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1083 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1084 */
1085#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1086#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1087#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1088#define IL_HOST_INT_CALIB_TIMEOUT_MAX   (0xFF)
1089#define IL_HOST_INT_CALIB_TIMEOUT_DEF   (0x10)
1090#define IL_HOST_INT_CALIB_TIMEOUT_MIN   (0x0)
1091
1092#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1093
1094/* TX queue watchdog timeouts in mSecs */
1095#define IL_DEF_WD_TIMEOUT       (2000)
1096#define IL_LONG_WD_TIMEOUT      (10000)
1097#define IL_MAX_WD_TIMEOUT       (120000)
1098
1099struct il_force_reset {
1100        int reset_request_count;
1101        int reset_success_count;
1102        int reset_reject_count;
1103        unsigned long reset_duration;
1104        unsigned long last_force_reset_jiffies;
1105};
1106
1107/* extend beacon time format bit shifting  */
1108/*
1109 * for _3945 devices
1110 * bits 31:24 - extended
1111 * bits 23:0  - interval
1112 */
1113#define IL3945_EXT_BEACON_TIME_POS      24
1114/*
1115 * for _4965 devices
1116 * bits 31:22 - extended
1117 * bits 21:0  - interval
1118 */
1119#define IL4965_EXT_BEACON_TIME_POS      22
1120
1121struct il_rxon_context {
1122        struct ieee80211_vif *vif;
1123};
1124
1125struct il_power_mgr {
1126        struct il_powertable_cmd sleep_cmd;
1127        struct il_powertable_cmd sleep_cmd_next;
1128        int debug_sleep_level_override;
1129        bool pci_pm;
1130};
1131
1132struct il_priv {
1133        struct ieee80211_hw *hw;
1134        struct ieee80211_channel *ieee_channels;
1135        struct ieee80211_rate *ieee_rates;
1136
1137        struct il_cfg *cfg;
1138        const struct il_ops *ops;
1139#ifdef CONFIG_IWLEGACY_DEBUGFS
1140        const struct il_debugfs_ops *debugfs_ops;
1141#endif
1142
1143        /* temporary frame storage list */
1144        struct list_head free_frames;
1145        int frames_count;
1146
1147        enum ieee80211_band band;
1148        int alloc_rxb_page;
1149
1150        void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1151                                     struct il_rx_buf *rxb);
1152
1153        struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1154
1155        /* spectrum measurement report caching */
1156        struct il_spectrum_notification measure_report;
1157        u8 measurement_status;
1158
1159        /* ucode beacon time */
1160        u32 ucode_beacon_time;
1161        int missed_beacon_threshold;
1162
1163        /* track IBSS manager (last beacon) status */
1164        u32 ibss_manager;
1165
1166        /* force reset */
1167        struct il_force_reset force_reset;
1168
1169        /* we allocate array of il_channel_info for NIC's valid channels.
1170         *    Access via channel # using indirect idx array */
1171        struct il_channel_info *channel_info;   /* channel info array */
1172        u8 channel_count;       /* # of channels */
1173
1174        /* thermal calibration */
1175        s32 temperature;        /* degrees Kelvin */
1176        s32 last_temperature;
1177
1178        /* Scan related variables */
1179        unsigned long scan_start;
1180        unsigned long scan_start_tsf;
1181        void *scan_cmd;
1182        enum ieee80211_band scan_band;
1183        struct cfg80211_scan_request *scan_request;
1184        struct ieee80211_vif *scan_vif;
1185        u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1186        u8 mgmt_tx_ant;
1187
1188        /* spinlock */
1189        spinlock_t lock;        /* protect general shared data */
1190        spinlock_t hcmd_lock;   /* protect hcmd */
1191        spinlock_t reg_lock;    /* protect hw register access */
1192        struct mutex mutex;
1193
1194        /* basic pci-network driver stuff */
1195        struct pci_dev *pci_dev;
1196
1197        /* pci hardware address support */
1198        void __iomem *hw_base;
1199        u32 hw_rev;
1200        u32 hw_wa_rev;
1201        u8 rev_id;
1202
1203        /* command queue number */
1204        u8 cmd_queue;
1205
1206        /* max number of station keys */
1207        u8 sta_key_max_num;
1208
1209        /* EEPROM MAC addresses */
1210        struct mac_address addresses[1];
1211
1212        /* uCode images, save to reload in case of failure */
1213        int fw_idx;             /* firmware we're trying to load */
1214        u32 ucode_ver;          /* version of ucode, copy of
1215                                   il_ucode.ver */
1216        struct fw_desc ucode_code;      /* runtime inst */
1217        struct fw_desc ucode_data;      /* runtime data original */
1218        struct fw_desc ucode_data_backup;       /* runtime data save/restore */
1219        struct fw_desc ucode_init;      /* initialization inst */
1220        struct fw_desc ucode_init_data; /* initialization data */
1221        struct fw_desc ucode_boot;      /* bootstrap inst */
1222        enum ucode_type ucode_type;
1223        u8 ucode_write_complete;        /* the image write is complete */
1224        char firmware_name[25];
1225
1226        struct ieee80211_vif *vif;
1227
1228        struct il_qos_info qos_data;
1229
1230        struct {
1231                bool enabled;
1232                bool is_40mhz;
1233                bool non_gf_sta_present;
1234                u8 protection;
1235                u8 extension_chan_offset;
1236        } ht;
1237
1238        /*
1239         * We declare this const so it can only be
1240         * changed via explicit cast within the
1241         * routines that actually update the physical
1242         * hardware.
1243         */
1244        const struct il_rxon_cmd active;
1245        struct il_rxon_cmd staging;
1246
1247        struct il_rxon_time_cmd timing;
1248
1249        __le16 switch_channel;
1250
1251        /* 1st responses from initialize and runtime uCode images.
1252         * _4965's initialize alive response contains some calibration data. */
1253        struct il_init_alive_resp card_alive_init;
1254        struct il_alive_resp card_alive;
1255
1256        u16 active_rate;
1257
1258        u8 start_calib;
1259        struct il_sensitivity_data sensitivity_data;
1260        struct il_chain_noise_data chain_noise_data;
1261        __le16 sensitivity_tbl[HD_TBL_SIZE];
1262
1263        struct il_ht_config current_ht_config;
1264
1265        /* Rate scaling data */
1266        u8 retry_rate;
1267
1268        wait_queue_head_t wait_command_queue;
1269
1270        int activity_timer_active;
1271
1272        /* Rx and Tx DMA processing queues */
1273        struct il_rx_queue rxq;
1274        struct il_tx_queue *txq;
1275        unsigned long txq_ctx_active_msk;
1276        struct il_dma_ptr kw;   /* keep warm address */
1277        struct il_dma_ptr scd_bc_tbls;
1278
1279        u32 scd_base_addr;      /* scheduler sram base address */
1280
1281        unsigned long status;
1282
1283        /* counts mgmt, ctl, and data packets */
1284        struct traffic_stats tx_stats;
1285        struct traffic_stats rx_stats;
1286
1287        /* counts interrupts */
1288        struct isr_stats isr_stats;
1289
1290        struct il_power_mgr power_data;
1291
1292        /* context information */
1293        u8 bssid[ETH_ALEN];     /* used only on 3945 but filled by core */
1294
1295        /* station table variables */
1296
1297        /* Note: if lock and sta_lock are needed, lock must be acquired first */
1298        spinlock_t sta_lock;
1299        int num_stations;
1300        struct il_station_entry stations[IL_STATION_COUNT];
1301        unsigned long ucode_key_table;
1302
1303        /* queue refcounts */
1304#define IL_MAX_HW_QUEUES        32
1305        unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1306        /* for each AC */
1307        atomic_t queue_stop_count[4];
1308
1309        /* Indication if ieee80211_ops->open has been called */
1310        u8 is_open;
1311
1312        u8 mac80211_registered;
1313
1314        /* eeprom -- this is in the card's little endian byte order */
1315        u8 *eeprom;
1316        struct il_eeprom_calib_info *calib_info;
1317
1318        enum nl80211_iftype iw_mode;
1319
1320        /* Last Rx'd beacon timestamp */
1321        u64 timestamp;
1322
1323        union {
1324#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1325                struct {
1326                        void *shared_virt;
1327                        dma_addr_t shared_phys;
1328
1329                        struct delayed_work thermal_periodic;
1330                        struct delayed_work rfkill_poll;
1331
1332                        struct il3945_notif_stats stats;
1333#ifdef CONFIG_IWLEGACY_DEBUGFS
1334                        struct il3945_notif_stats accum_stats;
1335                        struct il3945_notif_stats delta_stats;
1336                        struct il3945_notif_stats max_delta;
1337#endif
1338
1339                        u32 sta_supp_rates;
1340                        int last_rx_rssi;       /* From Rx packet stats */
1341
1342                        /* Rx'd packet timing information */
1343                        u32 last_beacon_time;
1344                        u64 last_tsf;
1345
1346                        /*
1347                         * each calibration channel group in the
1348                         * EEPROM has a derived clip setting for
1349                         * each rate.
1350                         */
1351                        const struct il3945_clip_group clip_groups[5];
1352
1353                } _3945;
1354#endif
1355#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1356                struct {
1357                        struct il_rx_phy_res last_phy_res;
1358                        bool last_phy_res_valid;
1359                        u32 ampdu_ref;
1360
1361                        struct completion firmware_loading_complete;
1362
1363                        /*
1364                         * chain noise reset and gain commands are the
1365                         * two extra calibration commands follows the standard
1366                         * phy calibration commands
1367                         */
1368                        u8 phy_calib_chain_noise_reset_cmd;
1369                        u8 phy_calib_chain_noise_gain_cmd;
1370
1371                        u8 key_mapping_keys;
1372                        struct il_wep_key wep_keys[WEP_KEYS_MAX];
1373
1374                        struct il_notif_stats stats;
1375#ifdef CONFIG_IWLEGACY_DEBUGFS
1376                        struct il_notif_stats accum_stats;
1377                        struct il_notif_stats delta_stats;
1378                        struct il_notif_stats max_delta;
1379#endif
1380
1381                } _4965;
1382#endif
1383        };
1384
1385        struct il_hw_params hw_params;
1386
1387        u32 inta_mask;
1388
1389        struct workqueue_struct *workqueue;
1390
1391        struct work_struct restart;
1392        struct work_struct scan_completed;
1393        struct work_struct rx_replenish;
1394        struct work_struct abort_scan;
1395
1396        bool beacon_enabled;
1397        struct sk_buff *beacon_skb;
1398
1399        struct work_struct tx_flush;
1400
1401        struct tasklet_struct irq_tasklet;
1402
1403        struct delayed_work init_alive_start;
1404        struct delayed_work alive_start;
1405        struct delayed_work scan_check;
1406
1407        /* TX Power */
1408        s8 tx_power_user_lmt;
1409        s8 tx_power_device_lmt;
1410        s8 tx_power_next;
1411
1412#ifdef CONFIG_IWLEGACY_DEBUG
1413        /* debugging info */
1414        u32 debug_level;        /* per device debugging will override global
1415                                   il_debug_level if set */
1416#endif                          /* CONFIG_IWLEGACY_DEBUG */
1417#ifdef CONFIG_IWLEGACY_DEBUGFS
1418        /* debugfs */
1419        u16 tx_traffic_idx;
1420        u16 rx_traffic_idx;
1421        u8 *tx_traffic;
1422        u8 *rx_traffic;
1423        struct dentry *debugfs_dir;
1424        u32 dbgfs_sram_offset, dbgfs_sram_len;
1425        bool disable_ht40;
1426#endif                          /* CONFIG_IWLEGACY_DEBUGFS */
1427
1428        struct work_struct txpower_work;
1429        u32 disable_sens_cal;
1430        u32 disable_chain_noise_cal;
1431        u32 disable_tx_power_cal;
1432        struct work_struct run_time_calib_work;
1433        struct timer_list stats_periodic;
1434        struct timer_list watchdog;
1435        bool hw_ready;
1436
1437        struct led_classdev led;
1438        unsigned long blink_on, blink_off;
1439        bool led_registered;
1440};                              /*il_priv */
1441
1442static inline void
1443il_txq_ctx_activate(struct il_priv *il, int txq_id)
1444{
1445        set_bit(txq_id, &il->txq_ctx_active_msk);
1446}
1447
1448static inline void
1449il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1450{
1451        clear_bit(txq_id, &il->txq_ctx_active_msk);
1452}
1453
1454static inline int
1455il_is_associated(struct il_priv *il)
1456{
1457        return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1458}
1459
1460static inline int
1461il_is_any_associated(struct il_priv *il)
1462{
1463        return il_is_associated(il);
1464}
1465
1466static inline int
1467il_is_channel_valid(const struct il_channel_info *ch_info)
1468{
1469        if (ch_info == NULL)
1470                return 0;
1471        return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1472}
1473
1474static inline int
1475il_is_channel_radar(const struct il_channel_info *ch_info)
1476{
1477        return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1478}
1479
1480static inline u8
1481il_is_channel_a_band(const struct il_channel_info *ch_info)
1482{
1483        return ch_info->band == IEEE80211_BAND_5GHZ;
1484}
1485
1486static inline int
1487il_is_channel_passive(const struct il_channel_info *ch)
1488{
1489        return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1490}
1491
1492static inline int
1493il_is_channel_ibss(const struct il_channel_info *ch)
1494{
1495        return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1496}
1497
1498static inline void
1499__il_free_pages(struct il_priv *il, struct page *page)
1500{
1501        __free_pages(page, il->hw_params.rx_page_order);
1502        il->alloc_rxb_page--;
1503}
1504
1505static inline void
1506il_free_pages(struct il_priv *il, unsigned long page)
1507{
1508        free_pages(page, il->hw_params.rx_page_order);
1509        il->alloc_rxb_page--;
1510}
1511
1512#define IWLWIFI_VERSION "in-tree:"
1513#define DRV_COPYRIGHT   "Copyright(c) 2003-2011 Intel Corporation"
1514#define DRV_AUTHOR     "<ilw@linux.intel.com>"
1515
1516#define IL_PCI_DEVICE(dev, subdev, cfg) \
1517        .vendor = PCI_VENDOR_ID_INTEL,  .device = (dev), \
1518        .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1519        .driver_data = (kernel_ulong_t)&(cfg)
1520
1521#define TIME_UNIT               1024
1522
1523#define IL_SKU_G       0x1
1524#define IL_SKU_A       0x2
1525#define IL_SKU_N       0x8
1526
1527#define IL_CMD(x) case x: return #x
1528
1529/* Size of one Rx buffer in host DRAM */
1530#define IL_RX_BUF_SIZE_3K (3 * 1000)    /* 3945 only */
1531#define IL_RX_BUF_SIZE_4K (4 * 1024)
1532#define IL_RX_BUF_SIZE_8K (8 * 1024)
1533
1534#ifdef CONFIG_IWLEGACY_DEBUGFS
1535struct il_debugfs_ops {
1536        ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1537                                 size_t count, loff_t *ppos);
1538        ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1539                                 size_t count, loff_t *ppos);
1540        ssize_t(*general_stats_read) (struct file *file,
1541                                      char __user *user_buf, size_t count,
1542                                      loff_t *ppos);
1543};
1544#endif
1545
1546struct il_ops {
1547        /* Handling TX */
1548        void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1549                                         struct il_tx_queue *txq,
1550                                         u16 byte_cnt);
1551        int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1552                                      struct il_tx_queue *txq, dma_addr_t addr,
1553                                      u16 len, u8 reset, u8 pad);
1554        void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1555        int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1556        /* alive notification after init uCode load */
1557        void (*init_alive_start) (struct il_priv *il);
1558        /* check validity of rtc data address */
1559        int (*is_valid_rtc_data_addr) (u32 addr);
1560        /* 1st ucode load */
1561        int (*load_ucode) (struct il_priv *il);
1562
1563        void (*dump_nic_error_log) (struct il_priv *il);
1564        int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1565        int (*set_channel_switch) (struct il_priv *il,
1566                                   struct ieee80211_channel_switch *ch_switch);
1567        /* power management */
1568        int (*apm_init) (struct il_priv *il);
1569
1570        /* tx power */
1571        int (*send_tx_power) (struct il_priv *il);
1572        void (*update_chain_flags) (struct il_priv *il);
1573
1574        /* eeprom operations */
1575        int (*eeprom_acquire_semaphore) (struct il_priv *il);
1576        void (*eeprom_release_semaphore) (struct il_priv *il);
1577
1578        int (*rxon_assoc) (struct il_priv *il);
1579        int (*commit_rxon) (struct il_priv *il);
1580        void (*set_rxon_chain) (struct il_priv *il);
1581
1582        u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1583        u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1584
1585        int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1586        void (*post_scan) (struct il_priv *il);
1587        void (*post_associate) (struct il_priv *il);
1588        void (*config_ap) (struct il_priv *il);
1589        /* station management */
1590        int (*update_bcast_stations) (struct il_priv *il);
1591        int (*manage_ibss_station) (struct il_priv *il,
1592                                    struct ieee80211_vif *vif, bool add);
1593
1594        int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1595};
1596
1597struct il_mod_params {
1598        int sw_crypto;          /* def: 0 = using hardware encryption */
1599        int disable_hw_scan;    /* def: 0 = use h/w scan */
1600        int num_of_queues;      /* def: HW dependent */
1601        int disable_11n;        /* def: 0 = 11n capabilities enabled */
1602        int amsdu_size_8K;      /* def: 1 = enable 8K amsdu size */
1603        int antenna;            /* def: 0 = both antennas (use diversity) */
1604        int restart_fw;         /* def: 1 = restart firmware */
1605};
1606
1607#define IL_LED_SOLID 11
1608#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1609
1610#define IL_LED_ACTIVITY       (0<<1)
1611#define IL_LED_LINK           (1<<1)
1612
1613/*
1614 * LED mode
1615 *    IL_LED_DEFAULT:  use device default
1616 *    IL_LED_RF_STATE: turn LED on/off based on RF state
1617 *                      LED ON  = RF ON
1618 *                      LED OFF = RF OFF
1619 *    IL_LED_BLINK:    adjust led blink rate based on blink table
1620 */
1621enum il_led_mode {
1622        IL_LED_DEFAULT,
1623        IL_LED_RF_STATE,
1624        IL_LED_BLINK,
1625};
1626
1627void il_leds_init(struct il_priv *il);
1628void il_leds_exit(struct il_priv *il);
1629
1630/**
1631 * struct il_cfg
1632 * @fw_name_pre: Firmware filename prefix. The api version and extension
1633 *      (.ucode) will be added to filename before loading from disk. The
1634 *      filename is constructed as fw_name_pre<api>.ucode.
1635 * @ucode_api_max: Highest version of uCode API supported by driver.
1636 * @ucode_api_min: Lowest version of uCode API supported by driver.
1637 * @scan_antennas: available antenna for scan operation
1638 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
1639 *
1640 * We enable the driver to be backward compatible wrt API version. The
1641 * driver specifies which APIs it supports (with @ucode_api_max being the
1642 * highest and @ucode_api_min the lowest). Firmware will only be loaded if
1643 * it has a supported API version. The firmware's API version will be
1644 * stored in @il_priv, enabling the driver to make runtime changes based
1645 * on firmware version used.
1646 *
1647 * For example,
1648 * if (IL_UCODE_API(il->ucode_ver) >= 2) {
1649 *      Driver interacts with Firmware API version >= 2.
1650 * } else {
1651 *      Driver interacts with Firmware API version 1.
1652 * }
1653 *
1654 * The ideal usage of this infrastructure is to treat a new ucode API
1655 * release as a new hardware revision. That is, through utilizing the
1656 * il_hcmd_utils_ops etc. we accommodate different command structures
1657 * and flows between hardware versions as well as their API
1658 * versions.
1659 *
1660 */
1661struct il_cfg {
1662        /* params specific to an individual device within a device family */
1663        const char *name;
1664        const char *fw_name_pre;
1665        const unsigned int ucode_api_max;
1666        const unsigned int ucode_api_min;
1667        u8 valid_tx_ant;
1668        u8 valid_rx_ant;
1669        unsigned int sku;
1670        u16 eeprom_ver;
1671        u16 eeprom_calib_ver;
1672        /* module based parameters which can be set from modprobe cmd */
1673        const struct il_mod_params *mod_params;
1674        /* params not likely to change within a device family */
1675        struct il_base_params *base_params;
1676        /* params likely to change within a device family */
1677        u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
1678        enum il_led_mode led_mode;
1679
1680        int eeprom_size;
1681        int num_of_queues;              /* def: HW dependent */
1682        int num_of_ampdu_queues;        /* def: HW dependent */
1683        /* for il_apm_init() */
1684        u32 pll_cfg_val;
1685        bool set_l0s;
1686        bool use_bsm;
1687
1688        u16 led_compensation;
1689        int chain_noise_num_beacons;
1690        unsigned int wd_timeout;
1691        bool temperature_kelvin;
1692        const bool ucode_tracing;
1693        const bool sensitivity_calib_by_driver;
1694        const bool chain_noise_calib_by_driver;
1695
1696        const u32 regulatory_bands[7];
1697};
1698
1699/***************************
1700 *   L i b                 *
1701 ***************************/
1702
1703int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1704                   u16 queue, const struct ieee80211_tx_queue_params *params);
1705int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1706
1707void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1708int il_check_rxon_cmd(struct il_priv *il);
1709int il_full_rxon_required(struct il_priv *il);
1710int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1711void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1712                           struct ieee80211_vif *vif);
1713u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1714void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1715bool il_is_ht40_tx_allowed(struct il_priv *il,
1716                           struct ieee80211_sta_ht_cap *ht_cap);
1717void il_connection_init_rx_config(struct il_priv *il);
1718void il_set_rate(struct il_priv *il);
1719int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1720                          u32 decrypt_res, struct ieee80211_rx_status *stats);
1721void il_irq_handle_error(struct il_priv *il);
1722int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1723void il_mac_remove_interface(struct ieee80211_hw *hw,
1724                             struct ieee80211_vif *vif);
1725int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1726                            enum nl80211_iftype newtype, bool newp2p);
1727void il_mac_flush(struct ieee80211_hw *hw, bool drop);
1728int il_alloc_txq_mem(struct il_priv *il);
1729void il_free_txq_mem(struct il_priv *il);
1730
1731#ifdef CONFIG_IWLEGACY_DEBUGFS
1732extern void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1733#else
1734static inline void
1735il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1736{
1737}
1738#endif
1739
1740/*****************************************************
1741 * Handlers
1742 ***************************************************/
1743void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1744void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1745void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1746void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1747
1748/*****************************************************
1749* RX
1750******************************************************/
1751void il_cmd_queue_unmap(struct il_priv *il);
1752void il_cmd_queue_free(struct il_priv *il);
1753int il_rx_queue_alloc(struct il_priv *il);
1754void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1755int il_rx_queue_space(const struct il_rx_queue *q);
1756void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1757
1758void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1759void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1760void il_chswitch_done(struct il_priv *il, bool is_success);
1761
1762/*****************************************************
1763* TX
1764******************************************************/
1765extern void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1766extern int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1767extern void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1768extern void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1769extern void il_tx_queue_free(struct il_priv *il, int txq_id);
1770extern void il_setup_watchdog(struct il_priv *il);
1771/*****************************************************
1772 * TX power
1773 ****************************************************/
1774int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1775
1776/*******************************************************************************
1777 * Rate
1778 ******************************************************************************/
1779
1780u8 il_get_lowest_plcp(struct il_priv *il);
1781
1782/*******************************************************************************
1783 * Scanning
1784 ******************************************************************************/
1785void il_init_scan_params(struct il_priv *il);
1786int il_scan_cancel(struct il_priv *il);
1787int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1788void il_force_scan_end(struct il_priv *il);
1789int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1790                   struct cfg80211_scan_request *req);
1791void il_internal_short_hw_scan(struct il_priv *il);
1792int il_force_reset(struct il_priv *il, bool external);
1793u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1794                      const u8 *ta, const u8 *ie, int ie_len, int left);
1795void il_setup_rx_scan_handlers(struct il_priv *il);
1796u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1797                             u8 n_probes);
1798u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1799                              struct ieee80211_vif *vif);
1800void il_setup_scan_deferred_work(struct il_priv *il);
1801void il_cancel_scan_deferred_work(struct il_priv *il);
1802
1803/* For faster active scanning, scan will move to the next channel if fewer than
1804 * PLCP_QUIET_THRESH packets are heard on this channel within
1805 * ACTIVE_QUIET_TIME after sending probe request.  This shortens the dwell
1806 * time if it's a quiet channel (nothing responded to our probe, and there's
1807 * no other traffic).
1808 * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
1809#define IL_ACTIVE_QUIET_TIME       cpu_to_le16(10)      /* msec */
1810#define IL_PLCP_QUIET_THRESH       cpu_to_le16(1)       /* packets */
1811
1812#define IL_SCAN_CHECK_WATCHDOG          (HZ * 7)
1813
1814/*****************************************************
1815 *   S e n d i n g     H o s t     C o m m a n d s   *
1816 *****************************************************/
1817
1818const char *il_get_cmd_string(u8 cmd);
1819int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1820int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1821int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1822                                 const void *data);
1823int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1824                          void (*callback) (struct il_priv *il,
1825                                            struct il_device_cmd *cmd,
1826                                            struct il_rx_pkt *pkt));
1827
1828int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1829
1830/*****************************************************
1831 * PCI                                               *
1832 *****************************************************/
1833
1834void il_bg_watchdog(unsigned long data);
1835u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1836__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1837                          u32 beacon_interval);
1838
1839#ifdef CONFIG_PM
1840extern const struct dev_pm_ops il_pm_ops;
1841
1842#define IL_LEGACY_PM_OPS        (&il_pm_ops)
1843
1844#else /* !CONFIG_PM */
1845
1846#define IL_LEGACY_PM_OPS        NULL
1847
1848#endif /* !CONFIG_PM */
1849
1850/*****************************************************
1851*  Error Handling Debugging
1852******************************************************/
1853void il4965_dump_nic_error_log(struct il_priv *il);
1854#ifdef CONFIG_IWLEGACY_DEBUG
1855void il_print_rx_config_cmd(struct il_priv *il);
1856#else
1857static inline void
1858il_print_rx_config_cmd(struct il_priv *il)
1859{
1860}
1861#endif
1862
1863void il_clear_isr_stats(struct il_priv *il);
1864
1865/*****************************************************
1866*  GEOS
1867******************************************************/
1868int il_init_geos(struct il_priv *il);
1869void il_free_geos(struct il_priv *il);
1870
1871/*************** DRIVER STATUS FUNCTIONS   *****/
1872
1873#define S_HCMD_ACTIVE   0       /* host command in progress */
1874/* 1 is unused (used to be S_HCMD_SYNC_ACTIVE) */
1875#define S_INT_ENABLED   2
1876#define S_RFKILL        3
1877#define S_CT_KILL               4
1878#define S_INIT          5
1879#define S_ALIVE         6
1880#define S_READY         7
1881#define S_TEMPERATURE   8
1882#define S_GEO_CONFIGURED        9
1883#define S_EXIT_PENDING  10
1884#define S_STATS         12
1885#define S_SCANNING              13
1886#define S_SCAN_ABORTING 14
1887#define S_SCAN_HW               15
1888#define S_POWER_PMI     16
1889#define S_FW_ERROR              17
1890#define S_CHANNEL_SWITCH_PENDING 18
1891
1892static inline int
1893il_is_ready(struct il_priv *il)
1894{
1895        /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
1896         * set but EXIT_PENDING is not */
1897        return test_bit(S_READY, &il->status) &&
1898            test_bit(S_GEO_CONFIGURED, &il->status) &&
1899            !test_bit(S_EXIT_PENDING, &il->status);
1900}
1901
1902static inline int
1903il_is_alive(struct il_priv *il)
1904{
1905        return test_bit(S_ALIVE, &il->status);
1906}
1907
1908static inline int
1909il_is_init(struct il_priv *il)
1910{
1911        return test_bit(S_INIT, &il->status);
1912}
1913
1914static inline int
1915il_is_rfkill(struct il_priv *il)
1916{
1917        return test_bit(S_RFKILL, &il->status);
1918}
1919
1920static inline int
1921il_is_ctkill(struct il_priv *il)
1922{
1923        return test_bit(S_CT_KILL, &il->status);
1924}
1925
1926static inline int
1927il_is_ready_rf(struct il_priv *il)
1928{
1929
1930        if (il_is_rfkill(il))
1931                return 0;
1932
1933        return il_is_ready(il);
1934}
1935
1936extern void il_send_bt_config(struct il_priv *il);
1937extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1938extern void il_apm_stop(struct il_priv *il);
1939extern void _il_apm_stop(struct il_priv *il);
1940
1941int il_apm_init(struct il_priv *il);
1942
1943int il_send_rxon_timing(struct il_priv *il);
1944
1945static inline int
1946il_send_rxon_assoc(struct il_priv *il)
1947{
1948        return il->ops->rxon_assoc(il);
1949}
1950
1951static inline int
1952il_commit_rxon(struct il_priv *il)
1953{
1954        return il->ops->commit_rxon(il);
1955}
1956
1957static inline const struct ieee80211_supported_band *
1958il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
1959{
1960        return il->hw->wiphy->bands[band];
1961}
1962
1963/* mac80211 handlers */
1964int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1965void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1966void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1967                             struct ieee80211_bss_conf *bss_conf, u32 changes);
1968void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1969                          __le16 fc, __le32 *tx_flags);
1970
1971irqreturn_t il_isr(int irq, void *data);
1972
1973extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
1974extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1975extern bool _il_grab_nic_access(struct il_priv *il);
1976extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1977extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1978extern u32 il_rd_prph(struct il_priv *il, u32 reg);
1979extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1980extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1981extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1982
1983static inline void
1984_il_write8(struct il_priv *il, u32 ofs, u8 val)
1985{
1986        writeb(val, il->hw_base + ofs);
1987}
1988#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1989
1990static inline void
1991_il_wr(struct il_priv *il, u32 ofs, u32 val)
1992{
1993        writel(val, il->hw_base + ofs);
1994}
1995
1996static inline u32
1997_il_rd(struct il_priv *il, u32 ofs)
1998{
1999        return readl(il->hw_base + ofs);
2000}
2001
2002static inline void
2003_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2004{
2005        _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2006}
2007
2008static inline void
2009_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2010{
2011        _il_wr(il, reg, _il_rd(il, reg) | mask);
2012}
2013
2014static inline void
2015_il_release_nic_access(struct il_priv *il)
2016{
2017        _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2018        /*
2019         * In above we are reading CSR_GP_CNTRL register, what will flush any
2020         * previous writes, but still want write, which clear MAC_ACCESS_REQ
2021         * bit, be performed on PCI bus before any other writes scheduled on
2022         * different CPUs (after we drop reg_lock).
2023         */
2024        mmiowb();
2025}
2026
2027static inline u32
2028il_rd(struct il_priv *il, u32 reg)
2029{
2030        u32 value;
2031        unsigned long reg_flags;
2032
2033        spin_lock_irqsave(&il->reg_lock, reg_flags);
2034        _il_grab_nic_access(il);
2035        value = _il_rd(il, reg);
2036        _il_release_nic_access(il);
2037        spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2038        return value;
2039}
2040
2041static inline void
2042il_wr(struct il_priv *il, u32 reg, u32 value)
2043{
2044        unsigned long reg_flags;
2045
2046        spin_lock_irqsave(&il->reg_lock, reg_flags);
2047        if (likely(_il_grab_nic_access(il))) {
2048                _il_wr(il, reg, value);
2049                _il_release_nic_access(il);
2050        }
2051        spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2052}
2053
2054static inline u32
2055_il_rd_prph(struct il_priv *il, u32 reg)
2056{
2057        _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2058        return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2059}
2060
2061static inline void
2062_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2063{
2064        _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2065        _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2066}
2067
2068static inline void
2069il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2070{
2071        unsigned long reg_flags;
2072
2073        spin_lock_irqsave(&il->reg_lock, reg_flags);
2074        if (likely(_il_grab_nic_access(il))) {
2075                _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2076                _il_release_nic_access(il);
2077        }
2078        spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2079}
2080
2081static inline void
2082il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2083{
2084        unsigned long reg_flags;
2085
2086        spin_lock_irqsave(&il->reg_lock, reg_flags);
2087        if (likely(_il_grab_nic_access(il))) {
2088                _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2089                _il_release_nic_access(il);
2090        }
2091        spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2092}
2093
2094static inline void
2095il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2096{
2097        unsigned long reg_flags;
2098        u32 val;
2099
2100        spin_lock_irqsave(&il->reg_lock, reg_flags);
2101        if (likely(_il_grab_nic_access(il))) {
2102                val = _il_rd_prph(il, reg);
2103                _il_wr_prph(il, reg, (val & ~mask));
2104                _il_release_nic_access(il);
2105        }
2106        spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2107}
2108
2109#define HW_KEY_DYNAMIC 0
2110#define HW_KEY_DEFAULT 1
2111
2112#define IL_STA_DRIVER_ACTIVE BIT(0)     /* driver entry is active */
2113#define IL_STA_UCODE_ACTIVE  BIT(1)     /* ucode entry is active */
2114#define IL_STA_UCODE_INPROGRESS  BIT(2) /* ucode entry is in process of
2115                                           being activated */
2116#define IL_STA_LOCAL BIT(3)     /* station state not directed by mac80211;
2117                                   (this is for the IBSS BSSID stations) */
2118#define IL_STA_BCAST BIT(4)     /* this station is the special bcast station */
2119
2120void il_restore_stations(struct il_priv *il);
2121void il_clear_ucode_stations(struct il_priv *il);
2122void il_dealloc_bcast_stations(struct il_priv *il);
2123int il_get_free_ucode_key_idx(struct il_priv *il);
2124int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2125int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2126                          struct ieee80211_sta *sta, u8 *sta_id_r);
2127int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2128int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2129                      struct ieee80211_sta *sta);
2130
2131u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2132                   struct ieee80211_sta *sta);
2133
2134int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2135                   u8 flags, bool init);
2136
2137/**
2138 * il_clear_driver_stations - clear knowledge of all stations from driver
2139 * @il: iwl il struct
2140 *
2141 * This is called during il_down() to make sure that in the case
2142 * we're coming there from a hardware restart mac80211 will be
2143 * able to reconfigure stations -- if we're getting there in the
2144 * normal down flow then the stations will already be cleared.
2145 */
2146static inline void
2147il_clear_driver_stations(struct il_priv *il)
2148{
2149        unsigned long flags;
2150
2151        spin_lock_irqsave(&il->sta_lock, flags);
2152        memset(il->stations, 0, sizeof(il->stations));
2153        il->num_stations = 0;
2154        il->ucode_key_table = 0;
2155        spin_unlock_irqrestore(&il->sta_lock, flags);
2156}
2157
2158static inline int
2159il_sta_id(struct ieee80211_sta *sta)
2160{
2161        if (WARN_ON(!sta))
2162                return IL_INVALID_STATION;
2163
2164        return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2165}
2166
2167/**
2168 * il_sta_id_or_broadcast - return sta_id or broadcast sta
2169 * @il: iwl il
2170 * @context: the current context
2171 * @sta: mac80211 station
2172 *
2173 * In certain circumstances mac80211 passes a station pointer
2174 * that may be %NULL, for example during TX or key setup. In
2175 * that case, we need to use the broadcast station, so this
2176 * inline wraps that pattern.
2177 */
2178static inline int
2179il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2180{
2181        int sta_id;
2182
2183        if (!sta)
2184                return il->hw_params.bcast_id;
2185
2186        sta_id = il_sta_id(sta);
2187
2188        /*
2189         * mac80211 should not be passing a partially
2190         * initialised station!
2191         */
2192        WARN_ON(sta_id == IL_INVALID_STATION);
2193
2194        return sta_id;
2195}
2196
2197/**
2198 * il_queue_inc_wrap - increment queue idx, wrap back to beginning
2199 * @idx -- current idx
2200 * @n_bd -- total number of entries in queue (must be power of 2)
2201 */
2202static inline int
2203il_queue_inc_wrap(int idx, int n_bd)
2204{
2205        return ++idx & (n_bd - 1);
2206}
2207
2208/**
2209 * il_queue_dec_wrap - decrement queue idx, wrap back to end
2210 * @idx -- current idx
2211 * @n_bd -- total number of entries in queue (must be power of 2)
2212 */
2213static inline int
2214il_queue_dec_wrap(int idx, int n_bd)
2215{
2216        return --idx & (n_bd - 1);
2217}
2218
2219/* TODO: Move fw_desc functions to iwl-pci.ko */
2220static inline void
2221il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2222{
2223        if (desc->v_addr)
2224                dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2225                                  desc->p_addr);
2226        desc->v_addr = NULL;
2227        desc->len = 0;
2228}
2229
2230static inline int
2231il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2232{
2233        if (!desc->len) {
2234                desc->v_addr = NULL;
2235                return -EINVAL;
2236        }
2237
2238        desc->v_addr =
2239            dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2240                               GFP_KERNEL);
2241        return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2242}
2243
2244/*
2245 * we have 8 bits used like this:
2246 *
2247 * 7 6 5 4 3 2 1 0
2248 * | | | | | | | |
2249 * | | | | | | +-+-------- AC queue (0-3)
2250 * | | | | | |
2251 * | +-+-+-+-+------------ HW queue ID
2252 * |
2253 * +---------------------- unused
2254 */
2255static inline void
2256il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2257{
2258        BUG_ON(ac > 3);         /* only have 2 bits */
2259        BUG_ON(hwq > 31);       /* only use 5 bits */
2260
2261        txq->swq_id = (hwq << 2) | ac;
2262}
2263
2264static inline void
2265il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2266{
2267        u8 queue = txq->swq_id;
2268        u8 ac = queue & 3;
2269        u8 hwq = (queue >> 2) & 0x1f;
2270
2271        if (test_and_clear_bit(hwq, il->queue_stopped))
2272                if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2273                        ieee80211_wake_queue(il->hw, ac);
2274}
2275
2276static inline void
2277il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2278{
2279        u8 queue = txq->swq_id;
2280        u8 ac = queue & 3;
2281        u8 hwq = (queue >> 2) & 0x1f;
2282
2283        if (!test_and_set_bit(hwq, il->queue_stopped))
2284                if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2285                        ieee80211_stop_queue(il->hw, ac);
2286}
2287
2288#ifdef ieee80211_stop_queue
2289#undef ieee80211_stop_queue
2290#endif
2291
2292#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2293
2294#ifdef ieee80211_wake_queue
2295#undef ieee80211_wake_queue
2296#endif
2297
2298#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2299
2300static inline void
2301il_disable_interrupts(struct il_priv *il)
2302{
2303        clear_bit(S_INT_ENABLED, &il->status);
2304
2305        /* disable interrupts from uCode/NIC to host */
2306        _il_wr(il, CSR_INT_MASK, 0x00000000);
2307
2308        /* acknowledge/clear/reset any interrupts still pending
2309         * from uCode or flow handler (Rx/Tx DMA) */
2310        _il_wr(il, CSR_INT, 0xffffffff);
2311        _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2312}
2313
2314static inline void
2315il_enable_rfkill_int(struct il_priv *il)
2316{
2317        _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2318}
2319
2320static inline void
2321il_enable_interrupts(struct il_priv *il)
2322{
2323        set_bit(S_INT_ENABLED, &il->status);
2324        _il_wr(il, CSR_INT_MASK, il->inta_mask);
2325}
2326
2327/**
2328 * il_beacon_time_mask_low - mask of lower 32 bit of beacon time
2329 * @il -- pointer to il_priv data structure
2330 * @tsf_bits -- number of bits need to shift for masking)
2331 */
2332static inline u32
2333il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2334{
2335        return (1 << tsf_bits) - 1;
2336}
2337
2338/**
2339 * il_beacon_time_mask_high - mask of higher 32 bit of beacon time
2340 * @il -- pointer to il_priv data structure
2341 * @tsf_bits -- number of bits need to shift for masking)
2342 */
2343static inline u32
2344il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2345{
2346        return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2347}
2348
2349/**
2350 * struct il_rb_status - reseve buffer status host memory mapped FH registers
2351 *
2352 * @closed_rb_num [0:11] - Indicates the idx of the RB which was closed
2353 * @closed_fr_num [0:11] - Indicates the idx of the RX Frame which was closed
2354 * @finished_rb_num [0:11] - Indicates the idx of the current RB
2355 *                           in which the last frame was written to
2356 * @finished_fr_num [0:11] - Indicates the idx of the RX Frame
2357 *                           which was transferred
2358 */
2359struct il_rb_status {
2360        __le16 closed_rb_num;
2361        __le16 closed_fr_num;
2362        __le16 finished_rb_num;
2363        __le16 finished_fr_nam;
2364        __le32 __unused;        /* 3945 only */
2365} __packed;
2366
2367#define TFD_QUEUE_SIZE_MAX      256
2368#define TFD_QUEUE_SIZE_BC_DUP   64
2369#define TFD_QUEUE_BC_SIZE       (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2370#define IL_TX_DMA_MASK          DMA_BIT_MASK(36)
2371#define IL_NUM_OF_TBS           20
2372
2373static inline u8
2374il_get_dma_hi_addr(dma_addr_t addr)
2375{
2376        return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2377}
2378
2379/**
2380 * struct il_tfd_tb transmit buffer descriptor within transmit frame descriptor
2381 *
2382 * This structure contains dma address and length of transmission address
2383 *
2384 * @lo: low [31:0] portion of the dma address of TX buffer every even is
2385 *      unaligned on 16 bit boundary
2386 * @hi_n_len: 0-3 [35:32] portion of dma
2387 *            4-15 length of the tx buffer
2388 */
2389struct il_tfd_tb {
2390        __le32 lo;
2391        __le16 hi_n_len;
2392} __packed;
2393
2394/**
2395 * struct il_tfd
2396 *
2397 * Transmit Frame Descriptor (TFD)
2398 *
2399 * @ __reserved1[3] reserved
2400 * @ num_tbs 0-4 number of active tbs
2401 *           5   reserved
2402 *           6-7 padding (not used)
2403 * @ tbs[20]    transmit frame buffer descriptors
2404 * @ __pad      padding
2405 *
2406 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
2407 * Both driver and device share these circular buffers, each of which must be
2408 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
2409 *
2410 * Driver must indicate the physical address of the base of each
2411 * circular buffer via the FH49_MEM_CBBC_QUEUE registers.
2412 *
2413 * Each TFD contains pointer/size information for up to 20 data buffers
2414 * in host DRAM.  These buffers collectively contain the (one) frame described
2415 * by the TFD.  Each buffer must be a single contiguous block of memory within
2416 * itself, but buffers may be scattered in host DRAM.  Each buffer has max size
2417 * of (4K - 4).  The concatenates all of a TFD's buffers into a single
2418 * Tx frame, up to 8 KBytes in size.
2419 *
2420 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
2421 */
2422struct il_tfd {
2423        u8 __reserved1[3];
2424        u8 num_tbs;
2425        struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2426        __le32 __pad;
2427} __packed;
2428/* PCI registers */
2429#define PCI_CFG_RETRY_TIMEOUT   0x041
2430
2431struct il_rate_info {
2432        u8 plcp;                /* uCode API:  RATE_6M_PLCP, etc. */
2433        u8 plcp_siso;           /* uCode API:  RATE_SISO_6M_PLCP, etc. */
2434        u8 plcp_mimo2;          /* uCode API:  RATE_MIMO2_6M_PLCP, etc. */
2435        u8 ieee;                /* MAC header:  RATE_6M_IEEE, etc. */
2436        u8 prev_ieee;           /* previous rate in IEEE speeds */
2437        u8 next_ieee;           /* next rate in IEEE speeds */
2438        u8 prev_rs;             /* previous rate used in rs algo */
2439        u8 next_rs;             /* next rate used in rs algo */
2440        u8 prev_rs_tgg;         /* previous rate used in TGG rs algo */
2441        u8 next_rs_tgg;         /* next rate used in TGG rs algo */
2442};
2443
2444struct il3945_rate_info {
2445        u8 plcp;                /* uCode API:  RATE_6M_PLCP, etc. */
2446        u8 ieee;                /* MAC header:  RATE_6M_IEEE, etc. */
2447        u8 prev_ieee;           /* previous rate in IEEE speeds */
2448        u8 next_ieee;           /* next rate in IEEE speeds */
2449        u8 prev_rs;             /* previous rate used in rs algo */
2450        u8 next_rs;             /* next rate used in rs algo */
2451        u8 prev_rs_tgg;         /* previous rate used in TGG rs algo */
2452        u8 next_rs_tgg;         /* next rate used in TGG rs algo */
2453        u8 table_rs_idx;        /* idx in rate scale table cmd */
2454        u8 prev_table_rs;       /* prev in rate table cmd */
2455};
2456
2457/*
2458 * These serve as idxes into
2459 * struct il_rate_info il_rates[RATE_COUNT];
2460 */
2461enum {
2462        RATE_1M_IDX = 0,
2463        RATE_2M_IDX,
2464        RATE_5M_IDX,
2465        RATE_11M_IDX,
2466        RATE_6M_IDX,
2467        RATE_9M_IDX,
2468        RATE_12M_IDX,
2469        RATE_18M_IDX,
2470        RATE_24M_IDX,
2471        RATE_36M_IDX,
2472        RATE_48M_IDX,
2473        RATE_54M_IDX,
2474        RATE_60M_IDX,
2475        RATE_COUNT,
2476        RATE_COUNT_LEGACY = RATE_COUNT - 1,     /* Excluding 60M */
2477        RATE_COUNT_3945 = RATE_COUNT - 1,
2478        RATE_INVM_IDX = RATE_COUNT,
2479        RATE_INVALID = RATE_COUNT,
2480};
2481
2482enum {
2483        RATE_6M_IDX_TBL = 0,
2484        RATE_9M_IDX_TBL,
2485        RATE_12M_IDX_TBL,
2486        RATE_18M_IDX_TBL,
2487        RATE_24M_IDX_TBL,
2488        RATE_36M_IDX_TBL,
2489        RATE_48M_IDX_TBL,
2490        RATE_54M_IDX_TBL,
2491        RATE_1M_IDX_TBL,
2492        RATE_2M_IDX_TBL,
2493        RATE_5M_IDX_TBL,
2494        RATE_11M_IDX_TBL,
2495        RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2496};
2497
2498enum {
2499        IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2500        IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2501        IL_LAST_OFDM_RATE = RATE_60M_IDX,
2502        IL_FIRST_CCK_RATE = RATE_1M_IDX,
2503        IL_LAST_CCK_RATE = RATE_11M_IDX,
2504};
2505
2506/* #define vs. enum to keep from defaulting to 'large integer' */
2507#define RATE_6M_MASK   (1 << RATE_6M_IDX)
2508#define RATE_9M_MASK   (1 << RATE_9M_IDX)
2509#define RATE_12M_MASK  (1 << RATE_12M_IDX)
2510#define RATE_18M_MASK  (1 << RATE_18M_IDX)
2511#define RATE_24M_MASK  (1 << RATE_24M_IDX)
2512#define RATE_36M_MASK  (1 << RATE_36M_IDX)
2513#define RATE_48M_MASK  (1 << RATE_48M_IDX)
2514#define RATE_54M_MASK  (1 << RATE_54M_IDX)
2515#define RATE_60M_MASK  (1 << RATE_60M_IDX)
2516#define RATE_1M_MASK   (1 << RATE_1M_IDX)
2517#define RATE_2M_MASK   (1 << RATE_2M_IDX)
2518#define RATE_5M_MASK   (1 << RATE_5M_IDX)
2519#define RATE_11M_MASK  (1 << RATE_11M_IDX)
2520
2521/* uCode API values for legacy bit rates, both OFDM and CCK */
2522enum {
2523        RATE_6M_PLCP = 13,
2524        RATE_9M_PLCP = 15,
2525        RATE_12M_PLCP = 5,
2526        RATE_18M_PLCP = 7,
2527        RATE_24M_PLCP = 9,
2528        RATE_36M_PLCP = 11,
2529        RATE_48M_PLCP = 1,
2530        RATE_54M_PLCP = 3,
2531        RATE_60M_PLCP = 3,      /*FIXME:RS:should be removed */
2532        RATE_1M_PLCP = 10,
2533        RATE_2M_PLCP = 20,
2534        RATE_5M_PLCP = 55,
2535        RATE_11M_PLCP = 110,
2536        /*FIXME:RS:add RATE_LEGACY_INVM_PLCP = 0, */
2537};
2538
2539/* uCode API values for OFDM high-throughput (HT) bit rates */
2540enum {
2541        RATE_SISO_6M_PLCP = 0,
2542        RATE_SISO_12M_PLCP = 1,
2543        RATE_SISO_18M_PLCP = 2,
2544        RATE_SISO_24M_PLCP = 3,
2545        RATE_SISO_36M_PLCP = 4,
2546        RATE_SISO_48M_PLCP = 5,
2547        RATE_SISO_54M_PLCP = 6,
2548        RATE_SISO_60M_PLCP = 7,
2549        RATE_MIMO2_6M_PLCP = 0x8,
2550        RATE_MIMO2_12M_PLCP = 0x9,
2551        RATE_MIMO2_18M_PLCP = 0xa,
2552        RATE_MIMO2_24M_PLCP = 0xb,
2553        RATE_MIMO2_36M_PLCP = 0xc,
2554        RATE_MIMO2_48M_PLCP = 0xd,
2555        RATE_MIMO2_54M_PLCP = 0xe,
2556        RATE_MIMO2_60M_PLCP = 0xf,
2557        RATE_SISO_INVM_PLCP,
2558        RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2559};
2560
2561/* MAC header values for bit rates */
2562enum {
2563        RATE_6M_IEEE = 12,
2564        RATE_9M_IEEE = 18,
2565        RATE_12M_IEEE = 24,
2566        RATE_18M_IEEE = 36,
2567        RATE_24M_IEEE = 48,
2568        RATE_36M_IEEE = 72,
2569        RATE_48M_IEEE = 96,
2570        RATE_54M_IEEE = 108,
2571        RATE_60M_IEEE = 120,
2572        RATE_1M_IEEE = 2,
2573        RATE_2M_IEEE = 4,
2574        RATE_5M_IEEE = 11,
2575        RATE_11M_IEEE = 22,
2576};
2577
2578#define IL_CCK_BASIC_RATES_MASK    \
2579        (RATE_1M_MASK          | \
2580        RATE_2M_MASK)
2581
2582#define IL_CCK_RATES_MASK          \
2583        (IL_CCK_BASIC_RATES_MASK  | \
2584        RATE_5M_MASK          | \
2585        RATE_11M_MASK)
2586
2587#define IL_OFDM_BASIC_RATES_MASK   \
2588        (RATE_6M_MASK         | \
2589        RATE_12M_MASK         | \
2590        RATE_24M_MASK)
2591
2592#define IL_OFDM_RATES_MASK         \
2593        (IL_OFDM_BASIC_RATES_MASK | \
2594        RATE_9M_MASK          | \
2595        RATE_18M_MASK         | \
2596        RATE_36M_MASK         | \
2597        RATE_48M_MASK         | \
2598        RATE_54M_MASK)
2599
2600#define IL_BASIC_RATES_MASK         \
2601        (IL_OFDM_BASIC_RATES_MASK | \
2602         IL_CCK_BASIC_RATES_MASK)
2603
2604#define RATES_MASK ((1 << RATE_COUNT) - 1)
2605#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2606
2607#define IL_INVALID_VALUE    -1
2608
2609#define IL_MIN_RSSI_VAL                 -100
2610#define IL_MAX_RSSI_VAL                    0
2611
2612/* These values specify how many Tx frame attempts before
2613 * searching for a new modulation mode */
2614#define IL_LEGACY_FAILURE_LIMIT 160
2615#define IL_LEGACY_SUCCESS_LIMIT 480
2616#define IL_LEGACY_TBL_COUNT             160
2617
2618#define IL_NONE_LEGACY_FAILURE_LIMIT    400
2619#define IL_NONE_LEGACY_SUCCESS_LIMIT    4500
2620#define IL_NONE_LEGACY_TBL_COUNT        1500
2621
2622/* Success ratio (ACKed / attempted tx frames) values (perfect is 128 * 100) */
2623#define IL_RS_GOOD_RATIO                12800   /* 100% */
2624#define RATE_SCALE_SWITCH               10880   /*  85% */
2625#define RATE_HIGH_TH            10880   /*  85% */
2626#define RATE_INCREASE_TH                6400    /*  50% */
2627#define RATE_DECREASE_TH                1920    /*  15% */
2628
2629/* possible actions when in legacy mode */
2630#define IL_LEGACY_SWITCH_ANTENNA1      0
2631#define IL_LEGACY_SWITCH_ANTENNA2      1
2632#define IL_LEGACY_SWITCH_SISO          2
2633#define IL_LEGACY_SWITCH_MIMO2_AB      3
2634#define IL_LEGACY_SWITCH_MIMO2_AC      4
2635#define IL_LEGACY_SWITCH_MIMO2_BC      5
2636
2637/* possible actions when in siso mode */
2638#define IL_SISO_SWITCH_ANTENNA1        0
2639#define IL_SISO_SWITCH_ANTENNA2        1
2640#define IL_SISO_SWITCH_MIMO2_AB        2
2641#define IL_SISO_SWITCH_MIMO2_AC        3
2642#define IL_SISO_SWITCH_MIMO2_BC        4
2643#define IL_SISO_SWITCH_GI              5
2644
2645/* possible actions when in mimo mode */
2646#define IL_MIMO2_SWITCH_ANTENNA1       0
2647#define IL_MIMO2_SWITCH_ANTENNA2       1
2648#define IL_MIMO2_SWITCH_SISO_A         2
2649#define IL_MIMO2_SWITCH_SISO_B         3
2650#define IL_MIMO2_SWITCH_SISO_C         4
2651#define IL_MIMO2_SWITCH_GI             5
2652
2653#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2654
2655#define IL_ACTION_LIMIT         3       /* # possible actions */
2656
2657#define LQ_SIZE         2       /* 2 mode tables:  "Active" and "Search" */
2658
2659/* load per tid defines for A-MPDU activation */
2660#define IL_AGG_TPT_THREHOLD     0
2661#define IL_AGG_LOAD_THRESHOLD   10
2662#define IL_AGG_ALL_TID          0xff
2663#define TID_QUEUE_CELL_SPACING  50      /*mS */
2664#define TID_QUEUE_MAX_SIZE      20
2665#define TID_ROUND_VALUE         5       /* mS */
2666#define TID_MAX_LOAD_COUNT      8
2667
2668#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2669#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2670
2671extern const struct il_rate_info il_rates[RATE_COUNT];
2672
2673enum il_table_type {
2674        LQ_NONE,
2675        LQ_G,                   /* legacy types */
2676        LQ_A,
2677        LQ_SISO,                /* high-throughput types */
2678        LQ_MIMO2,
2679        LQ_MAX,
2680};
2681
2682#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2683#define is_siso(tbl) ((tbl) == LQ_SISO)
2684#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2685#define is_mimo(tbl) (is_mimo2(tbl))
2686#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2687#define is_a_band(tbl) ((tbl) == LQ_A)
2688#define is_g_and(tbl) ((tbl) == LQ_G)
2689
2690#define ANT_NONE        0x0
2691#define ANT_A           BIT(0)
2692#define ANT_B           BIT(1)
2693#define ANT_AB          (ANT_A | ANT_B)
2694#define ANT_C           BIT(2)
2695#define ANT_AC          (ANT_A | ANT_C)
2696#define ANT_BC          (ANT_B | ANT_C)
2697#define ANT_ABC         (ANT_AB | ANT_C)
2698
2699#define IL_MAX_MCS_DISPLAY_SIZE 12
2700
2701struct il_rate_mcs_info {
2702        char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2703        char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2704};
2705
2706/**
2707 * struct il_rate_scale_data -- tx success history for one rate
2708 */
2709struct il_rate_scale_data {
2710        u64 data;               /* bitmap of successful frames */
2711        s32 success_counter;    /* number of frames successful */
2712        s32 success_ratio;      /* per-cent * 128  */
2713        s32 counter;            /* number of frames attempted */
2714        s32 average_tpt;        /* success ratio * expected throughput */
2715        unsigned long stamp;
2716};
2717
2718/**
2719 * struct il_scale_tbl_info -- tx params and success history for all rates
2720 *
2721 * There are two of these in struct il_lq_sta,
2722 * one for "active", and one for "search".
2723 */
2724struct il_scale_tbl_info {
2725        enum il_table_type lq_type;
2726        u8 ant_type;
2727        u8 is_SGI;              /* 1 = short guard interval */
2728        u8 is_ht40;             /* 1 = 40 MHz channel width */
2729        u8 is_dup;              /* 1 = duplicated data streams */
2730        u8 action;              /* change modulation; IL_[LEGACY/SISO/MIMO]_SWITCH_* */
2731        u8 max_search;          /* maximun number of tables we can search */
2732        s32 *expected_tpt;      /* throughput metrics; expected_tpt_G, etc. */
2733        u32 current_rate;       /* rate_n_flags, uCode API format */
2734        struct il_rate_scale_data win[RATE_COUNT];      /* rate histories */
2735};
2736
2737struct il_traffic_load {
2738        unsigned long time_stamp;       /* age of the oldest stats */
2739        u32 packet_count[TID_QUEUE_MAX_SIZE];   /* packet count in this time
2740                                                 * slice */
2741        u32 total;              /* total num of packets during the
2742                                 * last TID_MAX_TIME_DIFF */
2743        u8 queue_count;         /* number of queues that has
2744                                 * been used since the last cleanup */
2745        u8 head;                /* start of the circular buffer */
2746};
2747
2748/**
2749 * struct il_lq_sta -- driver's rate scaling ilate structure
2750 *
2751 * Pointer to this gets passed back and forth between driver and mac80211.
2752 */
2753struct il_lq_sta {
2754        u8 active_tbl;          /* idx of active table, range 0-1 */
2755        u8 enable_counter;      /* indicates HT mode */
2756        u8 stay_in_tbl;         /* 1: disallow, 0: allow search for new mode */
2757        u8 search_better_tbl;   /* 1: currently trying alternate mode */
2758        s32 last_tpt;
2759
2760        /* The following determine when to search for a new mode */
2761        u32 table_count_limit;
2762        u32 max_failure_limit;  /* # failed frames before new search */
2763        u32 max_success_limit;  /* # successful frames before new search */
2764        u32 table_count;
2765        u32 total_failed;       /* total failed frames, any/all rates */
2766        u32 total_success;      /* total successful frames, any/all rates */
2767        u64 flush_timer;        /* time staying in mode before new search */
2768
2769        u8 action_counter;      /* # mode-switch actions tried */
2770        u8 is_green;
2771        u8 is_dup;
2772        enum ieee80211_band band;
2773
2774        /* The following are bitmaps of rates; RATE_6M_MASK, etc. */
2775        u32 supp_rates;
2776        u16 active_legacy_rate;
2777        u16 active_siso_rate;
2778        u16 active_mimo2_rate;
2779        s8 max_rate_idx;        /* Max rate set by user */
2780        u8 missed_rate_counter;
2781
2782        struct il_link_quality_cmd lq;
2783        struct il_scale_tbl_info lq_info[LQ_SIZE];      /* "active", "search" */
2784        struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2785        u8 tx_agg_tid_en;
2786#ifdef CONFIG_MAC80211_DEBUGFS
2787        struct dentry *rs_sta_dbgfs_scale_table_file;
2788        struct dentry *rs_sta_dbgfs_stats_table_file;
2789        struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2790        struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2791        u32 dbg_fixed_rate;
2792#endif
2793        struct il_priv *drv;
2794
2795        /* used to be in sta_info */
2796        int last_txrate_idx;
2797        /* last tx rate_n_flags */
2798        u32 last_rate_n_flags;
2799        /* packets destined for this STA are aggregated */
2800        u8 is_agg;
2801};
2802
2803/*
2804 * il_station_priv: Driver's ilate station information
2805 *
2806 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
2807 * in the structure for use by driver. This structure is places in that
2808 * space.
2809 *
2810 * The common struct MUST be first because it is shared between
2811 * 3945 and 4965!
2812 */
2813struct il_station_priv {
2814        struct il_station_priv_common common;
2815        struct il_lq_sta lq_sta;
2816        atomic_t pending_frames;
2817        bool client;
2818        bool asleep;
2819};
2820
2821static inline u8
2822il4965_num_of_ant(u8 m)
2823{
2824        return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2825}
2826
2827static inline u8
2828il4965_first_antenna(u8 mask)
2829{
2830        if (mask & ANT_A)
2831                return ANT_A;
2832        if (mask & ANT_B)
2833                return ANT_B;
2834        return ANT_C;
2835}
2836
2837/**
2838 * il3945_rate_scale_init - Initialize the rate scale table based on assoc info
2839 *
2840 * The specific throughput table used is based on the type of network
2841 * the associated with, including A, B, G, and G w/ TGG protection
2842 */
2843extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2844
2845/* Initialize station's rate scaling information after adding station */
2846extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2847                                u8 sta_id);
2848extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2849                                u8 sta_id);
2850
2851/**
2852 * il_rate_control_register - Register the rate control algorithm callbacks
2853 *
2854 * Since the rate control algorithm is hardware specific, there is no need
2855 * or reason to place it as a stand alone module.  The driver can call
2856 * il_rate_control_register in order to register the rate control callbacks
2857 * with the mac80211 subsystem.  This should be performed prior to calling
2858 * ieee80211_register_hw
2859 *
2860 */
2861extern int il4965_rate_control_register(void);
2862extern int il3945_rate_control_register(void);
2863
2864/**
2865 * il_rate_control_unregister - Unregister the rate control callbacks
2866 *
2867 * This should be called after calling ieee80211_unregister_hw, but before
2868 * the driver is unloaded.
2869 */
2870extern void il4965_rate_control_unregister(void);
2871extern void il3945_rate_control_unregister(void);
2872
2873extern int il_power_update_mode(struct il_priv *il, bool force);
2874extern void il_power_initialize(struct il_priv *il);
2875
2876extern u32 il_debug_level;
2877
2878#ifdef CONFIG_IWLEGACY_DEBUG
2879/*
2880 * il_get_debug_level: Return active debug level for device
2881 *
2882 * Using sysfs it is possible to set per device debug level. This debug
2883 * level will be used if set, otherwise the global debug level which can be
2884 * set via module parameter is used.
2885 */
2886static inline u32
2887il_get_debug_level(struct il_priv *il)
2888{
2889        if (il->debug_level)
2890                return il->debug_level;
2891        else
2892                return il_debug_level;
2893}
2894#else
2895static inline u32
2896il_get_debug_level(struct il_priv *il)
2897{
2898        return il_debug_level;
2899}
2900#endif
2901
2902#define il_print_hex_error(il, p, len)                                  \
2903do {                                                                    \
2904        print_hex_dump(KERN_ERR, "iwl data: ",                          \
2905                       DUMP_PREFIX_OFFSET, 16, 1, p, len, 1);           \
2906} while (0)
2907
2908#ifdef CONFIG_IWLEGACY_DEBUG
2909#define IL_DBG(level, fmt, args...)                                     \
2910do {                                                                    \
2911        if (il_get_debug_level(il) & level)                             \
2912                dev_err(&il->hw->wiphy->dev, "%c %s " fmt,              \
2913                        in_interrupt() ? 'I' : 'U', __func__ , ##args); \
2914} while (0)
2915
2916#define il_print_hex_dump(il, level, p, len)                            \
2917do {                                                                    \
2918        if (il_get_debug_level(il) & level)                             \
2919                print_hex_dump(KERN_DEBUG, "iwl data: ",                \
2920                               DUMP_PREFIX_OFFSET, 16, 1, p, len, 1);   \
2921} while (0)
2922
2923#else
2924#define IL_DBG(level, fmt, args...)
2925static inline void
2926il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2927{
2928}
2929#endif /* CONFIG_IWLEGACY_DEBUG */
2930
2931#ifdef CONFIG_IWLEGACY_DEBUGFS
2932int il_dbgfs_register(struct il_priv *il, const char *name);
2933void il_dbgfs_unregister(struct il_priv *il);
2934#else
2935static inline int
2936il_dbgfs_register(struct il_priv *il, const char *name)
2937{
2938        return 0;
2939}
2940
2941static inline void
2942il_dbgfs_unregister(struct il_priv *il)
2943{
2944}
2945#endif /* CONFIG_IWLEGACY_DEBUGFS */
2946
2947/*
2948 * To use the debug system:
2949 *
2950 * If you are defining a new debug classification, simply add it to the #define
2951 * list here in the form of
2952 *
2953 * #define IL_DL_xxxx VALUE
2954 *
2955 * where xxxx should be the name of the classification (for example, WEP).
2956 *
2957 * You then need to either add a IL_xxxx_DEBUG() macro definition for your
2958 * classification, or use IL_DBG(IL_DL_xxxx, ...) whenever you want
2959 * to send output to that classification.
2960 *
2961 * The active debug levels can be accessed via files
2962 *
2963 *      /sys/module/iwl4965/parameters/debug
2964 *      /sys/module/iwl3945/parameters/debug
2965 *      /sys/class/net/wlan0/device/debug_level
2966 *
2967 * when CONFIG_IWLEGACY_DEBUG=y.
2968 */
2969
2970/* 0x0000000F - 0x00000001 */
2971#define IL_DL_INFO              (1 << 0)
2972#define IL_DL_MAC80211          (1 << 1)
2973#define IL_DL_HCMD              (1 << 2)
2974#define IL_DL_STATE             (1 << 3)
2975/* 0x000000F0 - 0x00000010 */
2976#define IL_DL_MACDUMP           (1 << 4)
2977#define IL_DL_HCMD_DUMP         (1 << 5)
2978#define IL_DL_EEPROM            (1 << 6)
2979#define IL_DL_RADIO             (1 << 7)
2980/* 0x00000F00 - 0x00000100 */
2981#define IL_DL_POWER             (1 << 8)
2982#define IL_DL_TEMP              (1 << 9)
2983#define IL_DL_NOTIF             (1 << 10)
2984#define IL_DL_SCAN              (1 << 11)
2985/* 0x0000F000 - 0x00001000 */
2986#define IL_DL_ASSOC             (1 << 12)
2987#define IL_DL_DROP              (1 << 13)
2988#define IL_DL_TXPOWER           (1 << 14)
2989#define IL_DL_AP                (1 << 15)
2990/* 0x000F0000 - 0x00010000 */
2991#define IL_DL_FW                (1 << 16)
2992#define IL_DL_RF_KILL           (1 << 17)
2993#define IL_DL_FW_ERRORS         (1 << 18)
2994#define IL_DL_LED               (1 << 19)
2995/* 0x00F00000 - 0x00100000 */
2996#define IL_DL_RATE              (1 << 20)
2997#define IL_DL_CALIB             (1 << 21)
2998#define IL_DL_WEP               (1 << 22)
2999#define IL_DL_TX                (1 << 23)
3000/* 0x0F000000 - 0x01000000 */
3001#define IL_DL_RX                (1 << 24)
3002#define IL_DL_ISR               (1 << 25)
3003#define IL_DL_HT                (1 << 26)
3004/* 0xF0000000 - 0x10000000 */
3005#define IL_DL_11H               (1 << 28)
3006#define IL_DL_STATS             (1 << 29)
3007#define IL_DL_TX_REPLY          (1 << 30)
3008#define IL_DL_QOS               (1 << 31)
3009
3010#define D_INFO(f, a...)         IL_DBG(IL_DL_INFO, f, ## a)
3011#define D_MAC80211(f, a...)     IL_DBG(IL_DL_MAC80211, f, ## a)
3012#define D_MACDUMP(f, a...)      IL_DBG(IL_DL_MACDUMP, f, ## a)
3013#define D_TEMP(f, a...)         IL_DBG(IL_DL_TEMP, f, ## a)
3014#define D_SCAN(f, a...)         IL_DBG(IL_DL_SCAN, f, ## a)
3015#define D_RX(f, a...)           IL_DBG(IL_DL_RX, f, ## a)
3016#define D_TX(f, a...)           IL_DBG(IL_DL_TX, f, ## a)
3017#define D_ISR(f, a...)          IL_DBG(IL_DL_ISR, f, ## a)
3018#define D_LED(f, a...)          IL_DBG(IL_DL_LED, f, ## a)
3019#define D_WEP(f, a...)          IL_DBG(IL_DL_WEP, f, ## a)
3020#define D_HC(f, a...)           IL_DBG(IL_DL_HCMD, f, ## a)
3021#define D_HC_DUMP(f, a...)      IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3022#define D_EEPROM(f, a...)       IL_DBG(IL_DL_EEPROM, f, ## a)
3023#define D_CALIB(f, a...)        IL_DBG(IL_DL_CALIB, f, ## a)
3024#define D_FW(f, a...)           IL_DBG(IL_DL_FW, f, ## a)
3025#define D_RF_KILL(f, a...)      IL_DBG(IL_DL_RF_KILL, f, ## a)
3026#define D_DROP(f, a...)         IL_DBG(IL_DL_DROP, f, ## a)
3027#define D_AP(f, a...)           IL_DBG(IL_DL_AP, f, ## a)
3028#define D_TXPOWER(f, a...)      IL_DBG(IL_DL_TXPOWER, f, ## a)
3029#define D_RATE(f, a...)         IL_DBG(IL_DL_RATE, f, ## a)
3030#define D_NOTIF(f, a...)        IL_DBG(IL_DL_NOTIF, f, ## a)
3031#define D_ASSOC(f, a...)        IL_DBG(IL_DL_ASSOC, f, ## a)
3032#define D_HT(f, a...)           IL_DBG(IL_DL_HT, f, ## a)
3033#define D_STATS(f, a...)        IL_DBG(IL_DL_STATS, f, ## a)
3034#define D_TX_REPLY(f, a...)     IL_DBG(IL_DL_TX_REPLY, f, ## a)
3035#define D_QOS(f, a...)          IL_DBG(IL_DL_QOS, f, ## a)
3036#define D_RADIO(f, a...)        IL_DBG(IL_DL_RADIO, f, ## a)
3037#define D_POWER(f, a...)        IL_DBG(IL_DL_POWER, f, ## a)
3038#define D_11H(f, a...)          IL_DBG(IL_DL_11H, f, ## a)
3039
3040#endif /* __il_core_h__ */
3041