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26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
34#include <linux/io.h>
35#include <net/mac80211.h>
36#include <net/ieee80211_radiotap.h>
37
38#include "commands.h"
39#include "csr.h"
40#include "prph.h"
41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
49
50#define RX_QUEUE_SIZE 256
51#define RX_QUEUE_MASK 255
52#define RX_QUEUE_SIZE_LOG 8
53
54
55
56
57#define RX_FREE_BUFFERS 64
58#define RX_LOW_WATERMARK 8
59
60#define U32_PAD(n) ((4-(n))&0x3)
61
62
63#define CT_KILL_THRESHOLD_LEGACY 110
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75
76#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
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85
86#define DEFAULT_RTS_THRESHOLD 2347U
87#define MIN_RTS_THRESHOLD 0U
88#define MAX_RTS_THRESHOLD 2347U
89#define MAX_MSDU_SIZE 2304U
90#define MAX_MPDU_SIZE 2346U
91#define DEFAULT_BEACON_INTERVAL 100U
92#define DEFAULT_SHORT_RETRY_LIMIT 7U
93#define DEFAULT_LONG_RETRY_LIMIT 4U
94
95struct il_rx_buf {
96 dma_addr_t page_dma;
97 struct page *page;
98 struct list_head list;
99};
100
101#define rxb_addr(r) page_address(r->page)
102
103
104struct il_device_cmd;
105
106struct il_cmd_meta {
107
108 struct il_host_cmd *source;
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116 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
117 struct il_rx_pkt *pkt);
118
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121 u32 flags;
122
123 DEFINE_DMA_UNMAP_ADDR(mapping);
124 DEFINE_DMA_UNMAP_LEN(len);
125};
126
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131
132struct il_queue {
133 int n_bd;
134 int write_ptr;
135 int read_ptr;
136
137 dma_addr_t dma_addr;
138 int n_win;
139 u32 id;
140 int low_mark;
141
142 int high_mark;
143
144};
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160
161#define TFD_TX_CMD_SLOTS 256
162#define TFD_CMD_SLOTS 32
163
164struct il_tx_queue {
165 struct il_queue q;
166 void *tfds;
167 struct il_device_cmd **cmd;
168 struct il_cmd_meta *meta;
169 struct sk_buff **skbs;
170 unsigned long time_stamp;
171 u8 need_update;
172 u8 sched_retry;
173 u8 active;
174 u8 swq_id;
175};
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184
185#define IL_EEPROM_ACCESS_TIMEOUT 5000
186
187#define IL_EEPROM_SEM_TIMEOUT 10
188#define IL_EEPROM_SEM_RETRY_LIMIT 1000
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205
206#define IL_NUM_TX_CALIB_GROUPS 5
207enum {
208 EEPROM_CHANNEL_VALID = (1 << 0),
209 EEPROM_CHANNEL_IBSS = (1 << 1),
210
211 EEPROM_CHANNEL_ACTIVE = (1 << 3),
212 EEPROM_CHANNEL_RADAR = (1 << 4),
213 EEPROM_CHANNEL_WIDE = (1 << 5),
214
215 EEPROM_CHANNEL_DFS = (1 << 7),
216};
217
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219
220#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
221#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
222
223
224
225struct il_eeprom_channel {
226 u8 flags;
227 s8 max_power_avg;
228} __packed;
229
230
231#define EEPROM_3945_EEPROM_VERSION (0x2f)
232
233
234#define EEPROM_TX_POWER_TX_CHAINS (2)
235
236
237#define EEPROM_TX_POWER_BANDS (8)
238
239
240
241#define EEPROM_TX_POWER_MEASUREMENTS (3)
242
243
244
245#define EEPROM_4965_TX_POWER_VERSION (5)
246#define EEPROM_4965_EEPROM_VERSION (0x2f)
247#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6)
248#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8)
249#define EEPROM_4965_BOARD_REVISION (2*0x4F)
250#define EEPROM_4965_BOARD_PBA (2*0x56+1)
251
252
253extern const u8 il_eeprom_band_1[14];
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268
269struct il_eeprom_calib_measure {
270 u8 temperature;
271 u8 gain_idx;
272 u8 actual_pow;
273 s8 pa_det;
274} __packed;
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283
284struct il_eeprom_calib_ch_info {
285 u8 ch_num;
286 struct il_eeprom_calib_measure
287 measurements[EEPROM_TX_POWER_TX_CHAINS]
288 [EEPROM_TX_POWER_MEASUREMENTS];
289} __packed;
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301struct il_eeprom_calib_subband_info {
302 u8 ch_from;
303 u8 ch_to;
304 struct il_eeprom_calib_ch_info ch1;
305 struct il_eeprom_calib_ch_info ch2;
306} __packed;
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328struct il_eeprom_calib_info {
329 u8 saturation_power24;
330 u8 saturation_power52;
331 __le16 voltage;
332 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
333} __packed;
334
335
336#define EEPROM_DEVICE_ID (2*0x08)
337#define EEPROM_MAC_ADDRESS (2*0x15)
338#define EEPROM_BOARD_REVISION (2*0x35)
339#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1)
340#define EEPROM_VERSION (2*0x44)
341#define EEPROM_SKU_CAP (2*0x45)
342#define EEPROM_OEM_MODE (2*0x46)
343#define EEPROM_WOWLAN_MODE (2*0x47)
344#define EEPROM_RADIO_CONFIG (2*0x48)
345#define EEPROM_NUM_MAC_ADDRESS (2*0x4C)
346
347
348#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3)
349#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3)
350#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3)
351#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3)
352#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF)
353#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)
354
355#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
356#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
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369
370#define EEPROM_REGULATORY_SKU_ID (2*0x60)
371#define EEPROM_REGULATORY_BAND_1 (2*0x62)
372#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63)
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379#define EEPROM_REGULATORY_BAND_2 (2*0x71)
380#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72)
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386#define EEPROM_REGULATORY_BAND_3 (2*0x7F)
387#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80)
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393#define EEPROM_REGULATORY_BAND_4 (2*0x8C)
394#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D)
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400#define EEPROM_REGULATORY_BAND_5 (2*0x98)
401#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99)
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418#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)
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424#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)
425
426#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
427
428int il_eeprom_init(struct il_priv *il);
429void il_eeprom_free(struct il_priv *il);
430const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
431u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
432int il_init_channel_map(struct il_priv *il);
433void il_free_channel_map(struct il_priv *il);
434const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
435 enum ieee80211_band band,
436 u16 channel);
437
438#define IL_NUM_SCAN_RATES (2)
439
440struct il4965_channel_tgd_info {
441 u8 type;
442 s8 max_power;
443};
444
445struct il4965_channel_tgh_info {
446 s64 last_radar_time;
447};
448
449#define IL4965_MAX_RATE (33)
450
451struct il3945_clip_group {
452
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454 const s8 clip_powers[IL_MAX_RATES];
455};
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464struct il3945_channel_power_info {
465 struct il3945_tx_power tpc;
466 s8 power_table_idx;
467 s8 base_power_idx;
468 s8 requested_power;
469};
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473struct il3945_scan_power_info {
474 struct il3945_tx_power tpc;
475 s8 power_table_idx;
476 s8 requested_power;
477};
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484struct il_channel_info {
485 struct il4965_channel_tgd_info tgd;
486 struct il4965_channel_tgh_info tgh;
487 struct il_eeprom_channel eeprom;
488 struct il_eeprom_channel ht40_eeprom;
489
490
491 u8 channel;
492 u8 flags;
493 s8 max_power_avg;
494 s8 curr_txpow;
495 s8 min_power;
496 s8 scan_power;
497
498 u8 group_idx;
499 u8 band_idx;
500 enum ieee80211_band band;
501
502
503 s8 ht40_max_power_avg;
504 u8 ht40_flags;
505 u8 ht40_extension_channel;
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510 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
511
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513 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
514};
515
516#define IL_TX_FIFO_BK 0
517#define IL_TX_FIFO_BE 1
518#define IL_TX_FIFO_VI 2
519#define IL_TX_FIFO_VO 3
520#define IL_TX_FIFO_UNUSED -1
521
522
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524
525#define IL_MIN_NUM_QUEUES 10
526
527#define IL_DEFAULT_CMD_QUEUE_NUM 4
528
529#define IEEE80211_DATA_LEN 2304
530#define IEEE80211_4ADDR_LEN 30
531#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
532#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
533
534struct il_frame {
535 union {
536 struct ieee80211_hdr frame;
537 struct il_tx_beacon_cmd beacon;
538 u8 raw[IEEE80211_FRAME_LEN];
539 u8 cmd[360];
540 } u;
541 struct list_head list;
542};
543
544#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
545#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
546#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
547
548enum {
549 CMD_SYNC = 0,
550 CMD_SIZE_NORMAL = 0,
551 CMD_NO_SKB = 0,
552 CMD_SIZE_HUGE = (1 << 0),
553 CMD_ASYNC = (1 << 1),
554 CMD_WANT_SKB = (1 << 2),
555 CMD_MAPPED = (1 << 3),
556};
557
558#define DEF_CMD_PAYLOAD_SIZE 320
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566
567struct il_device_cmd {
568 struct il_cmd_header hdr;
569 union {
570 u32 flags;
571 u8 val8;
572 u16 val16;
573 u32 val32;
574 struct il_tx_cmd tx;
575 u8 payload[DEF_CMD_PAYLOAD_SIZE];
576 } __packed cmd;
577} __packed;
578
579#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
580
581struct il_host_cmd {
582 const void *data;
583 unsigned long reply_page;
584 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
585 struct il_rx_pkt *pkt);
586 u32 flags;
587 u16 len;
588 u8 id;
589};
590
591#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
592#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
593#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
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610struct il_rx_queue {
611 __le32 *bd;
612 dma_addr_t bd_dma;
613 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
614 struct il_rx_buf *queue[RX_QUEUE_SIZE];
615 u32 read;
616 u32 write;
617 u32 free_count;
618 u32 write_actual;
619 struct list_head rx_free;
620 struct list_head rx_used;
621 int need_update;
622 struct il_rb_status *rb_stts;
623 dma_addr_t rb_stts_dma;
624 spinlock_t lock;
625};
626
627#define IL_SUPPORTED_RATES_IE_LEN 8
628
629#define MAX_TID_COUNT 9
630
631#define IL_INVALID_RATE 0xFF
632#define IL_INVALID_VALUE -1
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648struct il_ht_agg {
649 u16 txq_id;
650 u16 frame_count;
651 u16 wait_for_ba;
652 u16 start_idx;
653 u64 bitmap;
654 u32 rate_n_flags;
655#define IL_AGG_OFF 0
656#define IL_AGG_ON 1
657#define IL_EMPTYING_HW_QUEUE_ADDBA 2
658#define IL_EMPTYING_HW_QUEUE_DELBA 3
659 u8 state;
660};
661
662struct il_tid_data {
663 u16 seq_number;
664 u16 tfds_in_queue;
665 struct il_ht_agg agg;
666};
667
668struct il_hw_key {
669 u32 cipher;
670 int keylen;
671 u8 keyidx;
672 u8 key[32];
673};
674
675union il_ht_rate_supp {
676 u16 rates;
677 struct {
678 u8 siso_rate;
679 u8 mimo_rate;
680 };
681};
682
683#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
684#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
685#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
686#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
687#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
688#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
689#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
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698#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
699#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
700#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
701#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
702#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
703#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
704#define CFG_HT_MPDU_DENSITY_MIN (0x1)
705
706struct il_ht_config {
707 bool single_chain_sufficient;
708 enum ieee80211_smps_mode smps;
709};
710
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712struct il_qos_info {
713 int qos_active;
714 struct il_qosparam_cmd def_qos_parm;
715};
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723struct il_station_entry {
724 struct il_addsta_cmd sta;
725 struct il_tid_data tid[MAX_TID_COUNT];
726 u8 used;
727 struct il_hw_key keyinfo;
728 struct il_link_quality_cmd *lq;
729};
730
731struct il_station_priv_common {
732 u8 sta_id;
733};
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741struct il_vif_priv {
742 u8 ibss_bssid_sta_id;
743};
744
745
746struct fw_desc {
747 void *v_addr;
748 dma_addr_t p_addr;
749 u32 len;
750};
751
752
753struct il_ucode_header {
754 __le32 ver;
755 struct {
756 __le32 inst_size;
757 __le32 data_size;
758 __le32 init_size;
759 __le32 init_data_size;
760 __le32 boot_size;
761 u8 data[0];
762 } v1;
763};
764
765struct il4965_ibss_seq {
766 u8 mac[ETH_ALEN];
767 u16 seq_num;
768 u16 frag_num;
769 unsigned long packet_time;
770 struct list_head list;
771};
772
773struct il_sensitivity_ranges {
774 u16 min_nrg_cck;
775 u16 max_nrg_cck;
776
777 u16 nrg_th_cck;
778 u16 nrg_th_ofdm;
779
780 u16 auto_corr_min_ofdm;
781 u16 auto_corr_min_ofdm_mrc;
782 u16 auto_corr_min_ofdm_x1;
783 u16 auto_corr_min_ofdm_mrc_x1;
784
785 u16 auto_corr_max_ofdm;
786 u16 auto_corr_max_ofdm_mrc;
787 u16 auto_corr_max_ofdm_x1;
788 u16 auto_corr_max_ofdm_mrc_x1;
789
790 u16 auto_corr_max_cck;
791 u16 auto_corr_max_cck_mrc;
792 u16 auto_corr_min_cck;
793 u16 auto_corr_min_cck_mrc;
794
795 u16 barker_corr_th_min;
796 u16 barker_corr_th_min_mrc;
797 u16 nrg_th_cca;
798};
799
800#define KELVIN_TO_CELSIUS(x) ((x)-273)
801#define CELSIUS_TO_KELVIN(x) ((x)+273)
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825struct il_hw_params {
826 u8 bcast_id;
827 u8 max_txq_num;
828 u8 dma_chnl_num;
829 u16 scd_bc_tbls_size;
830 u32 tfd_size;
831 u8 tx_chains_num;
832 u8 rx_chains_num;
833 u8 valid_tx_ant;
834 u8 valid_rx_ant;
835 u16 max_rxq_size;
836 u16 max_rxq_log;
837 u32 rx_page_order;
838 u32 rx_wrt_ptr_reg;
839 u8 max_stations;
840 u8 ht40_channel;
841 u8 max_beacon_itrvl;
842 u32 max_inst_size;
843 u32 max_data_size;
844 u32 max_bsm_size;
845 u32 ct_kill_threshold;
846 u16 beacon_time_tsf_bits;
847 const struct il_sensitivity_ranges *sens;
848};
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864
865extern void il4965_update_chain_flags(struct il_priv *il);
866extern const u8 il_bcast_addr[ETH_ALEN];
867extern int il_queue_space(const struct il_queue *q);
868static inline int
869il_queue_used(const struct il_queue *q, int i)
870{
871 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
872 i < q->write_ptr) : !(i <
873 q->read_ptr
874 && i >=
875 q->
876 write_ptr);
877}
878
879static inline u8
880il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
881{
882
883
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885
886
887 if (is_huge)
888 return q->n_win;
889
890
891 return idx & (q->n_win - 1);
892}
893
894struct il_dma_ptr {
895 dma_addr_t dma;
896 void *addr;
897 size_t size;
898};
899
900#define IL_OPERATION_MODE_AUTO 0
901#define IL_OPERATION_MODE_HT_ONLY 1
902#define IL_OPERATION_MODE_MIXED 2
903#define IL_OPERATION_MODE_20MHZ 3
904
905#define IL_TX_CRC_SIZE 4
906#define IL_TX_DELIMITER_SIZE 4
907
908#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
909
910
911#define INITIALIZATION_VALUE 0xFFFF
912#define IL4965_CAL_NUM_BEACONS 20
913#define IL_CAL_NUM_BEACONS 16
914#define MAXIMUM_ALLOWED_PATHLOSS 15
915
916#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
917
918#define MAX_FA_OFDM 50
919#define MIN_FA_OFDM 5
920#define MAX_FA_CCK 50
921#define MIN_FA_CCK 5
922
923#define AUTO_CORR_STEP_OFDM 1
924
925#define AUTO_CORR_STEP_CCK 3
926#define AUTO_CORR_MAX_TH_CCK 160
927
928#define NRG_DIFF 2
929#define NRG_STEP_CCK 2
930#define NRG_MARGIN 8
931#define MAX_NUMBER_CCK_NO_FA 100
932
933#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
934
935#define CHAIN_A 0
936#define CHAIN_B 1
937#define CHAIN_C 2
938#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
939#define ALL_BAND_FILTER 0xFF00
940#define IN_BAND_FILTER 0xFF
941#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
942
943#define NRG_NUM_PREV_STAT_L 20
944#define NUM_RX_CHAINS 3
945
946enum il4965_false_alarm_state {
947 IL_FA_TOO_MANY = 0,
948 IL_FA_TOO_FEW = 1,
949 IL_FA_GOOD_RANGE = 2,
950};
951
952enum il4965_chain_noise_state {
953 IL_CHAIN_NOISE_ALIVE = 0,
954 IL_CHAIN_NOISE_ACCUMULATE,
955 IL_CHAIN_NOISE_CALIBRATED,
956 IL_CHAIN_NOISE_DONE,
957};
958
959enum ucode_type {
960 UCODE_NONE = 0,
961 UCODE_INIT,
962 UCODE_RT
963};
964
965
966struct il_sensitivity_data {
967 u32 auto_corr_ofdm;
968 u32 auto_corr_ofdm_mrc;
969 u32 auto_corr_ofdm_x1;
970 u32 auto_corr_ofdm_mrc_x1;
971 u32 auto_corr_cck;
972 u32 auto_corr_cck_mrc;
973
974 u32 last_bad_plcp_cnt_ofdm;
975 u32 last_fa_cnt_ofdm;
976 u32 last_bad_plcp_cnt_cck;
977 u32 last_fa_cnt_cck;
978
979 u32 nrg_curr_state;
980 u32 nrg_prev_state;
981 u32 nrg_value[10];
982 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
983 u32 nrg_silence_ref;
984 u32 nrg_energy_idx;
985 u32 nrg_silence_idx;
986 u32 nrg_th_cck;
987 s32 nrg_auto_corr_silence_diff;
988 u32 num_in_cck_no_fa;
989 u32 nrg_th_ofdm;
990
991 u16 barker_corr_th_min;
992 u16 barker_corr_th_min_mrc;
993 u16 nrg_th_cca;
994};
995
996
997struct il_chain_noise_data {
998 u32 active_chains;
999 u32 chain_noise_a;
1000 u32 chain_noise_b;
1001 u32 chain_noise_c;
1002 u32 chain_signal_a;
1003 u32 chain_signal_b;
1004 u32 chain_signal_c;
1005 u16 beacon_count;
1006 u8 disconn_array[NUM_RX_CHAINS];
1007 u8 delta_gain_code[NUM_RX_CHAINS];
1008 u8 radio_write;
1009 u8 state;
1010};
1011
1012#define EEPROM_SEM_TIMEOUT 10
1013#define EEPROM_SEM_RETRY_LIMIT 1000
1014
1015#define IL_TRAFFIC_ENTRIES (256)
1016#define IL_TRAFFIC_ENTRY_SIZE (64)
1017
1018enum {
1019 MEASUREMENT_READY = (1 << 0),
1020 MEASUREMENT_ACTIVE = (1 << 1),
1021};
1022
1023
1024struct isr_stats {
1025 u32 hw;
1026 u32 sw;
1027 u32 err_code;
1028 u32 sch;
1029 u32 alive;
1030 u32 rfkill;
1031 u32 ctkill;
1032 u32 wakeup;
1033 u32 rx;
1034 u32 handlers[IL_CN_MAX];
1035 u32 tx;
1036 u32 unhandled;
1037};
1038
1039
1040enum il_mgmt_stats {
1041 MANAGEMENT_ASSOC_REQ = 0,
1042 MANAGEMENT_ASSOC_RESP,
1043 MANAGEMENT_REASSOC_REQ,
1044 MANAGEMENT_REASSOC_RESP,
1045 MANAGEMENT_PROBE_REQ,
1046 MANAGEMENT_PROBE_RESP,
1047 MANAGEMENT_BEACON,
1048 MANAGEMENT_ATIM,
1049 MANAGEMENT_DISASSOC,
1050 MANAGEMENT_AUTH,
1051 MANAGEMENT_DEAUTH,
1052 MANAGEMENT_ACTION,
1053 MANAGEMENT_MAX,
1054};
1055
1056enum il_ctrl_stats {
1057 CONTROL_BACK_REQ = 0,
1058 CONTROL_BACK,
1059 CONTROL_PSPOLL,
1060 CONTROL_RTS,
1061 CONTROL_CTS,
1062 CONTROL_ACK,
1063 CONTROL_CFEND,
1064 CONTROL_CFENDACK,
1065 CONTROL_MAX,
1066};
1067
1068struct traffic_stats {
1069#ifdef CONFIG_IWLEGACY_DEBUGFS
1070 u32 mgmt[MANAGEMENT_MAX];
1071 u32 ctrl[CONTROL_MAX];
1072 u32 data_cnt;
1073 u64 data_bytes;
1074#endif
1075};
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1086#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1087#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1088#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1089#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1090#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1091
1092#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1093
1094
1095#define IL_DEF_WD_TIMEOUT (2000)
1096#define IL_LONG_WD_TIMEOUT (10000)
1097#define IL_MAX_WD_TIMEOUT (120000)
1098
1099struct il_force_reset {
1100 int reset_request_count;
1101 int reset_success_count;
1102 int reset_reject_count;
1103 unsigned long reset_duration;
1104 unsigned long last_force_reset_jiffies;
1105};
1106
1107
1108
1109
1110
1111
1112
1113#define IL3945_EXT_BEACON_TIME_POS 24
1114
1115
1116
1117
1118
1119#define IL4965_EXT_BEACON_TIME_POS 22
1120
1121struct il_rxon_context {
1122 struct ieee80211_vif *vif;
1123};
1124
1125struct il_power_mgr {
1126 struct il_powertable_cmd sleep_cmd;
1127 struct il_powertable_cmd sleep_cmd_next;
1128 int debug_sleep_level_override;
1129 bool pci_pm;
1130};
1131
1132struct il_priv {
1133 struct ieee80211_hw *hw;
1134 struct ieee80211_channel *ieee_channels;
1135 struct ieee80211_rate *ieee_rates;
1136
1137 struct il_cfg *cfg;
1138 const struct il_ops *ops;
1139#ifdef CONFIG_IWLEGACY_DEBUGFS
1140 const struct il_debugfs_ops *debugfs_ops;
1141#endif
1142
1143
1144 struct list_head free_frames;
1145 int frames_count;
1146
1147 enum ieee80211_band band;
1148 int alloc_rxb_page;
1149
1150 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1151 struct il_rx_buf *rxb);
1152
1153 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1154
1155
1156 struct il_spectrum_notification measure_report;
1157 u8 measurement_status;
1158
1159
1160 u32 ucode_beacon_time;
1161 int missed_beacon_threshold;
1162
1163
1164 u32 ibss_manager;
1165
1166
1167 struct il_force_reset force_reset;
1168
1169
1170
1171 struct il_channel_info *channel_info;
1172 u8 channel_count;
1173
1174
1175 s32 temperature;
1176 s32 last_temperature;
1177
1178
1179 unsigned long scan_start;
1180 unsigned long scan_start_tsf;
1181 void *scan_cmd;
1182 enum ieee80211_band scan_band;
1183 struct cfg80211_scan_request *scan_request;
1184 struct ieee80211_vif *scan_vif;
1185 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1186 u8 mgmt_tx_ant;
1187
1188
1189 spinlock_t lock;
1190 spinlock_t hcmd_lock;
1191 spinlock_t reg_lock;
1192 struct mutex mutex;
1193
1194
1195 struct pci_dev *pci_dev;
1196
1197
1198 void __iomem *hw_base;
1199 u32 hw_rev;
1200 u32 hw_wa_rev;
1201 u8 rev_id;
1202
1203
1204 u8 cmd_queue;
1205
1206
1207 u8 sta_key_max_num;
1208
1209
1210 struct mac_address addresses[1];
1211
1212
1213 int fw_idx;
1214 u32 ucode_ver;
1215
1216 struct fw_desc ucode_code;
1217 struct fw_desc ucode_data;
1218 struct fw_desc ucode_data_backup;
1219 struct fw_desc ucode_init;
1220 struct fw_desc ucode_init_data;
1221 struct fw_desc ucode_boot;
1222 enum ucode_type ucode_type;
1223 u8 ucode_write_complete;
1224 char firmware_name[25];
1225
1226 struct ieee80211_vif *vif;
1227
1228 struct il_qos_info qos_data;
1229
1230 struct {
1231 bool enabled;
1232 bool is_40mhz;
1233 bool non_gf_sta_present;
1234 u8 protection;
1235 u8 extension_chan_offset;
1236 } ht;
1237
1238
1239
1240
1241
1242
1243
1244 const struct il_rxon_cmd active;
1245 struct il_rxon_cmd staging;
1246
1247 struct il_rxon_time_cmd timing;
1248
1249 __le16 switch_channel;
1250
1251
1252
1253 struct il_init_alive_resp card_alive_init;
1254 struct il_alive_resp card_alive;
1255
1256 u16 active_rate;
1257
1258 u8 start_calib;
1259 struct il_sensitivity_data sensitivity_data;
1260 struct il_chain_noise_data chain_noise_data;
1261 __le16 sensitivity_tbl[HD_TBL_SIZE];
1262
1263 struct il_ht_config current_ht_config;
1264
1265
1266 u8 retry_rate;
1267
1268 wait_queue_head_t wait_command_queue;
1269
1270 int activity_timer_active;
1271
1272
1273 struct il_rx_queue rxq;
1274 struct il_tx_queue *txq;
1275 unsigned long txq_ctx_active_msk;
1276 struct il_dma_ptr kw;
1277 struct il_dma_ptr scd_bc_tbls;
1278
1279 u32 scd_base_addr;
1280
1281 unsigned long status;
1282
1283
1284 struct traffic_stats tx_stats;
1285 struct traffic_stats rx_stats;
1286
1287
1288 struct isr_stats isr_stats;
1289
1290 struct il_power_mgr power_data;
1291
1292
1293 u8 bssid[ETH_ALEN];
1294
1295
1296
1297
1298 spinlock_t sta_lock;
1299 int num_stations;
1300 struct il_station_entry stations[IL_STATION_COUNT];
1301 unsigned long ucode_key_table;
1302
1303
1304#define IL_MAX_HW_QUEUES 32
1305 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1306
1307 atomic_t queue_stop_count[4];
1308
1309
1310 u8 is_open;
1311
1312 u8 mac80211_registered;
1313
1314
1315 u8 *eeprom;
1316 struct il_eeprom_calib_info *calib_info;
1317
1318 enum nl80211_iftype iw_mode;
1319
1320
1321 u64 timestamp;
1322
1323 union {
1324#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1325 struct {
1326 void *shared_virt;
1327 dma_addr_t shared_phys;
1328
1329 struct delayed_work thermal_periodic;
1330 struct delayed_work rfkill_poll;
1331
1332 struct il3945_notif_stats stats;
1333#ifdef CONFIG_IWLEGACY_DEBUGFS
1334 struct il3945_notif_stats accum_stats;
1335 struct il3945_notif_stats delta_stats;
1336 struct il3945_notif_stats max_delta;
1337#endif
1338
1339 u32 sta_supp_rates;
1340 int last_rx_rssi;
1341
1342
1343 u32 last_beacon_time;
1344 u64 last_tsf;
1345
1346
1347
1348
1349
1350
1351 const struct il3945_clip_group clip_groups[5];
1352
1353 } _3945;
1354#endif
1355#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1356 struct {
1357 struct il_rx_phy_res last_phy_res;
1358 bool last_phy_res_valid;
1359 u32 ampdu_ref;
1360
1361 struct completion firmware_loading_complete;
1362
1363
1364
1365
1366
1367
1368 u8 phy_calib_chain_noise_reset_cmd;
1369 u8 phy_calib_chain_noise_gain_cmd;
1370
1371 u8 key_mapping_keys;
1372 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1373
1374 struct il_notif_stats stats;
1375#ifdef CONFIG_IWLEGACY_DEBUGFS
1376 struct il_notif_stats accum_stats;
1377 struct il_notif_stats delta_stats;
1378 struct il_notif_stats max_delta;
1379#endif
1380
1381 } _4965;
1382#endif
1383 };
1384
1385 struct il_hw_params hw_params;
1386
1387 u32 inta_mask;
1388
1389 struct workqueue_struct *workqueue;
1390
1391 struct work_struct restart;
1392 struct work_struct scan_completed;
1393 struct work_struct rx_replenish;
1394 struct work_struct abort_scan;
1395
1396 bool beacon_enabled;
1397 struct sk_buff *beacon_skb;
1398
1399 struct work_struct tx_flush;
1400
1401 struct tasklet_struct irq_tasklet;
1402
1403 struct delayed_work init_alive_start;
1404 struct delayed_work alive_start;
1405 struct delayed_work scan_check;
1406
1407
1408 s8 tx_power_user_lmt;
1409 s8 tx_power_device_lmt;
1410 s8 tx_power_next;
1411
1412#ifdef CONFIG_IWLEGACY_DEBUG
1413
1414 u32 debug_level;
1415
1416#endif
1417#ifdef CONFIG_IWLEGACY_DEBUGFS
1418
1419 u16 tx_traffic_idx;
1420 u16 rx_traffic_idx;
1421 u8 *tx_traffic;
1422 u8 *rx_traffic;
1423 struct dentry *debugfs_dir;
1424 u32 dbgfs_sram_offset, dbgfs_sram_len;
1425 bool disable_ht40;
1426#endif
1427
1428 struct work_struct txpower_work;
1429 u32 disable_sens_cal;
1430 u32 disable_chain_noise_cal;
1431 u32 disable_tx_power_cal;
1432 struct work_struct run_time_calib_work;
1433 struct timer_list stats_periodic;
1434 struct timer_list watchdog;
1435 bool hw_ready;
1436
1437 struct led_classdev led;
1438 unsigned long blink_on, blink_off;
1439 bool led_registered;
1440};
1441
1442static inline void
1443il_txq_ctx_activate(struct il_priv *il, int txq_id)
1444{
1445 set_bit(txq_id, &il->txq_ctx_active_msk);
1446}
1447
1448static inline void
1449il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1450{
1451 clear_bit(txq_id, &il->txq_ctx_active_msk);
1452}
1453
1454static inline int
1455il_is_associated(struct il_priv *il)
1456{
1457 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1458}
1459
1460static inline int
1461il_is_any_associated(struct il_priv *il)
1462{
1463 return il_is_associated(il);
1464}
1465
1466static inline int
1467il_is_channel_valid(const struct il_channel_info *ch_info)
1468{
1469 if (ch_info == NULL)
1470 return 0;
1471 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1472}
1473
1474static inline int
1475il_is_channel_radar(const struct il_channel_info *ch_info)
1476{
1477 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1478}
1479
1480static inline u8
1481il_is_channel_a_band(const struct il_channel_info *ch_info)
1482{
1483 return ch_info->band == IEEE80211_BAND_5GHZ;
1484}
1485
1486static inline int
1487il_is_channel_passive(const struct il_channel_info *ch)
1488{
1489 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1490}
1491
1492static inline int
1493il_is_channel_ibss(const struct il_channel_info *ch)
1494{
1495 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1496}
1497
1498static inline void
1499__il_free_pages(struct il_priv *il, struct page *page)
1500{
1501 __free_pages(page, il->hw_params.rx_page_order);
1502 il->alloc_rxb_page--;
1503}
1504
1505static inline void
1506il_free_pages(struct il_priv *il, unsigned long page)
1507{
1508 free_pages(page, il->hw_params.rx_page_order);
1509 il->alloc_rxb_page--;
1510}
1511
1512#define IWLWIFI_VERSION "in-tree:"
1513#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1514#define DRV_AUTHOR "<ilw@linux.intel.com>"
1515
1516#define IL_PCI_DEVICE(dev, subdev, cfg) \
1517 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1518 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1519 .driver_data = (kernel_ulong_t)&(cfg)
1520
1521#define TIME_UNIT 1024
1522
1523#define IL_SKU_G 0x1
1524#define IL_SKU_A 0x2
1525#define IL_SKU_N 0x8
1526
1527#define IL_CMD(x) case x: return #x
1528
1529
1530#define IL_RX_BUF_SIZE_3K (3 * 1000)
1531#define IL_RX_BUF_SIZE_4K (4 * 1024)
1532#define IL_RX_BUF_SIZE_8K (8 * 1024)
1533
1534#ifdef CONFIG_IWLEGACY_DEBUGFS
1535struct il_debugfs_ops {
1536 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1537 size_t count, loff_t *ppos);
1538 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1539 size_t count, loff_t *ppos);
1540 ssize_t(*general_stats_read) (struct file *file,
1541 char __user *user_buf, size_t count,
1542 loff_t *ppos);
1543};
1544#endif
1545
1546struct il_ops {
1547
1548 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1549 struct il_tx_queue *txq,
1550 u16 byte_cnt);
1551 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1552 struct il_tx_queue *txq, dma_addr_t addr,
1553 u16 len, u8 reset, u8 pad);
1554 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1555 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1556
1557 void (*init_alive_start) (struct il_priv *il);
1558
1559 int (*is_valid_rtc_data_addr) (u32 addr);
1560
1561 int (*load_ucode) (struct il_priv *il);
1562
1563 void (*dump_nic_error_log) (struct il_priv *il);
1564 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1565 int (*set_channel_switch) (struct il_priv *il,
1566 struct ieee80211_channel_switch *ch_switch);
1567
1568 int (*apm_init) (struct il_priv *il);
1569
1570
1571 int (*send_tx_power) (struct il_priv *il);
1572 void (*update_chain_flags) (struct il_priv *il);
1573
1574
1575 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1576 void (*eeprom_release_semaphore) (struct il_priv *il);
1577
1578 int (*rxon_assoc) (struct il_priv *il);
1579 int (*commit_rxon) (struct il_priv *il);
1580 void (*set_rxon_chain) (struct il_priv *il);
1581
1582 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1583 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1584
1585 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1586 void (*post_scan) (struct il_priv *il);
1587 void (*post_associate) (struct il_priv *il);
1588 void (*config_ap) (struct il_priv *il);
1589
1590 int (*update_bcast_stations) (struct il_priv *il);
1591 int (*manage_ibss_station) (struct il_priv *il,
1592 struct ieee80211_vif *vif, bool add);
1593
1594 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1595};
1596
1597struct il_mod_params {
1598 int sw_crypto;
1599 int disable_hw_scan;
1600 int num_of_queues;
1601 int disable_11n;
1602 int amsdu_size_8K;
1603 int antenna;
1604 int restart_fw;
1605};
1606
1607#define IL_LED_SOLID 11
1608#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1609
1610#define IL_LED_ACTIVITY (0<<1)
1611#define IL_LED_LINK (1<<1)
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621enum il_led_mode {
1622 IL_LED_DEFAULT,
1623 IL_LED_RF_STATE,
1624 IL_LED_BLINK,
1625};
1626
1627void il_leds_init(struct il_priv *il);
1628void il_leds_exit(struct il_priv *il);
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661struct il_cfg {
1662
1663 const char *name;
1664 const char *fw_name_pre;
1665 const unsigned int ucode_api_max;
1666 const unsigned int ucode_api_min;
1667 u8 valid_tx_ant;
1668 u8 valid_rx_ant;
1669 unsigned int sku;
1670 u16 eeprom_ver;
1671 u16 eeprom_calib_ver;
1672
1673 const struct il_mod_params *mod_params;
1674
1675 struct il_base_params *base_params;
1676
1677 u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
1678 enum il_led_mode led_mode;
1679
1680 int eeprom_size;
1681 int num_of_queues;
1682 int num_of_ampdu_queues;
1683
1684 u32 pll_cfg_val;
1685 bool set_l0s;
1686 bool use_bsm;
1687
1688 u16 led_compensation;
1689 int chain_noise_num_beacons;
1690 unsigned int wd_timeout;
1691 bool temperature_kelvin;
1692 const bool ucode_tracing;
1693 const bool sensitivity_calib_by_driver;
1694 const bool chain_noise_calib_by_driver;
1695
1696 const u32 regulatory_bands[7];
1697};
1698
1699
1700
1701
1702
1703int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1704 u16 queue, const struct ieee80211_tx_queue_params *params);
1705int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1706
1707void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1708int il_check_rxon_cmd(struct il_priv *il);
1709int il_full_rxon_required(struct il_priv *il);
1710int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1711void il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
1712 struct ieee80211_vif *vif);
1713u8 il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band);
1714void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1715bool il_is_ht40_tx_allowed(struct il_priv *il,
1716 struct ieee80211_sta_ht_cap *ht_cap);
1717void il_connection_init_rx_config(struct il_priv *il);
1718void il_set_rate(struct il_priv *il);
1719int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1720 u32 decrypt_res, struct ieee80211_rx_status *stats);
1721void il_irq_handle_error(struct il_priv *il);
1722int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1723void il_mac_remove_interface(struct ieee80211_hw *hw,
1724 struct ieee80211_vif *vif);
1725int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1726 enum nl80211_iftype newtype, bool newp2p);
1727void il_mac_flush(struct ieee80211_hw *hw, bool drop);
1728int il_alloc_txq_mem(struct il_priv *il);
1729void il_free_txq_mem(struct il_priv *il);
1730
1731#ifdef CONFIG_IWLEGACY_DEBUGFS
1732extern void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1733#else
1734static inline void
1735il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1736{
1737}
1738#endif
1739
1740
1741
1742
1743void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1744void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1745void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1746void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1747
1748
1749
1750
1751void il_cmd_queue_unmap(struct il_priv *il);
1752void il_cmd_queue_free(struct il_priv *il);
1753int il_rx_queue_alloc(struct il_priv *il);
1754void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1755int il_rx_queue_space(const struct il_rx_queue *q);
1756void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1757
1758void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1759void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1760void il_chswitch_done(struct il_priv *il, bool is_success);
1761
1762
1763
1764
1765extern void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1766extern int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1767extern void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1768extern void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1769extern void il_tx_queue_free(struct il_priv *il, int txq_id);
1770extern void il_setup_watchdog(struct il_priv *il);
1771
1772
1773
1774int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1775
1776
1777
1778
1779
1780u8 il_get_lowest_plcp(struct il_priv *il);
1781
1782
1783
1784
1785void il_init_scan_params(struct il_priv *il);
1786int il_scan_cancel(struct il_priv *il);
1787int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1788void il_force_scan_end(struct il_priv *il);
1789int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1790 struct cfg80211_scan_request *req);
1791void il_internal_short_hw_scan(struct il_priv *il);
1792int il_force_reset(struct il_priv *il, bool external);
1793u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1794 const u8 *ta, const u8 *ie, int ie_len, int left);
1795void il_setup_rx_scan_handlers(struct il_priv *il);
1796u16 il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1797 u8 n_probes);
1798u16 il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1799 struct ieee80211_vif *vif);
1800void il_setup_scan_deferred_work(struct il_priv *il);
1801void il_cancel_scan_deferred_work(struct il_priv *il);
1802
1803
1804
1805
1806
1807
1808
1809#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10)
1810#define IL_PLCP_QUIET_THRESH cpu_to_le16(1)
1811
1812#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1813
1814
1815
1816
1817
1818const char *il_get_cmd_string(u8 cmd);
1819int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1820int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1821int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1822 const void *data);
1823int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1824 void (*callback) (struct il_priv *il,
1825 struct il_device_cmd *cmd,
1826 struct il_rx_pkt *pkt));
1827
1828int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1829
1830
1831
1832
1833
1834void il_bg_watchdog(unsigned long data);
1835u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1836__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1837 u32 beacon_interval);
1838
1839#ifdef CONFIG_PM
1840extern const struct dev_pm_ops il_pm_ops;
1841
1842#define IL_LEGACY_PM_OPS (&il_pm_ops)
1843
1844#else
1845
1846#define IL_LEGACY_PM_OPS NULL
1847
1848#endif
1849
1850
1851
1852
1853void il4965_dump_nic_error_log(struct il_priv *il);
1854#ifdef CONFIG_IWLEGACY_DEBUG
1855void il_print_rx_config_cmd(struct il_priv *il);
1856#else
1857static inline void
1858il_print_rx_config_cmd(struct il_priv *il)
1859{
1860}
1861#endif
1862
1863void il_clear_isr_stats(struct il_priv *il);
1864
1865
1866
1867
1868int il_init_geos(struct il_priv *il);
1869void il_free_geos(struct il_priv *il);
1870
1871
1872
1873#define S_HCMD_ACTIVE 0
1874
1875#define S_INT_ENABLED 2
1876#define S_RFKILL 3
1877#define S_CT_KILL 4
1878#define S_INIT 5
1879#define S_ALIVE 6
1880#define S_READY 7
1881#define S_TEMPERATURE 8
1882#define S_GEO_CONFIGURED 9
1883#define S_EXIT_PENDING 10
1884#define S_STATS 12
1885#define S_SCANNING 13
1886#define S_SCAN_ABORTING 14
1887#define S_SCAN_HW 15
1888#define S_POWER_PMI 16
1889#define S_FW_ERROR 17
1890#define S_CHANNEL_SWITCH_PENDING 18
1891
1892static inline int
1893il_is_ready(struct il_priv *il)
1894{
1895
1896
1897 return test_bit(S_READY, &il->status) &&
1898 test_bit(S_GEO_CONFIGURED, &il->status) &&
1899 !test_bit(S_EXIT_PENDING, &il->status);
1900}
1901
1902static inline int
1903il_is_alive(struct il_priv *il)
1904{
1905 return test_bit(S_ALIVE, &il->status);
1906}
1907
1908static inline int
1909il_is_init(struct il_priv *il)
1910{
1911 return test_bit(S_INIT, &il->status);
1912}
1913
1914static inline int
1915il_is_rfkill(struct il_priv *il)
1916{
1917 return test_bit(S_RFKILL, &il->status);
1918}
1919
1920static inline int
1921il_is_ctkill(struct il_priv *il)
1922{
1923 return test_bit(S_CT_KILL, &il->status);
1924}
1925
1926static inline int
1927il_is_ready_rf(struct il_priv *il)
1928{
1929
1930 if (il_is_rfkill(il))
1931 return 0;
1932
1933 return il_is_ready(il);
1934}
1935
1936extern void il_send_bt_config(struct il_priv *il);
1937extern int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1938extern void il_apm_stop(struct il_priv *il);
1939extern void _il_apm_stop(struct il_priv *il);
1940
1941int il_apm_init(struct il_priv *il);
1942
1943int il_send_rxon_timing(struct il_priv *il);
1944
1945static inline int
1946il_send_rxon_assoc(struct il_priv *il)
1947{
1948 return il->ops->rxon_assoc(il);
1949}
1950
1951static inline int
1952il_commit_rxon(struct il_priv *il)
1953{
1954 return il->ops->commit_rxon(il);
1955}
1956
1957static inline const struct ieee80211_supported_band *
1958il_get_hw_mode(struct il_priv *il, enum ieee80211_band band)
1959{
1960 return il->hw->wiphy->bands[band];
1961}
1962
1963
1964int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1965void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1966void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1967 struct ieee80211_bss_conf *bss_conf, u32 changes);
1968void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1969 __le16 fc, __le32 *tx_flags);
1970
1971irqreturn_t il_isr(int irq, void *data);
1972
1973extern void il_set_bit(struct il_priv *p, u32 r, u32 m);
1974extern void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1975extern bool _il_grab_nic_access(struct il_priv *il);
1976extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1977extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1978extern u32 il_rd_prph(struct il_priv *il, u32 reg);
1979extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1980extern u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1981extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1982
1983static inline void
1984_il_write8(struct il_priv *il, u32 ofs, u8 val)
1985{
1986 writeb(val, il->hw_base + ofs);
1987}
1988#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
1989
1990static inline void
1991_il_wr(struct il_priv *il, u32 ofs, u32 val)
1992{
1993 writel(val, il->hw_base + ofs);
1994}
1995
1996static inline u32
1997_il_rd(struct il_priv *il, u32 ofs)
1998{
1999 return readl(il->hw_base + ofs);
2000}
2001
2002static inline void
2003_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2004{
2005 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2006}
2007
2008static inline void
2009_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2010{
2011 _il_wr(il, reg, _il_rd(il, reg) | mask);
2012}
2013
2014static inline void
2015_il_release_nic_access(struct il_priv *il)
2016{
2017 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2018
2019
2020
2021
2022
2023
2024 mmiowb();
2025}
2026
2027static inline u32
2028il_rd(struct il_priv *il, u32 reg)
2029{
2030 u32 value;
2031 unsigned long reg_flags;
2032
2033 spin_lock_irqsave(&il->reg_lock, reg_flags);
2034 _il_grab_nic_access(il);
2035 value = _il_rd(il, reg);
2036 _il_release_nic_access(il);
2037 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2038 return value;
2039}
2040
2041static inline void
2042il_wr(struct il_priv *il, u32 reg, u32 value)
2043{
2044 unsigned long reg_flags;
2045
2046 spin_lock_irqsave(&il->reg_lock, reg_flags);
2047 if (likely(_il_grab_nic_access(il))) {
2048 _il_wr(il, reg, value);
2049 _il_release_nic_access(il);
2050 }
2051 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2052}
2053
2054static inline u32
2055_il_rd_prph(struct il_priv *il, u32 reg)
2056{
2057 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2058 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2059}
2060
2061static inline void
2062_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2063{
2064 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2065 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2066}
2067
2068static inline void
2069il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2070{
2071 unsigned long reg_flags;
2072
2073 spin_lock_irqsave(&il->reg_lock, reg_flags);
2074 if (likely(_il_grab_nic_access(il))) {
2075 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2076 _il_release_nic_access(il);
2077 }
2078 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2079}
2080
2081static inline void
2082il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2083{
2084 unsigned long reg_flags;
2085
2086 spin_lock_irqsave(&il->reg_lock, reg_flags);
2087 if (likely(_il_grab_nic_access(il))) {
2088 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2089 _il_release_nic_access(il);
2090 }
2091 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2092}
2093
2094static inline void
2095il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2096{
2097 unsigned long reg_flags;
2098 u32 val;
2099
2100 spin_lock_irqsave(&il->reg_lock, reg_flags);
2101 if (likely(_il_grab_nic_access(il))) {
2102 val = _il_rd_prph(il, reg);
2103 _il_wr_prph(il, reg, (val & ~mask));
2104 _il_release_nic_access(il);
2105 }
2106 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2107}
2108
2109#define HW_KEY_DYNAMIC 0
2110#define HW_KEY_DEFAULT 1
2111
2112#define IL_STA_DRIVER_ACTIVE BIT(0)
2113#define IL_STA_UCODE_ACTIVE BIT(1)
2114#define IL_STA_UCODE_INPROGRESS BIT(2)
2115
2116#define IL_STA_LOCAL BIT(3)
2117
2118#define IL_STA_BCAST BIT(4)
2119
2120void il_restore_stations(struct il_priv *il);
2121void il_clear_ucode_stations(struct il_priv *il);
2122void il_dealloc_bcast_stations(struct il_priv *il);
2123int il_get_free_ucode_key_idx(struct il_priv *il);
2124int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2125int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2126 struct ieee80211_sta *sta, u8 *sta_id_r);
2127int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2128int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2129 struct ieee80211_sta *sta);
2130
2131u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2132 struct ieee80211_sta *sta);
2133
2134int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2135 u8 flags, bool init);
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146static inline void
2147il_clear_driver_stations(struct il_priv *il)
2148{
2149 unsigned long flags;
2150
2151 spin_lock_irqsave(&il->sta_lock, flags);
2152 memset(il->stations, 0, sizeof(il->stations));
2153 il->num_stations = 0;
2154 il->ucode_key_table = 0;
2155 spin_unlock_irqrestore(&il->sta_lock, flags);
2156}
2157
2158static inline int
2159il_sta_id(struct ieee80211_sta *sta)
2160{
2161 if (WARN_ON(!sta))
2162 return IL_INVALID_STATION;
2163
2164 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2165}
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178static inline int
2179il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2180{
2181 int sta_id;
2182
2183 if (!sta)
2184 return il->hw_params.bcast_id;
2185
2186 sta_id = il_sta_id(sta);
2187
2188
2189
2190
2191
2192 WARN_ON(sta_id == IL_INVALID_STATION);
2193
2194 return sta_id;
2195}
2196
2197
2198
2199
2200
2201
2202static inline int
2203il_queue_inc_wrap(int idx, int n_bd)
2204{
2205 return ++idx & (n_bd - 1);
2206}
2207
2208
2209
2210
2211
2212
2213static inline int
2214il_queue_dec_wrap(int idx, int n_bd)
2215{
2216 return --idx & (n_bd - 1);
2217}
2218
2219
2220static inline void
2221il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2222{
2223 if (desc->v_addr)
2224 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2225 desc->p_addr);
2226 desc->v_addr = NULL;
2227 desc->len = 0;
2228}
2229
2230static inline int
2231il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2232{
2233 if (!desc->len) {
2234 desc->v_addr = NULL;
2235 return -EINVAL;
2236 }
2237
2238 desc->v_addr =
2239 dma_alloc_coherent(&pci_dev->dev, desc->len, &desc->p_addr,
2240 GFP_KERNEL);
2241 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2242}
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255static inline void
2256il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2257{
2258 BUG_ON(ac > 3);
2259 BUG_ON(hwq > 31);
2260
2261 txq->swq_id = (hwq << 2) | ac;
2262}
2263
2264static inline void
2265il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2266{
2267 u8 queue = txq->swq_id;
2268 u8 ac = queue & 3;
2269 u8 hwq = (queue >> 2) & 0x1f;
2270
2271 if (test_and_clear_bit(hwq, il->queue_stopped))
2272 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2273 ieee80211_wake_queue(il->hw, ac);
2274}
2275
2276static inline void
2277il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2278{
2279 u8 queue = txq->swq_id;
2280 u8 ac = queue & 3;
2281 u8 hwq = (queue >> 2) & 0x1f;
2282
2283 if (!test_and_set_bit(hwq, il->queue_stopped))
2284 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2285 ieee80211_stop_queue(il->hw, ac);
2286}
2287
2288#ifdef ieee80211_stop_queue
2289#undef ieee80211_stop_queue
2290#endif
2291
2292#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2293
2294#ifdef ieee80211_wake_queue
2295#undef ieee80211_wake_queue
2296#endif
2297
2298#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2299
2300static inline void
2301il_disable_interrupts(struct il_priv *il)
2302{
2303 clear_bit(S_INT_ENABLED, &il->status);
2304
2305
2306 _il_wr(il, CSR_INT_MASK, 0x00000000);
2307
2308
2309
2310 _il_wr(il, CSR_INT, 0xffffffff);
2311 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2312}
2313
2314static inline void
2315il_enable_rfkill_int(struct il_priv *il)
2316{
2317 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2318}
2319
2320static inline void
2321il_enable_interrupts(struct il_priv *il)
2322{
2323 set_bit(S_INT_ENABLED, &il->status);
2324 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2325}
2326
2327
2328
2329
2330
2331
2332static inline u32
2333il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2334{
2335 return (1 << tsf_bits) - 1;
2336}
2337
2338
2339
2340
2341
2342
2343static inline u32
2344il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2345{
2346 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2347}
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359struct il_rb_status {
2360 __le16 closed_rb_num;
2361 __le16 closed_fr_num;
2362 __le16 finished_rb_num;
2363 __le16 finished_fr_nam;
2364 __le32 __unused;
2365} __packed;
2366
2367#define TFD_QUEUE_SIZE_MAX 256
2368#define TFD_QUEUE_SIZE_BC_DUP 64
2369#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2370#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2371#define IL_NUM_OF_TBS 20
2372
2373static inline u8
2374il_get_dma_hi_addr(dma_addr_t addr)
2375{
2376 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2377}
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389struct il_tfd_tb {
2390 __le32 lo;
2391 __le16 hi_n_len;
2392} __packed;
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422struct il_tfd {
2423 u8 __reserved1[3];
2424 u8 num_tbs;
2425 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2426 __le32 __pad;
2427} __packed;
2428
2429#define PCI_CFG_RETRY_TIMEOUT 0x041
2430
2431struct il_rate_info {
2432 u8 plcp;
2433 u8 plcp_siso;
2434 u8 plcp_mimo2;
2435 u8 ieee;
2436 u8 prev_ieee;
2437 u8 next_ieee;
2438 u8 prev_rs;
2439 u8 next_rs;
2440 u8 prev_rs_tgg;
2441 u8 next_rs_tgg;
2442};
2443
2444struct il3945_rate_info {
2445 u8 plcp;
2446 u8 ieee;
2447 u8 prev_ieee;
2448 u8 next_ieee;
2449 u8 prev_rs;
2450 u8 next_rs;
2451 u8 prev_rs_tgg;
2452 u8 next_rs_tgg;
2453 u8 table_rs_idx;
2454 u8 prev_table_rs;
2455};
2456
2457
2458
2459
2460
2461enum {
2462 RATE_1M_IDX = 0,
2463 RATE_2M_IDX,
2464 RATE_5M_IDX,
2465 RATE_11M_IDX,
2466 RATE_6M_IDX,
2467 RATE_9M_IDX,
2468 RATE_12M_IDX,
2469 RATE_18M_IDX,
2470 RATE_24M_IDX,
2471 RATE_36M_IDX,
2472 RATE_48M_IDX,
2473 RATE_54M_IDX,
2474 RATE_60M_IDX,
2475 RATE_COUNT,
2476 RATE_COUNT_LEGACY = RATE_COUNT - 1,
2477 RATE_COUNT_3945 = RATE_COUNT - 1,
2478 RATE_INVM_IDX = RATE_COUNT,
2479 RATE_INVALID = RATE_COUNT,
2480};
2481
2482enum {
2483 RATE_6M_IDX_TBL = 0,
2484 RATE_9M_IDX_TBL,
2485 RATE_12M_IDX_TBL,
2486 RATE_18M_IDX_TBL,
2487 RATE_24M_IDX_TBL,
2488 RATE_36M_IDX_TBL,
2489 RATE_48M_IDX_TBL,
2490 RATE_54M_IDX_TBL,
2491 RATE_1M_IDX_TBL,
2492 RATE_2M_IDX_TBL,
2493 RATE_5M_IDX_TBL,
2494 RATE_11M_IDX_TBL,
2495 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2496};
2497
2498enum {
2499 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2500 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2501 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2502 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2503 IL_LAST_CCK_RATE = RATE_11M_IDX,
2504};
2505
2506
2507#define RATE_6M_MASK (1 << RATE_6M_IDX)
2508#define RATE_9M_MASK (1 << RATE_9M_IDX)
2509#define RATE_12M_MASK (1 << RATE_12M_IDX)
2510#define RATE_18M_MASK (1 << RATE_18M_IDX)
2511#define RATE_24M_MASK (1 << RATE_24M_IDX)
2512#define RATE_36M_MASK (1 << RATE_36M_IDX)
2513#define RATE_48M_MASK (1 << RATE_48M_IDX)
2514#define RATE_54M_MASK (1 << RATE_54M_IDX)
2515#define RATE_60M_MASK (1 << RATE_60M_IDX)
2516#define RATE_1M_MASK (1 << RATE_1M_IDX)
2517#define RATE_2M_MASK (1 << RATE_2M_IDX)
2518#define RATE_5M_MASK (1 << RATE_5M_IDX)
2519#define RATE_11M_MASK (1 << RATE_11M_IDX)
2520
2521
2522enum {
2523 RATE_6M_PLCP = 13,
2524 RATE_9M_PLCP = 15,
2525 RATE_12M_PLCP = 5,
2526 RATE_18M_PLCP = 7,
2527 RATE_24M_PLCP = 9,
2528 RATE_36M_PLCP = 11,
2529 RATE_48M_PLCP = 1,
2530 RATE_54M_PLCP = 3,
2531 RATE_60M_PLCP = 3,
2532 RATE_1M_PLCP = 10,
2533 RATE_2M_PLCP = 20,
2534 RATE_5M_PLCP = 55,
2535 RATE_11M_PLCP = 110,
2536
2537};
2538
2539
2540enum {
2541 RATE_SISO_6M_PLCP = 0,
2542 RATE_SISO_12M_PLCP = 1,
2543 RATE_SISO_18M_PLCP = 2,
2544 RATE_SISO_24M_PLCP = 3,
2545 RATE_SISO_36M_PLCP = 4,
2546 RATE_SISO_48M_PLCP = 5,
2547 RATE_SISO_54M_PLCP = 6,
2548 RATE_SISO_60M_PLCP = 7,
2549 RATE_MIMO2_6M_PLCP = 0x8,
2550 RATE_MIMO2_12M_PLCP = 0x9,
2551 RATE_MIMO2_18M_PLCP = 0xa,
2552 RATE_MIMO2_24M_PLCP = 0xb,
2553 RATE_MIMO2_36M_PLCP = 0xc,
2554 RATE_MIMO2_48M_PLCP = 0xd,
2555 RATE_MIMO2_54M_PLCP = 0xe,
2556 RATE_MIMO2_60M_PLCP = 0xf,
2557 RATE_SISO_INVM_PLCP,
2558 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2559};
2560
2561
2562enum {
2563 RATE_6M_IEEE = 12,
2564 RATE_9M_IEEE = 18,
2565 RATE_12M_IEEE = 24,
2566 RATE_18M_IEEE = 36,
2567 RATE_24M_IEEE = 48,
2568 RATE_36M_IEEE = 72,
2569 RATE_48M_IEEE = 96,
2570 RATE_54M_IEEE = 108,
2571 RATE_60M_IEEE = 120,
2572 RATE_1M_IEEE = 2,
2573 RATE_2M_IEEE = 4,
2574 RATE_5M_IEEE = 11,
2575 RATE_11M_IEEE = 22,
2576};
2577
2578#define IL_CCK_BASIC_RATES_MASK \
2579 (RATE_1M_MASK | \
2580 RATE_2M_MASK)
2581
2582#define IL_CCK_RATES_MASK \
2583 (IL_CCK_BASIC_RATES_MASK | \
2584 RATE_5M_MASK | \
2585 RATE_11M_MASK)
2586
2587#define IL_OFDM_BASIC_RATES_MASK \
2588 (RATE_6M_MASK | \
2589 RATE_12M_MASK | \
2590 RATE_24M_MASK)
2591
2592#define IL_OFDM_RATES_MASK \
2593 (IL_OFDM_BASIC_RATES_MASK | \
2594 RATE_9M_MASK | \
2595 RATE_18M_MASK | \
2596 RATE_36M_MASK | \
2597 RATE_48M_MASK | \
2598 RATE_54M_MASK)
2599
2600#define IL_BASIC_RATES_MASK \
2601 (IL_OFDM_BASIC_RATES_MASK | \
2602 IL_CCK_BASIC_RATES_MASK)
2603
2604#define RATES_MASK ((1 << RATE_COUNT) - 1)
2605#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2606
2607#define IL_INVALID_VALUE -1
2608
2609#define IL_MIN_RSSI_VAL -100
2610#define IL_MAX_RSSI_VAL 0
2611
2612
2613
2614#define IL_LEGACY_FAILURE_LIMIT 160
2615#define IL_LEGACY_SUCCESS_LIMIT 480
2616#define IL_LEGACY_TBL_COUNT 160
2617
2618#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2619#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2620#define IL_NONE_LEGACY_TBL_COUNT 1500
2621
2622
2623#define IL_RS_GOOD_RATIO 12800
2624#define RATE_SCALE_SWITCH 10880
2625#define RATE_HIGH_TH 10880
2626#define RATE_INCREASE_TH 6400
2627#define RATE_DECREASE_TH 1920
2628
2629
2630#define IL_LEGACY_SWITCH_ANTENNA1 0
2631#define IL_LEGACY_SWITCH_ANTENNA2 1
2632#define IL_LEGACY_SWITCH_SISO 2
2633#define IL_LEGACY_SWITCH_MIMO2_AB 3
2634#define IL_LEGACY_SWITCH_MIMO2_AC 4
2635#define IL_LEGACY_SWITCH_MIMO2_BC 5
2636
2637
2638#define IL_SISO_SWITCH_ANTENNA1 0
2639#define IL_SISO_SWITCH_ANTENNA2 1
2640#define IL_SISO_SWITCH_MIMO2_AB 2
2641#define IL_SISO_SWITCH_MIMO2_AC 3
2642#define IL_SISO_SWITCH_MIMO2_BC 4
2643#define IL_SISO_SWITCH_GI 5
2644
2645
2646#define IL_MIMO2_SWITCH_ANTENNA1 0
2647#define IL_MIMO2_SWITCH_ANTENNA2 1
2648#define IL_MIMO2_SWITCH_SISO_A 2
2649#define IL_MIMO2_SWITCH_SISO_B 3
2650#define IL_MIMO2_SWITCH_SISO_C 4
2651#define IL_MIMO2_SWITCH_GI 5
2652
2653#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2654
2655#define IL_ACTION_LIMIT 3
2656
2657#define LQ_SIZE 2
2658
2659
2660#define IL_AGG_TPT_THREHOLD 0
2661#define IL_AGG_LOAD_THRESHOLD 10
2662#define IL_AGG_ALL_TID 0xff
2663#define TID_QUEUE_CELL_SPACING 50
2664#define TID_QUEUE_MAX_SIZE 20
2665#define TID_ROUND_VALUE 5
2666#define TID_MAX_LOAD_COUNT 8
2667
2668#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2669#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2670
2671extern const struct il_rate_info il_rates[RATE_COUNT];
2672
2673enum il_table_type {
2674 LQ_NONE,
2675 LQ_G,
2676 LQ_A,
2677 LQ_SISO,
2678 LQ_MIMO2,
2679 LQ_MAX,
2680};
2681
2682#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2683#define is_siso(tbl) ((tbl) == LQ_SISO)
2684#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2685#define is_mimo(tbl) (is_mimo2(tbl))
2686#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2687#define is_a_band(tbl) ((tbl) == LQ_A)
2688#define is_g_and(tbl) ((tbl) == LQ_G)
2689
2690#define ANT_NONE 0x0
2691#define ANT_A BIT(0)
2692#define ANT_B BIT(1)
2693#define ANT_AB (ANT_A | ANT_B)
2694#define ANT_C BIT(2)
2695#define ANT_AC (ANT_A | ANT_C)
2696#define ANT_BC (ANT_B | ANT_C)
2697#define ANT_ABC (ANT_AB | ANT_C)
2698
2699#define IL_MAX_MCS_DISPLAY_SIZE 12
2700
2701struct il_rate_mcs_info {
2702 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2703 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2704};
2705
2706
2707
2708
2709struct il_rate_scale_data {
2710 u64 data;
2711 s32 success_counter;
2712 s32 success_ratio;
2713 s32 counter;
2714 s32 average_tpt;
2715 unsigned long stamp;
2716};
2717
2718
2719
2720
2721
2722
2723
2724struct il_scale_tbl_info {
2725 enum il_table_type lq_type;
2726 u8 ant_type;
2727 u8 is_SGI;
2728 u8 is_ht40;
2729 u8 is_dup;
2730 u8 action;
2731 u8 max_search;
2732 s32 *expected_tpt;
2733 u32 current_rate;
2734 struct il_rate_scale_data win[RATE_COUNT];
2735};
2736
2737struct il_traffic_load {
2738 unsigned long time_stamp;
2739 u32 packet_count[TID_QUEUE_MAX_SIZE];
2740
2741 u32 total;
2742
2743 u8 queue_count;
2744
2745 u8 head;
2746};
2747
2748
2749
2750
2751
2752
2753struct il_lq_sta {
2754 u8 active_tbl;
2755 u8 enable_counter;
2756 u8 stay_in_tbl;
2757 u8 search_better_tbl;
2758 s32 last_tpt;
2759
2760
2761 u32 table_count_limit;
2762 u32 max_failure_limit;
2763 u32 max_success_limit;
2764 u32 table_count;
2765 u32 total_failed;
2766 u32 total_success;
2767 u64 flush_timer;
2768
2769 u8 action_counter;
2770 u8 is_green;
2771 u8 is_dup;
2772 enum ieee80211_band band;
2773
2774
2775 u32 supp_rates;
2776 u16 active_legacy_rate;
2777 u16 active_siso_rate;
2778 u16 active_mimo2_rate;
2779 s8 max_rate_idx;
2780 u8 missed_rate_counter;
2781
2782 struct il_link_quality_cmd lq;
2783 struct il_scale_tbl_info lq_info[LQ_SIZE];
2784 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2785 u8 tx_agg_tid_en;
2786#ifdef CONFIG_MAC80211_DEBUGFS
2787 struct dentry *rs_sta_dbgfs_scale_table_file;
2788 struct dentry *rs_sta_dbgfs_stats_table_file;
2789 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2790 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2791 u32 dbg_fixed_rate;
2792#endif
2793 struct il_priv *drv;
2794
2795
2796 int last_txrate_idx;
2797
2798 u32 last_rate_n_flags;
2799
2800 u8 is_agg;
2801};
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813struct il_station_priv {
2814 struct il_station_priv_common common;
2815 struct il_lq_sta lq_sta;
2816 atomic_t pending_frames;
2817 bool client;
2818 bool asleep;
2819};
2820
2821static inline u8
2822il4965_num_of_ant(u8 m)
2823{
2824 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2825}
2826
2827static inline u8
2828il4965_first_antenna(u8 mask)
2829{
2830 if (mask & ANT_A)
2831 return ANT_A;
2832 if (mask & ANT_B)
2833 return ANT_B;
2834 return ANT_C;
2835}
2836
2837
2838
2839
2840
2841
2842
2843extern void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2844
2845
2846extern void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2847 u8 sta_id);
2848extern void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2849 u8 sta_id);
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861extern int il4965_rate_control_register(void);
2862extern int il3945_rate_control_register(void);
2863
2864
2865
2866
2867
2868
2869
2870extern void il4965_rate_control_unregister(void);
2871extern void il3945_rate_control_unregister(void);
2872
2873extern int il_power_update_mode(struct il_priv *il, bool force);
2874extern void il_power_initialize(struct il_priv *il);
2875
2876extern u32 il_debug_level;
2877
2878#ifdef CONFIG_IWLEGACY_DEBUG
2879
2880
2881
2882
2883
2884
2885
2886static inline u32
2887il_get_debug_level(struct il_priv *il)
2888{
2889 if (il->debug_level)
2890 return il->debug_level;
2891 else
2892 return il_debug_level;
2893}
2894#else
2895static inline u32
2896il_get_debug_level(struct il_priv *il)
2897{
2898 return il_debug_level;
2899}
2900#endif
2901
2902#define il_print_hex_error(il, p, len) \
2903do { \
2904 print_hex_dump(KERN_ERR, "iwl data: ", \
2905 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2906} while (0)
2907
2908#ifdef CONFIG_IWLEGACY_DEBUG
2909#define IL_DBG(level, fmt, args...) \
2910do { \
2911 if (il_get_debug_level(il) & level) \
2912 dev_err(&il->hw->wiphy->dev, "%c %s " fmt, \
2913 in_interrupt() ? 'I' : 'U', __func__ , ##args); \
2914} while (0)
2915
2916#define il_print_hex_dump(il, level, p, len) \
2917do { \
2918 if (il_get_debug_level(il) & level) \
2919 print_hex_dump(KERN_DEBUG, "iwl data: ", \
2920 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2921} while (0)
2922
2923#else
2924#define IL_DBG(level, fmt, args...)
2925static inline void
2926il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2927{
2928}
2929#endif
2930
2931#ifdef CONFIG_IWLEGACY_DEBUGFS
2932int il_dbgfs_register(struct il_priv *il, const char *name);
2933void il_dbgfs_unregister(struct il_priv *il);
2934#else
2935static inline int
2936il_dbgfs_register(struct il_priv *il, const char *name)
2937{
2938 return 0;
2939}
2940
2941static inline void
2942il_dbgfs_unregister(struct il_priv *il)
2943{
2944}
2945#endif
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971#define IL_DL_INFO (1 << 0)
2972#define IL_DL_MAC80211 (1 << 1)
2973#define IL_DL_HCMD (1 << 2)
2974#define IL_DL_STATE (1 << 3)
2975
2976#define IL_DL_MACDUMP (1 << 4)
2977#define IL_DL_HCMD_DUMP (1 << 5)
2978#define IL_DL_EEPROM (1 << 6)
2979#define IL_DL_RADIO (1 << 7)
2980
2981#define IL_DL_POWER (1 << 8)
2982#define IL_DL_TEMP (1 << 9)
2983#define IL_DL_NOTIF (1 << 10)
2984#define IL_DL_SCAN (1 << 11)
2985
2986#define IL_DL_ASSOC (1 << 12)
2987#define IL_DL_DROP (1 << 13)
2988#define IL_DL_TXPOWER (1 << 14)
2989#define IL_DL_AP (1 << 15)
2990
2991#define IL_DL_FW (1 << 16)
2992#define IL_DL_RF_KILL (1 << 17)
2993#define IL_DL_FW_ERRORS (1 << 18)
2994#define IL_DL_LED (1 << 19)
2995
2996#define IL_DL_RATE (1 << 20)
2997#define IL_DL_CALIB (1 << 21)
2998#define IL_DL_WEP (1 << 22)
2999#define IL_DL_TX (1 << 23)
3000
3001#define IL_DL_RX (1 << 24)
3002#define IL_DL_ISR (1 << 25)
3003#define IL_DL_HT (1 << 26)
3004
3005#define IL_DL_11H (1 << 28)
3006#define IL_DL_STATS (1 << 29)
3007#define IL_DL_TX_REPLY (1 << 30)
3008#define IL_DL_QOS (1 << 31)
3009
3010#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3011#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3012#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3013#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3014#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3015#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3016#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3017#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3018#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3019#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3020#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3021#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3022#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3023#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3024#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3025#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3026#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3027#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3028#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3029#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3030#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3031#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3032#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3033#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3034#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3035#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3036#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3037#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3038#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3039
3040#endif
3041