1/* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the 17 Free Software Foundation, Inc., 18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21/* 22 Module: rt73usb 23 Abstract: Data structures and registers for the rt73usb module. 24 Supported chipsets: rt2571W & rt2671. 25 */ 26 27#ifndef RT73USB_H 28#define RT73USB_H 29 30/* 31 * RF chip defines. 32 */ 33#define RF5226 0x0001 34#define RF2528 0x0002 35#define RF5225 0x0003 36#define RF2527 0x0004 37 38/* 39 * Signal information. 40 * Default offset is required for RSSI <-> dBm conversion. 41 */ 42#define DEFAULT_RSSI_OFFSET 120 43 44/* 45 * Register layout information. 46 */ 47#define CSR_REG_BASE 0x3000 48#define CSR_REG_SIZE 0x04b0 49#define EEPROM_BASE 0x0000 50#define EEPROM_SIZE 0x0100 51#define BBP_BASE 0x0000 52#define BBP_SIZE 0x0080 53#define RF_BASE 0x0004 54#define RF_SIZE 0x0010 55 56/* 57 * Number of TX queues. 58 */ 59#define NUM_TX_QUEUES 4 60 61/* 62 * USB registers. 63 */ 64 65/* 66 * MCU_LEDCS: LED control for MCU Mailbox. 67 */ 68#define MCU_LEDCS_LED_MODE FIELD16(0x001f) 69#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020) 70#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040) 71#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080) 72#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100) 73#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200) 74#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400) 75#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800) 76#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000) 77#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000) 78#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000) 79#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000) 80 81/* 82 * 8051 firmware image. 83 */ 84#define FIRMWARE_RT2571 "rt73.bin" 85#define FIRMWARE_IMAGE_BASE 0x0800 86 87/* 88 * Security key table memory. 89 * 16 entries 32-byte for shared key table 90 * 64 entries 32-byte for pairwise key table 91 * 64 entries 8-byte for pairwise ta key table 92 */ 93#define SHARED_KEY_TABLE_BASE 0x1000 94#define PAIRWISE_KEY_TABLE_BASE 0x1200 95#define PAIRWISE_TA_TABLE_BASE 0x1a00 96 97#define SHARED_KEY_ENTRY(__idx) \ 98 ( SHARED_KEY_TABLE_BASE + \ 99 ((__idx) * sizeof(struct hw_key_entry)) ) 100#define PAIRWISE_KEY_ENTRY(__idx) \ 101 ( PAIRWISE_KEY_TABLE_BASE + \ 102 ((__idx) * sizeof(struct hw_key_entry)) ) 103#define PAIRWISE_TA_ENTRY(__idx) \ 104 ( PAIRWISE_TA_TABLE_BASE + \ 105 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) ) 106 107struct hw_key_entry { 108 u8 key[16]; 109 u8 tx_mic[8]; 110 u8 rx_mic[8]; 111} __packed; 112 113struct hw_pairwise_ta_entry { 114 u8 address[6]; 115 u8 cipher; 116 u8 reserved; 117} __packed; 118 119/* 120 * Since NULL frame won't be that long (256 byte), 121 * We steal 16 tail bytes to save debugging settings. 122 */ 123#define HW_DEBUG_SETTING_BASE 0x2bf0 124 125/* 126 * On-chip BEACON frame space. 127 */ 128#define HW_BEACON_BASE0 0x2400 129#define HW_BEACON_BASE1 0x2500 130#define HW_BEACON_BASE2 0x2600 131#define HW_BEACON_BASE3 0x2700 132 133#define HW_BEACON_OFFSET(__index) \ 134 ( HW_BEACON_BASE0 + (__index * 0x0100) ) 135 136/* 137 * MAC Control/Status Registers(CSR). 138 * Some values are set in TU, whereas 1 TU == 1024 us. 139 */ 140 141/* 142 * MAC_CSR0: ASIC revision number. 143 */ 144#define MAC_CSR0 0x3000 145#define MAC_CSR0_REVISION FIELD32(0x0000000f) 146#define MAC_CSR0_CHIPSET FIELD32(0x000ffff0) 147 148/* 149 * MAC_CSR1: System control register. 150 * SOFT_RESET: Software reset bit, 1: reset, 0: normal. 151 * BBP_RESET: Hardware reset BBP. 152 * HOST_READY: Host is ready after initialization, 1: ready. 153 */ 154#define MAC_CSR1 0x3004 155#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001) 156#define MAC_CSR1_BBP_RESET FIELD32(0x00000002) 157#define MAC_CSR1_HOST_READY FIELD32(0x00000004) 158 159/* 160 * MAC_CSR2: STA MAC register 0. 161 */ 162#define MAC_CSR2 0x3008 163#define MAC_CSR2_BYTE0 FIELD32(0x000000ff) 164#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00) 165#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000) 166#define MAC_CSR2_BYTE3 FIELD32(0xff000000) 167 168/* 169 * MAC_CSR3: STA MAC register 1. 170 * UNICAST_TO_ME_MASK: 171 * Used to mask off bits from byte 5 of the MAC address 172 * to determine the UNICAST_TO_ME bit for RX frames. 173 * The full mask is complemented by BSS_ID_MASK: 174 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK 175 */ 176#define MAC_CSR3 0x300c 177#define MAC_CSR3_BYTE4 FIELD32(0x000000ff) 178#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00) 179#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) 180 181/* 182 * MAC_CSR4: BSSID register 0. 183 */ 184#define MAC_CSR4 0x3010 185#define MAC_CSR4_BYTE0 FIELD32(0x000000ff) 186#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00) 187#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000) 188#define MAC_CSR4_BYTE3 FIELD32(0xff000000) 189 190/* 191 * MAC_CSR5: BSSID register 1. 192 * BSS_ID_MASK: 193 * This mask is used to mask off bits 0 and 1 of byte 5 of the 194 * BSSID. This will make sure that those bits will be ignored 195 * when determining the MY_BSS of RX frames. 196 * 0: 1-BSSID mode (BSS index = 0) 197 * 1: 2-BSSID mode (BSS index: Byte5, bit 0) 198 * 2: 2-BSSID mode (BSS index: byte5, bit 1) 199 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1) 200 */ 201#define MAC_CSR5 0x3014 202#define MAC_CSR5_BYTE4 FIELD32(0x000000ff) 203#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00) 204#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000) 205 206/* 207 * MAC_CSR6: Maximum frame length register. 208 */ 209#define MAC_CSR6 0x3018 210#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff) 211 212/* 213 * MAC_CSR7: Reserved 214 */ 215#define MAC_CSR7 0x301c 216 217/* 218 * MAC_CSR8: SIFS/EIFS register. 219 * All units are in US. 220 */ 221#define MAC_CSR8 0x3020 222#define MAC_CSR8_SIFS FIELD32(0x000000ff) 223#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00) 224#define MAC_CSR8_EIFS FIELD32(0xffff0000) 225 226/* 227 * MAC_CSR9: Back-Off control register. 228 * SLOT_TIME: Slot time, default is 20us for 802.11BG. 229 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1). 230 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1). 231 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD. 232 */ 233#define MAC_CSR9 0x3024 234#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff) 235#define MAC_CSR9_CWMIN FIELD32(0x00000f00) 236#define MAC_CSR9_CWMAX FIELD32(0x0000f000) 237#define MAC_CSR9_CW_SELECT FIELD32(0x00010000) 238 239/* 240 * MAC_CSR10: Power state configuration. 241 */ 242#define MAC_CSR10 0x3028 243 244/* 245 * MAC_CSR11: Power saving transition time register. 246 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU. 247 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. 248 * WAKEUP_LATENCY: In unit of TU. 249 */ 250#define MAC_CSR11 0x302c 251#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff) 252#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00) 253#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000) 254#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000) 255 256/* 257 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1). 258 * CURRENT_STATE: 0:sleep, 1:awake. 259 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP. 260 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake. 261 */ 262#define MAC_CSR12 0x3030 263#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001) 264#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002) 265#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004) 266#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008) 267 268/* 269 * MAC_CSR13: GPIO. 270 * MAC_CSR13_VALx: GPIO value 271 * MAC_CSR13_DIRx: GPIO direction: 0 = input; 1 = output 272 */ 273#define MAC_CSR13 0x3034 274#define MAC_CSR13_VAL0 FIELD32(0x00000001) 275#define MAC_CSR13_VAL1 FIELD32(0x00000002) 276#define MAC_CSR13_VAL2 FIELD32(0x00000004) 277#define MAC_CSR13_VAL3 FIELD32(0x00000008) 278#define MAC_CSR13_VAL4 FIELD32(0x00000010) 279#define MAC_CSR13_VAL5 FIELD32(0x00000020) 280#define MAC_CSR13_VAL6 FIELD32(0x00000040) 281#define MAC_CSR13_VAL7 FIELD32(0x00000080) 282#define MAC_CSR13_DIR0 FIELD32(0x00000100) 283#define MAC_CSR13_DIR1 FIELD32(0x00000200) 284#define MAC_CSR13_DIR2 FIELD32(0x00000400) 285#define MAC_CSR13_DIR3 FIELD32(0x00000800) 286#define MAC_CSR13_DIR4 FIELD32(0x00001000) 287#define MAC_CSR13_DIR5 FIELD32(0x00002000) 288#define MAC_CSR13_DIR6 FIELD32(0x00004000) 289#define MAC_CSR13_DIR7 FIELD32(0x00008000) 290 291/* 292 * MAC_CSR14: LED control register. 293 * ON_PERIOD: On period, default 70ms. 294 * OFF_PERIOD: Off period, default 30ms. 295 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON. 296 * SW_LED: s/w LED, 1: ON, 0: OFF. 297 * HW_LED_POLARITY: 0: active low, 1: active high. 298 */ 299#define MAC_CSR14 0x3038 300#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff) 301#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00) 302#define MAC_CSR14_HW_LED FIELD32(0x00010000) 303#define MAC_CSR14_SW_LED FIELD32(0x00020000) 304#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000) 305#define MAC_CSR14_SW_LED2 FIELD32(0x00080000) 306 307/* 308 * MAC_CSR15: NAV control. 309 */ 310#define MAC_CSR15 0x303c 311 312/* 313 * TXRX control registers. 314 * Some values are set in TU, whereas 1 TU == 1024 us. 315 */ 316 317/* 318 * TXRX_CSR0: TX/RX configuration register. 319 * TSF_OFFSET: Default is 24. 320 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame. 321 * DISABLE_RX: Disable Rx engine. 322 * DROP_CRC: Drop CRC error. 323 * DROP_PHYSICAL: Drop physical error. 324 * DROP_CONTROL: Drop control frame. 325 * DROP_NOT_TO_ME: Drop not to me unicast frame. 326 * DROP_TO_DS: Drop fram ToDs bit is true. 327 * DROP_VERSION_ERROR: Drop version error frame. 328 * DROP_MULTICAST: Drop multicast frames. 329 * DROP_BORADCAST: Drop broadcast frames. 330 * DROP_ACK_CTS: Drop received ACK and CTS. 331 */ 332#define TXRX_CSR0 0x3040 333#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff) 334#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00) 335#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000) 336#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000) 337#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000) 338#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000) 339#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000) 340#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000) 341#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000) 342#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000) 343#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000) 344#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000) 345#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000) 346#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000) 347 348/* 349 * TXRX_CSR1 350 */ 351#define TXRX_CSR1 0x3044 352#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f) 353#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080) 354#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00) 355#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000) 356#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000) 357#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000) 358#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000) 359#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000) 360 361/* 362 * TXRX_CSR2 363 */ 364#define TXRX_CSR2 0x3048 365#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f) 366#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080) 367#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00) 368#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000) 369#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000) 370#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000) 371#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000) 372#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000) 373 374/* 375 * TXRX_CSR3 376 */ 377#define TXRX_CSR3 0x304c 378#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f) 379#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080) 380#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00) 381#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000) 382#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000) 383#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000) 384#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000) 385#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000) 386 387/* 388 * TXRX_CSR4: Auto-Responder/Tx-retry register. 389 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble. 390 * OFDM_TX_RATE_DOWN: 1:enable. 391 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step. 392 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M. 393 */ 394#define TXRX_CSR4 0x3050 395#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff) 396#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700) 397#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000) 398#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000) 399#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000) 400#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000) 401#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000) 402#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000) 403#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000) 404#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000) 405 406/* 407 * TXRX_CSR5 408 */ 409#define TXRX_CSR5 0x3054 410 411/* 412 * TXRX_CSR6: ACK/CTS payload consumed time 413 */ 414#define TXRX_CSR6 0x3058 415 416/* 417 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. 418 */ 419#define TXRX_CSR7 0x305c 420#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff) 421#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00) 422#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000) 423#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000) 424 425/* 426 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. 427 */ 428#define TXRX_CSR8 0x3060 429#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff) 430#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00) 431#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000) 432#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000) 433 434/* 435 * TXRX_CSR9: Synchronization control register. 436 * BEACON_INTERVAL: In unit of 1/16 TU. 437 * TSF_TICKING: Enable TSF auto counting. 438 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. 439 * BEACON_GEN: Enable beacon generator. 440 */ 441#define TXRX_CSR9 0x3064 442#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff) 443#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000) 444#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000) 445#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000) 446#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000) 447#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000) 448 449/* 450 * TXRX_CSR10: BEACON alignment. 451 */ 452#define TXRX_CSR10 0x3068 453 454/* 455 * TXRX_CSR11: AES mask. 456 */ 457#define TXRX_CSR11 0x306c 458 459/* 460 * TXRX_CSR12: TSF low 32. 461 */ 462#define TXRX_CSR12 0x3070 463#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff) 464 465/* 466 * TXRX_CSR13: TSF high 32. 467 */ 468#define TXRX_CSR13 0x3074 469#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff) 470 471/* 472 * TXRX_CSR14: TBTT timer. 473 */ 474#define TXRX_CSR14 0x3078 475 476/* 477 * TXRX_CSR15: TKIP MIC priority byte "AND" mask. 478 */ 479#define TXRX_CSR15 0x307c 480 481/* 482 * PHY control registers. 483 * Some values are set in TU, whereas 1 TU == 1024 us. 484 */ 485 486/* 487 * PHY_CSR0: RF/PS control. 488 */ 489#define PHY_CSR0 0x3080 490#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000) 491#define PHY_CSR0_PA_PE_A FIELD32(0x00020000) 492 493/* 494 * PHY_CSR1 495 */ 496#define PHY_CSR1 0x3084 497#define PHY_CSR1_RF_RPI FIELD32(0x00010000) 498 499/* 500 * PHY_CSR2: Pre-TX BBP control. 501 */ 502#define PHY_CSR2 0x3088 503 504/* 505 * PHY_CSR3: BBP serial control register. 506 * VALUE: Register value to program into BBP. 507 * REG_NUM: Selected BBP register. 508 * READ_CONTROL: 0: Write BBP, 1: Read BBP. 509 * BUSY: 1: ASIC is busy execute BBP programming. 510 */ 511#define PHY_CSR3 0x308c 512#define PHY_CSR3_VALUE FIELD32(0x000000ff) 513#define PHY_CSR3_REGNUM FIELD32(0x00007f00) 514#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000) 515#define PHY_CSR3_BUSY FIELD32(0x00010000) 516 517/* 518 * PHY_CSR4: RF serial control register 519 * VALUE: Register value (include register id) serial out to RF/IF chip. 520 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22). 521 * IF_SELECT: 1: select IF to program, 0: select RF to program. 522 * PLL_LD: RF PLL_LD status. 523 * BUSY: 1: ASIC is busy execute RF programming. 524 */ 525#define PHY_CSR4 0x3090 526#define PHY_CSR4_VALUE FIELD32(0x00ffffff) 527#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000) 528#define PHY_CSR4_IF_SELECT FIELD32(0x20000000) 529#define PHY_CSR4_PLL_LD FIELD32(0x40000000) 530#define PHY_CSR4_BUSY FIELD32(0x80000000) 531 532/* 533 * PHY_CSR5: RX to TX signal switch timing control. 534 */ 535#define PHY_CSR5 0x3094 536#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004) 537 538/* 539 * PHY_CSR6: TX to RX signal timing control. 540 */ 541#define PHY_CSR6 0x3098 542#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004) 543 544/* 545 * PHY_CSR7: TX DAC switching timing control. 546 */ 547#define PHY_CSR7 0x309c 548 549/* 550 * Security control register. 551 */ 552 553/* 554 * SEC_CSR0: Shared key table control. 555 */ 556#define SEC_CSR0 0x30a0 557#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001) 558#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002) 559#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004) 560#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008) 561#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010) 562#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020) 563#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040) 564#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080) 565#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100) 566#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200) 567#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400) 568#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800) 569#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000) 570#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000) 571#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000) 572#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000) 573 574/* 575 * SEC_CSR1: Shared key table security mode register. 576 */ 577#define SEC_CSR1 0x30a4 578#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007) 579#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070) 580#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700) 581#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000) 582#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000) 583#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000) 584#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000) 585#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000) 586 587/* 588 * Pairwise key table valid bitmap registers. 589 * SEC_CSR2: pairwise key table valid bitmap 0. 590 * SEC_CSR3: pairwise key table valid bitmap 1. 591 */ 592#define SEC_CSR2 0x30a8 593#define SEC_CSR3 0x30ac 594 595/* 596 * SEC_CSR4: Pairwise key table lookup control. 597 */ 598#define SEC_CSR4 0x30b0 599#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001) 600#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002) 601#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004) 602#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008) 603 604/* 605 * SEC_CSR5: shared key table security mode register. 606 */ 607#define SEC_CSR5 0x30b4 608#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007) 609#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070) 610#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700) 611#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000) 612#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000) 613#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000) 614#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000) 615#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000) 616 617/* 618 * STA control registers. 619 */ 620 621/* 622 * STA_CSR0: RX PLCP error count & RX FCS error count. 623 */ 624#define STA_CSR0 0x30c0 625#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff) 626#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000) 627 628/* 629 * STA_CSR1: RX False CCA count & RX LONG frame count. 630 */ 631#define STA_CSR1 0x30c4 632#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff) 633#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000) 634 635/* 636 * STA_CSR2: TX Beacon count and RX FIFO overflow count. 637 */ 638#define STA_CSR2 0x30c8 639#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff) 640#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000) 641 642/* 643 * STA_CSR3: TX Beacon count. 644 */ 645#define STA_CSR3 0x30cc 646#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff) 647 648/* 649 * STA_CSR4: TX Retry count. 650 */ 651#define STA_CSR4 0x30d0 652#define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff) 653#define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000) 654 655/* 656 * STA_CSR5: TX Retry count. 657 */ 658#define STA_CSR5 0x30d4 659#define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff) 660#define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000) 661 662/* 663 * QOS control registers. 664 */ 665 666/* 667 * QOS_CSR1: TXOP holder MAC address register. 668 */ 669#define QOS_CSR1 0x30e4 670#define QOS_CSR1_BYTE4 FIELD32(0x000000ff) 671#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00) 672 673/* 674 * QOS_CSR2: TXOP holder timeout register. 675 */ 676#define QOS_CSR2 0x30e8 677 678/* 679 * RX QOS-CFPOLL MAC address register. 680 * QOS_CSR3: RX QOS-CFPOLL MAC address 0. 681 * QOS_CSR4: RX QOS-CFPOLL MAC address 1. 682 */ 683#define QOS_CSR3 0x30ec 684#define QOS_CSR4 0x30f0 685 686/* 687 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL. 688 */ 689#define QOS_CSR5 0x30f4 690 691/* 692 * WMM Scheduler Register 693 */ 694 695/* 696 * AIFSN_CSR: AIFSN for each EDCA AC. 697 * AIFSN0: For AC_VO. 698 * AIFSN1: For AC_VI. 699 * AIFSN2: For AC_BE. 700 * AIFSN3: For AC_BK. 701 */ 702#define AIFSN_CSR 0x0400 703#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f) 704#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0) 705#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00) 706#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000) 707 708/* 709 * CWMIN_CSR: CWmin for each EDCA AC. 710 * CWMIN0: For AC_VO. 711 * CWMIN1: For AC_VI. 712 * CWMIN2: For AC_BE. 713 * CWMIN3: For AC_BK. 714 */ 715#define CWMIN_CSR 0x0404 716#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f) 717#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0) 718#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00) 719#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000) 720 721/* 722 * CWMAX_CSR: CWmax for each EDCA AC. 723 * CWMAX0: For AC_VO. 724 * CWMAX1: For AC_VI. 725 * CWMAX2: For AC_BE. 726 * CWMAX3: For AC_BK. 727 */ 728#define CWMAX_CSR 0x0408 729#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f) 730#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0) 731#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00) 732#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000) 733 734/* 735 * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register. 736 * AC0_TX_OP: For AC_VO, in unit of 32us. 737 * AC1_TX_OP: For AC_VI, in unit of 32us. 738 */ 739#define AC_TXOP_CSR0 0x040c 740#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff) 741#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000) 742 743/* 744 * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register. 745 * AC2_TX_OP: For AC_BE, in unit of 32us. 746 * AC3_TX_OP: For AC_BK, in unit of 32us. 747 */ 748#define AC_TXOP_CSR1 0x0410 749#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff) 750#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000) 751 752/* 753 * BBP registers. 754 * The wordsize of the BBP is 8 bits. 755 */ 756 757/* 758 * R2 759 */ 760#define BBP_R2_BG_MODE FIELD8(0x20) 761 762/* 763 * R3 764 */ 765#define BBP_R3_SMART_MODE FIELD8(0x01) 766 767/* 768 * R4: RX antenna control 769 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529) 770 */ 771 772/* 773 * ANTENNA_CONTROL semantics (guessed): 774 * 0x1: Software controlled antenna switching (fixed or SW diversity) 775 * 0x2: Hardware diversity. 776 */ 777#define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03) 778#define BBP_R4_RX_FRAME_END FIELD8(0x20) 779 780/* 781 * R77 782 */ 783#define BBP_R77_RX_ANTENNA FIELD8(0x03) 784 785/* 786 * RF registers 787 */ 788 789/* 790 * RF 3 791 */ 792#define RF3_TXPOWER FIELD32(0x00003e00) 793 794/* 795 * RF 4 796 */ 797#define RF4_FREQ_OFFSET FIELD32(0x0003f000) 798 799/* 800 * EEPROM content. 801 * The wordsize of the EEPROM is 16 bits. 802 */ 803 804/* 805 * HW MAC address. 806 */ 807#define EEPROM_MAC_ADDR_0 0x0002 808#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 809#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 810#define EEPROM_MAC_ADDR1 0x0003 811#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 812#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 813#define EEPROM_MAC_ADDR_2 0x0004 814#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 815#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 816 817/* 818 * EEPROM antenna. 819 * ANTENNA_NUM: Number of antennas. 820 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 821 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 822 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only. 823 * DYN_TXAGC: Dynamic TX AGC control. 824 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. 825 * RF_TYPE: Rf_type of this adapter. 826 */ 827#define EEPROM_ANTENNA 0x0010 828#define EEPROM_ANTENNA_NUM FIELD16(0x0003) 829#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) 830#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) 831#define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040) 832#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) 833#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) 834#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) 835 836/* 837 * EEPROM NIC config. 838 * EXTERNAL_LNA: External LNA. 839 */ 840#define EEPROM_NIC 0x0011 841#define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010) 842 843/* 844 * EEPROM geography. 845 * GEO_A: Default geographical setting for 5GHz band 846 * GEO: Default geographical setting. 847 */ 848#define EEPROM_GEOGRAPHY 0x0012 849#define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff) 850#define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00) 851 852/* 853 * EEPROM BBP. 854 */ 855#define EEPROM_BBP_START 0x0013 856#define EEPROM_BBP_SIZE 16 857#define EEPROM_BBP_VALUE FIELD16(0x00ff) 858#define EEPROM_BBP_REG_ID FIELD16(0xff00) 859 860/* 861 * EEPROM TXPOWER 802.11G 862 */ 863#define EEPROM_TXPOWER_G_START 0x0023 864#define EEPROM_TXPOWER_G_SIZE 7 865#define EEPROM_TXPOWER_G_1 FIELD16(0x00ff) 866#define EEPROM_TXPOWER_G_2 FIELD16(0xff00) 867 868/* 869 * EEPROM Frequency 870 */ 871#define EEPROM_FREQ 0x002f 872#define EEPROM_FREQ_OFFSET FIELD16(0x00ff) 873#define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00) 874#define EEPROM_FREQ_SEQ FIELD16(0x0300) 875 876/* 877 * EEPROM LED. 878 * POLARITY_RDY_G: Polarity RDY_G setting. 879 * POLARITY_RDY_A: Polarity RDY_A setting. 880 * POLARITY_ACT: Polarity ACT setting. 881 * POLARITY_GPIO_0: Polarity GPIO0 setting. 882 * POLARITY_GPIO_1: Polarity GPIO1 setting. 883 * POLARITY_GPIO_2: Polarity GPIO2 setting. 884 * POLARITY_GPIO_3: Polarity GPIO3 setting. 885 * POLARITY_GPIO_4: Polarity GPIO4 setting. 886 * LED_MODE: Led mode. 887 */ 888#define EEPROM_LED 0x0030 889#define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001) 890#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) 891#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) 892#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) 893#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) 894#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) 895#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) 896#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) 897#define EEPROM_LED_LED_MODE FIELD16(0x1f00) 898 899/* 900 * EEPROM TXPOWER 802.11A 901 */ 902#define EEPROM_TXPOWER_A_START 0x0031 903#define EEPROM_TXPOWER_A_SIZE 12 904#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) 905#define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 906 907/* 908 * EEPROM RSSI offset 802.11BG 909 */ 910#define EEPROM_RSSI_OFFSET_BG 0x004d 911#define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff) 912#define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00) 913 914/* 915 * EEPROM RSSI offset 802.11A 916 */ 917#define EEPROM_RSSI_OFFSET_A 0x004e 918#define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff) 919#define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00) 920 921/* 922 * DMA descriptor defines. 923 */ 924#define TXD_DESC_SIZE ( 6 * sizeof(__le32) ) 925#define TXINFO_SIZE ( 6 * sizeof(__le32) ) 926#define RXD_DESC_SIZE ( 6 * sizeof(__le32) ) 927 928/* 929 * TX descriptor format for TX, PRIO and Beacon Ring. 930 */ 931 932/* 933 * Word0 934 * BURST: Next frame belongs to same "burst" event. 935 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used. 936 * KEY_TABLE: Use per-client pairwise KEY table. 937 * KEY_INDEX: 938 * Key index (0~31) to the pairwise KEY table. 939 * 0~3 to shared KEY table 0 (BSS0). 940 * 4~7 to shared KEY table 1 (BSS1). 941 * 8~11 to shared KEY table 2 (BSS2). 942 * 12~15 to shared KEY table 3 (BSS3). 943 * BURST2: For backward compatibility, set to same value as BURST. 944 */ 945#define TXD_W0_BURST FIELD32(0x00000001) 946#define TXD_W0_VALID FIELD32(0x00000002) 947#define TXD_W0_MORE_FRAG FIELD32(0x00000004) 948#define TXD_W0_ACK FIELD32(0x00000008) 949#define TXD_W0_TIMESTAMP FIELD32(0x00000010) 950#define TXD_W0_OFDM FIELD32(0x00000020) 951#define TXD_W0_IFS FIELD32(0x00000040) 952#define TXD_W0_RETRY_MODE FIELD32(0x00000080) 953#define TXD_W0_TKIP_MIC FIELD32(0x00000100) 954#define TXD_W0_KEY_TABLE FIELD32(0x00000200) 955#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00) 956#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) 957#define TXD_W0_BURST2 FIELD32(0x10000000) 958#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000) 959 960/* 961 * Word1 962 * HOST_Q_ID: EDCA/HCCA queue ID. 963 * HW_SEQUENCE: MAC overwrites the frame sequence number. 964 * BUFFER_COUNT: Number of buffers in this TXD. 965 */ 966#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f) 967#define TXD_W1_AIFSN FIELD32(0x000000f0) 968#define TXD_W1_CWMIN FIELD32(0x00000f00) 969#define TXD_W1_CWMAX FIELD32(0x0000f000) 970#define TXD_W1_IV_OFFSET FIELD32(0x003f0000) 971#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000) 972#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000) 973 974/* 975 * Word2: PLCP information 976 */ 977#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff) 978#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00) 979#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000) 980#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000) 981 982/* 983 * Word3 984 */ 985#define TXD_W3_IV FIELD32(0xffffffff) 986 987/* 988 * Word4 989 */ 990#define TXD_W4_EIV FIELD32(0xffffffff) 991 992/* 993 * Word5 994 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field). 995 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt. 996 * WAITING_DMA_DONE_INT: TXD been filled with data 997 * and waiting for TxDoneISR housekeeping. 998 */ 999#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff) 1000#define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
1001#define TXD_W5_TX_POWER FIELD32(0x00ff0000) 1002#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000) 1003 1004/* 1005 * RX descriptor format for RX Ring. 1006 */ 1007 1008/* 1009 * Word0 1010 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key. 1011 * KEY_INDEX: Decryption key actually used. 1012 */ 1013#define RXD_W0_OWNER_NIC FIELD32(0x00000001) 1014#define RXD_W0_DROP FIELD32(0x00000002) 1015#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004) 1016#define RXD_W0_MULTICAST FIELD32(0x00000008) 1017#define RXD_W0_BROADCAST FIELD32(0x00000010) 1018#define RXD_W0_MY_BSS FIELD32(0x00000020) 1019#define RXD_W0_CRC_ERROR FIELD32(0x00000040) 1020#define RXD_W0_OFDM FIELD32(0x00000080) 1021#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300) 1022#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00) 1023#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) 1024#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000) 1025 1026/* 1027 * WORD1 1028 * SIGNAL: RX raw data rate reported by BBP. 1029 * RSSI: RSSI reported by BBP. 1030 */ 1031#define RXD_W1_SIGNAL FIELD32(0x000000ff) 1032#define RXD_W1_RSSI_AGC FIELD32(0x00001f00) 1033#define RXD_W1_RSSI_LNA FIELD32(0x00006000) 1034#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000) 1035 1036/* 1037 * Word2 1038 * IV: Received IV of originally encrypted. 1039 */ 1040#define RXD_W2_IV FIELD32(0xffffffff) 1041 1042/* 1043 * Word3 1044 * EIV: Received EIV of originally encrypted. 1045 */ 1046#define RXD_W3_EIV FIELD32(0xffffffff) 1047 1048/* 1049 * Word4 1050 * ICV: Received ICV of originally encrypted. 1051 * NOTE: This is a guess, the official definition is "reserved" 1052 */ 1053#define RXD_W4_ICV FIELD32(0xffffffff) 1054 1055/* 1056 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block 1057 * and passed to the HOST driver. 1058 * The following fields are for DMA block and HOST usage only. 1059 * Can't be touched by ASIC MAC block. 1060 */ 1061 1062/* 1063 * Word5 1064 */ 1065#define RXD_W5_RESERVED FIELD32(0xffffffff) 1066 1067/* 1068 * Macros for converting txpower from EEPROM to mac80211 value 1069 * and from mac80211 value to register value. 1070 */ 1071#define MIN_TXPOWER 0 1072#define MAX_TXPOWER 31 1073#define DEFAULT_TXPOWER 24 1074 1075#define TXPOWER_FROM_DEV(__txpower) \ 1076 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 1077 1078#define TXPOWER_TO_DEV(__txpower) \ 1079 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER) 1080 1081#endif /* RT73USB_H */ 1082