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57#include <linux/fs.h>
58#include <linux/init.h>
59#include <linux/types.h>
60#include <linux/errno.h>
61#include <linux/kernel.h>
62#include <linux/slab.h>
63#include <linux/vmalloc.h>
64#include <linux/ioport.h>
65#include <linux/delay.h>
66#include <linux/pci.h>
67#include <linux/wait.h>
68#include <linux/spinlock.h>
69#include <linux/sched.h>
70#include <linux/interrupt.h>
71#include <linux/blkdev.h>
72#include <linux/firmware.h>
73#include <linux/module.h>
74#include <linux/moduleparam.h>
75#include <linux/libata.h>
76#include <linux/hdreg.h>
77#include <linux/reboot.h>
78#include <linux/stringify.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/processor.h>
82#include <scsi/scsi.h>
83#include <scsi/scsi_host.h>
84#include <scsi/scsi_tcq.h>
85#include <scsi/scsi_eh.h>
86#include <scsi/scsi_cmnd.h>
87#include "ipr.h"
88
89
90
91
92static LIST_HEAD(ipr_ioa_head);
93static unsigned int ipr_log_level = IPR_DEFAULT_LOG_LEVEL;
94static unsigned int ipr_max_speed = 1;
95static int ipr_testmode = 0;
96static unsigned int ipr_fastfail = 0;
97static unsigned int ipr_transop_timeout = 0;
98static unsigned int ipr_debug = 0;
99static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS;
100static unsigned int ipr_dual_ioa_raid = 1;
101static unsigned int ipr_number_of_msix = 2;
102static DEFINE_SPINLOCK(ipr_driver_lock);
103
104
105static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
106 {
107 .mailbox = 0x0042C,
108 .max_cmds = 100,
109 .cache_line_size = 0x20,
110 .clear_isr = 1,
111 .iopoll_weight = 0,
112 {
113 .set_interrupt_mask_reg = 0x0022C,
114 .clr_interrupt_mask_reg = 0x00230,
115 .clr_interrupt_mask_reg32 = 0x00230,
116 .sense_interrupt_mask_reg = 0x0022C,
117 .sense_interrupt_mask_reg32 = 0x0022C,
118 .clr_interrupt_reg = 0x00228,
119 .clr_interrupt_reg32 = 0x00228,
120 .sense_interrupt_reg = 0x00224,
121 .sense_interrupt_reg32 = 0x00224,
122 .ioarrin_reg = 0x00404,
123 .sense_uproc_interrupt_reg = 0x00214,
124 .sense_uproc_interrupt_reg32 = 0x00214,
125 .set_uproc_interrupt_reg = 0x00214,
126 .set_uproc_interrupt_reg32 = 0x00214,
127 .clr_uproc_interrupt_reg = 0x00218,
128 .clr_uproc_interrupt_reg32 = 0x00218
129 }
130 },
131 {
132 .mailbox = 0x0052C,
133 .max_cmds = 100,
134 .cache_line_size = 0x20,
135 .clear_isr = 1,
136 .iopoll_weight = 0,
137 {
138 .set_interrupt_mask_reg = 0x00288,
139 .clr_interrupt_mask_reg = 0x0028C,
140 .clr_interrupt_mask_reg32 = 0x0028C,
141 .sense_interrupt_mask_reg = 0x00288,
142 .sense_interrupt_mask_reg32 = 0x00288,
143 .clr_interrupt_reg = 0x00284,
144 .clr_interrupt_reg32 = 0x00284,
145 .sense_interrupt_reg = 0x00280,
146 .sense_interrupt_reg32 = 0x00280,
147 .ioarrin_reg = 0x00504,
148 .sense_uproc_interrupt_reg = 0x00290,
149 .sense_uproc_interrupt_reg32 = 0x00290,
150 .set_uproc_interrupt_reg = 0x00290,
151 .set_uproc_interrupt_reg32 = 0x00290,
152 .clr_uproc_interrupt_reg = 0x00294,
153 .clr_uproc_interrupt_reg32 = 0x00294
154 }
155 },
156 {
157 .mailbox = 0x00044,
158 .max_cmds = 1000,
159 .cache_line_size = 0x20,
160 .clear_isr = 0,
161 .iopoll_weight = 64,
162 {
163 .set_interrupt_mask_reg = 0x00010,
164 .clr_interrupt_mask_reg = 0x00018,
165 .clr_interrupt_mask_reg32 = 0x0001C,
166 .sense_interrupt_mask_reg = 0x00010,
167 .sense_interrupt_mask_reg32 = 0x00014,
168 .clr_interrupt_reg = 0x00008,
169 .clr_interrupt_reg32 = 0x0000C,
170 .sense_interrupt_reg = 0x00000,
171 .sense_interrupt_reg32 = 0x00004,
172 .ioarrin_reg = 0x00070,
173 .sense_uproc_interrupt_reg = 0x00020,
174 .sense_uproc_interrupt_reg32 = 0x00024,
175 .set_uproc_interrupt_reg = 0x00020,
176 .set_uproc_interrupt_reg32 = 0x00024,
177 .clr_uproc_interrupt_reg = 0x00028,
178 .clr_uproc_interrupt_reg32 = 0x0002C,
179 .init_feedback_reg = 0x0005C,
180 .dump_addr_reg = 0x00064,
181 .dump_data_reg = 0x00068,
182 .endian_swap_reg = 0x00084
183 }
184 },
185};
186
187static const struct ipr_chip_t ipr_chip[] = {
188 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
189 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
190 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
191 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
192 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
193 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
194 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
195 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
196 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
197};
198
199static int ipr_max_bus_speeds[] = {
200 IPR_80MBs_SCSI_RATE, IPR_U160_SCSI_RATE, IPR_U320_SCSI_RATE
201};
202
203MODULE_AUTHOR("Brian King <brking@us.ibm.com>");
204MODULE_DESCRIPTION("IBM Power RAID SCSI Adapter Driver");
205module_param_named(max_speed, ipr_max_speed, uint, 0);
206MODULE_PARM_DESC(max_speed, "Maximum bus speed (0-2). Default: 1=U160. Speeds: 0=80 MB/s, 1=U160, 2=U320");
207module_param_named(log_level, ipr_log_level, uint, 0);
208MODULE_PARM_DESC(log_level, "Set to 0 - 4 for increasing verbosity of device driver");
209module_param_named(testmode, ipr_testmode, int, 0);
210MODULE_PARM_DESC(testmode, "DANGEROUS!!! Allows unsupported configurations");
211module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR);
212MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries");
213module_param_named(transop_timeout, ipr_transop_timeout, int, 0);
214MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)");
215module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR);
216MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)");
217module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0);
218MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)");
219module_param_named(max_devs, ipr_max_devs, int, 0);
220MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. "
221 "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]");
222module_param_named(number_of_msix, ipr_number_of_msix, int, 0);
223MODULE_PARM_DESC(number_of_msix, "Specify the number of MSIX interrupts to use on capable adapters (1 - 5). (default:2)");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(IPR_DRIVER_VERSION);
226
227
228static const
229struct ipr_error_table_t ipr_error_table[] = {
230 {0x00000000, 1, IPR_DEFAULT_LOG_LEVEL,
231 "8155: An unknown error was received"},
232 {0x00330000, 0, 0,
233 "Soft underlength error"},
234 {0x005A0000, 0, 0,
235 "Command to be cancelled not found"},
236 {0x00808000, 0, 0,
237 "Qualified success"},
238 {0x01080000, 1, IPR_DEFAULT_LOG_LEVEL,
239 "FFFE: Soft device bus error recovered by the IOA"},
240 {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL,
241 "4101: Soft device bus fabric error"},
242 {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL,
243 "FFFC: Logical block guard error recovered by the device"},
244 {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL,
245 "FFFC: Logical block reference tag error recovered by the device"},
246 {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL,
247 "4171: Recovered scatter list tag / sequence number error"},
248 {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL,
249 "FF3D: Recovered logical block CRC error on IOA to Host transfer"},
250 {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL,
251 "4171: Recovered logical block sequence number error on IOA to Host transfer"},
252 {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL,
253 "FFFD: Recovered logical block reference tag error detected by the IOA"},
254 {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL,
255 "FFFD: Logical block guard error recovered by the IOA"},
256 {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL,
257 "FFF9: Device sector reassign successful"},
258 {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL,
259 "FFF7: Media error recovered by device rewrite procedures"},
260 {0x01180200, 0, IPR_DEFAULT_LOG_LEVEL,
261 "7001: IOA sector reassignment successful"},
262 {0x01180500, 0, IPR_DEFAULT_LOG_LEVEL,
263 "FFF9: Soft media error. Sector reassignment recommended"},
264 {0x01180600, 0, IPR_DEFAULT_LOG_LEVEL,
265 "FFF7: Media error recovered by IOA rewrite procedures"},
266 {0x01418000, 0, IPR_DEFAULT_LOG_LEVEL,
267 "FF3D: Soft PCI bus error recovered by the IOA"},
268 {0x01440000, 1, IPR_DEFAULT_LOG_LEVEL,
269 "FFF6: Device hardware error recovered by the IOA"},
270 {0x01448100, 0, IPR_DEFAULT_LOG_LEVEL,
271 "FFF6: Device hardware error recovered by the device"},
272 {0x01448200, 1, IPR_DEFAULT_LOG_LEVEL,
273 "FF3D: Soft IOA error recovered by the IOA"},
274 {0x01448300, 0, IPR_DEFAULT_LOG_LEVEL,
275 "FFFA: Undefined device response recovered by the IOA"},
276 {0x014A0000, 1, IPR_DEFAULT_LOG_LEVEL,
277 "FFF6: Device bus error, message or command phase"},
278 {0x014A8000, 0, IPR_DEFAULT_LOG_LEVEL,
279 "FFFE: Task Management Function failed"},
280 {0x015D0000, 0, IPR_DEFAULT_LOG_LEVEL,
281 "FFF6: Failure prediction threshold exceeded"},
282 {0x015D9200, 0, IPR_DEFAULT_LOG_LEVEL,
283 "8009: Impending cache battery pack failure"},
284 {0x02040400, 0, 0,
285 "34FF: Disk device format in progress"},
286 {0x02048000, 0, IPR_DEFAULT_LOG_LEVEL,
287 "9070: IOA requested reset"},
288 {0x023F0000, 0, 0,
289 "Synchronization required"},
290 {0x024E0000, 0, 0,
291 "No ready, IOA shutdown"},
292 {0x025A0000, 0, 0,
293 "Not ready, IOA has been shutdown"},
294 {0x02670100, 0, IPR_DEFAULT_LOG_LEVEL,
295 "3020: Storage subsystem configuration error"},
296 {0x03110B00, 0, 0,
297 "FFF5: Medium error, data unreadable, recommend reassign"},
298 {0x03110C00, 0, 0,
299 "7000: Medium error, data unreadable, do not reassign"},
300 {0x03310000, 0, IPR_DEFAULT_LOG_LEVEL,
301 "FFF3: Disk media format bad"},
302 {0x04050000, 0, IPR_DEFAULT_LOG_LEVEL,
303 "3002: Addressed device failed to respond to selection"},
304 {0x04080000, 1, IPR_DEFAULT_LOG_LEVEL,
305 "3100: Device bus error"},
306 {0x04080100, 0, IPR_DEFAULT_LOG_LEVEL,
307 "3109: IOA timed out a device command"},
308 {0x04088000, 0, 0,
309 "3120: SCSI bus is not operational"},
310 {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL,
311 "4100: Hard device bus fabric error"},
312 {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL,
313 "310C: Logical block guard error detected by the device"},
314 {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL,
315 "310C: Logical block reference tag error detected by the device"},
316 {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL,
317 "4170: Scatter list tag / sequence number error"},
318 {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL,
319 "8150: Logical block CRC error on IOA to Host transfer"},
320 {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL,
321 "4170: Logical block sequence number error on IOA to Host transfer"},
322 {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL,
323 "310D: Logical block reference tag error detected by the IOA"},
324 {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL,
325 "310D: Logical block guard error detected by the IOA"},
326 {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL,
327 "9000: IOA reserved area data check"},
328 {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL,
329 "9001: IOA reserved area invalid data pattern"},
330 {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL,
331 "9002: IOA reserved area LRC error"},
332 {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL,
333 "Hardware Error, IOA metadata access error"},
334 {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL,
335 "102E: Out of alternate sectors for disk storage"},
336 {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL,
337 "FFF4: Data transfer underlength error"},
338 {0x04338000, 1, IPR_DEFAULT_LOG_LEVEL,
339 "FFF4: Data transfer overlength error"},
340 {0x043E0100, 0, IPR_DEFAULT_LOG_LEVEL,
341 "3400: Logical unit failure"},
342 {0x04408500, 0, IPR_DEFAULT_LOG_LEVEL,
343 "FFF4: Device microcode is corrupt"},
344 {0x04418000, 1, IPR_DEFAULT_LOG_LEVEL,
345 "8150: PCI bus error"},
346 {0x04430000, 1, 0,
347 "Unsupported device bus message received"},
348 {0x04440000, 1, IPR_DEFAULT_LOG_LEVEL,
349 "FFF4: Disk device problem"},
350 {0x04448200, 1, IPR_DEFAULT_LOG_LEVEL,
351 "8150: Permanent IOA failure"},
352 {0x04448300, 0, IPR_DEFAULT_LOG_LEVEL,
353 "3010: Disk device returned wrong response to IOA"},
354 {0x04448400, 0, IPR_DEFAULT_LOG_LEVEL,
355 "8151: IOA microcode error"},
356 {0x04448500, 0, 0,
357 "Device bus status error"},
358 {0x04448600, 0, IPR_DEFAULT_LOG_LEVEL,
359 "8157: IOA error requiring IOA reset to recover"},
360 {0x04448700, 0, 0,
361 "ATA device status error"},
362 {0x04490000, 0, 0,
363 "Message reject received from the device"},
364 {0x04449200, 0, IPR_DEFAULT_LOG_LEVEL,
365 "8008: A permanent cache battery pack failure occurred"},
366 {0x0444A000, 0, IPR_DEFAULT_LOG_LEVEL,
367 "9090: Disk unit has been modified after the last known status"},
368 {0x0444A200, 0, IPR_DEFAULT_LOG_LEVEL,
369 "9081: IOA detected device error"},
370 {0x0444A300, 0, IPR_DEFAULT_LOG_LEVEL,
371 "9082: IOA detected device error"},
372 {0x044A0000, 1, IPR_DEFAULT_LOG_LEVEL,
373 "3110: Device bus error, message or command phase"},
374 {0x044A8000, 1, IPR_DEFAULT_LOG_LEVEL,
375 "3110: SAS Command / Task Management Function failed"},
376 {0x04670400, 0, IPR_DEFAULT_LOG_LEVEL,
377 "9091: Incorrect hardware configuration change has been detected"},
378 {0x04678000, 0, IPR_DEFAULT_LOG_LEVEL,
379 "9073: Invalid multi-adapter configuration"},
380 {0x04678100, 0, IPR_DEFAULT_LOG_LEVEL,
381 "4010: Incorrect connection between cascaded expanders"},
382 {0x04678200, 0, IPR_DEFAULT_LOG_LEVEL,
383 "4020: Connections exceed IOA design limits"},
384 {0x04678300, 0, IPR_DEFAULT_LOG_LEVEL,
385 "4030: Incorrect multipath connection"},
386 {0x04679000, 0, IPR_DEFAULT_LOG_LEVEL,
387 "4110: Unsupported enclosure function"},
388 {0x046E0000, 0, IPR_DEFAULT_LOG_LEVEL,
389 "FFF4: Command to logical unit failed"},
390 {0x05240000, 1, 0,
391 "Illegal request, invalid request type or request packet"},
392 {0x05250000, 0, 0,
393 "Illegal request, invalid resource handle"},
394 {0x05258000, 0, 0,
395 "Illegal request, commands not allowed to this device"},
396 {0x05258100, 0, 0,
397 "Illegal request, command not allowed to a secondary adapter"},
398 {0x05258200, 0, 0,
399 "Illegal request, command not allowed to a non-optimized resource"},
400 {0x05260000, 0, 0,
401 "Illegal request, invalid field in parameter list"},
402 {0x05260100, 0, 0,
403 "Illegal request, parameter not supported"},
404 {0x05260200, 0, 0,
405 "Illegal request, parameter value invalid"},
406 {0x052C0000, 0, 0,
407 "Illegal request, command sequence error"},
408 {0x052C8000, 1, 0,
409 "Illegal request, dual adapter support not enabled"},
410 {0x06040500, 0, IPR_DEFAULT_LOG_LEVEL,
411 "9031: Array protection temporarily suspended, protection resuming"},
412 {0x06040600, 0, IPR_DEFAULT_LOG_LEVEL,
413 "9040: Array protection temporarily suspended, protection resuming"},
414 {0x06288000, 0, IPR_DEFAULT_LOG_LEVEL,
415 "3140: Device bus not ready to ready transition"},
416 {0x06290000, 0, IPR_DEFAULT_LOG_LEVEL,
417 "FFFB: SCSI bus was reset"},
418 {0x06290500, 0, 0,
419 "FFFE: SCSI bus transition to single ended"},
420 {0x06290600, 0, 0,
421 "FFFE: SCSI bus transition to LVD"},
422 {0x06298000, 0, IPR_DEFAULT_LOG_LEVEL,
423 "FFFB: SCSI bus was reset by another initiator"},
424 {0x063F0300, 0, IPR_DEFAULT_LOG_LEVEL,
425 "3029: A device replacement has occurred"},
426 {0x064C8000, 0, IPR_DEFAULT_LOG_LEVEL,
427 "9051: IOA cache data exists for a missing or failed device"},
428 {0x064C8100, 0, IPR_DEFAULT_LOG_LEVEL,
429 "9055: Auxiliary cache IOA contains cache data needed by the primary IOA"},
430 {0x06670100, 0, IPR_DEFAULT_LOG_LEVEL,
431 "9025: Disk unit is not supported at its physical location"},
432 {0x06670600, 0, IPR_DEFAULT_LOG_LEVEL,
433 "3020: IOA detected a SCSI bus configuration error"},
434 {0x06678000, 0, IPR_DEFAULT_LOG_LEVEL,
435 "3150: SCSI bus configuration error"},
436 {0x06678100, 0, IPR_DEFAULT_LOG_LEVEL,
437 "9074: Asymmetric advanced function disk configuration"},
438 {0x06678300, 0, IPR_DEFAULT_LOG_LEVEL,
439 "4040: Incomplete multipath connection between IOA and enclosure"},
440 {0x06678400, 0, IPR_DEFAULT_LOG_LEVEL,
441 "4041: Incomplete multipath connection between enclosure and device"},
442 {0x06678500, 0, IPR_DEFAULT_LOG_LEVEL,
443 "9075: Incomplete multipath connection between IOA and remote IOA"},
444 {0x06678600, 0, IPR_DEFAULT_LOG_LEVEL,
445 "9076: Configuration error, missing remote IOA"},
446 {0x06679100, 0, IPR_DEFAULT_LOG_LEVEL,
447 "4050: Enclosure does not support a required multipath function"},
448 {0x06690000, 0, IPR_DEFAULT_LOG_LEVEL,
449 "4070: Logically bad block written on device"},
450 {0x06690200, 0, IPR_DEFAULT_LOG_LEVEL,
451 "9041: Array protection temporarily suspended"},
452 {0x06698200, 0, IPR_DEFAULT_LOG_LEVEL,
453 "9042: Corrupt array parity detected on specified device"},
454 {0x066B0200, 0, IPR_DEFAULT_LOG_LEVEL,
455 "9030: Array no longer protected due to missing or failed disk unit"},
456 {0x066B8000, 0, IPR_DEFAULT_LOG_LEVEL,
457 "9071: Link operational transition"},
458 {0x066B8100, 0, IPR_DEFAULT_LOG_LEVEL,
459 "9072: Link not operational transition"},
460 {0x066B8200, 0, IPR_DEFAULT_LOG_LEVEL,
461 "9032: Array exposed but still protected"},
462 {0x066B8300, 0, IPR_DEFAULT_LOG_LEVEL + 1,
463 "70DD: Device forced failed by disrupt device command"},
464 {0x066B9100, 0, IPR_DEFAULT_LOG_LEVEL,
465 "4061: Multipath redundancy level got better"},
466 {0x066B9200, 0, IPR_DEFAULT_LOG_LEVEL,
467 "4060: Multipath redundancy level got worse"},
468 {0x07270000, 0, 0,
469 "Failure due to other device"},
470 {0x07278000, 0, IPR_DEFAULT_LOG_LEVEL,
471 "9008: IOA does not support functions expected by devices"},
472 {0x07278100, 0, IPR_DEFAULT_LOG_LEVEL,
473 "9010: Cache data associated with attached devices cannot be found"},
474 {0x07278200, 0, IPR_DEFAULT_LOG_LEVEL,
475 "9011: Cache data belongs to devices other than those attached"},
476 {0x07278400, 0, IPR_DEFAULT_LOG_LEVEL,
477 "9020: Array missing 2 or more devices with only 1 device present"},
478 {0x07278500, 0, IPR_DEFAULT_LOG_LEVEL,
479 "9021: Array missing 2 or more devices with 2 or more devices present"},
480 {0x07278600, 0, IPR_DEFAULT_LOG_LEVEL,
481 "9022: Exposed array is missing a required device"},
482 {0x07278700, 0, IPR_DEFAULT_LOG_LEVEL,
483 "9023: Array member(s) not at required physical locations"},
484 {0x07278800, 0, IPR_DEFAULT_LOG_LEVEL,
485 "9024: Array not functional due to present hardware configuration"},
486 {0x07278900, 0, IPR_DEFAULT_LOG_LEVEL,
487 "9026: Array not functional due to present hardware configuration"},
488 {0x07278A00, 0, IPR_DEFAULT_LOG_LEVEL,
489 "9027: Array is missing a device and parity is out of sync"},
490 {0x07278B00, 0, IPR_DEFAULT_LOG_LEVEL,
491 "9028: Maximum number of arrays already exist"},
492 {0x07278C00, 0, IPR_DEFAULT_LOG_LEVEL,
493 "9050: Required cache data cannot be located for a disk unit"},
494 {0x07278D00, 0, IPR_DEFAULT_LOG_LEVEL,
495 "9052: Cache data exists for a device that has been modified"},
496 {0x07278F00, 0, IPR_DEFAULT_LOG_LEVEL,
497 "9054: IOA resources not available due to previous problems"},
498 {0x07279100, 0, IPR_DEFAULT_LOG_LEVEL,
499 "9092: Disk unit requires initialization before use"},
500 {0x07279200, 0, IPR_DEFAULT_LOG_LEVEL,
501 "9029: Incorrect hardware configuration change has been detected"},
502 {0x07279600, 0, IPR_DEFAULT_LOG_LEVEL,
503 "9060: One or more disk pairs are missing from an array"},
504 {0x07279700, 0, IPR_DEFAULT_LOG_LEVEL,
505 "9061: One or more disks are missing from an array"},
506 {0x07279800, 0, IPR_DEFAULT_LOG_LEVEL,
507 "9062: One or more disks are missing from an array"},
508 {0x07279900, 0, IPR_DEFAULT_LOG_LEVEL,
509 "9063: Maximum number of functional arrays has been exceeded"},
510 {0x0B260000, 0, 0,
511 "Aborted command, invalid descriptor"},
512 {0x0B5A0000, 0, 0,
513 "Command terminated by host"}
514};
515
516static const struct ipr_ses_table_entry ipr_ses_table[] = {
517 { "2104-DL1 ", "XXXXXXXXXXXXXXXX", 80 },
518 { "2104-TL1 ", "XXXXXXXXXXXXXXXX", 80 },
519 { "HSBP07M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
520 { "HSBP05M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
521 { "HSBP05M S U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
522 { "HSBP06E ASU2SCSI", "XXXXXXXXXXXXXXXX", 80 },
523 { "2104-DU3 ", "XXXXXXXXXXXXXXXX", 160 },
524 { "2104-TU3 ", "XXXXXXXXXXXXXXXX", 160 },
525 { "HSBP04C RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
526 { "HSBP06E RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
527 { "St V1S2 ", "XXXXXXXXXXXXXXXX", 160 },
528 { "HSBPD4M PU3SCSI", "XXXXXXX*XXXXXXXX", 160 },
529 { "VSBPD1H U3SCSI", "XXXXXXX*XXXXXXXX", 160 }
530};
531
532
533
534
535static int ipr_reset_alert(struct ipr_cmnd *);
536static void ipr_process_ccn(struct ipr_cmnd *);
537static void ipr_process_error(struct ipr_cmnd *);
538static void ipr_reset_ioa_job(struct ipr_cmnd *);
539static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *,
540 enum ipr_shutdown_type);
541
542#ifdef CONFIG_SCSI_IPR_TRACE
543
544
545
546
547
548
549
550
551
552static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd,
553 u8 type, u32 add_data)
554{
555 struct ipr_trace_entry *trace_entry;
556 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
557
558 trace_entry = &ioa_cfg->trace[atomic_add_return
559 (1, &ioa_cfg->trace_index)%IPR_NUM_TRACE_ENTRIES];
560 trace_entry->time = jiffies;
561 trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0];
562 trace_entry->type = type;
563 if (ipr_cmd->ioa_cfg->sis64)
564 trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command;
565 else
566 trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command;
567 trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff;
568 trace_entry->res_handle = ipr_cmd->ioarcb.res_handle;
569 trace_entry->u.add_data = add_data;
570 wmb();
571}
572#else
573#define ipr_trc_hook(ipr_cmd, type, add_data) do { } while (0)
574#endif
575
576
577
578
579
580
581
582
583static void ipr_lock_and_done(struct ipr_cmnd *ipr_cmd)
584{
585 unsigned long lock_flags;
586 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
587
588 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
589 ipr_cmd->done(ipr_cmd);
590 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
591}
592
593
594
595
596
597
598
599
600static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
601{
602 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
603 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
604 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
605 dma_addr_t dma_addr = ipr_cmd->dma_addr;
606 int hrrq_id;
607
608 hrrq_id = ioarcb->cmd_pkt.hrrq_id;
609 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
610 ioarcb->cmd_pkt.hrrq_id = hrrq_id;
611 ioarcb->data_transfer_length = 0;
612 ioarcb->read_data_transfer_length = 0;
613 ioarcb->ioadl_len = 0;
614 ioarcb->read_ioadl_len = 0;
615
616 if (ipr_cmd->ioa_cfg->sis64) {
617 ioarcb->u.sis64_addr_data.data_ioadl_addr =
618 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
619 ioasa64->u.gata.status = 0;
620 } else {
621 ioarcb->write_ioadl_addr =
622 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
623 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
624 ioasa->u.gata.status = 0;
625 }
626
627 ioasa->hdr.ioasc = 0;
628 ioasa->hdr.residual_data_len = 0;
629 ipr_cmd->scsi_cmd = NULL;
630 ipr_cmd->qc = NULL;
631 ipr_cmd->sense_buffer[0] = 0;
632 ipr_cmd->dma_use_sg = 0;
633}
634
635
636
637
638
639
640
641
642static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd,
643 void (*fast_done) (struct ipr_cmnd *))
644{
645 ipr_reinit_ipr_cmnd(ipr_cmd);
646 ipr_cmd->u.scratch = 0;
647 ipr_cmd->sibling = NULL;
648 ipr_cmd->fast_done = fast_done;
649 init_timer(&ipr_cmd->timer);
650}
651
652
653
654
655
656
657
658
659static
660struct ipr_cmnd *__ipr_get_free_ipr_cmnd(struct ipr_hrr_queue *hrrq)
661{
662 struct ipr_cmnd *ipr_cmd = NULL;
663
664 if (likely(!list_empty(&hrrq->hrrq_free_q))) {
665 ipr_cmd = list_entry(hrrq->hrrq_free_q.next,
666 struct ipr_cmnd, queue);
667 list_del(&ipr_cmd->queue);
668 }
669
670
671 return ipr_cmd;
672}
673
674
675
676
677
678
679
680
681static
682struct ipr_cmnd *ipr_get_free_ipr_cmnd(struct ipr_ioa_cfg *ioa_cfg)
683{
684 struct ipr_cmnd *ipr_cmd =
685 __ipr_get_free_ipr_cmnd(&ioa_cfg->hrrq[IPR_INIT_HRRQ]);
686 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
687 return ipr_cmd;
688}
689
690
691
692
693
694
695
696
697
698
699
700
701static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
702 u32 clr_ints)
703{
704 volatile u32 int_reg;
705 int i;
706
707
708 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
709 spin_lock(&ioa_cfg->hrrq[i]._lock);
710 ioa_cfg->hrrq[i].allow_interrupts = 0;
711 spin_unlock(&ioa_cfg->hrrq[i]._lock);
712 }
713 wmb();
714
715
716 if (ioa_cfg->sis64)
717 writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
718 else
719 writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
720
721
722 if (ioa_cfg->sis64)
723 writel(~0, ioa_cfg->regs.clr_interrupt_reg);
724 writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
725 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
726}
727
728
729
730
731
732
733
734
735static int ipr_save_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
736{
737 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
738
739 if (pcix_cmd_reg == 0)
740 return 0;
741
742 if (pci_read_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
743 &ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
744 dev_err(&ioa_cfg->pdev->dev, "Failed to save PCI-X command register\n");
745 return -EIO;
746 }
747
748 ioa_cfg->saved_pcix_cmd_reg |= PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO;
749 return 0;
750}
751
752
753
754
755
756
757
758
759static int ipr_set_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
760{
761 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
762
763 if (pcix_cmd_reg) {
764 if (pci_write_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
765 ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
766 dev_err(&ioa_cfg->pdev->dev, "Failed to setup PCI-X command register\n");
767 return -EIO;
768 }
769 }
770
771 return 0;
772}
773
774
775
776
777
778
779
780
781
782
783
784static void ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
785{
786 struct ata_queued_cmd *qc = ipr_cmd->qc;
787 struct ipr_sata_port *sata_port = qc->ap->private_data;
788
789 qc->err_mask |= AC_ERR_OTHER;
790 sata_port->ioasa.status |= ATA_BUSY;
791 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
792 ata_qc_complete(qc);
793}
794
795
796
797
798
799
800
801
802
803
804
805static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
806{
807 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
808
809 scsi_cmd->result |= (DID_ERROR << 16);
810
811 scsi_dma_unmap(ipr_cmd->scsi_cmd);
812 scsi_cmd->scsi_done(scsi_cmd);
813 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
814}
815
816
817
818
819
820
821
822
823
824
825static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg)
826{
827 struct ipr_cmnd *ipr_cmd, *temp;
828 struct ipr_hrr_queue *hrrq;
829
830 ENTER;
831 for_each_hrrq(hrrq, ioa_cfg) {
832 spin_lock(&hrrq->_lock);
833 list_for_each_entry_safe(ipr_cmd,
834 temp, &hrrq->hrrq_pending_q, queue) {
835 list_del(&ipr_cmd->queue);
836
837 ipr_cmd->s.ioasa.hdr.ioasc =
838 cpu_to_be32(IPR_IOASC_IOA_WAS_RESET);
839 ipr_cmd->s.ioasa.hdr.ilid =
840 cpu_to_be32(IPR_DRIVER_ILID);
841
842 if (ipr_cmd->scsi_cmd)
843 ipr_cmd->done = ipr_scsi_eh_done;
844 else if (ipr_cmd->qc)
845 ipr_cmd->done = ipr_sata_eh_done;
846
847 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH,
848 IPR_IOASC_IOA_WAS_RESET);
849 del_timer(&ipr_cmd->timer);
850 ipr_cmd->done(ipr_cmd);
851 }
852 spin_unlock(&hrrq->_lock);
853 }
854 LEAVE;
855}
856
857
858
859
860
861
862
863
864
865
866
867
868static void ipr_send_command(struct ipr_cmnd *ipr_cmd)
869{
870 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
871 dma_addr_t send_dma_addr = ipr_cmd->dma_addr;
872
873 if (ioa_cfg->sis64) {
874
875 send_dma_addr |= 0x1;
876
877
878
879 if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 )
880 send_dma_addr |= 0x4;
881 writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
882 } else
883 writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
884}
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899static void ipr_do_req(struct ipr_cmnd *ipr_cmd,
900 void (*done) (struct ipr_cmnd *),
901 void (*timeout_func) (struct ipr_cmnd *), u32 timeout)
902{
903 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
904
905 ipr_cmd->done = done;
906
907 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
908 ipr_cmd->timer.expires = jiffies + timeout;
909 ipr_cmd->timer.function = (void (*)(unsigned long))timeout_func;
910
911 add_timer(&ipr_cmd->timer);
912
913 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0);
914
915 ipr_send_command(ipr_cmd);
916}
917
918
919
920
921
922
923
924
925
926
927
928static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd)
929{
930 if (ipr_cmd->sibling)
931 ipr_cmd->sibling = NULL;
932 else
933 complete(&ipr_cmd->completion);
934}
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr,
950 u32 len, int flags)
951{
952 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
953 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
954
955 ipr_cmd->dma_use_sg = 1;
956
957 if (ipr_cmd->ioa_cfg->sis64) {
958 ioadl64->flags = cpu_to_be32(flags);
959 ioadl64->data_len = cpu_to_be32(len);
960 ioadl64->address = cpu_to_be64(dma_addr);
961
962 ipr_cmd->ioarcb.ioadl_len =
963 cpu_to_be32(sizeof(struct ipr_ioadl64_desc));
964 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
965 } else {
966 ioadl->flags_and_data_len = cpu_to_be32(flags | len);
967 ioadl->address = cpu_to_be32(dma_addr);
968
969 if (flags == IPR_IOADL_FLAGS_READ_LAST) {
970 ipr_cmd->ioarcb.read_ioadl_len =
971 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
972 ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len);
973 } else {
974 ipr_cmd->ioarcb.ioadl_len =
975 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
976 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
977 }
978 }
979}
980
981
982
983
984
985
986
987
988
989
990static void ipr_send_blocking_cmd(struct ipr_cmnd *ipr_cmd,
991 void (*timeout_func) (struct ipr_cmnd *ipr_cmd),
992 u32 timeout)
993{
994 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
995
996 init_completion(&ipr_cmd->completion);
997 ipr_do_req(ipr_cmd, ipr_internal_cmd_done, timeout_func, timeout);
998
999 spin_unlock_irq(ioa_cfg->host->host_lock);
1000 wait_for_completion(&ipr_cmd->completion);
1001 spin_lock_irq(ioa_cfg->host->host_lock);
1002}
1003
1004static int ipr_get_hrrq_index(struct ipr_ioa_cfg *ioa_cfg)
1005{
1006 if (ioa_cfg->hrrq_num == 1)
1007 return 0;
1008 else
1009 return (atomic_add_return(1, &ioa_cfg->hrrq_index) % (ioa_cfg->hrrq_num - 1)) + 1;
1010}
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type,
1026 struct ipr_hostrcb *hostrcb)
1027{
1028 struct ipr_cmnd *ipr_cmd;
1029 struct ipr_ioarcb *ioarcb;
1030
1031 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
1032 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
1033 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
1034 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_pending_q);
1035
1036 ipr_cmd->u.hostrcb = hostrcb;
1037 ioarcb = &ipr_cmd->ioarcb;
1038
1039 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
1040 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_HCAM;
1041 ioarcb->cmd_pkt.cdb[0] = IPR_HOST_CONTROLLED_ASYNC;
1042 ioarcb->cmd_pkt.cdb[1] = type;
1043 ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff;
1044 ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff;
1045
1046 ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma,
1047 sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST);
1048
1049 if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE)
1050 ipr_cmd->done = ipr_process_ccn;
1051 else
1052 ipr_cmd->done = ipr_process_error;
1053
1054 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR);
1055
1056 ipr_send_command(ipr_cmd);
1057 } else {
1058 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
1059 }
1060}
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto)
1071{
1072 switch (proto) {
1073 case IPR_PROTO_SATA:
1074 case IPR_PROTO_SAS_STP:
1075 res->ata_class = ATA_DEV_ATA;
1076 break;
1077 case IPR_PROTO_SATA_ATAPI:
1078 case IPR_PROTO_SAS_STP_ATAPI:
1079 res->ata_class = ATA_DEV_ATAPI;
1080 break;
1081 default:
1082 res->ata_class = ATA_DEV_UNKNOWN;
1083 break;
1084 };
1085}
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095static void ipr_init_res_entry(struct ipr_resource_entry *res,
1096 struct ipr_config_table_entry_wrapper *cfgtew)
1097{
1098 int found = 0;
1099 unsigned int proto;
1100 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1101 struct ipr_resource_entry *gscsi_res = NULL;
1102
1103 res->needs_sync_complete = 0;
1104 res->in_erp = 0;
1105 res->add_to_ml = 0;
1106 res->del_from_ml = 0;
1107 res->resetting_device = 0;
1108 res->sdev = NULL;
1109 res->sata_port = NULL;
1110
1111 if (ioa_cfg->sis64) {
1112 proto = cfgtew->u.cfgte64->proto;
1113 res->res_flags = cfgtew->u.cfgte64->res_flags;
1114 res->qmodel = IPR_QUEUEING_MODEL64(res);
1115 res->type = cfgtew->u.cfgte64->res_type;
1116
1117 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1118 sizeof(res->res_path));
1119
1120 res->bus = 0;
1121 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1122 sizeof(res->dev_lun.scsi_lun));
1123 res->lun = scsilun_to_int(&res->dev_lun);
1124
1125 if (res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1126 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) {
1127 if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) {
1128 found = 1;
1129 res->target = gscsi_res->target;
1130 break;
1131 }
1132 }
1133 if (!found) {
1134 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1135 ioa_cfg->max_devs_supported);
1136 set_bit(res->target, ioa_cfg->target_ids);
1137 }
1138 } else if (res->type == IPR_RES_TYPE_IOAFP) {
1139 res->bus = IPR_IOAFP_VIRTUAL_BUS;
1140 res->target = 0;
1141 } else if (res->type == IPR_RES_TYPE_ARRAY) {
1142 res->bus = IPR_ARRAY_VIRTUAL_BUS;
1143 res->target = find_first_zero_bit(ioa_cfg->array_ids,
1144 ioa_cfg->max_devs_supported);
1145 set_bit(res->target, ioa_cfg->array_ids);
1146 } else if (res->type == IPR_RES_TYPE_VOLUME_SET) {
1147 res->bus = IPR_VSET_VIRTUAL_BUS;
1148 res->target = find_first_zero_bit(ioa_cfg->vset_ids,
1149 ioa_cfg->max_devs_supported);
1150 set_bit(res->target, ioa_cfg->vset_ids);
1151 } else {
1152 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1153 ioa_cfg->max_devs_supported);
1154 set_bit(res->target, ioa_cfg->target_ids);
1155 }
1156 } else {
1157 proto = cfgtew->u.cfgte->proto;
1158 res->qmodel = IPR_QUEUEING_MODEL(res);
1159 res->flags = cfgtew->u.cfgte->flags;
1160 if (res->flags & IPR_IS_IOA_RESOURCE)
1161 res->type = IPR_RES_TYPE_IOAFP;
1162 else
1163 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1164
1165 res->bus = cfgtew->u.cfgte->res_addr.bus;
1166 res->target = cfgtew->u.cfgte->res_addr.target;
1167 res->lun = cfgtew->u.cfgte->res_addr.lun;
1168 res->lun_wwn = get_unaligned_be64(cfgtew->u.cfgte->lun_wwn);
1169 }
1170
1171 ipr_update_ata_class(res, proto);
1172}
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182static int ipr_is_same_device(struct ipr_resource_entry *res,
1183 struct ipr_config_table_entry_wrapper *cfgtew)
1184{
1185 if (res->ioa_cfg->sis64) {
1186 if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id,
1187 sizeof(cfgtew->u.cfgte64->dev_id)) &&
1188 !memcmp(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1189 sizeof(cfgtew->u.cfgte64->lun))) {
1190 return 1;
1191 }
1192 } else {
1193 if (res->bus == cfgtew->u.cfgte->res_addr.bus &&
1194 res->target == cfgtew->u.cfgte->res_addr.target &&
1195 res->lun == cfgtew->u.cfgte->res_addr.lun)
1196 return 1;
1197 }
1198
1199 return 0;
1200}
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211static char *__ipr_format_res_path(u8 *res_path, char *buffer, int len)
1212{
1213 int i;
1214 char *p = buffer;
1215
1216 *p = '\0';
1217 p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
1218 for (i = 1; res_path[i] != 0xff && ((i * 3) < len); i++)
1219 p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
1220
1221 return buffer;
1222}
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234static char *ipr_format_res_path(struct ipr_ioa_cfg *ioa_cfg,
1235 u8 *res_path, char *buffer, int len)
1236{
1237 char *p = buffer;
1238
1239 *p = '\0';
1240 p += snprintf(p, buffer + len - p, "%d/", ioa_cfg->host->host_no);
1241 __ipr_format_res_path(res_path, p, len - (buffer - p));
1242 return buffer;
1243}
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253static void ipr_update_res_entry(struct ipr_resource_entry *res,
1254 struct ipr_config_table_entry_wrapper *cfgtew)
1255{
1256 char buffer[IPR_MAX_RES_PATH_LENGTH];
1257 unsigned int proto;
1258 int new_path = 0;
1259
1260 if (res->ioa_cfg->sis64) {
1261 res->flags = cfgtew->u.cfgte64->flags;
1262 res->res_flags = cfgtew->u.cfgte64->res_flags;
1263 res->type = cfgtew->u.cfgte64->res_type;
1264
1265 memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data,
1266 sizeof(struct ipr_std_inq_data));
1267
1268 res->qmodel = IPR_QUEUEING_MODEL64(res);
1269 proto = cfgtew->u.cfgte64->proto;
1270 res->res_handle = cfgtew->u.cfgte64->res_handle;
1271 res->dev_id = cfgtew->u.cfgte64->dev_id;
1272
1273 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1274 sizeof(res->dev_lun.scsi_lun));
1275
1276 if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path,
1277 sizeof(res->res_path))) {
1278 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1279 sizeof(res->res_path));
1280 new_path = 1;
1281 }
1282
1283 if (res->sdev && new_path)
1284 sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
1285 ipr_format_res_path(res->ioa_cfg,
1286 res->res_path, buffer, sizeof(buffer)));
1287 } else {
1288 res->flags = cfgtew->u.cfgte->flags;
1289 if (res->flags & IPR_IS_IOA_RESOURCE)
1290 res->type = IPR_RES_TYPE_IOAFP;
1291 else
1292 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1293
1294 memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data,
1295 sizeof(struct ipr_std_inq_data));
1296
1297 res->qmodel = IPR_QUEUEING_MODEL(res);
1298 proto = cfgtew->u.cfgte->proto;
1299 res->res_handle = cfgtew->u.cfgte->res_handle;
1300 }
1301
1302 ipr_update_ata_class(res, proto);
1303}
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314static void ipr_clear_res_target(struct ipr_resource_entry *res)
1315{
1316 struct ipr_resource_entry *gscsi_res = NULL;
1317 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1318
1319 if (!ioa_cfg->sis64)
1320 return;
1321
1322 if (res->bus == IPR_ARRAY_VIRTUAL_BUS)
1323 clear_bit(res->target, ioa_cfg->array_ids);
1324 else if (res->bus == IPR_VSET_VIRTUAL_BUS)
1325 clear_bit(res->target, ioa_cfg->vset_ids);
1326 else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1327 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue)
1328 if (gscsi_res->dev_id == res->dev_id && gscsi_res != res)
1329 return;
1330 clear_bit(res->target, ioa_cfg->target_ids);
1331
1332 } else if (res->bus == 0)
1333 clear_bit(res->target, ioa_cfg->target_ids);
1334}
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
1345 struct ipr_hostrcb *hostrcb)
1346{
1347 struct ipr_resource_entry *res = NULL;
1348 struct ipr_config_table_entry_wrapper cfgtew;
1349 __be32 cc_res_handle;
1350
1351 u32 is_ndn = 1;
1352
1353 if (ioa_cfg->sis64) {
1354 cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64;
1355 cc_res_handle = cfgtew.u.cfgte64->res_handle;
1356 } else {
1357 cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte;
1358 cc_res_handle = cfgtew.u.cfgte->res_handle;
1359 }
1360
1361 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
1362 if (res->res_handle == cc_res_handle) {
1363 is_ndn = 0;
1364 break;
1365 }
1366 }
1367
1368 if (is_ndn) {
1369 if (list_empty(&ioa_cfg->free_res_q)) {
1370 ipr_send_hcam(ioa_cfg,
1371 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
1372 hostrcb);
1373 return;
1374 }
1375
1376 res = list_entry(ioa_cfg->free_res_q.next,
1377 struct ipr_resource_entry, queue);
1378
1379 list_del(&res->queue);
1380 ipr_init_res_entry(res, &cfgtew);
1381 list_add_tail(&res->queue, &ioa_cfg->used_res_q);
1382 }
1383
1384 ipr_update_res_entry(res, &cfgtew);
1385
1386 if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) {
1387 if (res->sdev) {
1388 res->del_from_ml = 1;
1389 res->res_handle = IPR_INVALID_RES_HANDLE;
1390 if (ioa_cfg->allow_ml_add_del)
1391 schedule_work(&ioa_cfg->work_q);
1392 } else {
1393 ipr_clear_res_target(res);
1394 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
1395 }
1396 } else if (!res->sdev || res->del_from_ml) {
1397 res->add_to_ml = 1;
1398 if (ioa_cfg->allow_ml_add_del)
1399 schedule_work(&ioa_cfg->work_q);
1400 }
1401
1402 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1403}
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd)
1416{
1417 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1418 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
1419 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
1420
1421 list_del(&hostrcb->queue);
1422 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
1423
1424 if (ioasc) {
1425 if (ioasc != IPR_IOASC_IOA_WAS_RESET)
1426 dev_err(&ioa_cfg->pdev->dev,
1427 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
1428
1429 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1430 } else {
1431 ipr_handle_config_change(ioa_cfg, hostrcb);
1432 }
1433}
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446static int strip_and_pad_whitespace(int i, char *buf)
1447{
1448 while (i && buf[i] == ' ')
1449 i--;
1450 buf[i+1] = ' ';
1451 buf[i+2] = '\0';
1452 return i + 2;
1453}
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1465 struct ipr_vpd *vpd)
1466{
1467 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3];
1468 int i = 0;
1469
1470 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1471 i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer);
1472
1473 memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN);
1474 i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer);
1475
1476 memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN);
1477 buffer[IPR_SERIAL_NUM_LEN + i] = '\0';
1478
1479 ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer);
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489static void ipr_log_vpd(struct ipr_vpd *vpd)
1490{
1491 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN
1492 + IPR_SERIAL_NUM_LEN];
1493
1494 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1495 memcpy(buffer + IPR_VENDOR_ID_LEN, vpd->vpids.product_id,
1496 IPR_PROD_ID_LEN);
1497 buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN] = '\0';
1498 ipr_err("Vendor/Product ID: %s\n", buffer);
1499
1500 memcpy(buffer, vpd->sn, IPR_SERIAL_NUM_LEN);
1501 buffer[IPR_SERIAL_NUM_LEN] = '\0';
1502 ipr_err(" Serial Number: %s\n", buffer);
1503}
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514static void ipr_log_ext_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1515 struct ipr_ext_vpd *vpd)
1516{
1517 ipr_log_vpd_compact(prefix, hostrcb, &vpd->vpd);
1518 ipr_hcam_err(hostrcb, "%s WWN: %08X%08X\n", prefix,
1519 be32_to_cpu(vpd->wwid[0]), be32_to_cpu(vpd->wwid[1]));
1520}
1521
1522
1523
1524
1525
1526
1527
1528
1529static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd)
1530{
1531 ipr_log_vpd(&vpd->vpd);
1532 ipr_err(" WWN: %08X%08X\n", be32_to_cpu(vpd->wwid[0]),
1533 be32_to_cpu(vpd->wwid[1]));
1534}
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1545 struct ipr_hostrcb *hostrcb)
1546{
1547 struct ipr_hostrcb_type_12_error *error;
1548
1549 if (ioa_cfg->sis64)
1550 error = &hostrcb->hcam.u.error64.u.type_12_error;
1551 else
1552 error = &hostrcb->hcam.u.error.u.type_12_error;
1553
1554 ipr_err("-----Current Configuration-----\n");
1555 ipr_err("Cache Directory Card Information:\n");
1556 ipr_log_ext_vpd(&error->ioa_vpd);
1557 ipr_err("Adapter Card Information:\n");
1558 ipr_log_ext_vpd(&error->cfc_vpd);
1559
1560 ipr_err("-----Expected Configuration-----\n");
1561 ipr_err("Cache Directory Card Information:\n");
1562 ipr_log_ext_vpd(&error->ioa_last_attached_to_cfc_vpd);
1563 ipr_err("Adapter Card Information:\n");
1564 ipr_log_ext_vpd(&error->cfc_last_attached_to_ioa_vpd);
1565
1566 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1567 be32_to_cpu(error->ioa_data[0]),
1568 be32_to_cpu(error->ioa_data[1]),
1569 be32_to_cpu(error->ioa_data[2]));
1570}
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580static void ipr_log_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1581 struct ipr_hostrcb *hostrcb)
1582{
1583 struct ipr_hostrcb_type_02_error *error =
1584 &hostrcb->hcam.u.error.u.type_02_error;
1585
1586 ipr_err("-----Current Configuration-----\n");
1587 ipr_err("Cache Directory Card Information:\n");
1588 ipr_log_vpd(&error->ioa_vpd);
1589 ipr_err("Adapter Card Information:\n");
1590 ipr_log_vpd(&error->cfc_vpd);
1591
1592 ipr_err("-----Expected Configuration-----\n");
1593 ipr_err("Cache Directory Card Information:\n");
1594 ipr_log_vpd(&error->ioa_last_attached_to_cfc_vpd);
1595 ipr_err("Adapter Card Information:\n");
1596 ipr_log_vpd(&error->cfc_last_attached_to_ioa_vpd);
1597
1598 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1599 be32_to_cpu(error->ioa_data[0]),
1600 be32_to_cpu(error->ioa_data[1]),
1601 be32_to_cpu(error->ioa_data[2]));
1602}
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg,
1613 struct ipr_hostrcb *hostrcb)
1614{
1615 int errors_logged, i;
1616 struct ipr_hostrcb_device_data_entry_enhanced *dev_entry;
1617 struct ipr_hostrcb_type_13_error *error;
1618
1619 error = &hostrcb->hcam.u.error.u.type_13_error;
1620 errors_logged = be32_to_cpu(error->errors_logged);
1621
1622 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1623 be32_to_cpu(error->errors_detected), errors_logged);
1624
1625 dev_entry = error->dev;
1626
1627 for (i = 0; i < errors_logged; i++, dev_entry++) {
1628 ipr_err_separator;
1629
1630 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1631 ipr_log_ext_vpd(&dev_entry->vpd);
1632
1633 ipr_err("-----New Device Information-----\n");
1634 ipr_log_ext_vpd(&dev_entry->new_vpd);
1635
1636 ipr_err("Cache Directory Card Information:\n");
1637 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1638
1639 ipr_err("Adapter Card Information:\n");
1640 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1641 }
1642}
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
1653 struct ipr_hostrcb *hostrcb)
1654{
1655 int errors_logged, i;
1656 struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry;
1657 struct ipr_hostrcb_type_23_error *error;
1658 char buffer[IPR_MAX_RES_PATH_LENGTH];
1659
1660 error = &hostrcb->hcam.u.error64.u.type_23_error;
1661 errors_logged = be32_to_cpu(error->errors_logged);
1662
1663 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1664 be32_to_cpu(error->errors_detected), errors_logged);
1665
1666 dev_entry = error->dev;
1667
1668 for (i = 0; i < errors_logged; i++, dev_entry++) {
1669 ipr_err_separator;
1670
1671 ipr_err("Device %d : %s", i + 1,
1672 __ipr_format_res_path(dev_entry->res_path,
1673 buffer, sizeof(buffer)));
1674 ipr_log_ext_vpd(&dev_entry->vpd);
1675
1676 ipr_err("-----New Device Information-----\n");
1677 ipr_log_ext_vpd(&dev_entry->new_vpd);
1678
1679 ipr_err("Cache Directory Card Information:\n");
1680 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1681
1682 ipr_err("Adapter Card Information:\n");
1683 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1684 }
1685}
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695static void ipr_log_config_error(struct ipr_ioa_cfg *ioa_cfg,
1696 struct ipr_hostrcb *hostrcb)
1697{
1698 int errors_logged, i;
1699 struct ipr_hostrcb_device_data_entry *dev_entry;
1700 struct ipr_hostrcb_type_03_error *error;
1701
1702 error = &hostrcb->hcam.u.error.u.type_03_error;
1703 errors_logged = be32_to_cpu(error->errors_logged);
1704
1705 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1706 be32_to_cpu(error->errors_detected), errors_logged);
1707
1708 dev_entry = error->dev;
1709
1710 for (i = 0; i < errors_logged; i++, dev_entry++) {
1711 ipr_err_separator;
1712
1713 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1714 ipr_log_vpd(&dev_entry->vpd);
1715
1716 ipr_err("-----New Device Information-----\n");
1717 ipr_log_vpd(&dev_entry->new_vpd);
1718
1719 ipr_err("Cache Directory Card Information:\n");
1720 ipr_log_vpd(&dev_entry->ioa_last_with_dev_vpd);
1721
1722 ipr_err("Adapter Card Information:\n");
1723 ipr_log_vpd(&dev_entry->cfc_last_with_dev_vpd);
1724
1725 ipr_err("Additional IOA Data: %08X %08X %08X %08X %08X\n",
1726 be32_to_cpu(dev_entry->ioa_data[0]),
1727 be32_to_cpu(dev_entry->ioa_data[1]),
1728 be32_to_cpu(dev_entry->ioa_data[2]),
1729 be32_to_cpu(dev_entry->ioa_data[3]),
1730 be32_to_cpu(dev_entry->ioa_data[4]));
1731 }
1732}
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742static void ipr_log_enhanced_array_error(struct ipr_ioa_cfg *ioa_cfg,
1743 struct ipr_hostrcb *hostrcb)
1744{
1745 int i, num_entries;
1746 struct ipr_hostrcb_type_14_error *error;
1747 struct ipr_hostrcb_array_data_entry_enhanced *array_entry;
1748 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1749
1750 error = &hostrcb->hcam.u.error.u.type_14_error;
1751
1752 ipr_err_separator;
1753
1754 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1755 error->protection_level,
1756 ioa_cfg->host->host_no,
1757 error->last_func_vset_res_addr.bus,
1758 error->last_func_vset_res_addr.target,
1759 error->last_func_vset_res_addr.lun);
1760
1761 ipr_err_separator;
1762
1763 array_entry = error->array_member;
1764 num_entries = min_t(u32, be32_to_cpu(error->num_entries),
1765 ARRAY_SIZE(error->array_member));
1766
1767 for (i = 0; i < num_entries; i++, array_entry++) {
1768 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1769 continue;
1770
1771 if (be32_to_cpu(error->exposed_mode_adn) == i)
1772 ipr_err("Exposed Array Member %d:\n", i);
1773 else
1774 ipr_err("Array Member %d:\n", i);
1775
1776 ipr_log_ext_vpd(&array_entry->vpd);
1777 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1778 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1779 "Expected Location");
1780
1781 ipr_err_separator;
1782 }
1783}
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793static void ipr_log_array_error(struct ipr_ioa_cfg *ioa_cfg,
1794 struct ipr_hostrcb *hostrcb)
1795{
1796 int i;
1797 struct ipr_hostrcb_type_04_error *error;
1798 struct ipr_hostrcb_array_data_entry *array_entry;
1799 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1800
1801 error = &hostrcb->hcam.u.error.u.type_04_error;
1802
1803 ipr_err_separator;
1804
1805 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1806 error->protection_level,
1807 ioa_cfg->host->host_no,
1808 error->last_func_vset_res_addr.bus,
1809 error->last_func_vset_res_addr.target,
1810 error->last_func_vset_res_addr.lun);
1811
1812 ipr_err_separator;
1813
1814 array_entry = error->array_member;
1815
1816 for (i = 0; i < 18; i++) {
1817 if (!memcmp(array_entry->vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1818 continue;
1819
1820 if (be32_to_cpu(error->exposed_mode_adn) == i)
1821 ipr_err("Exposed Array Member %d:\n", i);
1822 else
1823 ipr_err("Array Member %d:\n", i);
1824
1825 ipr_log_vpd(&array_entry->vpd);
1826
1827 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1828 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1829 "Expected Location");
1830
1831 ipr_err_separator;
1832
1833 if (i == 9)
1834 array_entry = error->array_member2;
1835 else
1836 array_entry++;
1837 }
1838}
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849static void ipr_log_hex_data(struct ipr_ioa_cfg *ioa_cfg, u32 *data, int len)
1850{
1851 int i;
1852
1853 if (len == 0)
1854 return;
1855
1856 if (ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
1857 len = min_t(int, len, IPR_DEFAULT_MAX_ERROR_DUMP);
1858
1859 for (i = 0; i < len / 4; i += 4) {
1860 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
1861 be32_to_cpu(data[i]),
1862 be32_to_cpu(data[i+1]),
1863 be32_to_cpu(data[i+2]),
1864 be32_to_cpu(data[i+3]));
1865 }
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1877 struct ipr_hostrcb *hostrcb)
1878{
1879 struct ipr_hostrcb_type_17_error *error;
1880
1881 if (ioa_cfg->sis64)
1882 error = &hostrcb->hcam.u.error64.u.type_17_error;
1883 else
1884 error = &hostrcb->hcam.u.error.u.type_17_error;
1885
1886 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1887 strim(error->failure_reason);
1888
1889 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1890 be32_to_cpu(hostrcb->hcam.u.error.prc));
1891 ipr_log_ext_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1892 ipr_log_hex_data(ioa_cfg, error->data,
1893 be32_to_cpu(hostrcb->hcam.length) -
1894 (offsetof(struct ipr_hostrcb_error, u) +
1895 offsetof(struct ipr_hostrcb_type_17_error, data)));
1896}
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906static void ipr_log_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1907 struct ipr_hostrcb *hostrcb)
1908{
1909 struct ipr_hostrcb_type_07_error *error;
1910
1911 error = &hostrcb->hcam.u.error.u.type_07_error;
1912 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1913 strim(error->failure_reason);
1914
1915 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1916 be32_to_cpu(hostrcb->hcam.u.error.prc));
1917 ipr_log_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1918 ipr_log_hex_data(ioa_cfg, error->data,
1919 be32_to_cpu(hostrcb->hcam.length) -
1920 (offsetof(struct ipr_hostrcb_error, u) +
1921 offsetof(struct ipr_hostrcb_type_07_error, data)));
1922}
1923
1924static const struct {
1925 u8 active;
1926 char *desc;
1927} path_active_desc[] = {
1928 { IPR_PATH_NO_INFO, "Path" },
1929 { IPR_PATH_ACTIVE, "Active path" },
1930 { IPR_PATH_NOT_ACTIVE, "Inactive path" }
1931};
1932
1933static const struct {
1934 u8 state;
1935 char *desc;
1936} path_state_desc[] = {
1937 { IPR_PATH_STATE_NO_INFO, "has no path state information available" },
1938 { IPR_PATH_HEALTHY, "is healthy" },
1939 { IPR_PATH_DEGRADED, "is degraded" },
1940 { IPR_PATH_FAILED, "is failed" }
1941};
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb,
1952 struct ipr_hostrcb_fabric_desc *fabric)
1953{
1954 int i, j;
1955 u8 path_state = fabric->path_state;
1956 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
1957 u8 state = path_state & IPR_PATH_STATE_MASK;
1958
1959 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
1960 if (path_active_desc[i].active != active)
1961 continue;
1962
1963 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
1964 if (path_state_desc[j].state != state)
1965 continue;
1966
1967 if (fabric->cascaded_expander == 0xff && fabric->phy == 0xff) {
1968 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d\n",
1969 path_active_desc[i].desc, path_state_desc[j].desc,
1970 fabric->ioa_port);
1971 } else if (fabric->cascaded_expander == 0xff) {
1972 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Phy=%d\n",
1973 path_active_desc[i].desc, path_state_desc[j].desc,
1974 fabric->ioa_port, fabric->phy);
1975 } else if (fabric->phy == 0xff) {
1976 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d\n",
1977 path_active_desc[i].desc, path_state_desc[j].desc,
1978 fabric->ioa_port, fabric->cascaded_expander);
1979 } else {
1980 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d, Phy=%d\n",
1981 path_active_desc[i].desc, path_state_desc[j].desc,
1982 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
1983 }
1984 return;
1985 }
1986 }
1987
1988 ipr_err("Path state=%02X IOA Port=%d Cascade=%d Phy=%d\n", path_state,
1989 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
1990}
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
2001 struct ipr_hostrcb64_fabric_desc *fabric)
2002{
2003 int i, j;
2004 u8 path_state = fabric->path_state;
2005 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2006 u8 state = path_state & IPR_PATH_STATE_MASK;
2007 char buffer[IPR_MAX_RES_PATH_LENGTH];
2008
2009 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2010 if (path_active_desc[i].active != active)
2011 continue;
2012
2013 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2014 if (path_state_desc[j].state != state)
2015 continue;
2016
2017 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
2018 path_active_desc[i].desc, path_state_desc[j].desc,
2019 ipr_format_res_path(hostrcb->ioa_cfg,
2020 fabric->res_path,
2021 buffer, sizeof(buffer)));
2022 return;
2023 }
2024 }
2025
2026 ipr_err("Path state=%02X Resource Path=%s\n", path_state,
2027 ipr_format_res_path(hostrcb->ioa_cfg, fabric->res_path,
2028 buffer, sizeof(buffer)));
2029}
2030
2031static const struct {
2032 u8 type;
2033 char *desc;
2034} path_type_desc[] = {
2035 { IPR_PATH_CFG_IOA_PORT, "IOA port" },
2036 { IPR_PATH_CFG_EXP_PORT, "Expander port" },
2037 { IPR_PATH_CFG_DEVICE_PORT, "Device port" },
2038 { IPR_PATH_CFG_DEVICE_LUN, "Device LUN" }
2039};
2040
2041static const struct {
2042 u8 status;
2043 char *desc;
2044} path_status_desc[] = {
2045 { IPR_PATH_CFG_NO_PROB, "Functional" },
2046 { IPR_PATH_CFG_DEGRADED, "Degraded" },
2047 { IPR_PATH_CFG_FAILED, "Failed" },
2048 { IPR_PATH_CFG_SUSPECT, "Suspect" },
2049 { IPR_PATH_NOT_DETECTED, "Missing" },
2050 { IPR_PATH_INCORRECT_CONN, "Incorrectly connected" }
2051};
2052
2053static const char *link_rate[] = {
2054 "unknown",
2055 "disabled",
2056 "phy reset problem",
2057 "spinup hold",
2058 "port selector",
2059 "unknown",
2060 "unknown",
2061 "unknown",
2062 "1.5Gbps",
2063 "3.0Gbps",
2064 "unknown",
2065 "unknown",
2066 "unknown",
2067 "unknown",
2068 "unknown",
2069 "unknown"
2070};
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb,
2081 struct ipr_hostrcb_config_element *cfg)
2082{
2083 int i, j;
2084 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2085 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2086
2087 if (type == IPR_PATH_CFG_NOT_EXIST)
2088 return;
2089
2090 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2091 if (path_type_desc[i].type != type)
2092 continue;
2093
2094 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2095 if (path_status_desc[j].status != status)
2096 continue;
2097
2098 if (type == IPR_PATH_CFG_IOA_PORT) {
2099 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, WWN=%08X%08X\n",
2100 path_status_desc[j].desc, path_type_desc[i].desc,
2101 cfg->phy, link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2102 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2103 } else {
2104 if (cfg->cascaded_expander == 0xff && cfg->phy == 0xff) {
2105 ipr_hcam_err(hostrcb, "%s %s: Link rate=%s, WWN=%08X%08X\n",
2106 path_status_desc[j].desc, path_type_desc[i].desc,
2107 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2108 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2109 } else if (cfg->cascaded_expander == 0xff) {
2110 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, "
2111 "WWN=%08X%08X\n", path_status_desc[j].desc,
2112 path_type_desc[i].desc, cfg->phy,
2113 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2114 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2115 } else if (cfg->phy == 0xff) {
2116 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Link rate=%s, "
2117 "WWN=%08X%08X\n", path_status_desc[j].desc,
2118 path_type_desc[i].desc, cfg->cascaded_expander,
2119 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2120 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2121 } else {
2122 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Phy=%d, Link rate=%s "
2123 "WWN=%08X%08X\n", path_status_desc[j].desc,
2124 path_type_desc[i].desc, cfg->cascaded_expander, cfg->phy,
2125 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2126 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2127 }
2128 }
2129 return;
2130 }
2131 }
2132
2133 ipr_hcam_err(hostrcb, "Path element=%02X: Cascade=%d Phy=%d Link rate=%s "
2134 "WWN=%08X%08X\n", cfg->type_status, cfg->cascaded_expander, cfg->phy,
2135 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2136 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2137}
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
2148 struct ipr_hostrcb64_config_element *cfg)
2149{
2150 int i, j;
2151 u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK;
2152 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2153 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2154 char buffer[IPR_MAX_RES_PATH_LENGTH];
2155
2156 if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64)
2157 return;
2158
2159 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2160 if (path_type_desc[i].type != type)
2161 continue;
2162
2163 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2164 if (path_status_desc[j].status != status)
2165 continue;
2166
2167 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
2168 path_status_desc[j].desc, path_type_desc[i].desc,
2169 ipr_format_res_path(hostrcb->ioa_cfg,
2170 cfg->res_path, buffer, sizeof(buffer)),
2171 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2172 be32_to_cpu(cfg->wwid[0]),
2173 be32_to_cpu(cfg->wwid[1]));
2174 return;
2175 }
2176 }
2177 ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
2178 "WWN=%08X%08X\n", cfg->type_status,
2179 ipr_format_res_path(hostrcb->ioa_cfg,
2180 cfg->res_path, buffer, sizeof(buffer)),
2181 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2182 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2183}
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2194 struct ipr_hostrcb *hostrcb)
2195{
2196 struct ipr_hostrcb_type_20_error *error;
2197 struct ipr_hostrcb_fabric_desc *fabric;
2198 struct ipr_hostrcb_config_element *cfg;
2199 int i, add_len;
2200
2201 error = &hostrcb->hcam.u.error.u.type_20_error;
2202 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2203 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2204
2205 add_len = be32_to_cpu(hostrcb->hcam.length) -
2206 (offsetof(struct ipr_hostrcb_error, u) +
2207 offsetof(struct ipr_hostrcb_type_20_error, desc));
2208
2209 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2210 ipr_log_fabric_path(hostrcb, fabric);
2211 for_each_fabric_cfg(fabric, cfg)
2212 ipr_log_path_elem(hostrcb, cfg);
2213
2214 add_len -= be16_to_cpu(fabric->length);
2215 fabric = (struct ipr_hostrcb_fabric_desc *)
2216 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2217 }
2218
2219 ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len);
2220}
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
2231 struct ipr_hostrcb *hostrcb)
2232{
2233 int i, num_entries;
2234 struct ipr_hostrcb_type_24_error *error;
2235 struct ipr_hostrcb64_array_data_entry *array_entry;
2236 char buffer[IPR_MAX_RES_PATH_LENGTH];
2237 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
2238
2239 error = &hostrcb->hcam.u.error64.u.type_24_error;
2240
2241 ipr_err_separator;
2242
2243 ipr_err("RAID %s Array Configuration: %s\n",
2244 error->protection_level,
2245 ipr_format_res_path(ioa_cfg, error->last_res_path,
2246 buffer, sizeof(buffer)));
2247
2248 ipr_err_separator;
2249
2250 array_entry = error->array_member;
2251 num_entries = min_t(u32, error->num_entries,
2252 ARRAY_SIZE(error->array_member));
2253
2254 for (i = 0; i < num_entries; i++, array_entry++) {
2255
2256 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
2257 continue;
2258
2259 if (error->exposed_mode_adn == i)
2260 ipr_err("Exposed Array Member %d:\n", i);
2261 else
2262 ipr_err("Array Member %d:\n", i);
2263
2264 ipr_err("Array Member %d:\n", i);
2265 ipr_log_ext_vpd(&array_entry->vpd);
2266 ipr_err("Current Location: %s\n",
2267 ipr_format_res_path(ioa_cfg, array_entry->res_path,
2268 buffer, sizeof(buffer)));
2269 ipr_err("Expected Location: %s\n",
2270 ipr_format_res_path(ioa_cfg,
2271 array_entry->expected_res_path,
2272 buffer, sizeof(buffer)));
2273
2274 ipr_err_separator;
2275 }
2276}
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2287 struct ipr_hostrcb *hostrcb)
2288{
2289 struct ipr_hostrcb_type_30_error *error;
2290 struct ipr_hostrcb64_fabric_desc *fabric;
2291 struct ipr_hostrcb64_config_element *cfg;
2292 int i, add_len;
2293
2294 error = &hostrcb->hcam.u.error64.u.type_30_error;
2295
2296 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2297 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2298
2299 add_len = be32_to_cpu(hostrcb->hcam.length) -
2300 (offsetof(struct ipr_hostrcb64_error, u) +
2301 offsetof(struct ipr_hostrcb_type_30_error, desc));
2302
2303 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2304 ipr_log64_fabric_path(hostrcb, fabric);
2305 for_each_fabric_cfg(fabric, cfg)
2306 ipr_log64_path_elem(hostrcb, cfg);
2307
2308 add_len -= be16_to_cpu(fabric->length);
2309 fabric = (struct ipr_hostrcb64_fabric_desc *)
2310 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2311 }
2312
2313 ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len);
2314}
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324static void ipr_log_generic_error(struct ipr_ioa_cfg *ioa_cfg,
2325 struct ipr_hostrcb *hostrcb)
2326{
2327 ipr_log_hex_data(ioa_cfg, hostrcb->hcam.u.raw.data,
2328 be32_to_cpu(hostrcb->hcam.length));
2329}
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342static u32 ipr_get_error(u32 ioasc)
2343{
2344 int i;
2345
2346 for (i = 0; i < ARRAY_SIZE(ipr_error_table); i++)
2347 if (ipr_error_table[i].ioasc == (ioasc & IPR_IOASC_IOASC_MASK))
2348 return i;
2349
2350 return 0;
2351}
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg,
2364 struct ipr_hostrcb *hostrcb)
2365{
2366 u32 ioasc;
2367 int error_index;
2368
2369 if (hostrcb->hcam.notify_type != IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY)
2370 return;
2371
2372 if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST)
2373 dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n");
2374
2375 if (ioa_cfg->sis64)
2376 ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2377 else
2378 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2379
2380 if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET ||
2381 ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) {
2382
2383 scsi_report_bus_reset(ioa_cfg->host,
2384 hostrcb->hcam.u.error.fd_res_addr.bus);
2385 }
2386
2387 error_index = ipr_get_error(ioasc);
2388
2389 if (!ipr_error_table[error_index].log_hcam)
2390 return;
2391
2392 ipr_hcam_err(hostrcb, "%s\n", ipr_error_table[error_index].error);
2393
2394
2395 ioa_cfg->errors_logged++;
2396
2397 if (ioa_cfg->log_level < ipr_error_table[error_index].log_hcam)
2398 return;
2399 if (be32_to_cpu(hostrcb->hcam.length) > sizeof(hostrcb->hcam.u.raw))
2400 hostrcb->hcam.length = cpu_to_be32(sizeof(hostrcb->hcam.u.raw));
2401
2402 switch (hostrcb->hcam.overlay_id) {
2403 case IPR_HOST_RCB_OVERLAY_ID_2:
2404 ipr_log_cache_error(ioa_cfg, hostrcb);
2405 break;
2406 case IPR_HOST_RCB_OVERLAY_ID_3:
2407 ipr_log_config_error(ioa_cfg, hostrcb);
2408 break;
2409 case IPR_HOST_RCB_OVERLAY_ID_4:
2410 case IPR_HOST_RCB_OVERLAY_ID_6:
2411 ipr_log_array_error(ioa_cfg, hostrcb);
2412 break;
2413 case IPR_HOST_RCB_OVERLAY_ID_7:
2414 ipr_log_dual_ioa_error(ioa_cfg, hostrcb);
2415 break;
2416 case IPR_HOST_RCB_OVERLAY_ID_12:
2417 ipr_log_enhanced_cache_error(ioa_cfg, hostrcb);
2418 break;
2419 case IPR_HOST_RCB_OVERLAY_ID_13:
2420 ipr_log_enhanced_config_error(ioa_cfg, hostrcb);
2421 break;
2422 case IPR_HOST_RCB_OVERLAY_ID_14:
2423 case IPR_HOST_RCB_OVERLAY_ID_16:
2424 ipr_log_enhanced_array_error(ioa_cfg, hostrcb);
2425 break;
2426 case IPR_HOST_RCB_OVERLAY_ID_17:
2427 ipr_log_enhanced_dual_ioa_error(ioa_cfg, hostrcb);
2428 break;
2429 case IPR_HOST_RCB_OVERLAY_ID_20:
2430 ipr_log_fabric_error(ioa_cfg, hostrcb);
2431 break;
2432 case IPR_HOST_RCB_OVERLAY_ID_23:
2433 ipr_log_sis64_config_error(ioa_cfg, hostrcb);
2434 break;
2435 case IPR_HOST_RCB_OVERLAY_ID_24:
2436 case IPR_HOST_RCB_OVERLAY_ID_26:
2437 ipr_log_sis64_array_error(ioa_cfg, hostrcb);
2438 break;
2439 case IPR_HOST_RCB_OVERLAY_ID_30:
2440 ipr_log_sis64_fabric_error(ioa_cfg, hostrcb);
2441 break;
2442 case IPR_HOST_RCB_OVERLAY_ID_1:
2443 case IPR_HOST_RCB_OVERLAY_ID_DEFAULT:
2444 default:
2445 ipr_log_generic_error(ioa_cfg, hostrcb);
2446 break;
2447 }
2448}
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2462{
2463 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2464 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2465 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2466 u32 fd_ioasc;
2467
2468 if (ioa_cfg->sis64)
2469 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2470 else
2471 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2472
2473 list_del(&hostrcb->queue);
2474 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
2475
2476 if (!ioasc) {
2477 ipr_handle_log_data(ioa_cfg, hostrcb);
2478 if (fd_ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED)
2479 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
2480 } else if (ioasc != IPR_IOASC_IOA_WAS_RESET) {
2481 dev_err(&ioa_cfg->pdev->dev,
2482 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
2483 }
2484
2485 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2486}
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498static void ipr_timeout(struct ipr_cmnd *ipr_cmd)
2499{
2500 unsigned long lock_flags = 0;
2501 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2502
2503 ENTER;
2504 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2505
2506 ioa_cfg->errors_logged++;
2507 dev_err(&ioa_cfg->pdev->dev,
2508 "Adapter being reset due to command timeout.\n");
2509
2510 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2511 ioa_cfg->sdt_state = GET_DUMP;
2512
2513 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd)
2514 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2515
2516 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2517 LEAVE;
2518}
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530static void ipr_oper_timeout(struct ipr_cmnd *ipr_cmd)
2531{
2532 unsigned long lock_flags = 0;
2533 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2534
2535 ENTER;
2536 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2537
2538 ioa_cfg->errors_logged++;
2539 dev_err(&ioa_cfg->pdev->dev,
2540 "Adapter timed out transitioning to operational.\n");
2541
2542 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2543 ioa_cfg->sdt_state = GET_DUMP;
2544
2545 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd) {
2546 if (ipr_fastfail)
2547 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
2548 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2549 }
2550
2551 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2552 LEAVE;
2553}
2554
2555
2556
2557
2558
2559
2560
2561
2562static const struct ipr_ses_table_entry *
2563ipr_find_ses_entry(struct ipr_resource_entry *res)
2564{
2565 int i, j, matches;
2566 struct ipr_std_inq_vpids *vpids;
2567 const struct ipr_ses_table_entry *ste = ipr_ses_table;
2568
2569 for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) {
2570 for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) {
2571 if (ste->compare_product_id_byte[j] == 'X') {
2572 vpids = &res->std_inq_data.vpids;
2573 if (vpids->product_id[j] == ste->product_id[j])
2574 matches++;
2575 else
2576 break;
2577 } else
2578 matches++;
2579 }
2580
2581 if (matches == IPR_PROD_ID_LEN)
2582 return ste;
2583 }
2584
2585 return NULL;
2586}
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_width)
2601{
2602 struct ipr_resource_entry *res;
2603 const struct ipr_ses_table_entry *ste;
2604 u32 max_xfer_rate = IPR_MAX_SCSI_RATE(bus_width);
2605
2606
2607 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
2608 if (!(IPR_IS_SES_DEVICE(res->std_inq_data)))
2609 continue;
2610
2611 if (bus != res->bus)
2612 continue;
2613
2614 if (!(ste = ipr_find_ses_entry(res)))
2615 continue;
2616
2617 max_xfer_rate = (ste->max_bus_speed_limit * 10) / (bus_width / 8);
2618 }
2619
2620 return max_xfer_rate;
2621}
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay)
2634{
2635 volatile u32 pcii_reg;
2636 int delay = 1;
2637
2638
2639 while (delay < max_delay) {
2640 pcii_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
2641
2642 if (pcii_reg & IPR_PCII_IO_DEBUG_ACKNOWLEDGE)
2643 return 0;
2644
2645
2646 if ((delay / 1000) > MAX_UDELAY_MS)
2647 mdelay(delay / 1000);
2648 else
2649 udelay(delay);
2650
2651 delay += delay;
2652 }
2653 return -EIO;
2654}
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2667 u32 start_addr,
2668 __be32 *dest, u32 length_in_words)
2669{
2670 int i;
2671
2672 for (i = 0; i < length_in_words; i++) {
2673 writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
2674 *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg));
2675 dest++;
2676 }
2677
2678 return 0;
2679}
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2692 u32 start_addr,
2693 __be32 *dest, u32 length_in_words)
2694{
2695 volatile u32 temp_pcii_reg;
2696 int i, delay = 0;
2697
2698 if (ioa_cfg->sis64)
2699 return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr,
2700 dest, length_in_words);
2701
2702
2703 writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
2704 ioa_cfg->regs.set_uproc_interrupt_reg32);
2705
2706
2707 if (ipr_wait_iodbg_ack(ioa_cfg,
2708 IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC)) {
2709 dev_err(&ioa_cfg->pdev->dev,
2710 "IOA dump long data transfer timeout\n");
2711 return -EIO;
2712 }
2713
2714
2715 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2716 ioa_cfg->regs.clr_interrupt_reg);
2717
2718
2719 writel(start_addr, ioa_cfg->ioa_mailbox);
2720
2721
2722 writel(IPR_UPROCI_RESET_ALERT,
2723 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2724
2725 for (i = 0; i < length_in_words; i++) {
2726
2727 if (ipr_wait_iodbg_ack(ioa_cfg,
2728 IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC)) {
2729 dev_err(&ioa_cfg->pdev->dev,
2730 "IOA dump short data transfer timeout\n");
2731 return -EIO;
2732 }
2733
2734
2735 *dest = cpu_to_be32(readl(ioa_cfg->ioa_mailbox));
2736 dest++;
2737
2738
2739 if (i < (length_in_words - 1)) {
2740
2741 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2742 ioa_cfg->regs.clr_interrupt_reg);
2743 }
2744 }
2745
2746
2747 writel(IPR_UPROCI_RESET_ALERT,
2748 ioa_cfg->regs.set_uproc_interrupt_reg32);
2749
2750 writel(IPR_UPROCI_IO_DEBUG_ALERT,
2751 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2752
2753
2754 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2755 ioa_cfg->regs.clr_interrupt_reg);
2756
2757
2758 while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
2759 temp_pcii_reg =
2760 readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
2761
2762 if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
2763 return 0;
2764
2765 udelay(10);
2766 delay += 10;
2767 }
2768
2769 return 0;
2770}
2771
2772#ifdef CONFIG_SCSI_IPR_DUMP
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784static int ipr_sdt_copy(struct ipr_ioa_cfg *ioa_cfg,
2785 unsigned long pci_address, u32 length)
2786{
2787 int bytes_copied = 0;
2788 int cur_len, rc, rem_len, rem_page_len, max_dump_size;
2789 __be32 *page;
2790 unsigned long lock_flags = 0;
2791 struct ipr_ioa_dump *ioa_dump = &ioa_cfg->dump->ioa_dump;
2792
2793 if (ioa_cfg->sis64)
2794 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2795 else
2796 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2797
2798 while (bytes_copied < length &&
2799 (ioa_dump->hdr.len + bytes_copied) < max_dump_size) {
2800 if (ioa_dump->page_offset >= PAGE_SIZE ||
2801 ioa_dump->page_offset == 0) {
2802 page = (__be32 *)__get_free_page(GFP_ATOMIC);
2803
2804 if (!page) {
2805 ipr_trace;
2806 return bytes_copied;
2807 }
2808
2809 ioa_dump->page_offset = 0;
2810 ioa_dump->ioa_data[ioa_dump->next_page_index] = page;
2811 ioa_dump->next_page_index++;
2812 } else
2813 page = ioa_dump->ioa_data[ioa_dump->next_page_index - 1];
2814
2815 rem_len = length - bytes_copied;
2816 rem_page_len = PAGE_SIZE - ioa_dump->page_offset;
2817 cur_len = min(rem_len, rem_page_len);
2818
2819 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2820 if (ioa_cfg->sdt_state == ABORT_DUMP) {
2821 rc = -EIO;
2822 } else {
2823 rc = ipr_get_ldump_data_section(ioa_cfg,
2824 pci_address + bytes_copied,
2825 &page[ioa_dump->page_offset / 4],
2826 (cur_len / sizeof(u32)));
2827 }
2828 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2829
2830 if (!rc) {
2831 ioa_dump->page_offset += cur_len;
2832 bytes_copied += cur_len;
2833 } else {
2834 ipr_trace;
2835 break;
2836 }
2837 schedule();
2838 }
2839
2840 return bytes_copied;
2841}
2842
2843
2844
2845
2846
2847
2848
2849
2850static void ipr_init_dump_entry_hdr(struct ipr_dump_entry_header *hdr)
2851{
2852 hdr->eye_catcher = IPR_DUMP_EYE_CATCHER;
2853 hdr->num_elems = 1;
2854 hdr->offset = sizeof(*hdr);
2855 hdr->status = IPR_DUMP_STATUS_SUCCESS;
2856}
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866static void ipr_dump_ioa_type_data(struct ipr_ioa_cfg *ioa_cfg,
2867 struct ipr_driver_dump *driver_dump)
2868{
2869 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
2870
2871 ipr_init_dump_entry_hdr(&driver_dump->ioa_type_entry.hdr);
2872 driver_dump->ioa_type_entry.hdr.len =
2873 sizeof(struct ipr_dump_ioa_type_entry) -
2874 sizeof(struct ipr_dump_entry_header);
2875 driver_dump->ioa_type_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2876 driver_dump->ioa_type_entry.hdr.id = IPR_DUMP_DRIVER_TYPE_ID;
2877 driver_dump->ioa_type_entry.type = ioa_cfg->type;
2878 driver_dump->ioa_type_entry.fw_version = (ucode_vpd->major_release << 24) |
2879 (ucode_vpd->card_type << 16) | (ucode_vpd->minor_release[0] << 8) |
2880 ucode_vpd->minor_release[1];
2881 driver_dump->hdr.num_entries++;
2882}
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892static void ipr_dump_version_data(struct ipr_ioa_cfg *ioa_cfg,
2893 struct ipr_driver_dump *driver_dump)
2894{
2895 ipr_init_dump_entry_hdr(&driver_dump->version_entry.hdr);
2896 driver_dump->version_entry.hdr.len =
2897 sizeof(struct ipr_dump_version_entry) -
2898 sizeof(struct ipr_dump_entry_header);
2899 driver_dump->version_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
2900 driver_dump->version_entry.hdr.id = IPR_DUMP_DRIVER_VERSION_ID;
2901 strcpy(driver_dump->version_entry.version, IPR_DRIVER_VERSION);
2902 driver_dump->hdr.num_entries++;
2903}
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913static void ipr_dump_trace_data(struct ipr_ioa_cfg *ioa_cfg,
2914 struct ipr_driver_dump *driver_dump)
2915{
2916 ipr_init_dump_entry_hdr(&driver_dump->trace_entry.hdr);
2917 driver_dump->trace_entry.hdr.len =
2918 sizeof(struct ipr_dump_trace_entry) -
2919 sizeof(struct ipr_dump_entry_header);
2920 driver_dump->trace_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2921 driver_dump->trace_entry.hdr.id = IPR_DUMP_TRACE_ID;
2922 memcpy(driver_dump->trace_entry.trace, ioa_cfg->trace, IPR_TRACE_SIZE);
2923 driver_dump->hdr.num_entries++;
2924}
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg,
2935 struct ipr_driver_dump *driver_dump)
2936{
2937 ipr_init_dump_entry_hdr(&driver_dump->location_entry.hdr);
2938 driver_dump->location_entry.hdr.len =
2939 sizeof(struct ipr_dump_location_entry) -
2940 sizeof(struct ipr_dump_entry_header);
2941 driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
2942 driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID;
2943 strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev));
2944 driver_dump->hdr.num_entries++;
2945}
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump)
2956{
2957 unsigned long start_addr, sdt_word;
2958 unsigned long lock_flags = 0;
2959 struct ipr_driver_dump *driver_dump = &dump->driver_dump;
2960 struct ipr_ioa_dump *ioa_dump = &dump->ioa_dump;
2961 u32 num_entries, max_num_entries, start_off, end_off;
2962 u32 max_dump_size, bytes_to_copy, bytes_copied, rc;
2963 struct ipr_sdt *sdt;
2964 int valid = 1;
2965 int i;
2966
2967 ENTER;
2968
2969 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2970
2971 if (ioa_cfg->sdt_state != READ_DUMP) {
2972 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2973 return;
2974 }
2975
2976 if (ioa_cfg->sis64) {
2977 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2978 ssleep(IPR_DUMP_DELAY_SECONDS);
2979 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2980 }
2981
2982 start_addr = readl(ioa_cfg->ioa_mailbox);
2983
2984 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) {
2985 dev_err(&ioa_cfg->pdev->dev,
2986 "Invalid dump table format: %lx\n", start_addr);
2987 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2988 return;
2989 }
2990
2991 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA initiated\n");
2992
2993 driver_dump->hdr.eye_catcher = IPR_DUMP_EYE_CATCHER;
2994
2995
2996 driver_dump->hdr.len = sizeof(struct ipr_driver_dump);
2997 driver_dump->hdr.num_entries = 1;
2998 driver_dump->hdr.first_entry_offset = sizeof(struct ipr_dump_header);
2999 driver_dump->hdr.status = IPR_DUMP_STATUS_SUCCESS;
3000 driver_dump->hdr.os = IPR_DUMP_OS_LINUX;
3001 driver_dump->hdr.driver_name = IPR_DUMP_DRIVER_NAME;
3002
3003 ipr_dump_version_data(ioa_cfg, driver_dump);
3004 ipr_dump_location_data(ioa_cfg, driver_dump);
3005 ipr_dump_ioa_type_data(ioa_cfg, driver_dump);
3006 ipr_dump_trace_data(ioa_cfg, driver_dump);
3007
3008
3009 driver_dump->hdr.len += sizeof(struct ipr_dump_entry_header);
3010
3011
3012 ipr_init_dump_entry_hdr(&ioa_dump->hdr);
3013 ioa_dump->hdr.len = 0;
3014 ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3015 ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID;
3016
3017
3018
3019
3020
3021 sdt = &ioa_dump->sdt;
3022
3023 if (ioa_cfg->sis64) {
3024 max_num_entries = IPR_FMT3_NUM_SDT_ENTRIES;
3025 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
3026 } else {
3027 max_num_entries = IPR_FMT2_NUM_SDT_ENTRIES;
3028 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
3029 }
3030
3031 bytes_to_copy = offsetof(struct ipr_sdt, entry) +
3032 (max_num_entries * sizeof(struct ipr_sdt_entry));
3033 rc = ipr_get_ldump_data_section(ioa_cfg, start_addr, (__be32 *)sdt,
3034 bytes_to_copy / sizeof(__be32));
3035
3036
3037 if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
3038 (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
3039 dev_err(&ioa_cfg->pdev->dev,
3040 "Dump of IOA failed. Dump table not valid: %d, %X.\n",
3041 rc, be32_to_cpu(sdt->hdr.state));
3042 driver_dump->hdr.status = IPR_DUMP_STATUS_FAILED;
3043 ioa_cfg->sdt_state = DUMP_OBTAINED;
3044 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3045 return;
3046 }
3047
3048 num_entries = be32_to_cpu(sdt->hdr.num_entries_used);
3049
3050 if (num_entries > max_num_entries)
3051 num_entries = max_num_entries;
3052
3053
3054 dump->driver_dump.hdr.len += sizeof(struct ipr_sdt_header);
3055 if (ioa_cfg->sis64)
3056 dump->driver_dump.hdr.len += num_entries * sizeof(struct ipr_sdt_entry);
3057 else
3058 dump->driver_dump.hdr.len += max_num_entries * sizeof(struct ipr_sdt_entry);
3059
3060 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3061
3062 for (i = 0; i < num_entries; i++) {
3063 if (ioa_dump->hdr.len > max_dump_size) {
3064 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3065 break;
3066 }
3067
3068 if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) {
3069 sdt_word = be32_to_cpu(sdt->entry[i].start_token);
3070 if (ioa_cfg->sis64)
3071 bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token);
3072 else {
3073 start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK;
3074 end_off = be32_to_cpu(sdt->entry[i].end_token);
3075
3076 if (ipr_sdt_is_fmt2(sdt_word) && sdt_word)
3077 bytes_to_copy = end_off - start_off;
3078 else
3079 valid = 0;
3080 }
3081 if (valid) {
3082 if (bytes_to_copy > max_dump_size) {
3083 sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY;
3084 continue;
3085 }
3086
3087
3088 bytes_copied = ipr_sdt_copy(ioa_cfg, sdt_word,
3089 bytes_to_copy);
3090
3091 ioa_dump->hdr.len += bytes_copied;
3092
3093 if (bytes_copied != bytes_to_copy) {
3094 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3095 break;
3096 }
3097 }
3098 }
3099 }
3100
3101 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA completed.\n");
3102
3103
3104 driver_dump->hdr.len += ioa_dump->hdr.len;
3105 wmb();
3106 ioa_cfg->sdt_state = DUMP_OBTAINED;
3107 LEAVE;
3108}
3109
3110#else
3111#define ipr_get_ioa_dump(ioa_cfg, dump) do { } while (0)
3112#endif
3113
3114
3115
3116
3117
3118
3119
3120
3121static void ipr_release_dump(struct kref *kref)
3122{
3123 struct ipr_dump *dump = container_of(kref, struct ipr_dump, kref);
3124 struct ipr_ioa_cfg *ioa_cfg = dump->ioa_cfg;
3125 unsigned long lock_flags = 0;
3126 int i;
3127
3128 ENTER;
3129 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3130 ioa_cfg->dump = NULL;
3131 ioa_cfg->sdt_state = INACTIVE;
3132 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3133
3134 for (i = 0; i < dump->ioa_dump.next_page_index; i++)
3135 free_page((unsigned long) dump->ioa_dump.ioa_data[i]);
3136
3137 vfree(dump->ioa_dump.ioa_data);
3138 kfree(dump);
3139 LEAVE;
3140}
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153static void ipr_worker_thread(struct work_struct *work)
3154{
3155 unsigned long lock_flags;
3156 struct ipr_resource_entry *res;
3157 struct scsi_device *sdev;
3158 struct ipr_dump *dump;
3159 struct ipr_ioa_cfg *ioa_cfg =
3160 container_of(work, struct ipr_ioa_cfg, work_q);
3161 u8 bus, target, lun;
3162 int did_work;
3163
3164 ENTER;
3165 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3166
3167 if (ioa_cfg->sdt_state == READ_DUMP) {
3168 dump = ioa_cfg->dump;
3169 if (!dump) {
3170 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3171 return;
3172 }
3173 kref_get(&dump->kref);
3174 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3175 ipr_get_ioa_dump(ioa_cfg, dump);
3176 kref_put(&dump->kref, ipr_release_dump);
3177
3178 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3179 if (ioa_cfg->sdt_state == DUMP_OBTAINED && !ioa_cfg->dump_timeout)
3180 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3181 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3182 return;
3183 }
3184
3185restart:
3186 do {
3187 did_work = 0;
3188 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds ||
3189 !ioa_cfg->allow_ml_add_del) {
3190 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3191 return;
3192 }
3193
3194 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3195 if (res->del_from_ml && res->sdev) {
3196 did_work = 1;
3197 sdev = res->sdev;
3198 if (!scsi_device_get(sdev)) {
3199 if (!res->add_to_ml)
3200 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
3201 else
3202 res->del_from_ml = 0;
3203 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3204 scsi_remove_device(sdev);
3205 scsi_device_put(sdev);
3206 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3207 }
3208 break;
3209 }
3210 }
3211 } while (did_work);
3212
3213 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3214 if (res->add_to_ml) {
3215 bus = res->bus;
3216 target = res->target;
3217 lun = res->lun;
3218 res->add_to_ml = 0;
3219 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3220 scsi_add_device(ioa_cfg->host, bus, target, lun);
3221 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3222 goto restart;
3223 }
3224 }
3225
3226 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3227 kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
3228 LEAVE;
3229}
3230
3231#ifdef CONFIG_SCSI_IPR_TRACE
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244static ssize_t ipr_read_trace(struct file *filp, struct kobject *kobj,
3245 struct bin_attribute *bin_attr,
3246 char *buf, loff_t off, size_t count)
3247{
3248 struct device *dev = container_of(kobj, struct device, kobj);
3249 struct Scsi_Host *shost = class_to_shost(dev);
3250 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3251 unsigned long lock_flags = 0;
3252 ssize_t ret;
3253
3254 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3255 ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
3256 IPR_TRACE_SIZE);
3257 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3258
3259 return ret;
3260}
3261
3262static struct bin_attribute ipr_trace_attr = {
3263 .attr = {
3264 .name = "trace",
3265 .mode = S_IRUGO,
3266 },
3267 .size = 0,
3268 .read = ipr_read_trace,
3269};
3270#endif
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280static ssize_t ipr_show_fw_version(struct device *dev,
3281 struct device_attribute *attr, char *buf)
3282{
3283 struct Scsi_Host *shost = class_to_shost(dev);
3284 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3285 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3286 unsigned long lock_flags = 0;
3287 int len;
3288
3289 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3290 len = snprintf(buf, PAGE_SIZE, "%02X%02X%02X%02X\n",
3291 ucode_vpd->major_release, ucode_vpd->card_type,
3292 ucode_vpd->minor_release[0],
3293 ucode_vpd->minor_release[1]);
3294 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3295 return len;
3296}
3297
3298static struct device_attribute ipr_fw_version_attr = {
3299 .attr = {
3300 .name = "fw_version",
3301 .mode = S_IRUGO,
3302 },
3303 .show = ipr_show_fw_version,
3304};
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314static ssize_t ipr_show_log_level(struct device *dev,
3315 struct device_attribute *attr, char *buf)
3316{
3317 struct Scsi_Host *shost = class_to_shost(dev);
3318 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3319 unsigned long lock_flags = 0;
3320 int len;
3321
3322 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3323 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->log_level);
3324 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3325 return len;
3326}
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336static ssize_t ipr_store_log_level(struct device *dev,
3337 struct device_attribute *attr,
3338 const char *buf, size_t count)
3339{
3340 struct Scsi_Host *shost = class_to_shost(dev);
3341 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3342 unsigned long lock_flags = 0;
3343
3344 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3345 ioa_cfg->log_level = simple_strtoul(buf, NULL, 10);
3346 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3347 return strlen(buf);
3348}
3349
3350static struct device_attribute ipr_log_level_attr = {
3351 .attr = {
3352 .name = "log_level",
3353 .mode = S_IRUGO | S_IWUSR,
3354 },
3355 .show = ipr_show_log_level,
3356 .store = ipr_store_log_level
3357};
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371static ssize_t ipr_store_diagnostics(struct device *dev,
3372 struct device_attribute *attr,
3373 const char *buf, size_t count)
3374{
3375 struct Scsi_Host *shost = class_to_shost(dev);
3376 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3377 unsigned long lock_flags = 0;
3378 int rc = count;
3379
3380 if (!capable(CAP_SYS_ADMIN))
3381 return -EACCES;
3382
3383 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3384 while (ioa_cfg->in_reset_reload) {
3385 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3386 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3387 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3388 }
3389
3390 ioa_cfg->errors_logged = 0;
3391 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3392
3393 if (ioa_cfg->in_reset_reload) {
3394 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3395 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3396
3397
3398 msleep(1000);
3399 } else {
3400 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3401 return -EIO;
3402 }
3403
3404 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3405 if (ioa_cfg->in_reset_reload || ioa_cfg->errors_logged)
3406 rc = -EIO;
3407 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3408
3409 return rc;
3410}
3411
3412static struct device_attribute ipr_diagnostics_attr = {
3413 .attr = {
3414 .name = "run_diagnostics",
3415 .mode = S_IWUSR,
3416 },
3417 .store = ipr_store_diagnostics
3418};
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428static ssize_t ipr_show_adapter_state(struct device *dev,
3429 struct device_attribute *attr, char *buf)
3430{
3431 struct Scsi_Host *shost = class_to_shost(dev);
3432 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3433 unsigned long lock_flags = 0;
3434 int len;
3435
3436 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3437 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
3438 len = snprintf(buf, PAGE_SIZE, "offline\n");
3439 else
3440 len = snprintf(buf, PAGE_SIZE, "online\n");
3441 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3442 return len;
3443}
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456static ssize_t ipr_store_adapter_state(struct device *dev,
3457 struct device_attribute *attr,
3458 const char *buf, size_t count)
3459{
3460 struct Scsi_Host *shost = class_to_shost(dev);
3461 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3462 unsigned long lock_flags;
3463 int result = count, i;
3464
3465 if (!capable(CAP_SYS_ADMIN))
3466 return -EACCES;
3467
3468 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3469 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead &&
3470 !strncmp(buf, "online", 6)) {
3471 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
3472 spin_lock(&ioa_cfg->hrrq[i]._lock);
3473 ioa_cfg->hrrq[i].ioa_is_dead = 0;
3474 spin_unlock(&ioa_cfg->hrrq[i]._lock);
3475 }
3476 wmb();
3477 ioa_cfg->reset_retries = 0;
3478 ioa_cfg->in_ioa_bringdown = 0;
3479 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3480 }
3481 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3482 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3483
3484 return result;
3485}
3486
3487static struct device_attribute ipr_ioa_state_attr = {
3488 .attr = {
3489 .name = "online_state",
3490 .mode = S_IRUGO | S_IWUSR,
3491 },
3492 .show = ipr_show_adapter_state,
3493 .store = ipr_store_adapter_state
3494};
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507static ssize_t ipr_store_reset_adapter(struct device *dev,
3508 struct device_attribute *attr,
3509 const char *buf, size_t count)
3510{
3511 struct Scsi_Host *shost = class_to_shost(dev);
3512 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3513 unsigned long lock_flags;
3514 int result = count;
3515
3516 if (!capable(CAP_SYS_ADMIN))
3517 return -EACCES;
3518
3519 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3520 if (!ioa_cfg->in_reset_reload)
3521 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3522 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3523 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3524
3525 return result;
3526}
3527
3528static struct device_attribute ipr_ioa_reset_attr = {
3529 .attr = {
3530 .name = "reset_host",
3531 .mode = S_IWUSR,
3532 },
3533 .store = ipr_store_reset_adapter
3534};
3535
3536static int ipr_iopoll(struct blk_iopoll *iop, int budget);
3537
3538
3539
3540
3541
3542
3543
3544
3545static ssize_t ipr_show_iopoll_weight(struct device *dev,
3546 struct device_attribute *attr, char *buf)
3547{
3548 struct Scsi_Host *shost = class_to_shost(dev);
3549 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3550 unsigned long lock_flags = 0;
3551 int len;
3552
3553 spin_lock_irqsave(shost->host_lock, lock_flags);
3554 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->iopoll_weight);
3555 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3556
3557 return len;
3558}
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568static ssize_t ipr_store_iopoll_weight(struct device *dev,
3569 struct device_attribute *attr,
3570 const char *buf, size_t count)
3571{
3572 struct Scsi_Host *shost = class_to_shost(dev);
3573 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3574 unsigned long user_iopoll_weight;
3575 unsigned long lock_flags = 0;
3576 int i;
3577
3578 if (!ioa_cfg->sis64) {
3579 dev_info(&ioa_cfg->pdev->dev, "blk-iopoll not supported on this adapter\n");
3580 return -EINVAL;
3581 }
3582 if (kstrtoul(buf, 10, &user_iopoll_weight))
3583 return -EINVAL;
3584
3585 if (user_iopoll_weight > 256) {
3586 dev_info(&ioa_cfg->pdev->dev, "Invalid blk-iopoll weight. It must be less than 256\n");
3587 return -EINVAL;
3588 }
3589
3590 if (user_iopoll_weight == ioa_cfg->iopoll_weight) {
3591 dev_info(&ioa_cfg->pdev->dev, "Current blk-iopoll weight has the same weight\n");
3592 return strlen(buf);
3593 }
3594
3595 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
3596 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3597 for (i = 1; i < ioa_cfg->hrrq_num; i++)
3598 blk_iopoll_disable(&ioa_cfg->hrrq[i].iopoll);
3599 }
3600
3601 spin_lock_irqsave(shost->host_lock, lock_flags);
3602 ioa_cfg->iopoll_weight = user_iopoll_weight;
3603 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
3604 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3605 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
3606 blk_iopoll_init(&ioa_cfg->hrrq[i].iopoll,
3607 ioa_cfg->iopoll_weight, ipr_iopoll);
3608 blk_iopoll_enable(&ioa_cfg->hrrq[i].iopoll);
3609 }
3610 }
3611 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3612
3613 return strlen(buf);
3614}
3615
3616static struct device_attribute ipr_iopoll_weight_attr = {
3617 .attr = {
3618 .name = "iopoll_weight",
3619 .mode = S_IRUGO | S_IWUSR,
3620 },
3621 .show = ipr_show_iopoll_weight,
3622 .store = ipr_store_iopoll_weight
3623};
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635static struct ipr_sglist *ipr_alloc_ucode_buffer(int buf_len)
3636{
3637 int sg_size, order, bsize_elem, num_elem, i, j;
3638 struct ipr_sglist *sglist;
3639 struct scatterlist *scatterlist;
3640 struct page *page;
3641
3642
3643 sg_size = buf_len / (IPR_MAX_SGLIST - 1);
3644
3645
3646 order = get_order(sg_size);
3647
3648
3649 bsize_elem = PAGE_SIZE * (1 << order);
3650
3651
3652 if (buf_len % bsize_elem)
3653 num_elem = (buf_len / bsize_elem) + 1;
3654 else
3655 num_elem = buf_len / bsize_elem;
3656
3657
3658 sglist = kzalloc(sizeof(struct ipr_sglist) +
3659 (sizeof(struct scatterlist) * (num_elem - 1)),
3660 GFP_KERNEL);
3661
3662 if (sglist == NULL) {
3663 ipr_trace;
3664 return NULL;
3665 }
3666
3667 scatterlist = sglist->scatterlist;
3668 sg_init_table(scatterlist, num_elem);
3669
3670 sglist->order = order;
3671 sglist->num_sg = num_elem;
3672
3673
3674 for (i = 0; i < num_elem; i++) {
3675 page = alloc_pages(GFP_KERNEL, order);
3676 if (!page) {
3677 ipr_trace;
3678
3679
3680 for (j = i - 1; j >= 0; j--)
3681 __free_pages(sg_page(&scatterlist[j]), order);
3682 kfree(sglist);
3683 return NULL;
3684 }
3685
3686 sg_set_page(&scatterlist[i], page, 0, 0);
3687 }
3688
3689 return sglist;
3690}
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702static void ipr_free_ucode_buffer(struct ipr_sglist *sglist)
3703{
3704 int i;
3705
3706 for (i = 0; i < sglist->num_sg; i++)
3707 __free_pages(sg_page(&sglist->scatterlist[i]), sglist->order);
3708
3709 kfree(sglist);
3710}
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist,
3725 u8 *buffer, u32 len)
3726{
3727 int bsize_elem, i, result = 0;
3728 struct scatterlist *scatterlist;
3729 void *kaddr;
3730
3731
3732 bsize_elem = PAGE_SIZE * (1 << sglist->order);
3733
3734 scatterlist = sglist->scatterlist;
3735
3736 for (i = 0; i < (len / bsize_elem); i++, buffer += bsize_elem) {
3737 struct page *page = sg_page(&scatterlist[i]);
3738
3739 kaddr = kmap(page);
3740 memcpy(kaddr, buffer, bsize_elem);
3741 kunmap(page);
3742
3743 scatterlist[i].length = bsize_elem;
3744
3745 if (result != 0) {
3746 ipr_trace;
3747 return result;
3748 }
3749 }
3750
3751 if (len % bsize_elem) {
3752 struct page *page = sg_page(&scatterlist[i]);
3753
3754 kaddr = kmap(page);
3755 memcpy(kaddr, buffer, len % bsize_elem);
3756 kunmap(page);
3757
3758 scatterlist[i].length = len % bsize_elem;
3759 }
3760
3761 sglist->buffer_len = len;
3762 return result;
3763}
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd,
3774 struct ipr_sglist *sglist)
3775{
3776 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3777 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
3778 struct scatterlist *scatterlist = sglist->scatterlist;
3779 int i;
3780
3781 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3782 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3783 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3784
3785 ioarcb->ioadl_len =
3786 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
3787 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3788 ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE);
3789 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(&scatterlist[i]));
3790 ioadl64[i].address = cpu_to_be64(sg_dma_address(&scatterlist[i]));
3791 }
3792
3793 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3794}
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd,
3805 struct ipr_sglist *sglist)
3806{
3807 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3808 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
3809 struct scatterlist *scatterlist = sglist->scatterlist;
3810 int i;
3811
3812 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3813 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3814 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3815
3816 ioarcb->ioadl_len =
3817 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
3818
3819 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3820 ioadl[i].flags_and_data_len =
3821 cpu_to_be32(IPR_IOADL_FLAGS_WRITE | sg_dma_len(&scatterlist[i]));
3822 ioadl[i].address =
3823 cpu_to_be32(sg_dma_address(&scatterlist[i]));
3824 }
3825
3826 ioadl[i-1].flags_and_data_len |=
3827 cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3828}
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
3841 struct ipr_sglist *sglist)
3842{
3843 unsigned long lock_flags;
3844
3845 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3846 while (ioa_cfg->in_reset_reload) {
3847 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3848 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3849 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3850 }
3851
3852 if (ioa_cfg->ucode_sglist) {
3853 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3854 dev_err(&ioa_cfg->pdev->dev,
3855 "Microcode download already in progress\n");
3856 return -EIO;
3857 }
3858
3859 sglist->num_dma_sg = pci_map_sg(ioa_cfg->pdev, sglist->scatterlist,
3860 sglist->num_sg, DMA_TO_DEVICE);
3861
3862 if (!sglist->num_dma_sg) {
3863 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3864 dev_err(&ioa_cfg->pdev->dev,
3865 "Failed to map microcode download buffer!\n");
3866 return -EIO;
3867 }
3868
3869 ioa_cfg->ucode_sglist = sglist;
3870 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3871 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3872 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3873
3874 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3875 ioa_cfg->ucode_sglist = NULL;
3876 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3877 return 0;
3878}
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891static ssize_t ipr_store_update_fw(struct device *dev,
3892 struct device_attribute *attr,
3893 const char *buf, size_t count)
3894{
3895 struct Scsi_Host *shost = class_to_shost(dev);
3896 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3897 struct ipr_ucode_image_header *image_hdr;
3898 const struct firmware *fw_entry;
3899 struct ipr_sglist *sglist;
3900 char fname[100];
3901 char *src;
3902 int len, result, dnld_size;
3903
3904 if (!capable(CAP_SYS_ADMIN))
3905 return -EACCES;
3906
3907 len = snprintf(fname, 99, "%s", buf);
3908 fname[len-1] = '\0';
3909
3910 if (request_firmware(&fw_entry, fname, &ioa_cfg->pdev->dev)) {
3911 dev_err(&ioa_cfg->pdev->dev, "Firmware file %s not found\n", fname);
3912 return -EIO;
3913 }
3914
3915 image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;
3916
3917 src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);
3918 dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);
3919 sglist = ipr_alloc_ucode_buffer(dnld_size);
3920
3921 if (!sglist) {
3922 dev_err(&ioa_cfg->pdev->dev, "Microcode buffer allocation failed\n");
3923 release_firmware(fw_entry);
3924 return -ENOMEM;
3925 }
3926
3927 result = ipr_copy_ucode_buffer(sglist, src, dnld_size);
3928
3929 if (result) {
3930 dev_err(&ioa_cfg->pdev->dev,
3931 "Microcode buffer copy to DMA buffer failed\n");
3932 goto out;
3933 }
3934
3935 ipr_info("Updating microcode, please be patient. This may take up to 30 minutes.\n");
3936
3937 result = ipr_update_ioa_ucode(ioa_cfg, sglist);
3938
3939 if (!result)
3940 result = count;
3941out:
3942 ipr_free_ucode_buffer(sglist);
3943 release_firmware(fw_entry);
3944 return result;
3945}
3946
3947static struct device_attribute ipr_update_fw_attr = {
3948 .attr = {
3949 .name = "update_fw",
3950 .mode = S_IWUSR,
3951 },
3952 .store = ipr_store_update_fw
3953};
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963static ssize_t ipr_show_fw_type(struct device *dev,
3964 struct device_attribute *attr, char *buf)
3965{
3966 struct Scsi_Host *shost = class_to_shost(dev);
3967 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3968 unsigned long lock_flags = 0;
3969 int len;
3970
3971 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3972 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->sis64);
3973 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3974 return len;
3975}
3976
3977static struct device_attribute ipr_ioa_fw_type_attr = {
3978 .attr = {
3979 .name = "fw_type",
3980 .mode = S_IRUGO,
3981 },
3982 .show = ipr_show_fw_type
3983};
3984
3985static struct device_attribute *ipr_ioa_attrs[] = {
3986 &ipr_fw_version_attr,
3987 &ipr_log_level_attr,
3988 &ipr_diagnostics_attr,
3989 &ipr_ioa_state_attr,
3990 &ipr_ioa_reset_attr,
3991 &ipr_update_fw_attr,
3992 &ipr_ioa_fw_type_attr,
3993 &ipr_iopoll_weight_attr,
3994 NULL,
3995};
3996
3997#ifdef CONFIG_SCSI_IPR_DUMP
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010static ssize_t ipr_read_dump(struct file *filp, struct kobject *kobj,
4011 struct bin_attribute *bin_attr,
4012 char *buf, loff_t off, size_t count)
4013{
4014 struct device *cdev = container_of(kobj, struct device, kobj);
4015 struct Scsi_Host *shost = class_to_shost(cdev);
4016 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4017 struct ipr_dump *dump;
4018 unsigned long lock_flags = 0;
4019 char *src;
4020 int len, sdt_end;
4021 size_t rc = count;
4022
4023 if (!capable(CAP_SYS_ADMIN))
4024 return -EACCES;
4025
4026 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4027 dump = ioa_cfg->dump;
4028
4029 if (ioa_cfg->sdt_state != DUMP_OBTAINED || !dump) {
4030 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4031 return 0;
4032 }
4033 kref_get(&dump->kref);
4034 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4035
4036 if (off > dump->driver_dump.hdr.len) {
4037 kref_put(&dump->kref, ipr_release_dump);
4038 return 0;
4039 }
4040
4041 if (off + count > dump->driver_dump.hdr.len) {
4042 count = dump->driver_dump.hdr.len - off;
4043 rc = count;
4044 }
4045
4046 if (count && off < sizeof(dump->driver_dump)) {
4047 if (off + count > sizeof(dump->driver_dump))
4048 len = sizeof(dump->driver_dump) - off;
4049 else
4050 len = count;
4051 src = (u8 *)&dump->driver_dump + off;
4052 memcpy(buf, src, len);
4053 buf += len;
4054 off += len;
4055 count -= len;
4056 }
4057
4058 off -= sizeof(dump->driver_dump);
4059
4060 if (ioa_cfg->sis64)
4061 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4062 (be32_to_cpu(dump->ioa_dump.sdt.hdr.num_entries_used) *
4063 sizeof(struct ipr_sdt_entry));
4064 else
4065 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4066 (IPR_FMT2_NUM_SDT_ENTRIES * sizeof(struct ipr_sdt_entry));
4067
4068 if (count && off < sdt_end) {
4069 if (off + count > sdt_end)
4070 len = sdt_end - off;
4071 else
4072 len = count;
4073 src = (u8 *)&dump->ioa_dump + off;
4074 memcpy(buf, src, len);
4075 buf += len;
4076 off += len;
4077 count -= len;
4078 }
4079
4080 off -= sdt_end;
4081
4082 while (count) {
4083 if ((off & PAGE_MASK) != ((off + count) & PAGE_MASK))
4084 len = PAGE_ALIGN(off) - off;
4085 else
4086 len = count;
4087 src = (u8 *)dump->ioa_dump.ioa_data[(off & PAGE_MASK) >> PAGE_SHIFT];
4088 src += off & ~PAGE_MASK;
4089 memcpy(buf, src, len);
4090 buf += len;
4091 off += len;
4092 count -= len;
4093 }
4094
4095 kref_put(&dump->kref, ipr_release_dump);
4096 return rc;
4097}
4098
4099
4100
4101
4102
4103
4104
4105
4106static int ipr_alloc_dump(struct ipr_ioa_cfg *ioa_cfg)
4107{
4108 struct ipr_dump *dump;
4109 __be32 **ioa_data;
4110 unsigned long lock_flags = 0;
4111
4112 dump = kzalloc(sizeof(struct ipr_dump), GFP_KERNEL);
4113
4114 if (!dump) {
4115 ipr_err("Dump memory allocation failed\n");
4116 return -ENOMEM;
4117 }
4118
4119 if (ioa_cfg->sis64)
4120 ioa_data = vmalloc(IPR_FMT3_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
4121 else
4122 ioa_data = vmalloc(IPR_FMT2_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
4123
4124 if (!ioa_data) {
4125 ipr_err("Dump memory allocation failed\n");
4126 kfree(dump);
4127 return -ENOMEM;
4128 }
4129
4130 dump->ioa_dump.ioa_data = ioa_data;
4131
4132 kref_init(&dump->kref);
4133 dump->ioa_cfg = ioa_cfg;
4134
4135 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4136
4137 if (INACTIVE != ioa_cfg->sdt_state) {
4138 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4139 vfree(dump->ioa_dump.ioa_data);
4140 kfree(dump);
4141 return 0;
4142 }
4143
4144 ioa_cfg->dump = dump;
4145 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
4146 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead && !ioa_cfg->dump_taken) {
4147 ioa_cfg->dump_taken = 1;
4148 schedule_work(&ioa_cfg->work_q);
4149 }
4150 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4151
4152 return 0;
4153}
4154
4155
4156
4157
4158
4159
4160
4161
4162static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg)
4163{
4164 struct ipr_dump *dump;
4165 unsigned long lock_flags = 0;
4166
4167 ENTER;
4168
4169 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4170 dump = ioa_cfg->dump;
4171 if (!dump) {
4172 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4173 return 0;
4174 }
4175
4176 ioa_cfg->dump = NULL;
4177 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4178
4179 kref_put(&dump->kref, ipr_release_dump);
4180
4181 LEAVE;
4182 return 0;
4183}
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197static ssize_t ipr_write_dump(struct file *filp, struct kobject *kobj,
4198 struct bin_attribute *bin_attr,
4199 char *buf, loff_t off, size_t count)
4200{
4201 struct device *cdev = container_of(kobj, struct device, kobj);
4202 struct Scsi_Host *shost = class_to_shost(cdev);
4203 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4204 int rc;
4205
4206 if (!capable(CAP_SYS_ADMIN))
4207 return -EACCES;
4208
4209 if (buf[0] == '1')
4210 rc = ipr_alloc_dump(ioa_cfg);
4211 else if (buf[0] == '0')
4212 rc = ipr_free_dump(ioa_cfg);
4213 else
4214 return -EINVAL;
4215
4216 if (rc)
4217 return rc;
4218 else
4219 return count;
4220}
4221
4222static struct bin_attribute ipr_dump_attr = {
4223 .attr = {
4224 .name = "dump",
4225 .mode = S_IRUSR | S_IWUSR,
4226 },
4227 .size = 0,
4228 .read = ipr_read_dump,
4229 .write = ipr_write_dump
4230};
4231#else
4232static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg) { return 0; };
4233#endif
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth,
4245 int reason)
4246{
4247 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4248 struct ipr_resource_entry *res;
4249 unsigned long lock_flags = 0;
4250
4251 if (reason != SCSI_QDEPTH_DEFAULT)
4252 return -EOPNOTSUPP;
4253
4254 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4255 res = (struct ipr_resource_entry *)sdev->hostdata;
4256
4257 if (res && ipr_is_gata(res) && qdepth > IPR_MAX_CMD_PER_ATA_LUN)
4258 qdepth = IPR_MAX_CMD_PER_ATA_LUN;
4259 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4260
4261 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4262 return sdev->queue_depth;
4263}
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273static int ipr_change_queue_type(struct scsi_device *sdev, int tag_type)
4274{
4275 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4276 struct ipr_resource_entry *res;
4277 unsigned long lock_flags = 0;
4278
4279 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4280 res = (struct ipr_resource_entry *)sdev->hostdata;
4281
4282 if (res) {
4283 if (ipr_is_gscsi(res) && sdev->tagged_supported) {
4284
4285
4286
4287
4288 scsi_set_tag_type(sdev, tag_type);
4289
4290 if (tag_type)
4291 scsi_activate_tcq(sdev, sdev->queue_depth);
4292 else
4293 scsi_deactivate_tcq(sdev, sdev->queue_depth);
4294 } else
4295 tag_type = 0;
4296 } else
4297 tag_type = 0;
4298
4299 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4300 return tag_type;
4301}
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribute *attr, char *buf)
4313{
4314 struct scsi_device *sdev = to_scsi_device(dev);
4315 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4316 struct ipr_resource_entry *res;
4317 unsigned long lock_flags = 0;
4318 ssize_t len = -ENXIO;
4319
4320 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4321 res = (struct ipr_resource_entry *)sdev->hostdata;
4322 if (res)
4323 len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle);
4324 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4325 return len;
4326}
4327
4328static struct device_attribute ipr_adapter_handle_attr = {
4329 .attr = {
4330 .name = "adapter_handle",
4331 .mode = S_IRUSR,
4332 },
4333 .show = ipr_show_adapter_handle
4334};
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf)
4347{
4348 struct scsi_device *sdev = to_scsi_device(dev);
4349 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4350 struct ipr_resource_entry *res;
4351 unsigned long lock_flags = 0;
4352 ssize_t len = -ENXIO;
4353 char buffer[IPR_MAX_RES_PATH_LENGTH];
4354
4355 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4356 res = (struct ipr_resource_entry *)sdev->hostdata;
4357 if (res && ioa_cfg->sis64)
4358 len = snprintf(buf, PAGE_SIZE, "%s\n",
4359 __ipr_format_res_path(res->res_path, buffer,
4360 sizeof(buffer)));
4361 else if (res)
4362 len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
4363 res->bus, res->target, res->lun);
4364
4365 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4366 return len;
4367}
4368
4369static struct device_attribute ipr_resource_path_attr = {
4370 .attr = {
4371 .name = "resource_path",
4372 .mode = S_IRUGO,
4373 },
4374 .show = ipr_show_resource_path
4375};
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386static ssize_t ipr_show_device_id(struct device *dev, struct device_attribute *attr, char *buf)
4387{
4388 struct scsi_device *sdev = to_scsi_device(dev);
4389 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4390 struct ipr_resource_entry *res;
4391 unsigned long lock_flags = 0;
4392 ssize_t len = -ENXIO;
4393
4394 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4395 res = (struct ipr_resource_entry *)sdev->hostdata;
4396 if (res && ioa_cfg->sis64)
4397 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->dev_id);
4398 else if (res)
4399 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->lun_wwn);
4400
4401 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4402 return len;
4403}
4404
4405static struct device_attribute ipr_device_id_attr = {
4406 .attr = {
4407 .name = "device_id",
4408 .mode = S_IRUGO,
4409 },
4410 .show = ipr_show_device_id
4411};
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422static ssize_t ipr_show_resource_type(struct device *dev, struct device_attribute *attr, char *buf)
4423{
4424 struct scsi_device *sdev = to_scsi_device(dev);
4425 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4426 struct ipr_resource_entry *res;
4427 unsigned long lock_flags = 0;
4428 ssize_t len = -ENXIO;
4429
4430 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4431 res = (struct ipr_resource_entry *)sdev->hostdata;
4432
4433 if (res)
4434 len = snprintf(buf, PAGE_SIZE, "%x\n", res->type);
4435
4436 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4437 return len;
4438}
4439
4440static struct device_attribute ipr_resource_type_attr = {
4441 .attr = {
4442 .name = "resource_type",
4443 .mode = S_IRUGO,
4444 },
4445 .show = ipr_show_resource_type
4446};
4447
4448static struct device_attribute *ipr_dev_attrs[] = {
4449 &ipr_adapter_handle_attr,
4450 &ipr_resource_path_attr,
4451 &ipr_device_id_attr,
4452 &ipr_resource_type_attr,
4453 NULL,
4454};
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470static int ipr_biosparam(struct scsi_device *sdev,
4471 struct block_device *block_device,
4472 sector_t capacity, int *parm)
4473{
4474 int heads, sectors;
4475 sector_t cylinders;
4476
4477 heads = 128;
4478 sectors = 32;
4479
4480 cylinders = capacity;
4481 sector_div(cylinders, (128 * 32));
4482
4483
4484 parm[0] = heads;
4485 parm[1] = sectors;
4486 parm[2] = cylinders;
4487
4488 return 0;
4489}
4490
4491
4492
4493
4494
4495
4496
4497
4498static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget)
4499{
4500 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4501 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4502 struct ipr_resource_entry *res;
4503
4504 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4505 if ((res->bus == starget->channel) &&
4506 (res->target == starget->id)) {
4507 return res;
4508 }
4509 }
4510
4511 return NULL;
4512}
4513
4514static struct ata_port_info sata_port_info;
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526static int ipr_target_alloc(struct scsi_target *starget)
4527{
4528 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4529 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4530 struct ipr_sata_port *sata_port;
4531 struct ata_port *ap;
4532 struct ipr_resource_entry *res;
4533 unsigned long lock_flags;
4534
4535 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4536 res = ipr_find_starget(starget);
4537 starget->hostdata = NULL;
4538
4539 if (res && ipr_is_gata(res)) {
4540 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4541 sata_port = kzalloc(sizeof(*sata_port), GFP_KERNEL);
4542 if (!sata_port)
4543 return -ENOMEM;
4544
4545 ap = ata_sas_port_alloc(&ioa_cfg->ata_host, &sata_port_info, shost);
4546 if (ap) {
4547 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4548 sata_port->ioa_cfg = ioa_cfg;
4549 sata_port->ap = ap;
4550 sata_port->res = res;
4551
4552 res->sata_port = sata_port;
4553 ap->private_data = sata_port;
4554 starget->hostdata = sata_port;
4555 } else {
4556 kfree(sata_port);
4557 return -ENOMEM;
4558 }
4559 }
4560 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4561
4562 return 0;
4563}
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573static void ipr_target_destroy(struct scsi_target *starget)
4574{
4575 struct ipr_sata_port *sata_port = starget->hostdata;
4576 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4577 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4578
4579 if (ioa_cfg->sis64) {
4580 if (!ipr_find_starget(starget)) {
4581 if (starget->channel == IPR_ARRAY_VIRTUAL_BUS)
4582 clear_bit(starget->id, ioa_cfg->array_ids);
4583 else if (starget->channel == IPR_VSET_VIRTUAL_BUS)
4584 clear_bit(starget->id, ioa_cfg->vset_ids);
4585 else if (starget->channel == 0)
4586 clear_bit(starget->id, ioa_cfg->target_ids);
4587 }
4588 }
4589
4590 if (sata_port) {
4591 starget->hostdata = NULL;
4592 ata_sas_port_destroy(sata_port->ap);
4593 kfree(sata_port);
4594 }
4595}
4596
4597
4598
4599
4600
4601
4602
4603
4604static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev)
4605{
4606 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4607 struct ipr_resource_entry *res;
4608
4609 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4610 if ((res->bus == sdev->channel) &&
4611 (res->target == sdev->id) &&
4612 (res->lun == sdev->lun))
4613 return res;
4614 }
4615
4616 return NULL;
4617}
4618
4619
4620
4621
4622
4623
4624
4625
4626static void ipr_slave_destroy(struct scsi_device *sdev)
4627{
4628 struct ipr_resource_entry *res;
4629 struct ipr_ioa_cfg *ioa_cfg;
4630 unsigned long lock_flags = 0;
4631
4632 ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4633
4634 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4635 res = (struct ipr_resource_entry *) sdev->hostdata;
4636 if (res) {
4637 if (res->sata_port)
4638 res->sata_port->ap->link.device[0].class = ATA_DEV_NONE;
4639 sdev->hostdata = NULL;
4640 res->sdev = NULL;
4641 res->sata_port = NULL;
4642 }
4643 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4644}
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655static int ipr_slave_configure(struct scsi_device *sdev)
4656{
4657 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4658 struct ipr_resource_entry *res;
4659 struct ata_port *ap = NULL;
4660 unsigned long lock_flags = 0;
4661 char buffer[IPR_MAX_RES_PATH_LENGTH];
4662
4663 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4664 res = sdev->hostdata;
4665 if (res) {
4666 if (ipr_is_af_dasd_device(res))
4667 sdev->type = TYPE_RAID;
4668 if (ipr_is_af_dasd_device(res) || ipr_is_ioa_resource(res)) {
4669 sdev->scsi_level = 4;
4670 sdev->no_uld_attach = 1;
4671 }
4672 if (ipr_is_vset_device(res)) {
4673 blk_queue_rq_timeout(sdev->request_queue,
4674 IPR_VSET_RW_TIMEOUT);
4675 blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
4676 }
4677 if (ipr_is_gata(res) && res->sata_port)
4678 ap = res->sata_port->ap;
4679 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4680
4681 if (ap) {
4682 scsi_adjust_queue_depth(sdev, 0, IPR_MAX_CMD_PER_ATA_LUN);
4683 ata_sas_slave_configure(sdev, ap);
4684 } else
4685 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4686 if (ioa_cfg->sis64)
4687 sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
4688 ipr_format_res_path(ioa_cfg,
4689 res->res_path, buffer, sizeof(buffer)));
4690 return 0;
4691 }
4692 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4693 return 0;
4694}
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706static int ipr_ata_slave_alloc(struct scsi_device *sdev)
4707{
4708 struct ipr_sata_port *sata_port = NULL;
4709 int rc = -ENXIO;
4710
4711 ENTER;
4712 if (sdev->sdev_target)
4713 sata_port = sdev->sdev_target->hostdata;
4714 if (sata_port) {
4715 rc = ata_sas_port_init(sata_port->ap);
4716 if (rc == 0)
4717 rc = ata_sas_sync_probe(sata_port->ap);
4718 }
4719
4720 if (rc)
4721 ipr_slave_destroy(sdev);
4722
4723 LEAVE;
4724 return rc;
4725}
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739static int ipr_slave_alloc(struct scsi_device *sdev)
4740{
4741 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4742 struct ipr_resource_entry *res;
4743 unsigned long lock_flags;
4744 int rc = -ENXIO;
4745
4746 sdev->hostdata = NULL;
4747
4748 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4749
4750 res = ipr_find_sdev(sdev);
4751 if (res) {
4752 res->sdev = sdev;
4753 res->add_to_ml = 0;
4754 res->in_erp = 0;
4755 sdev->hostdata = res;
4756 if (!ipr_is_naca_model(res))
4757 res->needs_sync_complete = 1;
4758 rc = 0;
4759 if (ipr_is_gata(res)) {
4760 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4761 return ipr_ata_slave_alloc(sdev);
4762 }
4763 }
4764
4765 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4766
4767 return rc;
4768}
4769
4770static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
4771{
4772 struct ipr_ioa_cfg *ioa_cfg;
4773 unsigned long lock_flags = 0;
4774 int rc = SUCCESS;
4775
4776 ENTER;
4777 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
4778 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4779
4780 if (!ioa_cfg->in_reset_reload) {
4781 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
4782 dev_err(&ioa_cfg->pdev->dev,
4783 "Adapter being reset as a result of error recovery.\n");
4784
4785 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
4786 ioa_cfg->sdt_state = GET_DUMP;
4787 }
4788
4789 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4790 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4791 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4792
4793
4794
4795 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
4796 ipr_trace;
4797 rc = FAILED;
4798 }
4799
4800 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4801 LEAVE;
4802 return rc;
4803}
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg,
4820 struct ipr_resource_entry *res)
4821{
4822 struct ipr_cmnd *ipr_cmd;
4823 struct ipr_ioarcb *ioarcb;
4824 struct ipr_cmd_pkt *cmd_pkt;
4825 struct ipr_ioarcb_ata_regs *regs;
4826 u32 ioasc;
4827
4828 ENTER;
4829 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
4830 ioarcb = &ipr_cmd->ioarcb;
4831 cmd_pkt = &ioarcb->cmd_pkt;
4832
4833 if (ipr_cmd->ioa_cfg->sis64) {
4834 regs = &ipr_cmd->i.ata_ioadl.regs;
4835 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
4836 } else
4837 regs = &ioarcb->u.add_data.u.regs;
4838
4839 ioarcb->res_handle = res->res_handle;
4840 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
4841 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
4842 if (ipr_is_gata(res)) {
4843 cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET;
4844 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags));
4845 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
4846 }
4847
4848 ipr_send_blocking_cmd(ipr_cmd, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
4849 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
4850 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
4851 if (ipr_is_gata(res) && res->sata_port && ioasc != IPR_IOASC_IOA_WAS_RESET) {
4852 if (ipr_cmd->ioa_cfg->sis64)
4853 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
4854 sizeof(struct ipr_ioasa_gata));
4855 else
4856 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
4857 sizeof(struct ipr_ioasa_gata));
4858 }
4859
4860 LEAVE;
4861 return IPR_IOASC_SENSE_KEY(ioasc) ? -EIO : 0;
4862}
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874static int ipr_sata_reset(struct ata_link *link, unsigned int *classes,
4875 unsigned long deadline)
4876{
4877 struct ipr_sata_port *sata_port = link->ap->private_data;
4878 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
4879 struct ipr_resource_entry *res;
4880 unsigned long lock_flags = 0;
4881 int rc = -ENXIO;
4882
4883 ENTER;
4884 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4885 while (ioa_cfg->in_reset_reload) {
4886 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4887 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4888 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4889 }
4890
4891 res = sata_port->res;
4892 if (res) {
4893 rc = ipr_device_reset(ioa_cfg, res);
4894 *classes = res->ata_class;
4895 }
4896
4897 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4898 LEAVE;
4899 return rc;
4900}
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913static int __ipr_eh_dev_reset(struct scsi_cmnd *scsi_cmd)
4914{
4915 struct ipr_cmnd *ipr_cmd;
4916 struct ipr_ioa_cfg *ioa_cfg;
4917 struct ipr_resource_entry *res;
4918 struct ata_port *ap;
4919 int rc = 0;
4920 struct ipr_hrr_queue *hrrq;
4921
4922 ENTER;
4923 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
4924 res = scsi_cmd->device->hostdata;
4925
4926 if (!res)
4927 return FAILED;
4928
4929
4930
4931
4932
4933
4934 if (ioa_cfg->in_reset_reload)
4935 return FAILED;
4936 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
4937 return FAILED;
4938
4939 for_each_hrrq(hrrq, ioa_cfg) {
4940 spin_lock(&hrrq->_lock);
4941 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
4942 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
4943 if (ipr_cmd->scsi_cmd)
4944 ipr_cmd->done = ipr_scsi_eh_done;
4945 if (ipr_cmd->qc)
4946 ipr_cmd->done = ipr_sata_eh_done;
4947 if (ipr_cmd->qc &&
4948 !(ipr_cmd->qc->flags & ATA_QCFLAG_FAILED)) {
4949 ipr_cmd->qc->err_mask |= AC_ERR_TIMEOUT;
4950 ipr_cmd->qc->flags |= ATA_QCFLAG_FAILED;
4951 }
4952 }
4953 }
4954 spin_unlock(&hrrq->_lock);
4955 }
4956 res->resetting_device = 1;
4957 scmd_printk(KERN_ERR, scsi_cmd, "Resetting device\n");
4958
4959 if (ipr_is_gata(res) && res->sata_port) {
4960 ap = res->sata_port->ap;
4961 spin_unlock_irq(scsi_cmd->device->host->host_lock);
4962 ata_std_error_handler(ap);
4963 spin_lock_irq(scsi_cmd->device->host->host_lock);
4964
4965 for_each_hrrq(hrrq, ioa_cfg) {
4966 spin_lock(&hrrq->_lock);
4967 list_for_each_entry(ipr_cmd,
4968 &hrrq->hrrq_pending_q, queue) {
4969 if (ipr_cmd->ioarcb.res_handle ==
4970 res->res_handle) {
4971 rc = -EIO;
4972 break;
4973 }
4974 }
4975 spin_unlock(&hrrq->_lock);
4976 }
4977 } else
4978 rc = ipr_device_reset(ioa_cfg, res);
4979 res->resetting_device = 0;
4980
4981 LEAVE;
4982 return rc ? FAILED : SUCCESS;
4983}
4984
4985static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
4986{
4987 int rc;
4988
4989 spin_lock_irq(cmd->device->host->host_lock);
4990 rc = __ipr_eh_dev_reset(cmd);
4991 spin_unlock_irq(cmd->device->host->host_lock);
4992
4993 return rc;
4994}
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd)
5006{
5007 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5008 struct ipr_resource_entry *res;
5009
5010 ENTER;
5011 if (!ioa_cfg->sis64)
5012 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
5013 if (res->res_handle == ipr_cmd->ioarcb.res_handle) {
5014 scsi_report_bus_reset(ioa_cfg->host, res->bus);
5015 break;
5016 }
5017 }
5018
5019
5020
5021
5022
5023 if (ipr_cmd->sibling->sibling)
5024 ipr_cmd->sibling->sibling = NULL;
5025 else
5026 ipr_cmd->sibling->done(ipr_cmd->sibling);
5027
5028 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5029 LEAVE;
5030}
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043static void ipr_abort_timeout(struct ipr_cmnd *ipr_cmd)
5044{
5045 struct ipr_cmnd *reset_cmd;
5046 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5047 struct ipr_cmd_pkt *cmd_pkt;
5048 unsigned long lock_flags = 0;
5049
5050 ENTER;
5051 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5052 if (ipr_cmd->completion.done || ioa_cfg->in_reset_reload) {
5053 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5054 return;
5055 }
5056
5057 sdev_printk(KERN_ERR, ipr_cmd->u.sdev, "Abort timed out. Resetting bus.\n");
5058 reset_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5059 ipr_cmd->sibling = reset_cmd;
5060 reset_cmd->sibling = ipr_cmd;
5061 reset_cmd->ioarcb.res_handle = ipr_cmd->ioarcb.res_handle;
5062 cmd_pkt = &reset_cmd->ioarcb.cmd_pkt;
5063 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5064 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5065 cmd_pkt->cdb[2] = IPR_RESET_TYPE_SELECT | IPR_BUS_RESET;
5066
5067 ipr_do_req(reset_cmd, ipr_bus_reset_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5068 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5069 LEAVE;
5070}
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081static int ipr_cancel_op(struct scsi_cmnd *scsi_cmd)
5082{
5083 struct ipr_cmnd *ipr_cmd;
5084 struct ipr_ioa_cfg *ioa_cfg;
5085 struct ipr_resource_entry *res;
5086 struct ipr_cmd_pkt *cmd_pkt;
5087 u32 ioasc, int_reg;
5088 int op_found = 0;
5089 struct ipr_hrr_queue *hrrq;
5090
5091 ENTER;
5092 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
5093 res = scsi_cmd->device->hostdata;
5094
5095
5096
5097
5098
5099 if (ioa_cfg->in_reset_reload ||
5100 ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5101 return FAILED;
5102 if (!res)
5103 return FAILED;
5104
5105
5106
5107
5108
5109
5110 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5111
5112 if (!ipr_is_gscsi(res))
5113 return FAILED;
5114
5115 for_each_hrrq(hrrq, ioa_cfg) {
5116 spin_lock(&hrrq->_lock);
5117 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
5118 if (ipr_cmd->scsi_cmd == scsi_cmd) {
5119 ipr_cmd->done = ipr_scsi_eh_done;
5120 op_found = 1;
5121 break;
5122 }
5123 }
5124 spin_unlock(&hrrq->_lock);
5125 }
5126
5127 if (!op_found)
5128 return SUCCESS;
5129
5130 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5131 ipr_cmd->ioarcb.res_handle = res->res_handle;
5132 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5133 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5134 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5135 ipr_cmd->u.sdev = scsi_cmd->device;
5136
5137 scmd_printk(KERN_ERR, scsi_cmd, "Aborting command: %02X\n",
5138 scsi_cmd->cmnd[0]);
5139 ipr_send_blocking_cmd(ipr_cmd, ipr_abort_timeout, IPR_CANCEL_ALL_TIMEOUT);
5140 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5141
5142
5143
5144
5145
5146 if (ioasc == IPR_IOASC_BUS_WAS_RESET || ioasc == IPR_IOASC_SYNC_REQUIRED) {
5147 ioasc = 0;
5148 ipr_trace;
5149 }
5150
5151 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5152 if (!ipr_is_naca_model(res))
5153 res->needs_sync_complete = 1;
5154
5155 LEAVE;
5156 return IPR_IOASC_SENSE_KEY(ioasc) ? FAILED : SUCCESS;
5157}
5158
5159
5160
5161
5162
5163
5164
5165
5166static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
5167{
5168 unsigned long flags;
5169 int rc;
5170
5171 ENTER;
5172
5173 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
5174 rc = ipr_cancel_op(scsi_cmd);
5175 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
5176
5177 LEAVE;
5178 return rc;
5179}
5180
5181
5182
5183
5184
5185
5186
5187
5188
5189static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
5190 u32 int_reg)
5191{
5192 irqreturn_t rc = IRQ_HANDLED;
5193 u32 int_mask_reg;
5194
5195 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
5196 int_reg &= ~int_mask_reg;
5197
5198
5199
5200
5201 if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
5202 if (ioa_cfg->sis64) {
5203 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
5204 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5205 if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
5206
5207
5208 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
5209 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5210 list_del(&ioa_cfg->reset_cmd->queue);
5211 del_timer(&ioa_cfg->reset_cmd->timer);
5212 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5213 return IRQ_HANDLED;
5214 }
5215 }
5216
5217 return IRQ_NONE;
5218 }
5219
5220 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
5221
5222 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
5223
5224
5225 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.clr_interrupt_reg);
5226 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5227
5228 list_del(&ioa_cfg->reset_cmd->queue);
5229 del_timer(&ioa_cfg->reset_cmd->timer);
5230 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5231 } else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
5232 if (ioa_cfg->clear_isr) {
5233 if (ipr_debug && printk_ratelimit())
5234 dev_err(&ioa_cfg->pdev->dev,
5235 "Spurious interrupt detected. 0x%08X\n", int_reg);
5236 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5237 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5238 return IRQ_NONE;
5239 }
5240 } else {
5241 if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
5242 ioa_cfg->ioa_unit_checked = 1;
5243 else if (int_reg & IPR_PCII_NO_HOST_RRQ)
5244 dev_err(&ioa_cfg->pdev->dev,
5245 "No Host RRQ. 0x%08X\n", int_reg);
5246 else
5247 dev_err(&ioa_cfg->pdev->dev,
5248 "Permanent IOA failure. 0x%08X\n", int_reg);
5249
5250 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5251 ioa_cfg->sdt_state = GET_DUMP;
5252
5253 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
5254 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5255 }
5256
5257 return rc;
5258}
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268static void ipr_isr_eh(struct ipr_ioa_cfg *ioa_cfg, char *msg, u16 number)
5269{
5270 ioa_cfg->errors_logged++;
5271 dev_err(&ioa_cfg->pdev->dev, "%s %d\n", msg, number);
5272
5273 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5274 ioa_cfg->sdt_state = GET_DUMP;
5275
5276 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5277}
5278
5279static int ipr_process_hrrq(struct ipr_hrr_queue *hrr_queue, int budget,
5280 struct list_head *doneq)
5281{
5282 u32 ioasc;
5283 u16 cmd_index;
5284 struct ipr_cmnd *ipr_cmd;
5285 struct ipr_ioa_cfg *ioa_cfg = hrr_queue->ioa_cfg;
5286 int num_hrrq = 0;
5287
5288
5289 if (!hrr_queue->allow_interrupts)
5290 return 0;
5291
5292 while ((be32_to_cpu(*hrr_queue->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5293 hrr_queue->toggle_bit) {
5294
5295 cmd_index = (be32_to_cpu(*hrr_queue->hrrq_curr) &
5296 IPR_HRRQ_REQ_RESP_HANDLE_MASK) >>
5297 IPR_HRRQ_REQ_RESP_HANDLE_SHIFT;
5298
5299 if (unlikely(cmd_index > hrr_queue->max_cmd_id ||
5300 cmd_index < hrr_queue->min_cmd_id)) {
5301 ipr_isr_eh(ioa_cfg,
5302 "Invalid response handle from IOA: ",
5303 cmd_index);
5304 break;
5305 }
5306
5307 ipr_cmd = ioa_cfg->ipr_cmnd_list[cmd_index];
5308 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5309
5310 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, ioasc);
5311
5312 list_move_tail(&ipr_cmd->queue, doneq);
5313
5314 if (hrr_queue->hrrq_curr < hrr_queue->hrrq_end) {
5315 hrr_queue->hrrq_curr++;
5316 } else {
5317 hrr_queue->hrrq_curr = hrr_queue->hrrq_start;
5318 hrr_queue->toggle_bit ^= 1u;
5319 }
5320 num_hrrq++;
5321 if (budget > 0 && num_hrrq >= budget)
5322 break;
5323 }
5324
5325 return num_hrrq;
5326}
5327
5328static int ipr_iopoll(struct blk_iopoll *iop, int budget)
5329{
5330 struct ipr_ioa_cfg *ioa_cfg;
5331 struct ipr_hrr_queue *hrrq;
5332 struct ipr_cmnd *ipr_cmd, *temp;
5333 unsigned long hrrq_flags;
5334 int completed_ops;
5335 LIST_HEAD(doneq);
5336
5337 hrrq = container_of(iop, struct ipr_hrr_queue, iopoll);
5338 ioa_cfg = hrrq->ioa_cfg;
5339
5340 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5341 completed_ops = ipr_process_hrrq(hrrq, budget, &doneq);
5342
5343 if (completed_ops < budget)
5344 blk_iopoll_complete(iop);
5345 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5346
5347 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5348 list_del(&ipr_cmd->queue);
5349 del_timer(&ipr_cmd->timer);
5350 ipr_cmd->fast_done(ipr_cmd);
5351 }
5352
5353 return completed_ops;
5354}
5355
5356
5357
5358
5359
5360
5361
5362
5363
5364static irqreturn_t ipr_isr(int irq, void *devp)
5365{
5366 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5367 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5368 unsigned long hrrq_flags = 0;
5369 u32 int_reg = 0;
5370 int num_hrrq = 0;
5371 int irq_none = 0;
5372 struct ipr_cmnd *ipr_cmd, *temp;
5373 irqreturn_t rc = IRQ_NONE;
5374 LIST_HEAD(doneq);
5375
5376 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5377
5378 if (!hrrq->allow_interrupts) {
5379 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5380 return IRQ_NONE;
5381 }
5382
5383 while (1) {
5384 if (ipr_process_hrrq(hrrq, -1, &doneq)) {
5385 rc = IRQ_HANDLED;
5386
5387 if (!ioa_cfg->clear_isr)
5388 break;
5389
5390
5391 num_hrrq = 0;
5392 do {
5393 writel(IPR_PCII_HRRQ_UPDATED,
5394 ioa_cfg->regs.clr_interrupt_reg32);
5395 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5396 } while (int_reg & IPR_PCII_HRRQ_UPDATED &&
5397 num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
5398
5399 } else if (rc == IRQ_NONE && irq_none == 0) {
5400 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5401 irq_none++;
5402 } else if (num_hrrq == IPR_MAX_HRRQ_RETRIES &&
5403 int_reg & IPR_PCII_HRRQ_UPDATED) {
5404 ipr_isr_eh(ioa_cfg,
5405 "Error clearing HRRQ: ", num_hrrq);
5406 rc = IRQ_HANDLED;
5407 break;
5408 } else
5409 break;
5410 }
5411
5412 if (unlikely(rc == IRQ_NONE))
5413 rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
5414
5415 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5416 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5417 list_del(&ipr_cmd->queue);
5418 del_timer(&ipr_cmd->timer);
5419 ipr_cmd->fast_done(ipr_cmd);
5420 }
5421 return rc;
5422}
5423
5424
5425
5426
5427
5428
5429
5430
5431
5432static irqreturn_t ipr_isr_mhrrq(int irq, void *devp)
5433{
5434 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5435 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5436 unsigned long hrrq_flags = 0;
5437 struct ipr_cmnd *ipr_cmd, *temp;
5438 irqreturn_t rc = IRQ_NONE;
5439 LIST_HEAD(doneq);
5440
5441 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5442
5443
5444 if (!hrrq->allow_interrupts) {
5445 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5446 return IRQ_NONE;
5447 }
5448
5449 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
5450 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
5451 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5452 hrrq->toggle_bit) {
5453 if (!blk_iopoll_sched_prep(&hrrq->iopoll))
5454 blk_iopoll_sched(&hrrq->iopoll);
5455 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5456 return IRQ_HANDLED;
5457 }
5458 } else {
5459 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5460 hrrq->toggle_bit)
5461
5462 if (ipr_process_hrrq(hrrq, -1, &doneq))
5463 rc = IRQ_HANDLED;
5464 }
5465
5466 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5467
5468 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5469 list_del(&ipr_cmd->queue);
5470 del_timer(&ipr_cmd->timer);
5471 ipr_cmd->fast_done(ipr_cmd);
5472 }
5473 return rc;
5474}
5475
5476
5477
5478
5479
5480
5481
5482
5483
5484static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
5485 struct ipr_cmnd *ipr_cmd)
5486{
5487 int i, nseg;
5488 struct scatterlist *sg;
5489 u32 length;
5490 u32 ioadl_flags = 0;
5491 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5492 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5493 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
5494
5495 length = scsi_bufflen(scsi_cmd);
5496 if (!length)
5497 return 0;
5498
5499 nseg = scsi_dma_map(scsi_cmd);
5500 if (nseg < 0) {
5501 if (printk_ratelimit())
5502 dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
5503 return -1;
5504 }
5505
5506 ipr_cmd->dma_use_sg = nseg;
5507
5508 ioarcb->data_transfer_length = cpu_to_be32(length);
5509 ioarcb->ioadl_len =
5510 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
5511
5512 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5513 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5514 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5515 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE)
5516 ioadl_flags = IPR_IOADL_FLAGS_READ;
5517
5518 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5519 ioadl64[i].flags = cpu_to_be32(ioadl_flags);
5520 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
5521 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
5522 }
5523
5524 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5525 return 0;
5526}
5527
5528
5529
5530
5531
5532
5533
5534
5535
5536static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
5537 struct ipr_cmnd *ipr_cmd)
5538{
5539 int i, nseg;
5540 struct scatterlist *sg;
5541 u32 length;
5542 u32 ioadl_flags = 0;
5543 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5544 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5545 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
5546
5547 length = scsi_bufflen(scsi_cmd);
5548 if (!length)
5549 return 0;
5550
5551 nseg = scsi_dma_map(scsi_cmd);
5552 if (nseg < 0) {
5553 dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
5554 return -1;
5555 }
5556
5557 ipr_cmd->dma_use_sg = nseg;
5558
5559 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5560 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5561 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5562 ioarcb->data_transfer_length = cpu_to_be32(length);
5563 ioarcb->ioadl_len =
5564 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5565 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) {
5566 ioadl_flags = IPR_IOADL_FLAGS_READ;
5567 ioarcb->read_data_transfer_length = cpu_to_be32(length);
5568 ioarcb->read_ioadl_len =
5569 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5570 }
5571
5572 if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) {
5573 ioadl = ioarcb->u.add_data.u.ioadl;
5574 ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) +
5575 offsetof(struct ipr_ioarcb, u.add_data));
5576 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5577 }
5578
5579 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5580 ioadl[i].flags_and_data_len =
5581 cpu_to_be32(ioadl_flags | sg_dma_len(sg));
5582 ioadl[i].address = cpu_to_be32(sg_dma_address(sg));
5583 }
5584
5585 ioadl[i-1].flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5586 return 0;
5587}
5588
5589
5590
5591
5592
5593
5594
5595
5596static u8 ipr_get_task_attributes(struct scsi_cmnd *scsi_cmd)
5597{
5598 u8 tag[2];
5599 u8 rc = IPR_FLAGS_LO_UNTAGGED_TASK;
5600
5601 if (scsi_populate_tag_msg(scsi_cmd, tag)) {
5602 switch (tag[0]) {
5603 case MSG_SIMPLE_TAG:
5604 rc = IPR_FLAGS_LO_SIMPLE_TASK;
5605 break;
5606 case MSG_HEAD_TAG:
5607 rc = IPR_FLAGS_LO_HEAD_OF_Q_TASK;
5608 break;
5609 case MSG_ORDERED_TAG:
5610 rc = IPR_FLAGS_LO_ORDERED_TASK;
5611 break;
5612 };
5613 }
5614
5615 return rc;
5616}
5617
5618
5619
5620
5621
5622
5623
5624
5625
5626
5627
5628static void ipr_erp_done(struct ipr_cmnd *ipr_cmd)
5629{
5630 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5631 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5632 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5633
5634 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5635 scsi_cmd->result |= (DID_ERROR << 16);
5636 scmd_printk(KERN_ERR, scsi_cmd,
5637 "Request Sense failed with IOASC: 0x%08X\n", ioasc);
5638 } else {
5639 memcpy(scsi_cmd->sense_buffer, ipr_cmd->sense_buffer,
5640 SCSI_SENSE_BUFFERSIZE);
5641 }
5642
5643 if (res) {
5644 if (!ipr_is_naca_model(res))
5645 res->needs_sync_complete = 1;
5646 res->in_erp = 0;
5647 }
5648 scsi_dma_unmap(ipr_cmd->scsi_cmd);
5649 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5650 scsi_cmd->scsi_done(scsi_cmd);
5651}
5652
5653
5654
5655
5656
5657
5658
5659
5660static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd)
5661{
5662 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5663 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5664 dma_addr_t dma_addr = ipr_cmd->dma_addr;
5665
5666 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
5667 ioarcb->data_transfer_length = 0;
5668 ioarcb->read_data_transfer_length = 0;
5669 ioarcb->ioadl_len = 0;
5670 ioarcb->read_ioadl_len = 0;
5671 ioasa->hdr.ioasc = 0;
5672 ioasa->hdr.residual_data_len = 0;
5673
5674 if (ipr_cmd->ioa_cfg->sis64)
5675 ioarcb->u.sis64_addr_data.data_ioadl_addr =
5676 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
5677 else {
5678 ioarcb->write_ioadl_addr =
5679 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
5680 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5681 }
5682}
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
5695{
5696 struct ipr_cmd_pkt *cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5697 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5698
5699 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5700 ipr_erp_done(ipr_cmd);
5701 return;
5702 }
5703
5704 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5705
5706 cmd_pkt->request_type = IPR_RQTYPE_SCSICDB;
5707 cmd_pkt->cdb[0] = REQUEST_SENSE;
5708 cmd_pkt->cdb[4] = SCSI_SENSE_BUFFERSIZE;
5709 cmd_pkt->flags_hi |= IPR_FLAGS_HI_SYNC_OVERRIDE;
5710 cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
5711 cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ);
5712
5713 ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma,
5714 SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST);
5715
5716 ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout,
5717 IPR_REQUEST_SENSE_TIMEOUT * 2);
5718}
5719
5720
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
5733{
5734 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5735 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5736 struct ipr_cmd_pkt *cmd_pkt;
5737
5738 res->in_erp = 1;
5739
5740 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5741
5742 if (!scsi_get_tag_type(scsi_cmd->device)) {
5743 ipr_erp_request_sense(ipr_cmd);
5744 return;
5745 }
5746
5747 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5748 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5749 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5750
5751 ipr_do_req(ipr_cmd, ipr_erp_request_sense, ipr_timeout,
5752 IPR_CANCEL_ALL_TIMEOUT);
5753}
5754
5755
5756
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768static void ipr_dump_ioasa(struct ipr_ioa_cfg *ioa_cfg,
5769 struct ipr_cmnd *ipr_cmd, struct ipr_resource_entry *res)
5770{
5771 int i;
5772 u16 data_len;
5773 u32 ioasc, fd_ioasc;
5774 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5775 __be32 *ioasa_data = (__be32 *)ioasa;
5776 int error_index;
5777
5778 ioasc = be32_to_cpu(ioasa->hdr.ioasc) & IPR_IOASC_IOASC_MASK;
5779 fd_ioasc = be32_to_cpu(ioasa->hdr.fd_ioasc) & IPR_IOASC_IOASC_MASK;
5780
5781 if (0 == ioasc)
5782 return;
5783
5784 if (ioa_cfg->log_level < IPR_DEFAULT_LOG_LEVEL)
5785 return;
5786
5787 if (ioasc == IPR_IOASC_BUS_WAS_RESET && fd_ioasc)
5788 error_index = ipr_get_error(fd_ioasc);
5789 else
5790 error_index = ipr_get_error(ioasc);
5791
5792 if (ioa_cfg->log_level < IPR_MAX_LOG_LEVEL) {
5793
5794 if (ioasa->hdr.ilid != 0)
5795 return;
5796
5797 if (!ipr_is_gscsi(res))
5798 return;
5799
5800 if (ipr_error_table[error_index].log_ioasa == 0)
5801 return;
5802 }
5803
5804 ipr_res_err(ioa_cfg, res, "%s\n", ipr_error_table[error_index].error);
5805
5806 data_len = be16_to_cpu(ioasa->hdr.ret_stat_len);
5807 if (ioa_cfg->sis64 && sizeof(struct ipr_ioasa64) < data_len)
5808 data_len = sizeof(struct ipr_ioasa64);
5809 else if (!ioa_cfg->sis64 && sizeof(struct ipr_ioasa) < data_len)
5810 data_len = sizeof(struct ipr_ioasa);
5811
5812 ipr_err("IOASA Dump:\n");
5813
5814 for (i = 0; i < data_len / 4; i += 4) {
5815 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
5816 be32_to_cpu(ioasa_data[i]),
5817 be32_to_cpu(ioasa_data[i+1]),
5818 be32_to_cpu(ioasa_data[i+2]),
5819 be32_to_cpu(ioasa_data[i+3]));
5820 }
5821}
5822
5823
5824
5825
5826
5827
5828
5829
5830
5831static void ipr_gen_sense(struct ipr_cmnd *ipr_cmd)
5832{
5833 u32 failing_lba;
5834 u8 *sense_buf = ipr_cmd->scsi_cmd->sense_buffer;
5835 struct ipr_resource_entry *res = ipr_cmd->scsi_cmd->device->hostdata;
5836 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5837 u32 ioasc = be32_to_cpu(ioasa->hdr.ioasc);
5838
5839 memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
5840
5841 if (ioasc >= IPR_FIRST_DRIVER_IOASC)
5842 return;
5843
5844 ipr_cmd->scsi_cmd->result = SAM_STAT_CHECK_CONDITION;
5845
5846 if (ipr_is_vset_device(res) &&
5847 ioasc == IPR_IOASC_MED_DO_NOT_REALLOC &&
5848 ioasa->u.vset.failing_lba_hi != 0) {
5849 sense_buf[0] = 0x72;
5850 sense_buf[1] = IPR_IOASC_SENSE_KEY(ioasc);
5851 sense_buf[2] = IPR_IOASC_SENSE_CODE(ioasc);
5852 sense_buf[3] = IPR_IOASC_SENSE_QUAL(ioasc);
5853
5854 sense_buf[7] = 12;
5855 sense_buf[8] = 0;
5856 sense_buf[9] = 0x0A;
5857 sense_buf[10] = 0x80;
5858
5859 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_hi);
5860
5861 sense_buf[12] = (failing_lba & 0xff000000) >> 24;
5862 sense_buf[13] = (failing_lba & 0x00ff0000) >> 16;
5863 sense_buf[14] = (failing_lba & 0x0000ff00) >> 8;
5864 sense_buf[15] = failing_lba & 0x000000ff;
5865
5866 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
5867
5868 sense_buf[16] = (failing_lba & 0xff000000) >> 24;
5869 sense_buf[17] = (failing_lba & 0x00ff0000) >> 16;
5870 sense_buf[18] = (failing_lba & 0x0000ff00) >> 8;
5871 sense_buf[19] = failing_lba & 0x000000ff;
5872 } else {
5873 sense_buf[0] = 0x70;
5874 sense_buf[2] = IPR_IOASC_SENSE_KEY(ioasc);
5875 sense_buf[12] = IPR_IOASC_SENSE_CODE(ioasc);
5876 sense_buf[13] = IPR_IOASC_SENSE_QUAL(ioasc);
5877
5878
5879 if ((IPR_IOASC_SENSE_KEY(ioasc) == 0x05) &&
5880 (be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_FIELD_POINTER_VALID)) {
5881 sense_buf[7] = 10;
5882
5883
5884 if (IPR_IOASC_SENSE_CODE(ioasc) == 0x24)
5885 sense_buf[15] = 0xC0;
5886 else
5887 sense_buf[15] = 0x80;
5888
5889 sense_buf[16] =
5890 ((IPR_FIELD_POINTER_MASK &
5891 be32_to_cpu(ioasa->hdr.ioasc_specific)) >> 8) & 0xff;
5892 sense_buf[17] =
5893 (IPR_FIELD_POINTER_MASK &
5894 be32_to_cpu(ioasa->hdr.ioasc_specific)) & 0xff;
5895 } else {
5896 if (ioasc == IPR_IOASC_MED_DO_NOT_REALLOC) {
5897 if (ipr_is_vset_device(res))
5898 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
5899 else
5900 failing_lba = be32_to_cpu(ioasa->u.dasd.failing_lba);
5901
5902 sense_buf[0] |= 0x80;
5903 sense_buf[3] = (failing_lba & 0xff000000) >> 24;
5904 sense_buf[4] = (failing_lba & 0x00ff0000) >> 16;
5905 sense_buf[5] = (failing_lba & 0x0000ff00) >> 8;
5906 sense_buf[6] = failing_lba & 0x000000ff;
5907 }
5908
5909 sense_buf[7] = 6;
5910 }
5911 }
5912}
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924static int ipr_get_autosense(struct ipr_cmnd *ipr_cmd)
5925{
5926 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5927 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
5928
5929 if ((be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_AUTOSENSE_VALID) == 0)
5930 return 0;
5931
5932 if (ipr_cmd->ioa_cfg->sis64)
5933 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa64->auto_sense.data,
5934 min_t(u16, be16_to_cpu(ioasa64->auto_sense.auto_sense_len),
5935 SCSI_SENSE_BUFFERSIZE));
5936 else
5937 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa->auto_sense.data,
5938 min_t(u16, be16_to_cpu(ioasa->auto_sense.auto_sense_len),
5939 SCSI_SENSE_BUFFERSIZE));
5940 return 1;
5941}
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954static void ipr_erp_start(struct ipr_ioa_cfg *ioa_cfg,
5955 struct ipr_cmnd *ipr_cmd)
5956{
5957 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5958 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5959 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5960 u32 masked_ioasc = ioasc & IPR_IOASC_IOASC_MASK;
5961
5962 if (!res) {
5963 ipr_scsi_eh_done(ipr_cmd);
5964 return;
5965 }
5966
5967 if (!ipr_is_gscsi(res) && masked_ioasc != IPR_IOASC_HW_DEV_BUS_STATUS)
5968 ipr_gen_sense(ipr_cmd);
5969
5970 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
5971
5972 switch (masked_ioasc) {
5973 case IPR_IOASC_ABORTED_CMD_TERM_BY_HOST:
5974 if (ipr_is_naca_model(res))
5975 scsi_cmd->result |= (DID_ABORT << 16);
5976 else
5977 scsi_cmd->result |= (DID_IMM_RETRY << 16);
5978 break;
5979 case IPR_IOASC_IR_RESOURCE_HANDLE:
5980 case IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA:
5981 scsi_cmd->result |= (DID_NO_CONNECT << 16);
5982 break;
5983 case IPR_IOASC_HW_SEL_TIMEOUT:
5984 scsi_cmd->result |= (DID_NO_CONNECT << 16);
5985 if (!ipr_is_naca_model(res))
5986 res->needs_sync_complete = 1;
5987 break;
5988 case IPR_IOASC_SYNC_REQUIRED:
5989 if (!res->in_erp)
5990 res->needs_sync_complete = 1;
5991 scsi_cmd->result |= (DID_IMM_RETRY << 16);
5992 break;
5993 case IPR_IOASC_MED_DO_NOT_REALLOC:
5994 case IPR_IOASA_IR_DUAL_IOA_DISABLED:
5995 scsi_cmd->result |= (DID_PASSTHROUGH << 16);
5996 break;
5997 case IPR_IOASC_BUS_WAS_RESET:
5998 case IPR_IOASC_BUS_WAS_RESET_BY_OTHER:
5999
6000
6001
6002
6003 if (!res->resetting_device)
6004 scsi_report_bus_reset(ioa_cfg->host, scsi_cmd->device->channel);
6005 scsi_cmd->result |= (DID_ERROR << 16);
6006 if (!ipr_is_naca_model(res))
6007 res->needs_sync_complete = 1;
6008 break;
6009 case IPR_IOASC_HW_DEV_BUS_STATUS:
6010 scsi_cmd->result |= IPR_IOASC_SENSE_STATUS(ioasc);
6011 if (IPR_IOASC_SENSE_STATUS(ioasc) == SAM_STAT_CHECK_CONDITION) {
6012 if (!ipr_get_autosense(ipr_cmd)) {
6013 if (!ipr_is_naca_model(res)) {
6014 ipr_erp_cancel_all(ipr_cmd);
6015 return;
6016 }
6017 }
6018 }
6019 if (!ipr_is_naca_model(res))
6020 res->needs_sync_complete = 1;
6021 break;
6022 case IPR_IOASC_NR_INIT_CMD_REQUIRED:
6023 break;
6024 default:
6025 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6026 scsi_cmd->result |= (DID_ERROR << 16);
6027 if (!ipr_is_vset_device(res) && !ipr_is_naca_model(res))
6028 res->needs_sync_complete = 1;
6029 break;
6030 }
6031
6032 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6033 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6034 scsi_cmd->scsi_done(scsi_cmd);
6035}
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047static void ipr_scsi_done(struct ipr_cmnd *ipr_cmd)
6048{
6049 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6050 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6051 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6052 unsigned long hrrq_flags;
6053
6054 scsi_set_resid(scsi_cmd, be32_to_cpu(ipr_cmd->s.ioasa.hdr.residual_data_len));
6055
6056 if (likely(IPR_IOASC_SENSE_KEY(ioasc) == 0)) {
6057 scsi_dma_unmap(scsi_cmd);
6058
6059 spin_lock_irqsave(ipr_cmd->hrrq->lock, hrrq_flags);
6060 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6061 scsi_cmd->scsi_done(scsi_cmd);
6062 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, hrrq_flags);
6063 } else {
6064 spin_lock_irqsave(ipr_cmd->hrrq->lock, hrrq_flags);
6065 ipr_erp_start(ioa_cfg, ipr_cmd);
6066 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, hrrq_flags);
6067 }
6068}
6069
6070
6071
6072
6073
6074
6075
6076
6077
6078
6079
6080
6081
6082static int ipr_queuecommand(struct Scsi_Host *shost,
6083 struct scsi_cmnd *scsi_cmd)
6084{
6085 struct ipr_ioa_cfg *ioa_cfg;
6086 struct ipr_resource_entry *res;
6087 struct ipr_ioarcb *ioarcb;
6088 struct ipr_cmnd *ipr_cmd;
6089 unsigned long hrrq_flags, lock_flags;
6090 int rc;
6091 struct ipr_hrr_queue *hrrq;
6092 int hrrq_id;
6093
6094 ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
6095
6096 scsi_cmd->result = (DID_OK << 16);
6097 res = scsi_cmd->device->hostdata;
6098
6099 if (ipr_is_gata(res) && res->sata_port) {
6100 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6101 rc = ata_sas_queuecmd(scsi_cmd, res->sata_port->ap);
6102 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6103 return rc;
6104 }
6105
6106 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6107 hrrq = &ioa_cfg->hrrq[hrrq_id];
6108
6109 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6110
6111
6112
6113
6114
6115 if (unlikely(!hrrq->allow_cmds && !hrrq->ioa_is_dead && !hrrq->removing_ioa)) {
6116 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6117 return SCSI_MLQUEUE_HOST_BUSY;
6118 }
6119
6120
6121
6122
6123
6124 if (unlikely(hrrq->ioa_is_dead || hrrq->removing_ioa || !res)) {
6125 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6126 goto err_nodev;
6127 }
6128
6129 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6130 if (ipr_cmd == NULL) {
6131 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6132 return SCSI_MLQUEUE_HOST_BUSY;
6133 }
6134 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6135
6136 ipr_init_ipr_cmnd(ipr_cmd, ipr_scsi_done);
6137 ioarcb = &ipr_cmd->ioarcb;
6138
6139 memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len);
6140 ipr_cmd->scsi_cmd = scsi_cmd;
6141 ipr_cmd->done = ipr_scsi_eh_done;
6142
6143 if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
6144 if (scsi_cmd->underflow == 0)
6145 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6146
6147 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6148 if (ipr_is_gscsi(res))
6149 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
6150 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
6151 ioarcb->cmd_pkt.flags_lo |= ipr_get_task_attributes(scsi_cmd);
6152 }
6153
6154 if (scsi_cmd->cmnd[0] >= 0xC0 &&
6155 (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE)) {
6156 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6157 }
6158
6159 if (ioa_cfg->sis64)
6160 rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd);
6161 else
6162 rc = ipr_build_ioadl(ioa_cfg, ipr_cmd);
6163
6164 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6165 if (unlikely(rc || (!hrrq->allow_cmds && !hrrq->ioa_is_dead))) {
6166 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6167 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6168 if (!rc)
6169 scsi_dma_unmap(scsi_cmd);
6170 return SCSI_MLQUEUE_HOST_BUSY;
6171 }
6172
6173 if (unlikely(hrrq->ioa_is_dead)) {
6174 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6175 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6176 scsi_dma_unmap(scsi_cmd);
6177 goto err_nodev;
6178 }
6179
6180 ioarcb->res_handle = res->res_handle;
6181 if (res->needs_sync_complete) {
6182 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_SYNC_COMPLETE;
6183 res->needs_sync_complete = 0;
6184 }
6185 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_pending_q);
6186 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6187 ipr_send_command(ipr_cmd);
6188 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6189 return 0;
6190
6191err_nodev:
6192 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6193 memset(scsi_cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
6194 scsi_cmd->result = (DID_NO_CONNECT << 16);
6195 scsi_cmd->scsi_done(scsi_cmd);
6196 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6197 return 0;
6198}
6199
6200
6201
6202
6203
6204
6205
6206
6207
6208
6209static int ipr_ioctl(struct scsi_device *sdev, int cmd, void __user *arg)
6210{
6211 struct ipr_resource_entry *res;
6212
6213 res = (struct ipr_resource_entry *)sdev->hostdata;
6214 if (res && ipr_is_gata(res)) {
6215 if (cmd == HDIO_GET_IDENTITY)
6216 return -ENOTTY;
6217 return ata_sas_scsi_ioctl(res->sata_port->ap, sdev, cmd, arg);
6218 }
6219
6220 return -EINVAL;
6221}
6222
6223
6224
6225
6226
6227
6228
6229
6230static const char *ipr_ioa_info(struct Scsi_Host *host)
6231{
6232 static char buffer[512];
6233 struct ipr_ioa_cfg *ioa_cfg;
6234 unsigned long lock_flags = 0;
6235
6236 ioa_cfg = (struct ipr_ioa_cfg *) host->hostdata;
6237
6238 spin_lock_irqsave(host->host_lock, lock_flags);
6239 sprintf(buffer, "IBM %X Storage Adapter", ioa_cfg->type);
6240 spin_unlock_irqrestore(host->host_lock, lock_flags);
6241
6242 return buffer;
6243}
6244
6245static struct scsi_host_template driver_template = {
6246 .module = THIS_MODULE,
6247 .name = "IPR",
6248 .info = ipr_ioa_info,
6249 .ioctl = ipr_ioctl,
6250 .queuecommand = ipr_queuecommand,
6251 .eh_abort_handler = ipr_eh_abort,
6252 .eh_device_reset_handler = ipr_eh_dev_reset,
6253 .eh_host_reset_handler = ipr_eh_host_reset,
6254 .slave_alloc = ipr_slave_alloc,
6255 .slave_configure = ipr_slave_configure,
6256 .slave_destroy = ipr_slave_destroy,
6257 .target_alloc = ipr_target_alloc,
6258 .target_destroy = ipr_target_destroy,
6259 .change_queue_depth = ipr_change_queue_depth,
6260 .change_queue_type = ipr_change_queue_type,
6261 .bios_param = ipr_biosparam,
6262 .can_queue = IPR_MAX_COMMANDS,
6263 .this_id = -1,
6264 .sg_tablesize = IPR_MAX_SGLIST,
6265 .max_sectors = IPR_IOA_MAX_SECTORS,
6266 .cmd_per_lun = IPR_MAX_CMD_PER_LUN,
6267 .use_clustering = ENABLE_CLUSTERING,
6268 .shost_attrs = ipr_ioa_attrs,
6269 .sdev_attrs = ipr_dev_attrs,
6270 .proc_name = IPR_NAME
6271};
6272
6273
6274
6275
6276
6277
6278static void ipr_ata_phy_reset(struct ata_port *ap)
6279{
6280 unsigned long flags;
6281 struct ipr_sata_port *sata_port = ap->private_data;
6282 struct ipr_resource_entry *res = sata_port->res;
6283 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6284 int rc;
6285
6286 ENTER;
6287 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6288 while (ioa_cfg->in_reset_reload) {
6289 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6290 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6291 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6292 }
6293
6294 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6295 goto out_unlock;
6296
6297 rc = ipr_device_reset(ioa_cfg, res);
6298
6299 if (rc) {
6300 ap->link.device[0].class = ATA_DEV_NONE;
6301 goto out_unlock;
6302 }
6303
6304 ap->link.device[0].class = res->ata_class;
6305 if (ap->link.device[0].class == ATA_DEV_UNKNOWN)
6306 ap->link.device[0].class = ATA_DEV_NONE;
6307
6308out_unlock:
6309 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6310 LEAVE;
6311}
6312
6313
6314
6315
6316
6317
6318
6319
6320static void ipr_ata_post_internal(struct ata_queued_cmd *qc)
6321{
6322 struct ipr_sata_port *sata_port = qc->ap->private_data;
6323 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6324 struct ipr_cmnd *ipr_cmd;
6325 struct ipr_hrr_queue *hrrq;
6326 unsigned long flags;
6327
6328 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6329 while (ioa_cfg->in_reset_reload) {
6330 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6331 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6332 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6333 }
6334
6335 for_each_hrrq(hrrq, ioa_cfg) {
6336 spin_lock(&hrrq->_lock);
6337 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
6338 if (ipr_cmd->qc == qc) {
6339 ipr_device_reset(ioa_cfg, sata_port->res);
6340 break;
6341 }
6342 }
6343 spin_unlock(&hrrq->_lock);
6344 }
6345 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6346}
6347
6348
6349
6350
6351
6352
6353
6354
6355
6356static void ipr_copy_sata_tf(struct ipr_ioarcb_ata_regs *regs,
6357 struct ata_taskfile *tf)
6358{
6359 regs->feature = tf->feature;
6360 regs->nsect = tf->nsect;
6361 regs->lbal = tf->lbal;
6362 regs->lbam = tf->lbam;
6363 regs->lbah = tf->lbah;
6364 regs->device = tf->device;
6365 regs->command = tf->command;
6366 regs->hob_feature = tf->hob_feature;
6367 regs->hob_nsect = tf->hob_nsect;
6368 regs->hob_lbal = tf->hob_lbal;
6369 regs->hob_lbam = tf->hob_lbam;
6370 regs->hob_lbah = tf->hob_lbah;
6371 regs->ctl = tf->ctl;
6372}
6373
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383
6384static void ipr_sata_done(struct ipr_cmnd *ipr_cmd)
6385{
6386 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6387 struct ata_queued_cmd *qc = ipr_cmd->qc;
6388 struct ipr_sata_port *sata_port = qc->ap->private_data;
6389 struct ipr_resource_entry *res = sata_port->res;
6390 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6391
6392 spin_lock(&ipr_cmd->hrrq->_lock);
6393 if (ipr_cmd->ioa_cfg->sis64)
6394 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
6395 sizeof(struct ipr_ioasa_gata));
6396 else
6397 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
6398 sizeof(struct ipr_ioasa_gata));
6399 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6400
6401 if (be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET)
6402 scsi_report_device_reset(ioa_cfg->host, res->bus, res->target);
6403
6404 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6405 qc->err_mask |= __ac_err_mask(sata_port->ioasa.status);
6406 else
6407 qc->err_mask |= ac_err_mask(sata_port->ioasa.status);
6408 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6409 spin_unlock(&ipr_cmd->hrrq->_lock);
6410 ata_qc_complete(qc);
6411}
6412
6413
6414
6415
6416
6417
6418
6419static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd,
6420 struct ata_queued_cmd *qc)
6421{
6422 u32 ioadl_flags = 0;
6423 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6424 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
6425 struct ipr_ioadl64_desc *last_ioadl64 = NULL;
6426 int len = qc->nbytes;
6427 struct scatterlist *sg;
6428 unsigned int si;
6429 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6430
6431 if (len == 0)
6432 return;
6433
6434 if (qc->dma_dir == DMA_TO_DEVICE) {
6435 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6436 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6437 } else if (qc->dma_dir == DMA_FROM_DEVICE)
6438 ioadl_flags = IPR_IOADL_FLAGS_READ;
6439
6440 ioarcb->data_transfer_length = cpu_to_be32(len);
6441 ioarcb->ioadl_len =
6442 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
6443 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6444 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl));
6445
6446 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6447 ioadl64->flags = cpu_to_be32(ioadl_flags);
6448 ioadl64->data_len = cpu_to_be32(sg_dma_len(sg));
6449 ioadl64->address = cpu_to_be64(sg_dma_address(sg));
6450
6451 last_ioadl64 = ioadl64;
6452 ioadl64++;
6453 }
6454
6455 if (likely(last_ioadl64))
6456 last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6457}
6458
6459
6460
6461
6462
6463
6464
6465static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd,
6466 struct ata_queued_cmd *qc)
6467{
6468 u32 ioadl_flags = 0;
6469 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6470 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
6471 struct ipr_ioadl_desc *last_ioadl = NULL;
6472 int len = qc->nbytes;
6473 struct scatterlist *sg;
6474 unsigned int si;
6475
6476 if (len == 0)
6477 return;
6478
6479 if (qc->dma_dir == DMA_TO_DEVICE) {
6480 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6481 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6482 ioarcb->data_transfer_length = cpu_to_be32(len);
6483 ioarcb->ioadl_len =
6484 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6485 } else if (qc->dma_dir == DMA_FROM_DEVICE) {
6486 ioadl_flags = IPR_IOADL_FLAGS_READ;
6487 ioarcb->read_data_transfer_length = cpu_to_be32(len);
6488 ioarcb->read_ioadl_len =
6489 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6490 }
6491
6492 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6493 ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6494 ioadl->address = cpu_to_be32(sg_dma_address(sg));
6495
6496 last_ioadl = ioadl;
6497 ioadl++;
6498 }
6499
6500 if (likely(last_ioadl))
6501 last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6502}
6503
6504
6505
6506
6507
6508
6509
6510
6511static int ipr_qc_defer(struct ata_queued_cmd *qc)
6512{
6513 struct ata_port *ap = qc->ap;
6514 struct ipr_sata_port *sata_port = ap->private_data;
6515 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6516 struct ipr_cmnd *ipr_cmd;
6517 struct ipr_hrr_queue *hrrq;
6518 int hrrq_id;
6519
6520 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6521 hrrq = &ioa_cfg->hrrq[hrrq_id];
6522
6523 qc->lldd_task = NULL;
6524 spin_lock(&hrrq->_lock);
6525 if (unlikely(hrrq->ioa_is_dead)) {
6526 spin_unlock(&hrrq->_lock);
6527 return 0;
6528 }
6529
6530 if (unlikely(!hrrq->allow_cmds)) {
6531 spin_unlock(&hrrq->_lock);
6532 return ATA_DEFER_LINK;
6533 }
6534
6535 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6536 if (ipr_cmd == NULL) {
6537 spin_unlock(&hrrq->_lock);
6538 return ATA_DEFER_LINK;
6539 }
6540
6541 qc->lldd_task = ipr_cmd;
6542 spin_unlock(&hrrq->_lock);
6543 return 0;
6544}
6545
6546
6547
6548
6549
6550
6551
6552
6553static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc)
6554{
6555 struct ata_port *ap = qc->ap;
6556 struct ipr_sata_port *sata_port = ap->private_data;
6557 struct ipr_resource_entry *res = sata_port->res;
6558 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6559 struct ipr_cmnd *ipr_cmd;
6560 struct ipr_ioarcb *ioarcb;
6561 struct ipr_ioarcb_ata_regs *regs;
6562
6563 if (qc->lldd_task == NULL)
6564 ipr_qc_defer(qc);
6565
6566 ipr_cmd = qc->lldd_task;
6567 if (ipr_cmd == NULL)
6568 return AC_ERR_SYSTEM;
6569
6570 qc->lldd_task = NULL;
6571 spin_lock(&ipr_cmd->hrrq->_lock);
6572 if (unlikely(!ipr_cmd->hrrq->allow_cmds ||
6573 ipr_cmd->hrrq->ioa_is_dead)) {
6574 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6575 spin_unlock(&ipr_cmd->hrrq->_lock);
6576 return AC_ERR_SYSTEM;
6577 }
6578
6579 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
6580 ioarcb = &ipr_cmd->ioarcb;
6581
6582 if (ioa_cfg->sis64) {
6583 regs = &ipr_cmd->i.ata_ioadl.regs;
6584 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
6585 } else
6586 regs = &ioarcb->u.add_data.u.regs;
6587
6588 memset(regs, 0, sizeof(*regs));
6589 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs));
6590
6591 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
6592 ipr_cmd->qc = qc;
6593 ipr_cmd->done = ipr_sata_done;
6594 ipr_cmd->ioarcb.res_handle = res->res_handle;
6595 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU;
6596 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6597 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6598 ipr_cmd->dma_use_sg = qc->n_elem;
6599
6600 if (ioa_cfg->sis64)
6601 ipr_build_ata_ioadl64(ipr_cmd, qc);
6602 else
6603 ipr_build_ata_ioadl(ipr_cmd, qc);
6604
6605 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
6606 ipr_copy_sata_tf(regs, &qc->tf);
6607 memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN);
6608 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6609
6610 switch (qc->tf.protocol) {
6611 case ATA_PROT_NODATA:
6612 case ATA_PROT_PIO:
6613 break;
6614
6615 case ATA_PROT_DMA:
6616 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6617 break;
6618
6619 case ATAPI_PROT_PIO:
6620 case ATAPI_PROT_NODATA:
6621 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6622 break;
6623
6624 case ATAPI_PROT_DMA:
6625 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6626 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6627 break;
6628
6629 default:
6630 WARN_ON(1);
6631 spin_unlock(&ipr_cmd->hrrq->_lock);
6632 return AC_ERR_INVALID;
6633 }
6634
6635 ipr_send_command(ipr_cmd);
6636 spin_unlock(&ipr_cmd->hrrq->_lock);
6637
6638 return 0;
6639}
6640
6641
6642
6643
6644
6645
6646
6647
6648static bool ipr_qc_fill_rtf(struct ata_queued_cmd *qc)
6649{
6650 struct ipr_sata_port *sata_port = qc->ap->private_data;
6651 struct ipr_ioasa_gata *g = &sata_port->ioasa;
6652 struct ata_taskfile *tf = &qc->result_tf;
6653
6654 tf->feature = g->error;
6655 tf->nsect = g->nsect;
6656 tf->lbal = g->lbal;
6657 tf->lbam = g->lbam;
6658 tf->lbah = g->lbah;
6659 tf->device = g->device;
6660 tf->command = g->status;
6661 tf->hob_nsect = g->hob_nsect;
6662 tf->hob_lbal = g->hob_lbal;
6663 tf->hob_lbam = g->hob_lbam;
6664 tf->hob_lbah = g->hob_lbah;
6665 tf->ctl = g->alt_status;
6666
6667 return true;
6668}
6669
6670static struct ata_port_operations ipr_sata_ops = {
6671 .phy_reset = ipr_ata_phy_reset,
6672 .hardreset = ipr_sata_reset,
6673 .post_internal_cmd = ipr_ata_post_internal,
6674 .qc_prep = ata_noop_qc_prep,
6675 .qc_defer = ipr_qc_defer,
6676 .qc_issue = ipr_qc_issue,
6677 .qc_fill_rtf = ipr_qc_fill_rtf,
6678 .port_start = ata_sas_port_start,
6679 .port_stop = ata_sas_port_stop
6680};
6681
6682static struct ata_port_info sata_port_info = {
6683 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
6684 .pio_mask = ATA_PIO4_ONLY,
6685 .mwdma_mask = ATA_MWDMA2,
6686 .udma_mask = ATA_UDMA6,
6687 .port_ops = &ipr_sata_ops
6688};
6689
6690#ifdef CONFIG_PPC_PSERIES
6691static const u16 ipr_blocked_processors[] = {
6692 PVR_NORTHSTAR,
6693 PVR_PULSAR,
6694 PVR_POWER4,
6695 PVR_ICESTAR,
6696 PVR_SSTAR,
6697 PVR_POWER4p,
6698 PVR_630,
6699 PVR_630p
6700};
6701
6702
6703
6704
6705
6706
6707
6708
6709
6710
6711
6712
6713static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
6714{
6715 int i;
6716
6717 if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
6718 for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++) {
6719 if (pvr_version_is(ipr_blocked_processors[i]))
6720 return 1;
6721 }
6722 }
6723 return 0;
6724}
6725#else
6726#define ipr_invalid_adapter(ioa_cfg) 0
6727#endif
6728
6729
6730
6731
6732
6733
6734
6735
6736
6737
6738
6739static int ipr_ioa_bringdown_done(struct ipr_cmnd *ipr_cmd)
6740{
6741 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6742
6743 ENTER;
6744 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
6745 ipr_trace;
6746 spin_unlock_irq(ioa_cfg->host->host_lock);
6747 scsi_unblock_requests(ioa_cfg->host);
6748 spin_lock_irq(ioa_cfg->host->host_lock);
6749 }
6750
6751 ioa_cfg->in_reset_reload = 0;
6752 ioa_cfg->reset_retries = 0;
6753 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6754 wake_up_all(&ioa_cfg->reset_wait_q);
6755 LEAVE;
6756
6757 return IPR_RC_JOB_RETURN;
6758}
6759
6760
6761
6762
6763
6764
6765
6766
6767
6768
6769
6770
6771static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
6772{
6773 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6774 struct ipr_resource_entry *res;
6775 struct ipr_hostrcb *hostrcb, *temp;
6776 int i = 0, j;
6777
6778 ENTER;
6779 ioa_cfg->in_reset_reload = 0;
6780 for (j = 0; j < ioa_cfg->hrrq_num; j++) {
6781 spin_lock(&ioa_cfg->hrrq[j]._lock);
6782 ioa_cfg->hrrq[j].allow_cmds = 1;
6783 spin_unlock(&ioa_cfg->hrrq[j]._lock);
6784 }
6785 wmb();
6786 ioa_cfg->reset_cmd = NULL;
6787 ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
6788
6789 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
6790 if (ioa_cfg->allow_ml_add_del && (res->add_to_ml || res->del_from_ml)) {
6791 ipr_trace;
6792 break;
6793 }
6794 }
6795 schedule_work(&ioa_cfg->work_q);
6796
6797 list_for_each_entry_safe(hostrcb, temp, &ioa_cfg->hostrcb_free_q, queue) {
6798 list_del(&hostrcb->queue);
6799 if (i++ < IPR_NUM_LOG_HCAMS)
6800 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
6801 else
6802 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
6803 }
6804
6805 scsi_report_bus_reset(ioa_cfg->host, IPR_VSET_BUS);
6806 dev_info(&ioa_cfg->pdev->dev, "IOA initialized.\n");
6807
6808 ioa_cfg->reset_retries = 0;
6809 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6810 wake_up_all(&ioa_cfg->reset_wait_q);
6811
6812 spin_unlock(ioa_cfg->host->host_lock);
6813 scsi_unblock_requests(ioa_cfg->host);
6814 spin_lock(ioa_cfg->host->host_lock);
6815
6816 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6817 scsi_block_requests(ioa_cfg->host);
6818
6819 LEAVE;
6820 return IPR_RC_JOB_RETURN;
6821}
6822
6823
6824
6825
6826
6827
6828
6829
6830
6831static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev,
6832 struct ipr_std_inq_vpids *vpids)
6833{
6834 memset(supported_dev, 0, sizeof(struct ipr_supported_device));
6835 memcpy(&supported_dev->vpids, vpids, sizeof(struct ipr_std_inq_vpids));
6836 supported_dev->num_records = 1;
6837 supported_dev->data_length =
6838 cpu_to_be16(sizeof(struct ipr_supported_device));
6839 supported_dev->reserved = 0;
6840}
6841
6842
6843
6844
6845
6846
6847
6848
6849
6850
6851static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd)
6852{
6853 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6854 struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev;
6855 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6856 struct ipr_resource_entry *res = ipr_cmd->u.res;
6857
6858 ipr_cmd->job_step = ipr_ioa_reset_done;
6859
6860 list_for_each_entry_continue(res, &ioa_cfg->used_res_q, queue) {
6861 if (!ipr_is_scsi_disk(res))
6862 continue;
6863
6864 ipr_cmd->u.res = res;
6865 ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids);
6866
6867 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
6868 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6869 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6870
6871 ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES;
6872 ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES;
6873 ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff;
6874 ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff;
6875
6876 ipr_init_ioadl(ipr_cmd,
6877 ioa_cfg->vpd_cbs_dma +
6878 offsetof(struct ipr_misc_cbs, supp_dev),
6879 sizeof(struct ipr_supported_device),
6880 IPR_IOADL_FLAGS_WRITE_LAST);
6881
6882 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
6883 IPR_SET_SUP_DEVICE_TIMEOUT);
6884
6885 if (!ioa_cfg->sis64)
6886 ipr_cmd->job_step = ipr_set_supported_devs;
6887 LEAVE;
6888 return IPR_RC_JOB_RETURN;
6889 }
6890
6891 LEAVE;
6892 return IPR_RC_JOB_CONTINUE;
6893}
6894
6895
6896
6897
6898
6899
6900
6901
6902
6903
6904static void *ipr_get_mode_page(struct ipr_mode_pages *mode_pages,
6905 u32 page_code, u32 len)
6906{
6907 struct ipr_mode_page_hdr *mode_hdr;
6908 u32 page_length;
6909 u32 length;
6910
6911 if (!mode_pages || (mode_pages->hdr.length == 0))
6912 return NULL;
6913
6914 length = (mode_pages->hdr.length + 1) - 4 - mode_pages->hdr.block_desc_len;
6915 mode_hdr = (struct ipr_mode_page_hdr *)
6916 (mode_pages->data + mode_pages->hdr.block_desc_len);
6917
6918 while (length) {
6919 if (IPR_GET_MODE_PAGE_CODE(mode_hdr) == page_code) {
6920 if (mode_hdr->page_length >= (len - sizeof(struct ipr_mode_page_hdr)))
6921 return mode_hdr;
6922 break;
6923 } else {
6924 page_length = (sizeof(struct ipr_mode_page_hdr) +
6925 mode_hdr->page_length);
6926 length -= page_length;
6927 mode_hdr = (struct ipr_mode_page_hdr *)
6928 ((unsigned long)mode_hdr + page_length);
6929 }
6930 }
6931 return NULL;
6932}
6933
6934
6935
6936
6937
6938
6939
6940
6941
6942
6943
6944static void ipr_check_term_power(struct ipr_ioa_cfg *ioa_cfg,
6945 struct ipr_mode_pages *mode_pages)
6946{
6947 int i;
6948 int entry_length;
6949 struct ipr_dev_bus_entry *bus;
6950 struct ipr_mode_page28 *mode_page;
6951
6952 mode_page = ipr_get_mode_page(mode_pages, 0x28,
6953 sizeof(struct ipr_mode_page28));
6954
6955 entry_length = mode_page->entry_length;
6956
6957 bus = mode_page->bus;
6958
6959 for (i = 0; i < mode_page->num_entries; i++) {
6960 if (bus->flags & IPR_SCSI_ATTR_NO_TERM_PWR) {
6961 dev_err(&ioa_cfg->pdev->dev,
6962 "Term power is absent on scsi bus %d\n",
6963 bus->res_addr.bus);
6964 }
6965
6966 bus = (struct ipr_dev_bus_entry *)((char *)bus + entry_length);
6967 }
6968}
6969
6970
6971
6972
6973
6974
6975
6976
6977
6978
6979
6980
6981static void ipr_scsi_bus_speed_limit(struct ipr_ioa_cfg *ioa_cfg)
6982{
6983 u32 max_xfer_rate;
6984 int i;
6985
6986 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
6987 max_xfer_rate = ipr_get_max_scsi_speed(ioa_cfg, i,
6988 ioa_cfg->bus_attr[i].bus_width);
6989
6990 if (max_xfer_rate < ioa_cfg->bus_attr[i].max_xfer_rate)
6991 ioa_cfg->bus_attr[i].max_xfer_rate = max_xfer_rate;
6992 }
6993}
6994
6995
6996
6997
6998
6999
7000
7001
7002
7003
7004
7005static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg,
7006 struct ipr_mode_pages *mode_pages)
7007{
7008 int i, entry_length;
7009 struct ipr_dev_bus_entry *bus;
7010 struct ipr_bus_attributes *bus_attr;
7011 struct ipr_mode_page28 *mode_page;
7012
7013 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7014 sizeof(struct ipr_mode_page28));
7015
7016 entry_length = mode_page->entry_length;
7017
7018
7019 for (i = 0, bus = mode_page->bus;
7020 i < mode_page->num_entries;
7021 i++, bus = (struct ipr_dev_bus_entry *)((u8 *)bus + entry_length)) {
7022 if (bus->res_addr.bus > IPR_MAX_NUM_BUSES) {
7023 dev_err(&ioa_cfg->pdev->dev,
7024 "Invalid resource address reported: 0x%08X\n",
7025 IPR_GET_PHYS_LOC(bus->res_addr));
7026 continue;
7027 }
7028
7029 bus_attr = &ioa_cfg->bus_attr[i];
7030 bus->extended_reset_delay = IPR_EXTENDED_RESET_DELAY;
7031 bus->bus_width = bus_attr->bus_width;
7032 bus->max_xfer_rate = cpu_to_be32(bus_attr->max_xfer_rate);
7033 bus->flags &= ~IPR_SCSI_ATTR_QAS_MASK;
7034 if (bus_attr->qas_enabled)
7035 bus->flags |= IPR_SCSI_ATTR_ENABLE_QAS;
7036 else
7037 bus->flags |= IPR_SCSI_ATTR_DISABLE_QAS;
7038 }
7039}
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050
7051
7052static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd,
7053 __be32 res_handle, u8 parm,
7054 dma_addr_t dma_addr, u8 xfer_len)
7055{
7056 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7057
7058 ioarcb->res_handle = res_handle;
7059 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7060 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7061 ioarcb->cmd_pkt.cdb[0] = MODE_SELECT;
7062 ioarcb->cmd_pkt.cdb[1] = parm;
7063 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7064
7065 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST);
7066}
7067
7068
7069
7070
7071
7072
7073
7074
7075
7076
7077
7078static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd)
7079{
7080 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7081 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7082 int length;
7083
7084 ENTER;
7085 ipr_scsi_bus_speed_limit(ioa_cfg);
7086 ipr_check_term_power(ioa_cfg, mode_pages);
7087 ipr_modify_ioafp_mode_page_28(ioa_cfg, mode_pages);
7088 length = mode_pages->hdr.length + 1;
7089 mode_pages->hdr.length = 0;
7090
7091 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7092 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7093 length);
7094
7095 ipr_cmd->job_step = ipr_set_supported_devs;
7096 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7097 struct ipr_resource_entry, queue);
7098 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7099
7100 LEAVE;
7101 return IPR_RC_JOB_RETURN;
7102}
7103
7104
7105
7106
7107
7108
7109
7110
7111
7112
7113
7114
7115static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd,
7116 __be32 res_handle,
7117 u8 parm, dma_addr_t dma_addr, u8 xfer_len)
7118{
7119 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7120
7121 ioarcb->res_handle = res_handle;
7122 ioarcb->cmd_pkt.cdb[0] = MODE_SENSE;
7123 ioarcb->cmd_pkt.cdb[2] = parm;
7124 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7125 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7126
7127 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7128}
7129
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd)
7140{
7141 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7142 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7143
7144 dev_err(&ioa_cfg->pdev->dev,
7145 "0x%02X failed with IOASC: 0x%08X\n",
7146 ipr_cmd->ioarcb.cmd_pkt.cdb[0], ioasc);
7147
7148 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
7149 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7150 return IPR_RC_JOB_RETURN;
7151}
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd)
7164{
7165 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7166 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7167
7168 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7169 ipr_cmd->job_step = ipr_set_supported_devs;
7170 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7171 struct ipr_resource_entry, queue);
7172 return IPR_RC_JOB_CONTINUE;
7173 }
7174
7175 return ipr_reset_cmd_failed(ipr_cmd);
7176}
7177
7178
7179
7180
7181
7182
7183
7184
7185
7186
7187
7188static int ipr_ioafp_mode_sense_page28(struct ipr_cmnd *ipr_cmd)
7189{
7190 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7191
7192 ENTER;
7193 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7194 0x28, ioa_cfg->vpd_cbs_dma +
7195 offsetof(struct ipr_misc_cbs, mode_pages),
7196 sizeof(struct ipr_mode_pages));
7197
7198 ipr_cmd->job_step = ipr_ioafp_mode_select_page28;
7199 ipr_cmd->job_step_failed = ipr_reset_mode_sense_failed;
7200
7201 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7202
7203 LEAVE;
7204 return IPR_RC_JOB_RETURN;
7205}
7206
7207
7208
7209
7210
7211
7212
7213
7214
7215
7216static int ipr_ioafp_mode_select_page24(struct ipr_cmnd *ipr_cmd)
7217{
7218 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7219 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7220 struct ipr_mode_page24 *mode_page;
7221 int length;
7222
7223 ENTER;
7224 mode_page = ipr_get_mode_page(mode_pages, 0x24,
7225 sizeof(struct ipr_mode_page24));
7226
7227 if (mode_page)
7228 mode_page->flags |= IPR_ENABLE_DUAL_IOA_AF;
7229
7230 length = mode_pages->hdr.length + 1;
7231 mode_pages->hdr.length = 0;
7232
7233 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7234 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7235 length);
7236
7237 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7238 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7239
7240 LEAVE;
7241 return IPR_RC_JOB_RETURN;
7242}
7243
7244
7245
7246
7247
7248
7249
7250
7251
7252
7253
7254static int ipr_reset_mode_sense_page24_failed(struct ipr_cmnd *ipr_cmd)
7255{
7256 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7257
7258 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7259 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7260 return IPR_RC_JOB_CONTINUE;
7261 }
7262
7263 return ipr_reset_cmd_failed(ipr_cmd);
7264}
7265
7266
7267
7268
7269
7270
7271
7272
7273
7274
7275
7276static int ipr_ioafp_mode_sense_page24(struct ipr_cmnd *ipr_cmd)
7277{
7278 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7279
7280 ENTER;
7281 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7282 0x24, ioa_cfg->vpd_cbs_dma +
7283 offsetof(struct ipr_misc_cbs, mode_pages),
7284 sizeof(struct ipr_mode_pages));
7285
7286 ipr_cmd->job_step = ipr_ioafp_mode_select_page24;
7287 ipr_cmd->job_step_failed = ipr_reset_mode_sense_page24_failed;
7288
7289 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7290
7291 LEAVE;
7292 return IPR_RC_JOB_RETURN;
7293}
7294
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd)
7308{
7309 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7310 struct ipr_resource_entry *res, *temp;
7311 struct ipr_config_table_entry_wrapper cfgtew;
7312 int entries, found, flag, i;
7313 LIST_HEAD(old_res);
7314
7315 ENTER;
7316 if (ioa_cfg->sis64)
7317 flag = ioa_cfg->u.cfg_table64->hdr64.flags;
7318 else
7319 flag = ioa_cfg->u.cfg_table->hdr.flags;
7320
7321 if (flag & IPR_UCODE_DOWNLOAD_REQ)
7322 dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n");
7323
7324 list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue)
7325 list_move_tail(&res->queue, &old_res);
7326
7327 if (ioa_cfg->sis64)
7328 entries = be16_to_cpu(ioa_cfg->u.cfg_table64->hdr64.num_entries);
7329 else
7330 entries = ioa_cfg->u.cfg_table->hdr.num_entries;
7331
7332 for (i = 0; i < entries; i++) {
7333 if (ioa_cfg->sis64)
7334 cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i];
7335 else
7336 cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i];
7337 found = 0;
7338
7339 list_for_each_entry_safe(res, temp, &old_res, queue) {
7340 if (ipr_is_same_device(res, &cfgtew)) {
7341 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7342 found = 1;
7343 break;
7344 }
7345 }
7346
7347 if (!found) {
7348 if (list_empty(&ioa_cfg->free_res_q)) {
7349 dev_err(&ioa_cfg->pdev->dev, "Too many devices attached\n");
7350 break;
7351 }
7352
7353 found = 1;
7354 res = list_entry(ioa_cfg->free_res_q.next,
7355 struct ipr_resource_entry, queue);
7356 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7357 ipr_init_res_entry(res, &cfgtew);
7358 res->add_to_ml = 1;
7359 } else if (res->sdev && (ipr_is_vset_device(res) || ipr_is_scsi_disk(res)))
7360 res->sdev->allow_restart = 1;
7361
7362 if (found)
7363 ipr_update_res_entry(res, &cfgtew);
7364 }
7365
7366 list_for_each_entry_safe(res, temp, &old_res, queue) {
7367 if (res->sdev) {
7368 res->del_from_ml = 1;
7369 res->res_handle = IPR_INVALID_RES_HANDLE;
7370 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7371 }
7372 }
7373
7374 list_for_each_entry_safe(res, temp, &old_res, queue) {
7375 ipr_clear_res_target(res);
7376 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
7377 }
7378
7379 if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
7380 ipr_cmd->job_step = ipr_ioafp_mode_sense_page24;
7381 else
7382 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7383
7384 LEAVE;
7385 return IPR_RC_JOB_CONTINUE;
7386}
7387
7388
7389
7390
7391
7392
7393
7394
7395
7396
7397
7398static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
7399{
7400 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7401 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7402 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
7403 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7404
7405 ENTER;
7406 if (cap->cap & IPR_CAP_DUAL_IOA_RAID)
7407 ioa_cfg->dual_raid = 1;
7408 dev_info(&ioa_cfg->pdev->dev, "Adapter firmware version: %02X%02X%02X%02X\n",
7409 ucode_vpd->major_release, ucode_vpd->card_type,
7410 ucode_vpd->minor_release[0], ucode_vpd->minor_release[1]);
7411 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7412 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7413
7414 ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG;
7415 ioarcb->cmd_pkt.cdb[6] = (ioa_cfg->cfg_table_size >> 16) & 0xff;
7416 ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff;
7417 ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff;
7418
7419 ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size,
7420 IPR_IOADL_FLAGS_READ_LAST);
7421
7422 ipr_cmd->job_step = ipr_init_res_table;
7423
7424 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7425
7426 LEAVE;
7427 return IPR_RC_JOB_RETURN;
7428}
7429
7430
7431
7432
7433
7434
7435
7436
7437
7438
7439static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page,
7440 dma_addr_t dma_addr, u8 xfer_len)
7441{
7442 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7443
7444 ENTER;
7445 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7446 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7447
7448 ioarcb->cmd_pkt.cdb[0] = INQUIRY;
7449 ioarcb->cmd_pkt.cdb[1] = flags;
7450 ioarcb->cmd_pkt.cdb[2] = page;
7451 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7452
7453 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7454
7455 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7456 LEAVE;
7457}
7458
7459
7460
7461
7462
7463
7464
7465
7466
7467
7468
7469static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
7470{
7471 int i;
7472
7473 for (i = 0; i < min_t(u8, page0->len, IPR_INQUIRY_PAGE0_ENTRIES); i++)
7474 if (page0->page[i] == page)
7475 return 1;
7476
7477 return 0;
7478}
7479
7480
7481
7482
7483
7484
7485
7486
7487
7488
7489
7490static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
7491{
7492 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7493 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
7494 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7495
7496 ENTER;
7497 ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
7498 memset(cap, 0, sizeof(*cap));
7499
7500 if (ipr_inquiry_page_supported(page0, 0xD0)) {
7501 ipr_ioafp_inquiry(ipr_cmd, 1, 0xD0,
7502 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, cap),
7503 sizeof(struct ipr_inquiry_cap));
7504 return IPR_RC_JOB_RETURN;
7505 }
7506
7507 LEAVE;
7508 return IPR_RC_JOB_CONTINUE;
7509}
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd)
7522{
7523 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7524
7525 ENTER;
7526
7527 ipr_cmd->job_step = ipr_ioafp_cap_inquiry;
7528
7529 ipr_ioafp_inquiry(ipr_cmd, 1, 3,
7530 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page3_data),
7531 sizeof(struct ipr_inquiry_page3));
7532
7533 LEAVE;
7534 return IPR_RC_JOB_RETURN;
7535}
7536
7537
7538
7539
7540
7541
7542
7543
7544
7545
7546
7547static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
7548{
7549 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7550 char type[5];
7551
7552 ENTER;
7553
7554
7555 memcpy(type, ioa_cfg->vpd_cbs->ioa_vpd.std_inq_data.vpids.product_id, 4);
7556 type[4] = '\0';
7557 ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
7558
7559 ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
7560
7561 ipr_ioafp_inquiry(ipr_cmd, 1, 0,
7562 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page0_data),
7563 sizeof(struct ipr_inquiry_page0));
7564
7565 LEAVE;
7566 return IPR_RC_JOB_RETURN;
7567}
7568
7569
7570
7571
7572
7573
7574
7575
7576
7577
7578static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
7579{
7580 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7581
7582 ENTER;
7583 ipr_cmd->job_step = ipr_ioafp_page0_inquiry;
7584
7585 ipr_ioafp_inquiry(ipr_cmd, 0, 0,
7586 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, ioa_vpd),
7587 sizeof(struct ipr_ioa_vpd));
7588
7589 LEAVE;
7590 return IPR_RC_JOB_RETURN;
7591}
7592
7593
7594
7595
7596
7597
7598
7599
7600
7601
7602
7603static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
7604{
7605 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7606 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7607 struct ipr_hrr_queue *hrrq;
7608
7609 ENTER;
7610 ipr_cmd->job_step = ipr_ioafp_std_inquiry;
7611 dev_info(&ioa_cfg->pdev->dev, "Starting IOA initialization sequence.\n");
7612
7613 if (ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num) {
7614 hrrq = &ioa_cfg->hrrq[ioa_cfg->identify_hrrq_index];
7615
7616 ioarcb->cmd_pkt.cdb[0] = IPR_ID_HOST_RR_Q;
7617 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7618
7619 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7620 if (ioa_cfg->sis64)
7621 ioarcb->cmd_pkt.cdb[1] = 0x1;
7622
7623 if (ioa_cfg->nvectors == 1)
7624 ioarcb->cmd_pkt.cdb[1] &= ~IPR_ID_HRRQ_SELE_ENABLE;
7625 else
7626 ioarcb->cmd_pkt.cdb[1] |= IPR_ID_HRRQ_SELE_ENABLE;
7627
7628 ioarcb->cmd_pkt.cdb[2] =
7629 ((u64) hrrq->host_rrq_dma >> 24) & 0xff;
7630 ioarcb->cmd_pkt.cdb[3] =
7631 ((u64) hrrq->host_rrq_dma >> 16) & 0xff;
7632 ioarcb->cmd_pkt.cdb[4] =
7633 ((u64) hrrq->host_rrq_dma >> 8) & 0xff;
7634 ioarcb->cmd_pkt.cdb[5] =
7635 ((u64) hrrq->host_rrq_dma) & 0xff;
7636 ioarcb->cmd_pkt.cdb[7] =
7637 ((sizeof(u32) * hrrq->size) >> 8) & 0xff;
7638 ioarcb->cmd_pkt.cdb[8] =
7639 (sizeof(u32) * hrrq->size) & 0xff;
7640
7641 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
7642 ioarcb->cmd_pkt.cdb[9] =
7643 ioa_cfg->identify_hrrq_index;
7644
7645 if (ioa_cfg->sis64) {
7646 ioarcb->cmd_pkt.cdb[10] =
7647 ((u64) hrrq->host_rrq_dma >> 56) & 0xff;
7648 ioarcb->cmd_pkt.cdb[11] =
7649 ((u64) hrrq->host_rrq_dma >> 48) & 0xff;
7650 ioarcb->cmd_pkt.cdb[12] =
7651 ((u64) hrrq->host_rrq_dma >> 40) & 0xff;
7652 ioarcb->cmd_pkt.cdb[13] =
7653 ((u64) hrrq->host_rrq_dma >> 32) & 0xff;
7654 }
7655
7656 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
7657 ioarcb->cmd_pkt.cdb[14] =
7658 ioa_cfg->identify_hrrq_index;
7659
7660 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7661 IPR_INTERNAL_TIMEOUT);
7662
7663 if (++ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num)
7664 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7665
7666 LEAVE;
7667 return IPR_RC_JOB_RETURN;
7668 }
7669
7670 LEAVE;
7671 return IPR_RC_JOB_CONTINUE;
7672}
7673
7674
7675
7676
7677
7678
7679
7680
7681
7682
7683
7684
7685
7686
7687static void ipr_reset_timer_done(struct ipr_cmnd *ipr_cmd)
7688{
7689 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7690 unsigned long lock_flags = 0;
7691
7692 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
7693
7694 if (ioa_cfg->reset_cmd == ipr_cmd) {
7695 list_del(&ipr_cmd->queue);
7696 ipr_cmd->done(ipr_cmd);
7697 }
7698
7699 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
7700}
7701
7702
7703
7704
7705
7706
7707
7708
7709
7710
7711
7712
7713
7714
7715
7716static void ipr_reset_start_timer(struct ipr_cmnd *ipr_cmd,
7717 unsigned long timeout)
7718{
7719
7720 ENTER;
7721 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7722 ipr_cmd->done = ipr_reset_ioa_job;
7723
7724 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7725 ipr_cmd->timer.expires = jiffies + timeout;
7726 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_reset_timer_done;
7727 add_timer(&ipr_cmd->timer);
7728}
7729
7730
7731
7732
7733
7734
7735
7736
7737static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
7738{
7739 struct ipr_hrr_queue *hrrq;
7740
7741 for_each_hrrq(hrrq, ioa_cfg) {
7742 spin_lock(&hrrq->_lock);
7743 memset(hrrq->host_rrq, 0, sizeof(u32) * hrrq->size);
7744
7745
7746 hrrq->hrrq_start = hrrq->host_rrq;
7747 hrrq->hrrq_end = &hrrq->host_rrq[hrrq->size - 1];
7748 hrrq->hrrq_curr = hrrq->hrrq_start;
7749 hrrq->toggle_bit = 1;
7750 spin_unlock(&hrrq->_lock);
7751 }
7752 wmb();
7753
7754 ioa_cfg->identify_hrrq_index = 0;
7755 if (ioa_cfg->hrrq_num == 1)
7756 atomic_set(&ioa_cfg->hrrq_index, 0);
7757 else
7758 atomic_set(&ioa_cfg->hrrq_index, 1);
7759
7760
7761 memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
7762}
7763
7764
7765
7766
7767
7768
7769
7770
7771static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
7772{
7773 unsigned long stage, stage_time;
7774 u32 feedback;
7775 volatile u32 int_reg;
7776 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7777 u64 maskval = 0;
7778
7779 feedback = readl(ioa_cfg->regs.init_feedback_reg);
7780 stage = feedback & IPR_IPL_INIT_STAGE_MASK;
7781 stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
7782
7783 ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
7784
7785
7786 if (stage_time == 0)
7787 stage_time = IPR_IPL_INIT_DEFAULT_STAGE_TIME;
7788 else if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
7789 stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
7790 else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
7791 stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
7792
7793 if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
7794 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
7795 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7796 stage_time = ioa_cfg->transop_timeout;
7797 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7798 } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
7799 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
7800 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
7801 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7802 maskval = IPR_PCII_IPL_STAGE_CHANGE;
7803 maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
7804 writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
7805 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7806 return IPR_RC_JOB_CONTINUE;
7807 }
7808 }
7809
7810 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7811 ipr_cmd->timer.expires = jiffies + stage_time * HZ;
7812 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
7813 ipr_cmd->done = ipr_reset_ioa_job;
7814 add_timer(&ipr_cmd->timer);
7815
7816 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7817
7818 return IPR_RC_JOB_RETURN;
7819}
7820
7821
7822
7823
7824
7825
7826
7827
7828
7829
7830
7831static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
7832{
7833 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7834 volatile u32 int_reg;
7835 volatile u64 maskval;
7836 int i;
7837
7838 ENTER;
7839 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7840 ipr_init_ioa_mem(ioa_cfg);
7841
7842 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
7843 spin_lock(&ioa_cfg->hrrq[i]._lock);
7844 ioa_cfg->hrrq[i].allow_interrupts = 1;
7845 spin_unlock(&ioa_cfg->hrrq[i]._lock);
7846 }
7847 wmb();
7848 if (ioa_cfg->sis64) {
7849
7850 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
7851 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
7852 }
7853
7854 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
7855
7856 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
7857 writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
7858 ioa_cfg->regs.clr_interrupt_mask_reg32);
7859 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7860 return IPR_RC_JOB_CONTINUE;
7861 }
7862
7863
7864 writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
7865
7866 if (ioa_cfg->sis64) {
7867 maskval = IPR_PCII_IPL_STAGE_CHANGE;
7868 maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS;
7869 writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);
7870 } else
7871 writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
7872
7873 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7874
7875 dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
7876
7877 if (ioa_cfg->sis64) {
7878 ipr_cmd->job_step = ipr_reset_next_stage;
7879 return IPR_RC_JOB_CONTINUE;
7880 }
7881
7882 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7883 ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
7884 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
7885 ipr_cmd->done = ipr_reset_ioa_job;
7886 add_timer(&ipr_cmd->timer);
7887 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7888
7889 LEAVE;
7890 return IPR_RC_JOB_RETURN;
7891}
7892
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902
7903static int ipr_reset_wait_for_dump(struct ipr_cmnd *ipr_cmd)
7904{
7905 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7906
7907 if (ioa_cfg->sdt_state == GET_DUMP)
7908 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
7909 else if (ioa_cfg->sdt_state == READ_DUMP)
7910 ioa_cfg->sdt_state = ABORT_DUMP;
7911
7912 ioa_cfg->dump_timeout = 1;
7913 ipr_cmd->job_step = ipr_reset_alert;
7914
7915 return IPR_RC_JOB_CONTINUE;
7916}
7917
7918
7919
7920
7921
7922
7923
7924
7925
7926
7927
7928static void ipr_unit_check_no_data(struct ipr_ioa_cfg *ioa_cfg)
7929{
7930 ioa_cfg->errors_logged++;
7931 dev_err(&ioa_cfg->pdev->dev, "IOA unit check with no data\n");
7932}
7933
7934
7935
7936
7937
7938
7939
7940
7941
7942
7943
7944static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg)
7945{
7946 unsigned long mailbox;
7947 struct ipr_hostrcb *hostrcb;
7948 struct ipr_uc_sdt sdt;
7949 int rc, length;
7950 u32 ioasc;
7951
7952 mailbox = readl(ioa_cfg->ioa_mailbox);
7953
7954 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) {
7955 ipr_unit_check_no_data(ioa_cfg);
7956 return;
7957 }
7958
7959 memset(&sdt, 0, sizeof(struct ipr_uc_sdt));
7960 rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt,
7961 (sizeof(struct ipr_uc_sdt)) / sizeof(__be32));
7962
7963 if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) ||
7964 ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
7965 (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
7966 ipr_unit_check_no_data(ioa_cfg);
7967 return;
7968 }
7969
7970
7971 if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE)
7972 length = be32_to_cpu(sdt.entry[0].end_token);
7973 else
7974 length = (be32_to_cpu(sdt.entry[0].end_token) -
7975 be32_to_cpu(sdt.entry[0].start_token)) &
7976 IPR_FMT2_MBX_ADDR_MASK;
7977
7978 hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next,
7979 struct ipr_hostrcb, queue);
7980 list_del(&hostrcb->queue);
7981 memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam));
7982
7983 rc = ipr_get_ldump_data_section(ioa_cfg,
7984 be32_to_cpu(sdt.entry[0].start_token),
7985 (__be32 *)&hostrcb->hcam,
7986 min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32));
7987
7988 if (!rc) {
7989 ipr_handle_log_data(ioa_cfg, hostrcb);
7990 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
7991 if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED &&
7992 ioa_cfg->sdt_state == GET_DUMP)
7993 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
7994 } else
7995 ipr_unit_check_no_data(ioa_cfg);
7996
7997 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
7998}
7999
8000
8001
8002
8003
8004
8005
8006
8007
8008
8009static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
8010{
8011 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8012
8013 ENTER;
8014 ioa_cfg->ioa_unit_checked = 0;
8015 ipr_get_unit_check_buffer(ioa_cfg);
8016 ipr_cmd->job_step = ipr_reset_alert;
8017 ipr_reset_start_timer(ipr_cmd, 0);
8018
8019 LEAVE;
8020 return IPR_RC_JOB_RETURN;
8021}
8022
8023
8024
8025
8026
8027
8028
8029
8030
8031
8032
8033
8034static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
8035{
8036 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8037 u32 int_reg;
8038
8039 ENTER;
8040 ioa_cfg->pdev->state_saved = true;
8041 pci_restore_state(ioa_cfg->pdev);
8042
8043 if (ipr_set_pcix_cmd_reg(ioa_cfg)) {
8044 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8045 return IPR_RC_JOB_CONTINUE;
8046 }
8047
8048 ipr_fail_all_ops(ioa_cfg);
8049
8050 if (ioa_cfg->sis64) {
8051
8052 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8053 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8054 }
8055
8056 if (ioa_cfg->ioa_unit_checked) {
8057 if (ioa_cfg->sis64) {
8058 ipr_cmd->job_step = ipr_reset_get_unit_check_job;
8059 ipr_reset_start_timer(ipr_cmd, IPR_DUMP_DELAY_TIMEOUT);
8060 return IPR_RC_JOB_RETURN;
8061 } else {
8062 ioa_cfg->ioa_unit_checked = 0;
8063 ipr_get_unit_check_buffer(ioa_cfg);
8064 ipr_cmd->job_step = ipr_reset_alert;
8065 ipr_reset_start_timer(ipr_cmd, 0);
8066 return IPR_RC_JOB_RETURN;
8067 }
8068 }
8069
8070 if (ioa_cfg->in_ioa_bringdown) {
8071 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8072 } else {
8073 ipr_cmd->job_step = ipr_reset_enable_ioa;
8074
8075 if (GET_DUMP == ioa_cfg->sdt_state) {
8076 ioa_cfg->sdt_state = READ_DUMP;
8077 ioa_cfg->dump_timeout = 0;
8078 if (ioa_cfg->sis64)
8079 ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
8080 else
8081 ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
8082 ipr_cmd->job_step = ipr_reset_wait_for_dump;
8083 schedule_work(&ioa_cfg->work_q);
8084 return IPR_RC_JOB_RETURN;
8085 }
8086 }
8087
8088 LEAVE;
8089 return IPR_RC_JOB_CONTINUE;
8090}
8091
8092
8093
8094
8095
8096
8097
8098
8099
8100
8101static int ipr_reset_bist_done(struct ipr_cmnd *ipr_cmd)
8102{
8103 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8104
8105 ENTER;
8106 if (ioa_cfg->cfg_locked)
8107 pci_cfg_access_unlock(ioa_cfg->pdev);
8108 ioa_cfg->cfg_locked = 0;
8109 ipr_cmd->job_step = ipr_reset_restore_cfg_space;
8110 LEAVE;
8111 return IPR_RC_JOB_CONTINUE;
8112}
8113
8114
8115
8116
8117
8118
8119
8120
8121
8122
8123static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
8124{
8125 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8126 int rc = PCIBIOS_SUCCESSFUL;
8127
8128 ENTER;
8129 if (ioa_cfg->ipr_chip->bist_method == IPR_MMIO)
8130 writel(IPR_UPROCI_SIS64_START_BIST,
8131 ioa_cfg->regs.set_uproc_interrupt_reg32);
8132 else
8133 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
8134
8135 if (rc == PCIBIOS_SUCCESSFUL) {
8136 ipr_cmd->job_step = ipr_reset_bist_done;
8137 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8138 rc = IPR_RC_JOB_RETURN;
8139 } else {
8140 if (ioa_cfg->cfg_locked)
8141 pci_cfg_access_unlock(ipr_cmd->ioa_cfg->pdev);
8142 ioa_cfg->cfg_locked = 0;
8143 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8144 rc = IPR_RC_JOB_CONTINUE;
8145 }
8146
8147 LEAVE;
8148 return rc;
8149}
8150
8151
8152
8153
8154
8155
8156
8157
8158
8159
8160static int ipr_reset_slot_reset_done(struct ipr_cmnd *ipr_cmd)
8161{
8162 ENTER;
8163 pci_set_pcie_reset_state(ipr_cmd->ioa_cfg->pdev, pcie_deassert_reset);
8164 ipr_cmd->job_step = ipr_reset_bist_done;
8165 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8166 LEAVE;
8167 return IPR_RC_JOB_RETURN;
8168}
8169
8170
8171
8172
8173
8174
8175
8176
8177
8178
8179static int ipr_reset_slot_reset(struct ipr_cmnd *ipr_cmd)
8180{
8181 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8182 struct pci_dev *pdev = ioa_cfg->pdev;
8183
8184 ENTER;
8185 pci_set_pcie_reset_state(pdev, pcie_warm_reset);
8186 ipr_cmd->job_step = ipr_reset_slot_reset_done;
8187 ipr_reset_start_timer(ipr_cmd, IPR_PCI_RESET_TIMEOUT);
8188 LEAVE;
8189 return IPR_RC_JOB_RETURN;
8190}
8191
8192
8193
8194
8195
8196
8197
8198
8199
8200
8201static int ipr_reset_block_config_access_wait(struct ipr_cmnd *ipr_cmd)
8202{
8203 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8204 int rc = IPR_RC_JOB_CONTINUE;
8205
8206 if (pci_cfg_access_trylock(ioa_cfg->pdev)) {
8207 ioa_cfg->cfg_locked = 1;
8208 ipr_cmd->job_step = ioa_cfg->reset;
8209 } else {
8210 if (ipr_cmd->u.time_left) {
8211 rc = IPR_RC_JOB_RETURN;
8212 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8213 ipr_reset_start_timer(ipr_cmd,
8214 IPR_CHECK_FOR_RESET_TIMEOUT);
8215 } else {
8216 ipr_cmd->job_step = ioa_cfg->reset;
8217 dev_err(&ioa_cfg->pdev->dev,
8218 "Timed out waiting to lock config access. Resetting anyway.\n");
8219 }
8220 }
8221
8222 return rc;
8223}
8224
8225
8226
8227
8228
8229
8230
8231
8232
8233
8234static int ipr_reset_block_config_access(struct ipr_cmnd *ipr_cmd)
8235{
8236 ipr_cmd->ioa_cfg->cfg_locked = 0;
8237 ipr_cmd->job_step = ipr_reset_block_config_access_wait;
8238 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8239 return IPR_RC_JOB_CONTINUE;
8240}
8241
8242
8243
8244
8245
8246
8247
8248
8249static int ipr_reset_allowed(struct ipr_ioa_cfg *ioa_cfg)
8250{
8251 volatile u32 temp_reg;
8252
8253 temp_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
8254 return ((temp_reg & IPR_PCII_CRITICAL_OPERATION) == 0);
8255}
8256
8257
8258
8259
8260
8261
8262
8263
8264
8265
8266
8267
8268
8269
8270
8271
8272static int ipr_reset_wait_to_start_bist(struct ipr_cmnd *ipr_cmd)
8273{
8274 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8275 int rc = IPR_RC_JOB_RETURN;
8276
8277 if (!ipr_reset_allowed(ioa_cfg) && ipr_cmd->u.time_left) {
8278 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8279 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8280 } else {
8281 ipr_cmd->job_step = ipr_reset_block_config_access;
8282 rc = IPR_RC_JOB_CONTINUE;
8283 }
8284
8285 return rc;
8286}
8287
8288
8289
8290
8291
8292
8293
8294
8295
8296
8297
8298
8299
8300static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
8301{
8302 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8303 u16 cmd_reg;
8304 int rc;
8305
8306 ENTER;
8307 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
8308
8309 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
8310 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
8311 writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
8312 ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
8313 } else {
8314 ipr_cmd->job_step = ipr_reset_block_config_access;
8315 }
8316
8317 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8318 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8319
8320 LEAVE;
8321 return IPR_RC_JOB_RETURN;
8322}
8323
8324
8325
8326
8327
8328
8329
8330
8331
8332
8333static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
8334{
8335 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8336 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
8337
8338 pci_unmap_sg(ioa_cfg->pdev, sglist->scatterlist,
8339 sglist->num_sg, DMA_TO_DEVICE);
8340
8341 ipr_cmd->job_step = ipr_reset_alert;
8342 return IPR_RC_JOB_CONTINUE;
8343}
8344
8345
8346
8347
8348
8349
8350
8351
8352
8353
8354
8355static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd)
8356{
8357 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8358 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
8359
8360 ENTER;
8361 ipr_cmd->job_step = ipr_reset_alert;
8362
8363 if (!sglist)
8364 return IPR_RC_JOB_CONTINUE;
8365
8366 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8367 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
8368 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = WRITE_BUFFER;
8369 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_WR_BUF_DOWNLOAD_AND_SAVE;
8370 ipr_cmd->ioarcb.cmd_pkt.cdb[6] = (sglist->buffer_len & 0xff0000) >> 16;
8371 ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8;
8372 ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff;
8373
8374 if (ioa_cfg->sis64)
8375 ipr_build_ucode_ioadl64(ipr_cmd, sglist);
8376 else
8377 ipr_build_ucode_ioadl(ipr_cmd, sglist);
8378 ipr_cmd->job_step = ipr_reset_ucode_download_done;
8379
8380 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8381 IPR_WRITE_BUFFER_TIMEOUT);
8382
8383 LEAVE;
8384 return IPR_RC_JOB_RETURN;
8385}
8386
8387
8388
8389
8390
8391
8392
8393
8394
8395
8396
8397
8398static int ipr_reset_shutdown_ioa(struct ipr_cmnd *ipr_cmd)
8399{
8400 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8401 enum ipr_shutdown_type shutdown_type = ipr_cmd->u.shutdown_type;
8402 unsigned long timeout;
8403 int rc = IPR_RC_JOB_CONTINUE;
8404
8405 ENTER;
8406 if (shutdown_type != IPR_SHUTDOWN_NONE &&
8407 !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
8408 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8409 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
8410 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
8411 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = shutdown_type;
8412
8413 if (shutdown_type == IPR_SHUTDOWN_NORMAL)
8414 timeout = IPR_SHUTDOWN_TIMEOUT;
8415 else if (shutdown_type == IPR_SHUTDOWN_PREPARE_FOR_NORMAL)
8416 timeout = IPR_INTERNAL_TIMEOUT;
8417 else if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
8418 timeout = IPR_DUAL_IOA_ABBR_SHUTDOWN_TO;
8419 else
8420 timeout = IPR_ABBREV_SHUTDOWN_TIMEOUT;
8421
8422 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, timeout);
8423
8424 rc = IPR_RC_JOB_RETURN;
8425 ipr_cmd->job_step = ipr_reset_ucode_download;
8426 } else
8427 ipr_cmd->job_step = ipr_reset_alert;
8428
8429 LEAVE;
8430 return rc;
8431}
8432
8433
8434
8435
8436
8437
8438
8439
8440
8441
8442static void ipr_reset_ioa_job(struct ipr_cmnd *ipr_cmd)
8443{
8444 u32 rc, ioasc;
8445 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8446
8447 do {
8448 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
8449
8450 if (ioa_cfg->reset_cmd != ipr_cmd) {
8451
8452
8453
8454
8455 list_add_tail(&ipr_cmd->queue,
8456 &ipr_cmd->hrrq->hrrq_free_q);
8457 return;
8458 }
8459
8460 if (IPR_IOASC_SENSE_KEY(ioasc)) {
8461 rc = ipr_cmd->job_step_failed(ipr_cmd);
8462 if (rc == IPR_RC_JOB_RETURN)
8463 return;
8464 }
8465
8466 ipr_reinit_ipr_cmnd(ipr_cmd);
8467 ipr_cmd->job_step_failed = ipr_reset_cmd_failed;
8468 rc = ipr_cmd->job_step(ipr_cmd);
8469 } while (rc == IPR_RC_JOB_CONTINUE);
8470}
8471
8472
8473
8474
8475
8476
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486static void _ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
8487 int (*job_step) (struct ipr_cmnd *),
8488 enum ipr_shutdown_type shutdown_type)
8489{
8490 struct ipr_cmnd *ipr_cmd;
8491 int i;
8492
8493 ioa_cfg->in_reset_reload = 1;
8494 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8495 spin_lock(&ioa_cfg->hrrq[i]._lock);
8496 ioa_cfg->hrrq[i].allow_cmds = 0;
8497 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8498 }
8499 wmb();
8500 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa)
8501 scsi_block_requests(ioa_cfg->host);
8502
8503 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
8504 ioa_cfg->reset_cmd = ipr_cmd;
8505 ipr_cmd->job_step = job_step;
8506 ipr_cmd->u.shutdown_type = shutdown_type;
8507
8508 ipr_reset_ioa_job(ipr_cmd);
8509}
8510
8511
8512
8513
8514
8515
8516
8517
8518
8519
8520
8521
8522
8523static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
8524 enum ipr_shutdown_type shutdown_type)
8525{
8526 int i;
8527
8528 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
8529 return;
8530
8531 if (ioa_cfg->in_reset_reload) {
8532 if (ioa_cfg->sdt_state == GET_DUMP)
8533 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8534 else if (ioa_cfg->sdt_state == READ_DUMP)
8535 ioa_cfg->sdt_state = ABORT_DUMP;
8536 }
8537
8538 if (ioa_cfg->reset_retries++ >= IPR_NUM_RESET_RELOAD_RETRIES) {
8539 dev_err(&ioa_cfg->pdev->dev,
8540 "IOA taken offline - error recovery failed\n");
8541
8542 ioa_cfg->reset_retries = 0;
8543 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8544 spin_lock(&ioa_cfg->hrrq[i]._lock);
8545 ioa_cfg->hrrq[i].ioa_is_dead = 1;
8546 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8547 }
8548 wmb();
8549
8550 if (ioa_cfg->in_ioa_bringdown) {
8551 ioa_cfg->reset_cmd = NULL;
8552 ioa_cfg->in_reset_reload = 0;
8553 ipr_fail_all_ops(ioa_cfg);
8554 wake_up_all(&ioa_cfg->reset_wait_q);
8555
8556 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
8557 spin_unlock_irq(ioa_cfg->host->host_lock);
8558 scsi_unblock_requests(ioa_cfg->host);
8559 spin_lock_irq(ioa_cfg->host->host_lock);
8560 }
8561 return;
8562 } else {
8563 ioa_cfg->in_ioa_bringdown = 1;
8564 shutdown_type = IPR_SHUTDOWN_NONE;
8565 }
8566 }
8567
8568 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_shutdown_ioa,
8569 shutdown_type);
8570}
8571
8572
8573
8574
8575
8576
8577
8578
8579
8580static int ipr_reset_freeze(struct ipr_cmnd *ipr_cmd)
8581{
8582 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8583 int i;
8584
8585
8586 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8587 spin_lock(&ioa_cfg->hrrq[i]._lock);
8588 ioa_cfg->hrrq[i].allow_interrupts = 0;
8589 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8590 }
8591 wmb();
8592 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8593 ipr_cmd->done = ipr_reset_ioa_job;
8594 return IPR_RC_JOB_RETURN;
8595}
8596
8597
8598
8599
8600
8601
8602
8603
8604
8605static void ipr_pci_frozen(struct pci_dev *pdev)
8606{
8607 unsigned long flags = 0;
8608 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8609
8610 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8611 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_freeze, IPR_SHUTDOWN_NONE);
8612 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8613}
8614
8615
8616
8617
8618
8619
8620
8621
8622
8623static pci_ers_result_t ipr_pci_slot_reset(struct pci_dev *pdev)
8624{
8625 unsigned long flags = 0;
8626 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8627
8628 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8629 if (ioa_cfg->needs_warm_reset)
8630 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8631 else
8632 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_restore_cfg_space,
8633 IPR_SHUTDOWN_NONE);
8634 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8635 return PCI_ERS_RESULT_RECOVERED;
8636}
8637
8638
8639
8640
8641
8642
8643
8644
8645static void ipr_pci_perm_failure(struct pci_dev *pdev)
8646{
8647 unsigned long flags = 0;
8648 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8649 int i;
8650
8651 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8652 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
8653 ioa_cfg->sdt_state = ABORT_DUMP;
8654 ioa_cfg->reset_retries = IPR_NUM_RESET_RELOAD_RETRIES;
8655 ioa_cfg->in_ioa_bringdown = 1;
8656 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8657 spin_lock(&ioa_cfg->hrrq[i]._lock);
8658 ioa_cfg->hrrq[i].allow_cmds = 0;
8659 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8660 }
8661 wmb();
8662 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8663 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8664}
8665
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676static pci_ers_result_t ipr_pci_error_detected(struct pci_dev *pdev,
8677 pci_channel_state_t state)
8678{
8679 switch (state) {
8680 case pci_channel_io_frozen:
8681 ipr_pci_frozen(pdev);
8682 return PCI_ERS_RESULT_NEED_RESET;
8683 case pci_channel_io_perm_failure:
8684 ipr_pci_perm_failure(pdev);
8685 return PCI_ERS_RESULT_DISCONNECT;
8686 break;
8687 default:
8688 break;
8689 }
8690 return PCI_ERS_RESULT_NEED_RESET;
8691}
8692
8693
8694
8695
8696
8697
8698
8699
8700
8701
8702
8703
8704static int ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
8705{
8706 int rc = 0;
8707 unsigned long host_lock_flags = 0;
8708
8709 ENTER;
8710 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8711 dev_dbg(&ioa_cfg->pdev->dev, "ioa_cfg adx: 0x%p\n", ioa_cfg);
8712 if (ioa_cfg->needs_hard_reset) {
8713 ioa_cfg->needs_hard_reset = 0;
8714 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8715 } else
8716 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
8717 IPR_SHUTDOWN_NONE);
8718 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8719 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
8720 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8721
8722 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
8723 rc = -EIO;
8724 } else if (ipr_invalid_adapter(ioa_cfg)) {
8725 if (!ipr_testmode)
8726 rc = -EIO;
8727
8728 dev_err(&ioa_cfg->pdev->dev,
8729 "Adapter not supported in this hardware configuration.\n");
8730 }
8731
8732 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8733
8734 LEAVE;
8735 return rc;
8736}
8737
8738
8739
8740
8741
8742
8743
8744
8745static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
8746{
8747 int i;
8748
8749 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
8750 if (ioa_cfg->ipr_cmnd_list[i])
8751 pci_pool_free(ioa_cfg->ipr_cmd_pool,
8752 ioa_cfg->ipr_cmnd_list[i],
8753 ioa_cfg->ipr_cmnd_list_dma[i]);
8754
8755 ioa_cfg->ipr_cmnd_list[i] = NULL;
8756 }
8757
8758 if (ioa_cfg->ipr_cmd_pool)
8759 pci_pool_destroy(ioa_cfg->ipr_cmd_pool);
8760
8761 kfree(ioa_cfg->ipr_cmnd_list);
8762 kfree(ioa_cfg->ipr_cmnd_list_dma);
8763 ioa_cfg->ipr_cmnd_list = NULL;
8764 ioa_cfg->ipr_cmnd_list_dma = NULL;
8765 ioa_cfg->ipr_cmd_pool = NULL;
8766}
8767
8768
8769
8770
8771
8772
8773
8774
8775static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
8776{
8777 int i;
8778
8779 kfree(ioa_cfg->res_entries);
8780 pci_free_consistent(ioa_cfg->pdev, sizeof(struct ipr_misc_cbs),
8781 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
8782 ipr_free_cmd_blks(ioa_cfg);
8783
8784 for (i = 0; i < ioa_cfg->hrrq_num; i++)
8785 pci_free_consistent(ioa_cfg->pdev,
8786 sizeof(u32) * ioa_cfg->hrrq[i].size,
8787 ioa_cfg->hrrq[i].host_rrq,
8788 ioa_cfg->hrrq[i].host_rrq_dma);
8789
8790 pci_free_consistent(ioa_cfg->pdev, ioa_cfg->cfg_table_size,
8791 ioa_cfg->u.cfg_table,
8792 ioa_cfg->cfg_table_dma);
8793
8794 for (i = 0; i < IPR_NUM_HCAMS; i++) {
8795 pci_free_consistent(ioa_cfg->pdev,
8796 sizeof(struct ipr_hostrcb),
8797 ioa_cfg->hostrcb[i],
8798 ioa_cfg->hostrcb_dma[i]);
8799 }
8800
8801 ipr_free_dump(ioa_cfg);
8802 kfree(ioa_cfg->trace);
8803}
8804
8805
8806
8807
8808
8809
8810
8811
8812
8813
8814
8815static void ipr_free_all_resources(struct ipr_ioa_cfg *ioa_cfg)
8816{
8817 struct pci_dev *pdev = ioa_cfg->pdev;
8818
8819 ENTER;
8820 if (ioa_cfg->intr_flag == IPR_USE_MSI ||
8821 ioa_cfg->intr_flag == IPR_USE_MSIX) {
8822 int i;
8823 for (i = 0; i < ioa_cfg->nvectors; i++)
8824 free_irq(ioa_cfg->vectors_info[i].vec,
8825 &ioa_cfg->hrrq[i]);
8826 } else
8827 free_irq(pdev->irq, &ioa_cfg->hrrq[0]);
8828
8829 if (ioa_cfg->intr_flag == IPR_USE_MSI) {
8830 pci_disable_msi(pdev);
8831 ioa_cfg->intr_flag &= ~IPR_USE_MSI;
8832 } else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
8833 pci_disable_msix(pdev);
8834 ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
8835 }
8836
8837 iounmap(ioa_cfg->hdw_dma_regs);
8838 pci_release_regions(pdev);
8839 ipr_free_mem(ioa_cfg);
8840 scsi_host_put(ioa_cfg->host);
8841 pci_disable_device(pdev);
8842 LEAVE;
8843}
8844
8845
8846
8847
8848
8849
8850
8851
8852static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
8853{
8854 struct ipr_cmnd *ipr_cmd;
8855 struct ipr_ioarcb *ioarcb;
8856 dma_addr_t dma_addr;
8857 int i, entries_each_hrrq, hrrq_id = 0;
8858
8859 ioa_cfg->ipr_cmd_pool = pci_pool_create(IPR_NAME, ioa_cfg->pdev,
8860 sizeof(struct ipr_cmnd), 512, 0);
8861
8862 if (!ioa_cfg->ipr_cmd_pool)
8863 return -ENOMEM;
8864
8865 ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL);
8866 ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL);
8867
8868 if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) {
8869 ipr_free_cmd_blks(ioa_cfg);
8870 return -ENOMEM;
8871 }
8872
8873 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8874 if (ioa_cfg->hrrq_num > 1) {
8875 if (i == 0) {
8876 entries_each_hrrq = IPR_NUM_INTERNAL_CMD_BLKS;
8877 ioa_cfg->hrrq[i].min_cmd_id = 0;
8878 ioa_cfg->hrrq[i].max_cmd_id =
8879 (entries_each_hrrq - 1);
8880 } else {
8881 entries_each_hrrq =
8882 IPR_NUM_BASE_CMD_BLKS/
8883 (ioa_cfg->hrrq_num - 1);
8884 ioa_cfg->hrrq[i].min_cmd_id =
8885 IPR_NUM_INTERNAL_CMD_BLKS +
8886 (i - 1) * entries_each_hrrq;
8887 ioa_cfg->hrrq[i].max_cmd_id =
8888 (IPR_NUM_INTERNAL_CMD_BLKS +
8889 i * entries_each_hrrq - 1);
8890 }
8891 } else {
8892 entries_each_hrrq = IPR_NUM_CMD_BLKS;
8893 ioa_cfg->hrrq[i].min_cmd_id = 0;
8894 ioa_cfg->hrrq[i].max_cmd_id = (entries_each_hrrq - 1);
8895 }
8896 ioa_cfg->hrrq[i].size = entries_each_hrrq;
8897 }
8898
8899 BUG_ON(ioa_cfg->hrrq_num == 0);
8900
8901 i = IPR_NUM_CMD_BLKS -
8902 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id - 1;
8903 if (i > 0) {
8904 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].size += i;
8905 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id += i;
8906 }
8907
8908 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
8909 ipr_cmd = pci_pool_alloc(ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
8910
8911 if (!ipr_cmd) {
8912 ipr_free_cmd_blks(ioa_cfg);
8913 return -ENOMEM;
8914 }
8915
8916 memset(ipr_cmd, 0, sizeof(*ipr_cmd));
8917 ioa_cfg->ipr_cmnd_list[i] = ipr_cmd;
8918 ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr;
8919
8920 ioarcb = &ipr_cmd->ioarcb;
8921 ipr_cmd->dma_addr = dma_addr;
8922 if (ioa_cfg->sis64)
8923 ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr);
8924 else
8925 ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr);
8926
8927 ioarcb->host_response_handle = cpu_to_be32(i << 2);
8928 if (ioa_cfg->sis64) {
8929 ioarcb->u.sis64_addr_data.data_ioadl_addr =
8930 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
8931 ioarcb->u.sis64_addr_data.ioasa_host_pci_addr =
8932 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, s.ioasa64));
8933 } else {
8934 ioarcb->write_ioadl_addr =
8935 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
8936 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
8937 ioarcb->ioasa_host_pci_addr =
8938 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, s.ioasa));
8939 }
8940 ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa));
8941 ipr_cmd->cmd_index = i;
8942 ipr_cmd->ioa_cfg = ioa_cfg;
8943 ipr_cmd->sense_buffer_dma = dma_addr +
8944 offsetof(struct ipr_cmnd, sense_buffer);
8945
8946 ipr_cmd->ioarcb.cmd_pkt.hrrq_id = hrrq_id;
8947 ipr_cmd->hrrq = &ioa_cfg->hrrq[hrrq_id];
8948 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
8949 if (i >= ioa_cfg->hrrq[hrrq_id].max_cmd_id)
8950 hrrq_id++;
8951 }
8952
8953 return 0;
8954}
8955
8956
8957
8958
8959
8960
8961
8962
8963static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
8964{
8965 struct pci_dev *pdev = ioa_cfg->pdev;
8966 int i, rc = -ENOMEM;
8967
8968 ENTER;
8969 ioa_cfg->res_entries = kzalloc(sizeof(struct ipr_resource_entry) *
8970 ioa_cfg->max_devs_supported, GFP_KERNEL);
8971
8972 if (!ioa_cfg->res_entries)
8973 goto out;
8974
8975 if (ioa_cfg->sis64) {
8976 ioa_cfg->target_ids = kzalloc(sizeof(unsigned long) *
8977 BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL);
8978 ioa_cfg->array_ids = kzalloc(sizeof(unsigned long) *
8979 BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL);
8980 ioa_cfg->vset_ids = kzalloc(sizeof(unsigned long) *
8981 BITS_TO_LONGS(ioa_cfg->max_devs_supported), GFP_KERNEL);
8982
8983 if (!ioa_cfg->target_ids || !ioa_cfg->array_ids
8984 || !ioa_cfg->vset_ids)
8985 goto out_free_res_entries;
8986 }
8987
8988 for (i = 0; i < ioa_cfg->max_devs_supported; i++) {
8989 list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q);
8990 ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
8991 }
8992
8993 ioa_cfg->vpd_cbs = pci_alloc_consistent(ioa_cfg->pdev,
8994 sizeof(struct ipr_misc_cbs),
8995 &ioa_cfg->vpd_cbs_dma);
8996
8997 if (!ioa_cfg->vpd_cbs)
8998 goto out_free_res_entries;
8999
9000 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9001 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_free_q);
9002 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_pending_q);
9003 spin_lock_init(&ioa_cfg->hrrq[i]._lock);
9004 if (i == 0)
9005 ioa_cfg->hrrq[i].lock = ioa_cfg->host->host_lock;
9006 else
9007 ioa_cfg->hrrq[i].lock = &ioa_cfg->hrrq[i]._lock;
9008 }
9009
9010 if (ipr_alloc_cmd_blks(ioa_cfg))
9011 goto out_free_vpd_cbs;
9012
9013 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9014 ioa_cfg->hrrq[i].host_rrq = pci_alloc_consistent(ioa_cfg->pdev,
9015 sizeof(u32) * ioa_cfg->hrrq[i].size,
9016 &ioa_cfg->hrrq[i].host_rrq_dma);
9017
9018 if (!ioa_cfg->hrrq[i].host_rrq) {
9019 while (--i > 0)
9020 pci_free_consistent(pdev,
9021 sizeof(u32) * ioa_cfg->hrrq[i].size,
9022 ioa_cfg->hrrq[i].host_rrq,
9023 ioa_cfg->hrrq[i].host_rrq_dma);
9024 goto out_ipr_free_cmd_blocks;
9025 }
9026 ioa_cfg->hrrq[i].ioa_cfg = ioa_cfg;
9027 }
9028
9029 ioa_cfg->u.cfg_table = pci_alloc_consistent(ioa_cfg->pdev,
9030 ioa_cfg->cfg_table_size,
9031 &ioa_cfg->cfg_table_dma);
9032
9033 if (!ioa_cfg->u.cfg_table)
9034 goto out_free_host_rrq;
9035
9036 for (i = 0; i < IPR_NUM_HCAMS; i++) {
9037 ioa_cfg->hostrcb[i] = pci_alloc_consistent(ioa_cfg->pdev,
9038 sizeof(struct ipr_hostrcb),
9039 &ioa_cfg->hostrcb_dma[i]);
9040
9041 if (!ioa_cfg->hostrcb[i])
9042 goto out_free_hostrcb_dma;
9043
9044 ioa_cfg->hostrcb[i]->hostrcb_dma =
9045 ioa_cfg->hostrcb_dma[i] + offsetof(struct ipr_hostrcb, hcam);
9046 ioa_cfg->hostrcb[i]->ioa_cfg = ioa_cfg;
9047 list_add_tail(&ioa_cfg->hostrcb[i]->queue, &ioa_cfg->hostrcb_free_q);
9048 }
9049
9050 ioa_cfg->trace = kzalloc(sizeof(struct ipr_trace_entry) *
9051 IPR_NUM_TRACE_ENTRIES, GFP_KERNEL);
9052
9053 if (!ioa_cfg->trace)
9054 goto out_free_hostrcb_dma;
9055
9056 rc = 0;
9057out:
9058 LEAVE;
9059 return rc;
9060
9061out_free_hostrcb_dma:
9062 while (i-- > 0) {
9063 pci_free_consistent(pdev, sizeof(struct ipr_hostrcb),
9064 ioa_cfg->hostrcb[i],
9065 ioa_cfg->hostrcb_dma[i]);
9066 }
9067 pci_free_consistent(pdev, ioa_cfg->cfg_table_size,
9068 ioa_cfg->u.cfg_table,
9069 ioa_cfg->cfg_table_dma);
9070out_free_host_rrq:
9071 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9072 pci_free_consistent(pdev,
9073 sizeof(u32) * ioa_cfg->hrrq[i].size,
9074 ioa_cfg->hrrq[i].host_rrq,
9075 ioa_cfg->hrrq[i].host_rrq_dma);
9076 }
9077out_ipr_free_cmd_blocks:
9078 ipr_free_cmd_blks(ioa_cfg);
9079out_free_vpd_cbs:
9080 pci_free_consistent(pdev, sizeof(struct ipr_misc_cbs),
9081 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9082out_free_res_entries:
9083 kfree(ioa_cfg->res_entries);
9084 kfree(ioa_cfg->target_ids);
9085 kfree(ioa_cfg->array_ids);
9086 kfree(ioa_cfg->vset_ids);
9087 goto out;
9088}
9089
9090
9091
9092
9093
9094
9095
9096
9097static void ipr_initialize_bus_attr(struct ipr_ioa_cfg *ioa_cfg)
9098{
9099 int i;
9100
9101 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
9102 ioa_cfg->bus_attr[i].bus = i;
9103 ioa_cfg->bus_attr[i].qas_enabled = 0;
9104 ioa_cfg->bus_attr[i].bus_width = IPR_DEFAULT_BUS_WIDTH;
9105 if (ipr_max_speed < ARRAY_SIZE(ipr_max_bus_speeds))
9106 ioa_cfg->bus_attr[i].max_xfer_rate = ipr_max_bus_speeds[ipr_max_speed];
9107 else
9108 ioa_cfg->bus_attr[i].max_xfer_rate = IPR_U160_SCSI_RATE;
9109 }
9110}
9111
9112
9113
9114
9115
9116
9117
9118
9119
9120
9121static void ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
9122 struct Scsi_Host *host, struct pci_dev *pdev)
9123{
9124 const struct ipr_interrupt_offsets *p;
9125 struct ipr_interrupts *t;
9126 void __iomem *base;
9127
9128 ioa_cfg->host = host;
9129 ioa_cfg->pdev = pdev;
9130 ioa_cfg->log_level = ipr_log_level;
9131 ioa_cfg->doorbell = IPR_DOORBELL;
9132 sprintf(ioa_cfg->eye_catcher, IPR_EYECATCHER);
9133 sprintf(ioa_cfg->trace_start, IPR_TRACE_START_LABEL);
9134 sprintf(ioa_cfg->cfg_table_start, IPR_CFG_TBL_START);
9135 sprintf(ioa_cfg->resource_table_label, IPR_RES_TABLE_LABEL);
9136 sprintf(ioa_cfg->ipr_hcam_label, IPR_HCAM_LABEL);
9137 sprintf(ioa_cfg->ipr_cmd_label, IPR_CMD_LABEL);
9138
9139 INIT_LIST_HEAD(&ioa_cfg->hostrcb_free_q);
9140 INIT_LIST_HEAD(&ioa_cfg->hostrcb_pending_q);
9141 INIT_LIST_HEAD(&ioa_cfg->free_res_q);
9142 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9143 INIT_WORK(&ioa_cfg->work_q, ipr_worker_thread);
9144 init_waitqueue_head(&ioa_cfg->reset_wait_q);
9145 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9146 ioa_cfg->sdt_state = INACTIVE;
9147
9148 ipr_initialize_bus_attr(ioa_cfg);
9149 ioa_cfg->max_devs_supported = ipr_max_devs;
9150
9151 if (ioa_cfg->sis64) {
9152 host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
9153 host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
9154 if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
9155 ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS;
9156 } else {
9157 host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
9158 host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
9159 if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
9160 ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS;
9161 }
9162 host->max_channel = IPR_MAX_BUS_TO_SCAN;
9163 host->unique_id = host->host_no;
9164 host->max_cmd_len = IPR_MAX_CDB_LEN;
9165 host->can_queue = ioa_cfg->max_cmds;
9166 pci_set_drvdata(pdev, ioa_cfg);
9167
9168 p = &ioa_cfg->chip_cfg->regs;
9169 t = &ioa_cfg->regs;
9170 base = ioa_cfg->hdw_dma_regs;
9171
9172 t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
9173 t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
9174 t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
9175 t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
9176 t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
9177 t->clr_interrupt_reg = base + p->clr_interrupt_reg;
9178 t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
9179 t->sense_interrupt_reg = base + p->sense_interrupt_reg;
9180 t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
9181 t->ioarrin_reg = base + p->ioarrin_reg;
9182 t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
9183 t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
9184 t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
9185 t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
9186 t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
9187 t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
9188
9189 if (ioa_cfg->sis64) {
9190 t->init_feedback_reg = base + p->init_feedback_reg;
9191 t->dump_addr_reg = base + p->dump_addr_reg;
9192 t->dump_data_reg = base + p->dump_data_reg;
9193 t->endian_swap_reg = base + p->endian_swap_reg;
9194 }
9195}
9196
9197
9198
9199
9200
9201
9202
9203
9204static const struct ipr_chip_t *
9205ipr_get_chip_info(const struct pci_device_id *dev_id)
9206{
9207 int i;
9208
9209 for (i = 0; i < ARRAY_SIZE(ipr_chip); i++)
9210 if (ipr_chip[i].vendor == dev_id->vendor &&
9211 ipr_chip[i].device == dev_id->device)
9212 return &ipr_chip[i];
9213 return NULL;
9214}
9215
9216static int ipr_enable_msix(struct ipr_ioa_cfg *ioa_cfg)
9217{
9218 struct msix_entry entries[IPR_MAX_MSIX_VECTORS];
9219 int i, err, vectors;
9220
9221 for (i = 0; i < ARRAY_SIZE(entries); ++i)
9222 entries[i].entry = i;
9223
9224 vectors = ipr_number_of_msix;
9225
9226 while ((err = pci_enable_msix(ioa_cfg->pdev, entries, vectors)) > 0)
9227 vectors = err;
9228
9229 if (err < 0) {
9230 pci_disable_msix(ioa_cfg->pdev);
9231 return err;
9232 }
9233
9234 if (!err) {
9235 for (i = 0; i < vectors; i++)
9236 ioa_cfg->vectors_info[i].vec = entries[i].vector;
9237 ioa_cfg->nvectors = vectors;
9238 }
9239
9240 return err;
9241}
9242
9243static int ipr_enable_msi(struct ipr_ioa_cfg *ioa_cfg)
9244{
9245 int i, err, vectors;
9246
9247 vectors = ipr_number_of_msix;
9248
9249 while ((err = pci_enable_msi_block(ioa_cfg->pdev, vectors)) > 0)
9250 vectors = err;
9251
9252 if (err < 0) {
9253 pci_disable_msi(ioa_cfg->pdev);
9254 return err;
9255 }
9256
9257 if (!err) {
9258 for (i = 0; i < vectors; i++)
9259 ioa_cfg->vectors_info[i].vec = ioa_cfg->pdev->irq + i;
9260 ioa_cfg->nvectors = vectors;
9261 }
9262
9263 return err;
9264}
9265
9266static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
9267{
9268 int vec_idx, n = sizeof(ioa_cfg->vectors_info[0].desc) - 1;
9269
9270 for (vec_idx = 0; vec_idx < ioa_cfg->nvectors; vec_idx++) {
9271 snprintf(ioa_cfg->vectors_info[vec_idx].desc, n,
9272 "host%d-%d", ioa_cfg->host->host_no, vec_idx);
9273 ioa_cfg->vectors_info[vec_idx].
9274 desc[strlen(ioa_cfg->vectors_info[vec_idx].desc)] = 0;
9275 }
9276}
9277
9278static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg)
9279{
9280 int i, rc;
9281
9282 for (i = 1; i < ioa_cfg->nvectors; i++) {
9283 rc = request_irq(ioa_cfg->vectors_info[i].vec,
9284 ipr_isr_mhrrq,
9285 0,
9286 ioa_cfg->vectors_info[i].desc,
9287 &ioa_cfg->hrrq[i]);
9288 if (rc) {
9289 while (--i >= 0)
9290 free_irq(ioa_cfg->vectors_info[i].vec,
9291 &ioa_cfg->hrrq[i]);
9292 return rc;
9293 }
9294 }
9295 return 0;
9296}
9297
9298
9299
9300
9301
9302
9303
9304
9305
9306
9307
9308static irqreturn_t ipr_test_intr(int irq, void *devp)
9309{
9310 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
9311 unsigned long lock_flags = 0;
9312 irqreturn_t rc = IRQ_HANDLED;
9313
9314 dev_info(&ioa_cfg->pdev->dev, "Received IRQ : %d\n", irq);
9315 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9316
9317 ioa_cfg->msi_received = 1;
9318 wake_up(&ioa_cfg->msi_wait_q);
9319
9320 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9321 return rc;
9322}
9323
9324
9325
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
9337{
9338 int rc;
9339 volatile u32 int_reg;
9340 unsigned long lock_flags = 0;
9341
9342 ENTER;
9343
9344 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9345 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9346 ioa_cfg->msi_received = 0;
9347 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9348 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
9349 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
9350 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9351
9352 if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9353 rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
9354 else
9355 rc = request_irq(pdev->irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
9356 if (rc) {
9357 dev_err(&pdev->dev, "Can not assign irq %d\n", pdev->irq);
9358 return rc;
9359 } else if (ipr_debug)
9360 dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq);
9361
9362 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
9363 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
9364 wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
9365 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9366 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9367
9368 if (!ioa_cfg->msi_received) {
9369
9370 dev_info(&pdev->dev, "MSI test failed. Falling back to LSI.\n");
9371 rc = -EOPNOTSUPP;
9372 } else if (ipr_debug)
9373 dev_info(&pdev->dev, "MSI test succeeded.\n");
9374
9375 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9376
9377 if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9378 free_irq(ioa_cfg->vectors_info[0].vec, ioa_cfg);
9379 else
9380 free_irq(pdev->irq, ioa_cfg);
9381
9382 LEAVE;
9383
9384 return rc;
9385}
9386
9387
9388
9389
9390
9391
9392
9393
9394static int ipr_probe_ioa(struct pci_dev *pdev,
9395 const struct pci_device_id *dev_id)
9396{
9397 struct ipr_ioa_cfg *ioa_cfg;
9398 struct Scsi_Host *host;
9399 unsigned long ipr_regs_pci;
9400 void __iomem *ipr_regs;
9401 int rc = PCIBIOS_SUCCESSFUL;
9402 volatile u32 mask, uproc, interrupts;
9403 unsigned long lock_flags;
9404
9405 ENTER;
9406
9407 if ((rc = pci_enable_device(pdev))) {
9408 dev_err(&pdev->dev, "Cannot enable adapter\n");
9409 goto out;
9410 }
9411
9412 dev_info(&pdev->dev, "Found IOA with IRQ: %d\n", pdev->irq);
9413
9414 host = scsi_host_alloc(&driver_template, sizeof(*ioa_cfg));
9415
9416 if (!host) {
9417 dev_err(&pdev->dev, "call to scsi_host_alloc failed!\n");
9418 rc = -ENOMEM;
9419 goto out_disable;
9420 }
9421
9422 ioa_cfg = (struct ipr_ioa_cfg *)host->hostdata;
9423 memset(ioa_cfg, 0, sizeof(struct ipr_ioa_cfg));
9424 ata_host_init(&ioa_cfg->ata_host, &pdev->dev, &ipr_sata_ops);
9425
9426 ioa_cfg->ipr_chip = ipr_get_chip_info(dev_id);
9427
9428 if (!ioa_cfg->ipr_chip) {
9429 dev_err(&pdev->dev, "Unknown adapter chipset 0x%04X 0x%04X\n",
9430 dev_id->vendor, dev_id->device);
9431 goto out_scsi_host_put;
9432 }
9433
9434
9435 ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
9436 ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
9437 ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
9438 ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds;
9439
9440 if (ipr_transop_timeout)
9441 ioa_cfg->transop_timeout = ipr_transop_timeout;
9442 else if (dev_id->driver_data & IPR_USE_LONG_TRANSOP_TIMEOUT)
9443 ioa_cfg->transop_timeout = IPR_LONG_OPERATIONAL_TIMEOUT;
9444 else
9445 ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
9446
9447 ioa_cfg->revid = pdev->revision;
9448
9449 ipr_regs_pci = pci_resource_start(pdev, 0);
9450
9451 rc = pci_request_regions(pdev, IPR_NAME);
9452 if (rc < 0) {
9453 dev_err(&pdev->dev,
9454 "Couldn't register memory range of registers\n");
9455 goto out_scsi_host_put;
9456 }
9457
9458 ipr_regs = pci_ioremap_bar(pdev, 0);
9459
9460 if (!ipr_regs) {
9461 dev_err(&pdev->dev,
9462 "Couldn't map memory range of registers\n");
9463 rc = -ENOMEM;
9464 goto out_release_regions;
9465 }
9466
9467 ioa_cfg->hdw_dma_regs = ipr_regs;
9468 ioa_cfg->hdw_dma_regs_pci = ipr_regs_pci;
9469 ioa_cfg->ioa_mailbox = ioa_cfg->chip_cfg->mailbox + ipr_regs;
9470
9471 ipr_init_ioa_cfg(ioa_cfg, host, pdev);
9472
9473 pci_set_master(pdev);
9474
9475 if (ioa_cfg->sis64) {
9476 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9477 if (rc < 0) {
9478 dev_dbg(&pdev->dev, "Failed to set 64 bit PCI DMA mask\n");
9479 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9480 }
9481
9482 } else
9483 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9484
9485 if (rc < 0) {
9486 dev_err(&pdev->dev, "Failed to set PCI DMA mask\n");
9487 goto cleanup_nomem;
9488 }
9489
9490 rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
9491 ioa_cfg->chip_cfg->cache_line_size);
9492
9493 if (rc != PCIBIOS_SUCCESSFUL) {
9494 dev_err(&pdev->dev, "Write of cache line size failed\n");
9495 rc = -EIO;
9496 goto cleanup_nomem;
9497 }
9498
9499 if (ipr_number_of_msix > IPR_MAX_MSIX_VECTORS) {
9500 dev_err(&pdev->dev, "The max number of MSIX is %d\n",
9501 IPR_MAX_MSIX_VECTORS);
9502 ipr_number_of_msix = IPR_MAX_MSIX_VECTORS;
9503 }
9504
9505 if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
9506 ipr_enable_msix(ioa_cfg) == 0)
9507 ioa_cfg->intr_flag = IPR_USE_MSIX;
9508 else if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
9509 ipr_enable_msi(ioa_cfg) == 0)
9510 ioa_cfg->intr_flag = IPR_USE_MSI;
9511 else {
9512 ioa_cfg->intr_flag = IPR_USE_LSI;
9513 ioa_cfg->nvectors = 1;
9514 dev_info(&pdev->dev, "Cannot enable MSI.\n");
9515 }
9516
9517 if (ioa_cfg->intr_flag == IPR_USE_MSI ||
9518 ioa_cfg->intr_flag == IPR_USE_MSIX) {
9519 rc = ipr_test_msi(ioa_cfg, pdev);
9520 if (rc == -EOPNOTSUPP) {
9521 if (ioa_cfg->intr_flag == IPR_USE_MSI) {
9522 ioa_cfg->intr_flag &= ~IPR_USE_MSI;
9523 pci_disable_msi(pdev);
9524 } else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
9525 ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
9526 pci_disable_msix(pdev);
9527 }
9528
9529 ioa_cfg->intr_flag = IPR_USE_LSI;
9530 ioa_cfg->nvectors = 1;
9531 }
9532 else if (rc)
9533 goto out_msi_disable;
9534 else {
9535 if (ioa_cfg->intr_flag == IPR_USE_MSI)
9536 dev_info(&pdev->dev,
9537 "Request for %d MSIs succeeded with starting IRQ: %d\n",
9538 ioa_cfg->nvectors, pdev->irq);
9539 else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9540 dev_info(&pdev->dev,
9541 "Request for %d MSIXs succeeded.",
9542 ioa_cfg->nvectors);
9543 }
9544 }
9545
9546 ioa_cfg->hrrq_num = min3(ioa_cfg->nvectors,
9547 (unsigned int)num_online_cpus(),
9548 (unsigned int)IPR_MAX_HRRQ_NUM);
9549
9550
9551 rc = pci_save_state(pdev);
9552
9553 if (rc != PCIBIOS_SUCCESSFUL) {
9554 dev_err(&pdev->dev, "Failed to save PCI config space\n");
9555 rc = -EIO;
9556 goto out_msi_disable;
9557 }
9558
9559 if ((rc = ipr_save_pcix_cmd_reg(ioa_cfg)))
9560 goto out_msi_disable;
9561
9562 if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg)))
9563 goto out_msi_disable;
9564
9565 if (ioa_cfg->sis64)
9566 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64)
9567 + ((sizeof(struct ipr_config_table_entry64)
9568 * ioa_cfg->max_devs_supported)));
9569 else
9570 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr)
9571 + ((sizeof(struct ipr_config_table_entry)
9572 * ioa_cfg->max_devs_supported)));
9573
9574 rc = ipr_alloc_mem(ioa_cfg);
9575 if (rc < 0) {
9576 dev_err(&pdev->dev,
9577 "Couldn't allocate enough memory for device driver!\n");
9578 goto out_msi_disable;
9579 }
9580
9581
9582
9583
9584
9585 mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
9586 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
9587 uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
9588 if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
9589 ioa_cfg->needs_hard_reset = 1;
9590 if ((interrupts & IPR_PCII_ERROR_INTERRUPTS) || reset_devices)
9591 ioa_cfg->needs_hard_reset = 1;
9592 if (interrupts & IPR_PCII_IOA_UNIT_CHECKED)
9593 ioa_cfg->ioa_unit_checked = 1;
9594
9595 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9596 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9597 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9598
9599 if (ioa_cfg->intr_flag == IPR_USE_MSI
9600 || ioa_cfg->intr_flag == IPR_USE_MSIX) {
9601 name_msi_vectors(ioa_cfg);
9602 rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_isr,
9603 0,
9604 ioa_cfg->vectors_info[0].desc,
9605 &ioa_cfg->hrrq[0]);
9606 if (!rc)
9607 rc = ipr_request_other_msi_irqs(ioa_cfg);
9608 } else {
9609 rc = request_irq(pdev->irq, ipr_isr,
9610 IRQF_SHARED,
9611 IPR_NAME, &ioa_cfg->hrrq[0]);
9612 }
9613 if (rc) {
9614 dev_err(&pdev->dev, "Couldn't register IRQ %d! rc=%d\n",
9615 pdev->irq, rc);
9616 goto cleanup_nolog;
9617 }
9618
9619 if ((dev_id->driver_data & IPR_USE_PCI_WARM_RESET) ||
9620 (dev_id->device == PCI_DEVICE_ID_IBM_OBSIDIAN_E && !ioa_cfg->revid)) {
9621 ioa_cfg->needs_warm_reset = 1;
9622 ioa_cfg->reset = ipr_reset_slot_reset;
9623 } else
9624 ioa_cfg->reset = ipr_reset_start_bist;
9625
9626 spin_lock(&ipr_driver_lock);
9627 list_add_tail(&ioa_cfg->queue, &ipr_ioa_head);
9628 spin_unlock(&ipr_driver_lock);
9629
9630 LEAVE;
9631out:
9632 return rc;
9633
9634cleanup_nolog:
9635 ipr_free_mem(ioa_cfg);
9636out_msi_disable:
9637 if (ioa_cfg->intr_flag == IPR_USE_MSI)
9638 pci_disable_msi(pdev);
9639 else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9640 pci_disable_msix(pdev);
9641cleanup_nomem:
9642 iounmap(ipr_regs);
9643out_release_regions:
9644 pci_release_regions(pdev);
9645out_scsi_host_put:
9646 scsi_host_put(host);
9647out_disable:
9648 pci_disable_device(pdev);
9649 goto out;
9650}
9651
9652
9653
9654
9655
9656
9657
9658
9659
9660
9661
9662static void ipr_scan_vsets(struct ipr_ioa_cfg *ioa_cfg)
9663{
9664 int target, lun;
9665
9666 for (target = 0; target < IPR_MAX_NUM_TARGETS_PER_BUS; target++)
9667 for (lun = 0; lun < IPR_MAX_NUM_VSET_LUNS_PER_TARGET; lun++)
9668 scsi_add_device(ioa_cfg->host, IPR_VSET_BUS, target, lun);
9669}
9670
9671
9672
9673
9674
9675
9676
9677
9678
9679
9680
9681
9682
9683
9684
9685static void ipr_initiate_ioa_bringdown(struct ipr_ioa_cfg *ioa_cfg,
9686 enum ipr_shutdown_type shutdown_type)
9687{
9688 ENTER;
9689 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
9690 ioa_cfg->sdt_state = ABORT_DUMP;
9691 ioa_cfg->reset_retries = 0;
9692 ioa_cfg->in_ioa_bringdown = 1;
9693 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
9694 LEAVE;
9695}
9696
9697
9698
9699
9700
9701
9702
9703
9704
9705
9706static void __ipr_remove(struct pci_dev *pdev)
9707{
9708 unsigned long host_lock_flags = 0;
9709 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9710 int i;
9711 ENTER;
9712
9713 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9714 while (ioa_cfg->in_reset_reload) {
9715 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9716 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9717 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9718 }
9719
9720 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9721 spin_lock(&ioa_cfg->hrrq[i]._lock);
9722 ioa_cfg->hrrq[i].removing_ioa = 1;
9723 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9724 }
9725 wmb();
9726 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
9727
9728 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9729 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9730 flush_work(&ioa_cfg->work_q);
9731 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9732 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9733
9734 spin_lock(&ipr_driver_lock);
9735 list_del(&ioa_cfg->queue);
9736 spin_unlock(&ipr_driver_lock);
9737
9738 if (ioa_cfg->sdt_state == ABORT_DUMP)
9739 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
9740 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9741
9742 ipr_free_all_resources(ioa_cfg);
9743
9744 LEAVE;
9745}
9746
9747
9748
9749
9750
9751
9752
9753
9754
9755
9756static void ipr_remove(struct pci_dev *pdev)
9757{
9758 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9759
9760 ENTER;
9761
9762 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
9763 &ipr_trace_attr);
9764 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
9765 &ipr_dump_attr);
9766 scsi_remove_host(ioa_cfg->host);
9767
9768 __ipr_remove(pdev);
9769
9770 LEAVE;
9771}
9772
9773
9774
9775
9776
9777
9778
9779static int ipr_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
9780{
9781 struct ipr_ioa_cfg *ioa_cfg;
9782 int rc, i;
9783
9784 rc = ipr_probe_ioa(pdev, dev_id);
9785
9786 if (rc)
9787 return rc;
9788
9789 ioa_cfg = pci_get_drvdata(pdev);
9790 rc = ipr_probe_ioa_part2(ioa_cfg);
9791
9792 if (rc) {
9793 __ipr_remove(pdev);
9794 return rc;
9795 }
9796
9797 rc = scsi_add_host(ioa_cfg->host, &pdev->dev);
9798
9799 if (rc) {
9800 __ipr_remove(pdev);
9801 return rc;
9802 }
9803
9804 rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
9805 &ipr_trace_attr);
9806
9807 if (rc) {
9808 scsi_remove_host(ioa_cfg->host);
9809 __ipr_remove(pdev);
9810 return rc;
9811 }
9812
9813 rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
9814 &ipr_dump_attr);
9815
9816 if (rc) {
9817 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
9818 &ipr_trace_attr);
9819 scsi_remove_host(ioa_cfg->host);
9820 __ipr_remove(pdev);
9821 return rc;
9822 }
9823
9824 scsi_scan_host(ioa_cfg->host);
9825 ipr_scan_vsets(ioa_cfg);
9826 scsi_add_device(ioa_cfg->host, IPR_IOA_BUS, IPR_IOA_TARGET, IPR_IOA_LUN);
9827 ioa_cfg->allow_ml_add_del = 1;
9828 ioa_cfg->host->max_channel = IPR_VSET_BUS;
9829 ioa_cfg->iopoll_weight = ioa_cfg->chip_cfg->iopoll_weight;
9830
9831 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
9832 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
9833 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
9834 blk_iopoll_init(&ioa_cfg->hrrq[i].iopoll,
9835 ioa_cfg->iopoll_weight, ipr_iopoll);
9836 blk_iopoll_enable(&ioa_cfg->hrrq[i].iopoll);
9837 }
9838 }
9839
9840 schedule_work(&ioa_cfg->work_q);
9841 return 0;
9842}
9843
9844
9845
9846
9847
9848
9849
9850
9851
9852
9853
9854static void ipr_shutdown(struct pci_dev *pdev)
9855{
9856 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9857 unsigned long lock_flags = 0;
9858 int i;
9859
9860 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9861 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
9862 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
9863 ioa_cfg->iopoll_weight = 0;
9864 for (i = 1; i < ioa_cfg->hrrq_num; i++)
9865 blk_iopoll_disable(&ioa_cfg->hrrq[i].iopoll);
9866 }
9867
9868 while (ioa_cfg->in_reset_reload) {
9869 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9870 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9871 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9872 }
9873
9874 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
9875 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9876 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9877}
9878
9879static struct pci_device_id ipr_pci_table[] = {
9880 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9881 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5702, 0, 0, 0 },
9882 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9883 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5703, 0, 0, 0 },
9884 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9885 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573D, 0, 0, 0 },
9886 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9887 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573E, 0, 0, 0 },
9888 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9889 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571B, 0, 0, 0 },
9890 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9891 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572E, 0, 0, 0 },
9892 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9893 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571A, 0, 0, 0 },
9894 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9895 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575B, 0, 0,
9896 IPR_USE_LONG_TRANSOP_TIMEOUT },
9897 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9898 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
9899 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9900 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
9901 IPR_USE_LONG_TRANSOP_TIMEOUT },
9902 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9903 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
9904 IPR_USE_LONG_TRANSOP_TIMEOUT },
9905 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9906 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
9907 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9908 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
9909 IPR_USE_LONG_TRANSOP_TIMEOUT},
9910 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9911 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
9912 IPR_USE_LONG_TRANSOP_TIMEOUT },
9913 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9914 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0,
9915 IPR_USE_LONG_TRANSOP_TIMEOUT },
9916 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9917 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 },
9918 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9919 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CC, 0, 0, 0 },
9920 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9921 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B7, 0, 0,
9922 IPR_USE_LONG_TRANSOP_TIMEOUT | IPR_USE_PCI_WARM_RESET },
9923 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE,
9924 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2780, 0, 0, 0 },
9925 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9926 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571E, 0, 0, 0 },
9927 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9928 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571F, 0, 0,
9929 IPR_USE_LONG_TRANSOP_TIMEOUT },
9930 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9931 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0,
9932 IPR_USE_LONG_TRANSOP_TIMEOUT },
9933 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9934 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 },
9935 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9936 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 },
9937 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9938 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 },
9939 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9940 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C0, 0, 0, 0 },
9941 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9942 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },
9943 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9944 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },
9945 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9946 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },
9947 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9948 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },
9949 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9950 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },
9951 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9952 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C8, 0, 0, 0 },
9953 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9954 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },
9955 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9956 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D5, 0, 0, 0 },
9957 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9958 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D6, 0, 0, 0 },
9959 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9960 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D7, 0, 0, 0 },
9961 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9962 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D8, 0, 0, 0 },
9963 { }
9964};
9965MODULE_DEVICE_TABLE(pci, ipr_pci_table);
9966
9967static const struct pci_error_handlers ipr_err_handler = {
9968 .error_detected = ipr_pci_error_detected,
9969 .slot_reset = ipr_pci_slot_reset,
9970};
9971
9972static struct pci_driver ipr_driver = {
9973 .name = IPR_NAME,
9974 .id_table = ipr_pci_table,
9975 .probe = ipr_probe,
9976 .remove = ipr_remove,
9977 .shutdown = ipr_shutdown,
9978 .err_handler = &ipr_err_handler,
9979};
9980
9981
9982
9983
9984
9985
9986
9987static void ipr_halt_done(struct ipr_cmnd *ipr_cmd)
9988{
9989 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
9990}
9991
9992
9993
9994
9995
9996
9997
9998static int ipr_halt(struct notifier_block *nb, ulong event, void *buf)
9999{
10000 struct ipr_cmnd *ipr_cmd;
10001 struct ipr_ioa_cfg *ioa_cfg;
10002 unsigned long flags = 0;
10003
10004 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
10005 return NOTIFY_DONE;
10006
10007 spin_lock(&ipr_driver_lock);
10008
10009 list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) {
10010 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10011 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
10012 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10013 continue;
10014 }
10015
10016 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
10017 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
10018 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
10019 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
10020 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL;
10021
10022 ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
10023 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10024 }
10025 spin_unlock(&ipr_driver_lock);
10026
10027 return NOTIFY_OK;
10028}
10029
10030static struct notifier_block ipr_notifier = {
10031 ipr_halt, NULL, 0
10032};
10033
10034
10035
10036
10037
10038
10039
10040static int __init ipr_init(void)
10041{
10042 ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n",
10043 IPR_DRIVER_VERSION, IPR_DRIVER_DATE);
10044
10045 register_reboot_notifier(&ipr_notifier);
10046 return pci_register_driver(&ipr_driver);
10047}
10048
10049
10050
10051
10052
10053
10054
10055
10056
10057static void __exit ipr_exit(void)
10058{
10059 unregister_reboot_notifier(&ipr_notifier);
10060 pci_unregister_driver(&ipr_driver);
10061}
10062
10063module_init(ipr_init);
10064module_exit(ipr_exit);
10065
