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8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
27#include <linux/aer.h>
28#include <linux/bsg-lib.h>
29
30#include <net/tcp.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_host.h>
33#include <scsi/scsi_device.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_transport.h>
36#include <scsi/scsi_transport_iscsi.h>
37#include <scsi/scsi_bsg_iscsi.h>
38#include <scsi/scsi_netlink.h>
39#include <scsi/libiscsi.h>
40
41#include "ql4_dbg.h"
42#include "ql4_nx.h"
43#include "ql4_fw.h"
44#include "ql4_nvram.h"
45#include "ql4_83xx.h"
46
47#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49#endif
50
51#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53#endif
54
55#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57#endif
58
59#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61#endif
62
63#ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64#define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65#endif
66
67#define ISP4XXX_PCI_FN_1 0x1
68#define ISP4XXX_PCI_FN_2 0x3
69
70#define QLA_SUCCESS 0
71#define QLA_ERROR 1
72
73
74
75
76#define BIT_0 0x1
77#define BIT_1 0x2
78#define BIT_2 0x4
79#define BIT_3 0x8
80#define BIT_4 0x10
81#define BIT_5 0x20
82#define BIT_6 0x40
83#define BIT_7 0x80
84#define BIT_8 0x100
85#define BIT_9 0x200
86#define BIT_10 0x400
87#define BIT_11 0x800
88#define BIT_12 0x1000
89#define BIT_13 0x2000
90#define BIT_14 0x4000
91#define BIT_15 0x8000
92#define BIT_16 0x10000
93#define BIT_17 0x20000
94#define BIT_18 0x40000
95#define BIT_19 0x80000
96#define BIT_20 0x100000
97#define BIT_21 0x200000
98#define BIT_22 0x400000
99#define BIT_23 0x800000
100#define BIT_24 0x1000000
101#define BIT_25 0x2000000
102#define BIT_26 0x4000000
103#define BIT_27 0x8000000
104#define BIT_28 0x10000000
105#define BIT_29 0x20000000
106#define BIT_30 0x40000000
107#define BIT_31 0x80000000
108
109
110
111
112#define ql4_printk(level, ha, format, arg...) \
113 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
114
115
116
117
118
119#define MAX_HBAS 16
120#define MAX_BUSES 1
121#define MAX_TARGETS MAX_DEV_DB_ENTRIES
122#define MAX_LUNS 0xffff
123#define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
124#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
125#define MAX_PDU_ENTRIES 32
126#define INVALID_ENTRY 0xFFFF
127#define MAX_CMDS_TO_RISC 1024
128#define MAX_SRBS MAX_CMDS_TO_RISC
129#define MBOX_AEN_REG_COUNT 8
130#define MAX_INIT_RETRIES 5
131
132
133
134
135#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
136#define RESPONSE_QUEUE_DEPTH 64
137#define QUEUE_SIZE 64
138#define DMA_BUFFER_SIZE 512
139#define IOCB_HIWAT_CUSHION 4
140
141
142
143
144#define MAC_ADDR_LEN 6
145#define IP_ADDR_LEN 4
146#define IPv6_ADDR_LEN 16
147#define DRIVER_NAME "qla4xxx"
148
149#define MAX_LINKED_CMDS_PER_LUN 3
150#define MAX_REQS_SERVICED_PER_INTR 1
151
152#define ISCSI_IPADDR_SIZE 4
153#define ISCSI_ALIAS_SIZE 32
154#define ISCSI_NAME_SIZE 0xE0
155
156#define QL4_SESS_RECOVERY_TMO 120
157
158
159#define LSDW(x) ((u32)((u64)(x)))
160#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
161
162
163
164
165#define MBOX_TOV 60
166#define SOFT_RESET_TOV 30
167#define RESET_INTR_TOV 3
168#define SEMAPHORE_TOV 10
169#define ADAPTER_INIT_TOV 30
170#define ADAPTER_RESET_TOV 180
171#define EXTEND_CMD_TOV 60
172#define WAIT_CMD_TOV 30
173#define EH_WAIT_CMD_TOV 120
174#define FIRMWARE_UP_TOV 60
175#define RESET_FIRMWARE_TOV 30
176#define LOGOUT_TOV 10
177#define IOCB_TOV_MARGIN 10
178#define RELOGIN_TOV 18
179#define ISNS_DEREG_TOV 5
180#define HBA_ONLINE_TOV 30
181#define DISABLE_ACB_TOV 30
182#define IP_CONFIG_TOV 30
183#define LOGIN_TOV 12
184#define BOOT_LOGIN_RESP_TOV 60
185
186#define MAX_RESET_HA_RETRIES 2
187#define FW_ALIVE_WAIT_TOV 3
188
189#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
190
191
192
193
194
195struct srb {
196 struct list_head list;
197 struct scsi_qla_host *ha;
198 struct ddb_entry *ddb;
199 uint16_t flags;
200
201#define SRB_DMA_VALID BIT_3
202#define SRB_GOT_SENSE BIT_4
203 uint8_t state;
204
205#define SRB_NO_QUEUE_STATE 0
206#define SRB_FREE_STATE 1
207#define SRB_ACTIVE_STATE 3
208#define SRB_ACTIVE_TIMEOUT_STATE 4
209#define SRB_SUSPENDED_STATE 7
210
211 struct scsi_cmnd *cmd;
212 dma_addr_t dma_handle;
213 struct kref srb_ref;
214 uint8_t err_id;
215#define SRB_ERR_PORT 1
216#define SRB_ERR_LOOP 2
217#define SRB_ERR_DEVICE 3
218#define SRB_ERR_OTHER 4
219
220 uint16_t reserved;
221 uint16_t iocb_tov;
222 uint16_t iocb_cnt;
223 uint16_t cc_stat;
224
225
226 uint8_t *req_sense_ptr;
227 uint16_t req_sense_len;
228 uint16_t reserved2;
229};
230
231
232struct mrb {
233 struct scsi_qla_host *ha;
234 struct mbox_cmd_iocb *mbox;
235 uint32_t mbox_cmd;
236 uint16_t iocb_cnt;
237 uint32_t pid;
238};
239
240
241
242
243struct aen {
244 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
245};
246
247struct ql4_aen_log {
248 int count;
249 struct aen entry[MAX_AEN_ENTRIES];
250};
251
252
253
254
255struct ddb_entry {
256 struct scsi_qla_host *ha;
257 struct iscsi_cls_session *sess;
258 struct iscsi_cls_conn *conn;
259
260 uint16_t fw_ddb_index;
261 uint32_t fw_ddb_device_state;
262 uint16_t ddb_type;
263#define FLASH_DDB 0x01
264
265 struct dev_db_entry fw_ddb_entry;
266 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
267 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
268 struct ddb_entry *ddb_entry, uint32_t state);
269
270
271 unsigned long flags;
272 uint16_t default_relogin_timeout;
273
274 atomic_t retry_relogin_timer;
275
276 atomic_t relogin_timer;
277
278 atomic_t relogin_retry_count;
279
280 uint32_t default_time2wait;
281
282 uint16_t chap_tbl_idx;
283};
284
285struct qla_ddb_index {
286 struct list_head list;
287 uint16_t fw_ddb_idx;
288 struct dev_db_entry fw_ddb;
289 uint8_t flash_isid[6];
290};
291
292#define DDB_IPADDR_LEN 64
293
294struct ql4_tuple_ddb {
295 int port;
296 int tpgt;
297 char ip_addr[DDB_IPADDR_LEN];
298 char iscsi_name[ISCSI_NAME_SIZE];
299 uint16_t options;
300#define DDB_OPT_IPV6 0x0e0e
301#define DDB_OPT_IPV4 0x0f0f
302 uint8_t isid[6];
303};
304
305
306
307
308#define DDB_STATE_DEAD 0
309
310#define DDB_STATE_ONLINE 1
311
312#define DDB_STATE_MISSING 2
313
314
315
316
317
318#define DF_RELOGIN 0
319#define DF_BOOT_TGT 1
320#define DF_ISNS_DISCOVERED 2
321#define DF_FO_MASKED 3
322
323enum qla4_work_type {
324 QLA4_EVENT_AEN,
325 QLA4_EVENT_PING_STATUS,
326};
327
328struct qla4_work_evt {
329 struct list_head list;
330 enum qla4_work_type type;
331 union {
332 struct {
333 enum iscsi_host_event_code code;
334 uint32_t data_size;
335 uint8_t data[0];
336 } aen;
337 struct {
338 uint32_t status;
339 uint32_t pid;
340 uint32_t data_size;
341 uint8_t data[0];
342 } ping;
343 } u;
344};
345
346struct ql82xx_hw_data {
347
348 uint32_t flash_conf_off;
349 uint32_t flash_data_off;
350
351 uint32_t fdt_wrt_disable;
352 uint32_t fdt_erase_cmd;
353 uint32_t fdt_block_size;
354 uint32_t fdt_unprotect_sec_cmd;
355 uint32_t fdt_protect_sec_cmd;
356
357 uint32_t flt_region_flt;
358 uint32_t flt_region_fdt;
359 uint32_t flt_region_boot;
360 uint32_t flt_region_bootload;
361 uint32_t flt_region_fw;
362
363 uint32_t flt_iscsi_param;
364 uint32_t flt_region_chap;
365 uint32_t flt_chap_size;
366};
367
368struct qla4_8xxx_legacy_intr_set {
369 uint32_t int_vec_bit;
370 uint32_t tgt_status_reg;
371 uint32_t tgt_mask_reg;
372 uint32_t pci_int_reg;
373};
374
375
376
377#define QLA_MSIX_DEFAULT 0x00
378#define QLA_MSIX_RSP_Q 0x01
379
380#define QLA_MSIX_ENTRIES 2
381#define QLA_MIDX_DEFAULT 0
382#define QLA_MIDX_RSP_Q 1
383
384struct ql4_msix_entry {
385 int have_irq;
386 uint16_t msix_vector;
387 uint16_t msix_entry;
388};
389
390
391
392
393struct isp_operations {
394 int (*iospace_config) (struct scsi_qla_host *ha);
395 void (*pci_config) (struct scsi_qla_host *);
396 void (*disable_intrs) (struct scsi_qla_host *);
397 void (*enable_intrs) (struct scsi_qla_host *);
398 int (*start_firmware) (struct scsi_qla_host *);
399 int (*restart_firmware) (struct scsi_qla_host *);
400 irqreturn_t (*intr_handler) (int , void *);
401 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
402 int (*need_reset) (struct scsi_qla_host *);
403 int (*reset_chip) (struct scsi_qla_host *);
404 int (*reset_firmware) (struct scsi_qla_host *);
405 void (*queue_iocb) (struct scsi_qla_host *);
406 void (*complete_iocb) (struct scsi_qla_host *);
407 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
408 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
409 int (*get_sys_info) (struct scsi_qla_host *);
410 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
411 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
412 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
413 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
414 int (*idc_lock) (struct scsi_qla_host *);
415 void (*idc_unlock) (struct scsi_qla_host *);
416 void (*rom_lock_recovery) (struct scsi_qla_host *);
417 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
418 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
419};
420
421struct ql4_mdump_size_table {
422 uint32_t size;
423 uint32_t size_cmask_02;
424 uint32_t size_cmask_04;
425 uint32_t size_cmask_08;
426 uint32_t size_cmask_10;
427 uint32_t size_cmask_FF;
428 uint32_t version;
429};
430
431
432struct ipaddress_config {
433 uint16_t ipv4_options;
434 uint16_t tcp_options;
435 uint16_t ipv4_vlan_tag;
436 uint8_t ipv4_addr_state;
437 uint8_t ip_address[IP_ADDR_LEN];
438 uint8_t subnet_mask[IP_ADDR_LEN];
439 uint8_t gateway[IP_ADDR_LEN];
440 uint32_t ipv6_options;
441 uint32_t ipv6_addl_options;
442 uint8_t ipv6_link_local_state;
443 uint8_t ipv6_addr0_state;
444 uint8_t ipv6_addr1_state;
445 uint8_t ipv6_default_router_state;
446 uint16_t ipv6_vlan_tag;
447 struct in6_addr ipv6_link_local_addr;
448 struct in6_addr ipv6_addr0;
449 struct in6_addr ipv6_addr1;
450 struct in6_addr ipv6_default_router_addr;
451 uint16_t eth_mtu_size;
452 uint16_t ipv4_port;
453 uint16_t ipv6_port;
454};
455
456#define QL4_CHAP_MAX_NAME_LEN 256
457#define QL4_CHAP_MAX_SECRET_LEN 100
458#define LOCAL_CHAP 0
459#define BIDI_CHAP 1
460
461struct ql4_chap_format {
462 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
463 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
464 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
465 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
466 u16 intr_chap_name_length;
467 u16 intr_secret_length;
468 u16 target_chap_name_length;
469 u16 target_secret_length;
470};
471
472struct ip_address_format {
473 u8 ip_type;
474 u8 ip_address[16];
475};
476
477struct ql4_conn_info {
478 u16 dest_port;
479 struct ip_address_format dest_ipaddr;
480 struct ql4_chap_format chap;
481};
482
483struct ql4_boot_session_info {
484 u8 target_name[224];
485 struct ql4_conn_info conn_list[1];
486};
487
488struct ql4_boot_tgt_info {
489 struct ql4_boot_session_info boot_pri_sess;
490 struct ql4_boot_session_info boot_sec_sess;
491};
492
493
494
495
496struct scsi_qla_host {
497
498 unsigned long flags;
499
500#define AF_ONLINE 0
501#define AF_INIT_DONE 1
502#define AF_MBOX_COMMAND 2
503#define AF_MBOX_COMMAND_DONE 3
504#define AF_INTERRUPTS_ON 6
505#define AF_GET_CRASH_RECORD 7
506#define AF_LINK_UP 8
507#define AF_LOOPBACK 9
508#define AF_IRQ_ATTACHED 10
509#define AF_DISABLE_ACB_COMPLETE 11
510#define AF_HA_REMOVAL 12
511#define AF_INTx_ENABLED 15
512#define AF_MSI_ENABLED 16
513#define AF_MSIX_ENABLED 17
514#define AF_MBOX_COMMAND_NOPOLL 18
515#define AF_FW_RECOVERY 19
516#define AF_EEH_BUSY 20
517#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21
518#define AF_BUILD_DDB_LIST 22
519#define AF_82XX_FW_DUMPED 24
520#define AF_8XXX_RST_OWNER 25
521#define AF_82XX_DUMP_READING 26
522#define AF_83XX_NO_FW_DUMP 27
523#define AF_83XX_IOCB_INTR_ON 28
524#define AF_83XX_MBOX_INTR_ON 29
525
526 unsigned long dpc_flags;
527
528#define DPC_RESET_HA 1
529#define DPC_RETRY_RESET_HA 2
530#define DPC_RELOGIN_DEVICE 3
531#define DPC_RESET_HA_FW_CONTEXT 4
532#define DPC_RESET_HA_INTR 5
533#define DPC_ISNS_RESTART 7
534#define DPC_AEN 9
535#define DPC_GET_DHCP_IP_ADDR 15
536#define DPC_LINK_CHANGED 18
537#define DPC_RESET_ACTIVE 20
538#define DPC_HA_UNRECOVERABLE 21
539#define DPC_HA_NEED_QUIESCENT 22
540#define DPC_POST_IDC_ACK 23
541
542 struct Scsi_Host *host;
543 uint32_t tot_ddbs;
544
545 uint16_t iocb_cnt;
546 uint16_t iocb_hiwat;
547
548
549#define SRB_MIN_REQ 128
550 mempool_t *srb_mempool;
551
552
553 struct pci_dev *pdev;
554
555 struct isp_reg __iomem *reg;
556 unsigned long pio_address;
557 unsigned long pio_length;
558#define MIN_IOBASE_LEN 0x100
559
560 uint16_t req_q_count;
561
562 unsigned long host_no;
563
564
565 struct eeprom_data *nvram;
566 spinlock_t hardware_lock ____cacheline_aligned;
567 uint32_t eeprom_cmd_data;
568
569
570 uint64_t isr_count;
571 uint64_t adapter_error_count;
572 uint64_t device_error_count;
573 uint64_t total_io_count;
574 uint64_t total_mbytes_xferred;
575 uint64_t link_failure_count;
576 uint64_t invalid_crc_count;
577 uint32_t bytes_xfered;
578 uint32_t spurious_int_count;
579 uint32_t aborted_io_count;
580 uint32_t io_timeout_count;
581 uint32_t mailbox_timeout_count;
582 uint32_t seconds_since_last_intr;
583 uint32_t seconds_since_last_heartbeat;
584 uint32_t mac_index;
585
586
587
588 uint32_t firmware_version[2];
589 uint32_t patch_number;
590 uint32_t build_number;
591 uint32_t board_id;
592
593
594
595 uint16_t firmware_options;
596 uint8_t alias[32];
597 uint8_t name_string[256];
598 uint8_t heartbeat_interval;
599
600
601 uint8_t my_mac[MAC_ADDR_LEN];
602 uint8_t serial_number[16];
603 uint16_t port_num;
604
605 uint32_t firmware_state;
606 uint32_t addl_fw_state;
607
608
609 struct workqueue_struct *dpc_thread;
610 struct work_struct dpc_work;
611
612
613 struct timer_list timer;
614 uint32_t timer_active;
615
616
617 atomic_t check_relogin_timeouts;
618 uint32_t retry_reset_ha_cnt;
619 uint32_t isp_reset_timer;
620 uint32_t nic_reset_timer;
621 int eh_start;
622 struct list_head free_srb_q;
623 uint16_t free_srb_q_count;
624 uint16_t num_srbs_allocated;
625
626
627 void *queues;
628 dma_addr_t queues_dma;
629 unsigned long queues_len;
630
631#define MEM_ALIGN_VALUE \
632 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
633 sizeof(struct queue_entry))
634
635 dma_addr_t request_dma;
636 struct queue_entry *request_ring;
637 struct queue_entry *request_ptr;
638 dma_addr_t response_dma;
639 struct queue_entry *response_ring;
640 struct queue_entry *response_ptr;
641 dma_addr_t shadow_regs_dma;
642 struct shadow_regs *shadow_regs;
643 uint16_t request_in;
644 uint16_t request_out;
645 uint16_t response_in;
646 uint16_t response_out;
647
648
649 uint16_t aen_q_count;
650 uint16_t aen_in;
651 uint16_t aen_out;
652 struct aen aen_q[MAX_AEN_ENTRIES];
653
654 struct ql4_aen_log aen_log;
655
656
657
658
659 struct mutex mbox_sem;
660
661
662 volatile uint8_t mbox_status_count;
663 volatile uint32_t mbox_status[MBOX_REG_COUNT];
664
665
666 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
667
668
669 struct srb *status_srb;
670
671 uint8_t acb_version;
672
673
674 struct device_reg_82xx __iomem *qla4_82xx_reg;
675 unsigned long nx_pcibase;
676 uint8_t *nx_db_rd_ptr;
677 unsigned long nx_db_wr_ptr;
678 unsigned long first_page_group_start;
679 unsigned long first_page_group_end;
680
681 uint32_t crb_win;
682 uint32_t curr_window;
683 uint32_t ddr_mn_window;
684 unsigned long mn_win_crb;
685 unsigned long ms_win_crb;
686 int qdr_sn_window;
687 rwlock_t hw_lock;
688 uint16_t func_num;
689 int link_width;
690
691 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
692 u32 nx_crb_mask;
693
694 uint8_t revision_id;
695 uint32_t fw_heartbeat_counter;
696
697 struct isp_operations *isp_ops;
698 struct ql82xx_hw_data hw;
699
700 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
701
702 uint32_t nx_dev_init_timeout;
703 uint32_t nx_reset_timeout;
704 void *fw_dump;
705 uint32_t fw_dump_size;
706 uint32_t fw_dump_capture_mask;
707 void *fw_dump_tmplt_hdr;
708 uint32_t fw_dump_tmplt_size;
709
710 struct completion mbx_intr_comp;
711
712 struct ipaddress_config ip_config;
713 struct iscsi_iface *iface_ipv4;
714 struct iscsi_iface *iface_ipv6_0;
715 struct iscsi_iface *iface_ipv6_1;
716
717
718 uint16_t iscsi_major;
719 uint16_t iscsi_minor;
720 uint16_t bootload_major;
721 uint16_t bootload_minor;
722 uint16_t bootload_patch;
723 uint16_t bootload_build;
724 uint16_t def_timeout;
725
726 uint32_t flash_state;
727#define QLFLASH_WAITING 0
728#define QLFLASH_READING 1
729#define QLFLASH_WRITING 2
730 struct dma_pool *chap_dma_pool;
731 uint8_t *chap_list;
732 struct mutex chap_sem;
733
734#define CHAP_DMA_BLOCK_SIZE 512
735 struct workqueue_struct *task_wq;
736 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
737#define SYSFS_FLAG_FW_SEL_BOOT 2
738 struct iscsi_boot_kset *boot_kset;
739 struct ql4_boot_tgt_info boot_tgt;
740 uint16_t phy_port_num;
741 uint16_t phy_port_cnt;
742 uint16_t iscsi_pci_func_cnt;
743 uint8_t model_name[16];
744 struct completion disable_acb_comp;
745 struct dma_pool *fw_ddb_dma_pool;
746#define DDB_DMA_BLOCK_SIZE 512
747 uint16_t pri_ddb_idx;
748 uint16_t sec_ddb_idx;
749 int is_reset;
750 uint16_t temperature;
751
752
753 struct list_head work_list;
754 spinlock_t work_lock;
755
756
757#define MAX_MRB 128
758 struct mrb *active_mrb_array[MAX_MRB];
759 uint32_t mrb_index;
760
761 uint32_t *reg_tbl;
762 struct qla4_83xx_reset_template reset_tmplt;
763 struct device_reg_83xx __iomem *qla4_83xx_reg;
764
765 uint32_t pf_bit;
766 struct qla4_83xx_idc_information idc_info;
767};
768
769struct ql4_task_data {
770 struct scsi_qla_host *ha;
771 uint8_t iocb_req_cnt;
772 dma_addr_t data_dma;
773 void *req_buffer;
774 dma_addr_t req_dma;
775 uint32_t req_len;
776 void *resp_buffer;
777 dma_addr_t resp_dma;
778 uint32_t resp_len;
779 struct iscsi_task *task;
780 struct passthru_status sts;
781 struct work_struct task_work;
782};
783
784struct qla_endpoint {
785 struct Scsi_Host *host;
786 struct sockaddr_storage dst_addr;
787};
788
789struct qla_conn {
790 struct qla_endpoint *qla_ep;
791};
792
793static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
794{
795 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
796}
797
798static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
799{
800 return ((ha->ip_config.ipv6_options &
801 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
802}
803
804static inline int is_qla4010(struct scsi_qla_host *ha)
805{
806 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
807}
808
809static inline int is_qla4022(struct scsi_qla_host *ha)
810{
811 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
812}
813
814static inline int is_qla4032(struct scsi_qla_host *ha)
815{
816 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
817}
818
819static inline int is_qla40XX(struct scsi_qla_host *ha)
820{
821 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
822}
823
824static inline int is_qla8022(struct scsi_qla_host *ha)
825{
826 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
827}
828
829static inline int is_qla8032(struct scsi_qla_host *ha)
830{
831 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
832}
833
834static inline int is_qla80XX(struct scsi_qla_host *ha)
835{
836 return is_qla8022(ha) || is_qla8032(ha);
837}
838
839static inline int is_aer_supported(struct scsi_qla_host *ha)
840{
841 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
842 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324));
843}
844
845static inline int adapter_up(struct scsi_qla_host *ha)
846{
847 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
848 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
849 (!test_bit(AF_LOOPBACK, &ha->flags));
850}
851
852static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
853{
854 return (struct scsi_qla_host *)iscsi_host_priv(shost);
855}
856
857static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
858{
859 return (is_qla4010(ha) ?
860 &ha->reg->u1.isp4010.nvram :
861 &ha->reg->u1.isp4022.semaphore);
862}
863
864static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
865{
866 return (is_qla4010(ha) ?
867 &ha->reg->u1.isp4010.nvram :
868 &ha->reg->u1.isp4022.nvram);
869}
870
871static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
872{
873 return (is_qla4010(ha) ?
874 &ha->reg->u2.isp4010.ext_hw_conf :
875 &ha->reg->u2.isp4022.p0.ext_hw_conf);
876}
877
878static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
879{
880 return (is_qla4010(ha) ?
881 &ha->reg->u2.isp4010.port_status :
882 &ha->reg->u2.isp4022.p0.port_status);
883}
884
885static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
886{
887 return (is_qla4010(ha) ?
888 &ha->reg->u2.isp4010.port_ctrl :
889 &ha->reg->u2.isp4022.p0.port_ctrl);
890}
891
892static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
893{
894 return (is_qla4010(ha) ?
895 &ha->reg->u2.isp4010.port_err_status :
896 &ha->reg->u2.isp4022.p0.port_err_status);
897}
898
899static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
900{
901 return (is_qla4010(ha) ?
902 &ha->reg->u2.isp4010.gp_out :
903 &ha->reg->u2.isp4022.p0.gp_out);
904}
905
906static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
907{
908 return (is_qla4010(ha) ?
909 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
910 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
911}
912
913int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
914void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
915int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
916
917static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
918{
919 if (is_qla4010(a))
920 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
921 QL4010_FLASH_SEM_BITS);
922 else
923 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
924 (QL4022_RESOURCE_BITS_BASE_CODE |
925 (a->mac_index)) << 13);
926}
927
928static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
929{
930 if (is_qla4010(a))
931 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
932 else
933 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
934}
935
936static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
937{
938 if (is_qla4010(a))
939 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
940 QL4010_NVRAM_SEM_BITS);
941 else
942 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
943 (QL4022_RESOURCE_BITS_BASE_CODE |
944 (a->mac_index)) << 10);
945}
946
947static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
948{
949 if (is_qla4010(a))
950 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
951 else
952 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
953}
954
955static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
956{
957 if (is_qla4010(a))
958 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
959 QL4010_DRVR_SEM_BITS);
960 else
961 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
962 (QL4022_RESOURCE_BITS_BASE_CODE |
963 (a->mac_index)) << 1);
964}
965
966static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
967{
968 if (is_qla4010(a))
969 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
970 else
971 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
972}
973
974static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
975{
976 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
977 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
978 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
979 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
980 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
981 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
982
983}
984
985static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
986 const uint32_t crb_reg)
987{
988 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
989}
990
991static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
992 const uint32_t crb_reg,
993 const uint32_t value)
994{
995 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
996}
997
998
999
1000
1001
1002#define INIT_ADAPTER 0
1003#define RESET_ADAPTER 1
1004
1005#define PRESERVE_DDB_LIST 0
1006#define REBUILD_DDB_LIST 1
1007
1008
1009#define PROCESS_ALL_AENS 0
1010#define FLUSH_DDB_CHANGED_AENS 1
1011
1012
1013#define QL4_UEVENT_CODE_FW_DUMP 0
1014
1015#endif
1016
