1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48#include <linux/pci.h>
49#include <linux/delay.h>
50#include <linux/interrupt.h>
51#include <linux/list.h>
52#include <linux/spinlock.h>
53
54#include "../comedidev.h"
55
56#include "comedi_fc.h"
57#include "8253.h"
58
59#if 0
60
61#include "me4000_fw.h"
62#endif
63
64#define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650
65#define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660
66#define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661
67#define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662
68#define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663
69#define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670
70#define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671
71#define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672
72#define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673
73#define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680
74#define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681
75#define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682
76#define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683
77
78
79
80
81#define ME4000_AO_CHAN(x) ((x) * 0x18)
82
83#define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
84#define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
85#define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
86#define ME4000_AO_CTRL_MASK_MODE (3 << 0)
87#define ME4000_AO_CTRL_BIT_STOP (1 << 2)
88#define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
89#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
90#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
91#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
92#define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
93#define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
94#define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
95#define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
96#define ME4000_AO_STATUS_BIT_FSM (1 << 0)
97#define ME4000_AO_STATUS_BIT_FF (1 << 1)
98#define ME4000_AO_STATUS_BIT_HF (1 << 2)
99#define ME4000_AO_STATUS_BIT_EF (1 << 3)
100#define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
101#define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
102#define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
103#define ME4000_AI_CTRL_REG 0x74
104#define ME4000_AI_STATUS_REG 0x74
105#define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
106#define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
107#define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
108#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
109#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
110#define ME4000_AI_CTRL_BIT_STOP (1 << 5)
111#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
112#define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
113#define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
114#define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
115#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
116#define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
117#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
118#define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
119#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
120#define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
121#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
122#define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
123#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
124#define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
125#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
126#define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
127#define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
128#define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
129#define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
130#define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
131#define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
132#define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
133#define ME4000_AI_STATUS_BIT_LE (1 << 28)
134#define ME4000_AI_STATUS_BIT_FSM (1 << 29)
135#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
136#define ME4000_AI_CHANNEL_LIST_REG 0x78
137#define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
138#define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
139#define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
140#define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
141#define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
142#define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
143#define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
144#define ME4000_AI_DATA_REG 0x7c
145#define ME4000_AI_CHAN_TIMER_REG 0x80
146#define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
147#define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
148#define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
149#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
150#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
151#define ME4000_AI_START_REG 0x98
152#define ME4000_IRQ_STATUS_REG 0x9c
153#define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
154#define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
155#define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
156#define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
157#define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
158#define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
159#define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
160#define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
161#define ME4000_DIO_PORT_0_REG 0xa0
162#define ME4000_DIO_PORT_1_REG 0xa4
163#define ME4000_DIO_PORT_2_REG 0xa8
164#define ME4000_DIO_PORT_3_REG 0xac
165#define ME4000_DIO_DIR_REG 0xb0
166#define ME4000_AO_LOADSETREG_XX 0xb4
167#define ME4000_DIO_CTRL_REG 0xb8
168#define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
169#define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
170#define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
171#define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
172#define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
173#define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
174#define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
175#define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
176#define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
177#define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
178#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
179#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
180#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
181#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
182#define ME4000_AO_DEMUX_ADJUST_REG 0xbc
183#define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
184#define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
185
186
187
188
189#define PLX_INTCSR 0x4c
190#define PLX_INTCSR_LOCAL_INT1_EN (1 << 0)
191#define PLX_INTCSR_LOCAL_INT1_POL (1 << 1)
192#define PLX_INTCSR_LOCAL_INT1_STATE (1 << 2)
193#define PLX_INTCSR_LOCAL_INT2_EN (1 << 3)
194#define PLX_INTCSR_LOCAL_INT2_POL (1 << 4)
195#define PLX_INTCSR_LOCAL_INT2_STATE (1 << 5)
196#define PLX_INTCSR_PCI_INT_EN (1 << 6)
197#define PLX_INTCSR_SOFT_INT (1 << 7)
198#define PLX_ICR 0x50
199#define PLX_ICR_BIT_EEPROM_CLOCK_SET (1 << 24)
200#define PLX_ICR_BIT_EEPROM_CHIP_SELECT (1 << 25)
201#define PLX_ICR_BIT_EEPROM_WRITE (1 << 26)
202#define PLX_ICR_BIT_EEPROM_READ (1 << 27)
203#define PLX_ICR_BIT_EEPROM_VALID (1 << 28)
204#define PLX_ICR_MASK_EEPROM (0x1f << 24)
205
206#define EEPROM_DELAY 1
207
208#define ME4000_AI_FIFO_COUNT 2048
209
210#define ME4000_AI_MIN_TICKS 66
211#define ME4000_AI_MIN_SAMPLE_TIME 2000
212#define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
213
214#define ME4000_AI_CHANNEL_LIST_COUNT 1024
215
216struct me4000_info {
217 unsigned long plx_regbase;
218 unsigned long timer_regbase;
219
220 unsigned int ao_readback[4];
221};
222
223struct me4000_board {
224 const char *name;
225 unsigned short device_id;
226 int ao_nchan;
227 int ao_fifo;
228 int ai_nchan;
229 int ai_diff_nchan;
230 int ai_sh_nchan;
231 int ex_trig_analog;
232 int dio_nchan;
233 int has_counter;
234};
235
236static const struct me4000_board me4000_boards[] = {
237 {
238 .name = "ME-4650",
239 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4650,
240 .ai_nchan = 16,
241 .dio_nchan = 32,
242 }, {
243 .name = "ME-4660",
244 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660,
245 .ai_nchan = 32,
246 .ai_diff_nchan = 16,
247 .dio_nchan = 32,
248 .has_counter = 1,
249 }, {
250 .name = "ME-4660i",
251 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660I,
252 .ai_nchan = 32,
253 .ai_diff_nchan = 16,
254 .dio_nchan = 32,
255 .has_counter = 1,
256 }, {
257 .name = "ME-4660s",
258 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660S,
259 .ai_nchan = 32,
260 .ai_diff_nchan = 16,
261 .ai_sh_nchan = 8,
262 .dio_nchan = 32,
263 .has_counter = 1,
264 }, {
265 .name = "ME-4660is",
266 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4660IS,
267 .ai_nchan = 32,
268 .ai_diff_nchan = 16,
269 .ai_sh_nchan = 8,
270 .dio_nchan = 32,
271 .has_counter = 1,
272 }, {
273 .name = "ME-4670",
274 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670,
275 .ao_nchan = 4,
276 .ai_nchan = 32,
277 .ai_diff_nchan = 16,
278 .ex_trig_analog = 1,
279 .dio_nchan = 32,
280 .has_counter = 1,
281 }, {
282 .name = "ME-4670i",
283 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670I,
284 .ao_nchan = 4,
285 .ai_nchan = 32,
286 .ai_diff_nchan = 16,
287 .ex_trig_analog = 1,
288 .dio_nchan = 32,
289 .has_counter = 1,
290 }, {
291 .name = "ME-4670s",
292 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670S,
293 .ao_nchan = 4,
294 .ai_nchan = 32,
295 .ai_diff_nchan = 16,
296 .ai_sh_nchan = 8,
297 .ex_trig_analog = 1,
298 .dio_nchan = 32,
299 .has_counter = 1,
300 }, {
301 .name = "ME-4670is",
302 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4670IS,
303 .ao_nchan = 4,
304 .ai_nchan = 32,
305 .ai_diff_nchan = 16,
306 .ai_sh_nchan = 8,
307 .ex_trig_analog = 1,
308 .dio_nchan = 32,
309 .has_counter = 1,
310 }, {
311 .name = "ME-4680",
312 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680,
313 .ao_nchan = 4,
314 .ao_fifo = 4,
315 .ai_nchan = 32,
316 .ai_diff_nchan = 16,
317 .ex_trig_analog = 1,
318 .dio_nchan = 32,
319 .has_counter = 1,
320 }, {
321 .name = "ME-4680i",
322 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680I,
323 .ao_nchan = 4,
324 .ao_fifo = 4,
325 .ai_nchan = 32,
326 .ai_diff_nchan = 16,
327 .ex_trig_analog = 1,
328 .dio_nchan = 32,
329 .has_counter = 1,
330 }, {
331 .name = "ME-4680s",
332 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680S,
333 .ao_nchan = 4,
334 .ao_fifo = 4,
335 .ai_nchan = 32,
336 .ai_diff_nchan = 16,
337 .ai_sh_nchan = 8,
338 .ex_trig_analog = 1,
339 .dio_nchan = 32,
340 .has_counter = 1,
341 }, {
342 .name = "ME-4680is",
343 .device_id = PCI_DEVICE_ID_MEILHAUS_ME4680IS,
344 .ao_nchan = 4,
345 .ao_fifo = 4,
346 .ai_nchan = 32,
347 .ai_diff_nchan = 16,
348 .ai_sh_nchan = 8,
349 .ex_trig_analog = 1,
350 .dio_nchan = 32,
351 .has_counter = 1,
352 },
353};
354
355static const struct comedi_lrange me4000_ai_range = {
356 4,
357 {
358 UNI_RANGE(2.5),
359 UNI_RANGE(10),
360 BIP_RANGE(2.5),
361 BIP_RANGE(10),
362 }
363};
364
365#define FIRMWARE_NOT_AVAILABLE 1
366#if FIRMWARE_NOT_AVAILABLE
367extern unsigned char *xilinx_firm;
368#endif
369
370static int xilinx_download(struct comedi_device *dev)
371{
372 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
373 struct me4000_info *info = dev->private;
374 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
375 u32 value = 0;
376 wait_queue_head_t queue;
377 int idx = 0;
378 int size = 0;
379
380 if (!xilinx_iobase)
381 return -ENODEV;
382
383 init_waitqueue_head(&queue);
384
385
386
387
388
389 outl(0x10, info->plx_regbase + PLX_INTCSR);
390
391
392 value = inl(info->plx_regbase + PLX_ICR);
393 value |= 0x100;
394 outl(value, info->plx_regbase + PLX_ICR);
395
396
397 inb(xilinx_iobase + 0xC8);
398
399
400 udelay(20);
401 if (!(inl(info->plx_regbase + PLX_INTCSR) & 0x20)) {
402 dev_err(dev->class_dev, "Can't init Xilinx\n");
403 return -EIO;
404 }
405
406
407 value = inl(info->plx_regbase + PLX_ICR);
408 value &= ~0x100;
409 outl(value, info->plx_regbase + PLX_ICR);
410 if (FIRMWARE_NOT_AVAILABLE) {
411 dev_err(dev->class_dev,
412 "xilinx firmware unavailable due to licensing, aborting");
413 return -EIO;
414 } else {
415
416 size = (xilinx_firm[0] << 24) + (xilinx_firm[1] << 16) +
417 (xilinx_firm[2] << 8) + xilinx_firm[3];
418 udelay(10);
419
420 for (idx = 0; idx < size; idx++) {
421 outb(xilinx_firm[16 + idx], xilinx_iobase);
422 udelay(10);
423
424
425 if (inl(info->plx_regbase + PLX_ICR) & 0x20) {
426 dev_err(dev->class_dev,
427 "Xilinx is still busy (idx = %d)\n",
428 idx);
429 return -EIO;
430 }
431 }
432 }
433
434
435 if (inl(info->plx_regbase + PLX_ICR) & 0x4) {
436 } else {
437 dev_err(dev->class_dev, "DONE flag is not set\n");
438 dev_err(dev->class_dev, "Download not successful\n");
439 return -EIO;
440 }
441
442
443 value = inl(info->plx_regbase + PLX_ICR);
444 value |= 0x100;
445 outl(value, info->plx_regbase + PLX_ICR);
446
447 return 0;
448}
449
450static void me4000_reset(struct comedi_device *dev)
451{
452 struct me4000_info *info = dev->private;
453 unsigned long val;
454 int chan;
455
456
457 val = inl(info->plx_regbase + PLX_ICR);
458 val |= 0x40000000;
459 outl(val, info->plx_regbase + PLX_ICR);
460 val &= ~0x40000000;
461 outl(val , info->plx_regbase + PLX_ICR);
462
463
464 for (chan = 0; chan < 4; chan++)
465 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
466
467
468 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
469 dev->iobase + ME4000_AI_CTRL_REG);
470
471
472 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
473 for (chan = 0; chan < 4; chan++)
474 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
475
476
477 outl(0x43, info->plx_regbase + PLX_INTCSR);
478
479
480 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
481 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
482
483
484
485
486
487 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
488 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
489}
490
491
492
493
494
495static int me4000_ai_insn_read(struct comedi_device *dev,
496 struct comedi_subdevice *subdevice,
497 struct comedi_insn *insn, unsigned int *data)
498{
499 const struct me4000_board *thisboard = comedi_board(dev);
500 int chan = CR_CHAN(insn->chanspec);
501 int rang = CR_RANGE(insn->chanspec);
502 int aref = CR_AREF(insn->chanspec);
503
504 unsigned long entry = 0;
505 unsigned long tmp;
506 long lval;
507
508 if (insn->n == 0) {
509 return 0;
510 } else if (insn->n > 1) {
511 dev_err(dev->class_dev, "Invalid instruction length %d\n",
512 insn->n);
513 return -EINVAL;
514 }
515
516 switch (rang) {
517 case 0:
518 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
519 break;
520 case 1:
521 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
522 break;
523 case 2:
524 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
525 break;
526 case 3:
527 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
528 break;
529 default:
530 dev_err(dev->class_dev, "Invalid range specified\n");
531 return -EINVAL;
532 }
533
534 switch (aref) {
535 case AREF_GROUND:
536 case AREF_COMMON:
537 if (chan >= thisboard->ai_nchan) {
538 dev_err(dev->class_dev,
539 "Analog input is not available\n");
540 return -EINVAL;
541 }
542 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
543 break;
544
545 case AREF_DIFF:
546 if (rang == 0 || rang == 1) {
547 dev_err(dev->class_dev,
548 "Range must be bipolar when aref = diff\n");
549 return -EINVAL;
550 }
551
552 if (chan >= thisboard->ai_diff_nchan) {
553 dev_err(dev->class_dev,
554 "Analog input is not available\n");
555 return -EINVAL;
556 }
557 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
558 break;
559 default:
560 dev_err(dev->class_dev, "Invalid aref specified\n");
561 return -EINVAL;
562 }
563
564 entry |= ME4000_AI_LIST_LAST_ENTRY;
565
566
567 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
568 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
569 ME4000_AI_CTRL_BIT_DATA_FIFO |
570 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
571 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
572
573
574 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
575 ME4000_AI_CTRL_BIT_MODE_2);
576 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
577
578
579 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
580 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
581
582
583 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
584
585
586 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
587 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
588
589
590 inl(dev->iobase + ME4000_AI_START_REG);
591
592
593 udelay(10);
594 if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
595 ME4000_AI_STATUS_BIT_EF_DATA)) {
596 dev_err(dev->class_dev, "Value not available after wait\n");
597 return -EIO;
598 }
599
600
601 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
602 data[0] = lval ^ 0x8000;
603
604 return 1;
605}
606
607static int me4000_ai_cancel(struct comedi_device *dev,
608 struct comedi_subdevice *s)
609{
610 unsigned long tmp;
611
612
613 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
614 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
615 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
616
617
618 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
619
620 return 0;
621}
622
623static int ai_check_chanlist(struct comedi_device *dev,
624 struct comedi_subdevice *s, struct comedi_cmd *cmd)
625{
626 const struct me4000_board *thisboard = comedi_board(dev);
627 int aref;
628 int i;
629
630
631 if (!cmd->chanlist_len) {
632 dev_err(dev->class_dev, "No channel list available\n");
633 return -EINVAL;
634 }
635
636
637 if (cmd->chanlist_len > ME4000_AI_CHANNEL_LIST_COUNT) {
638 dev_err(dev->class_dev, "Channel list is to large\n");
639 return -EINVAL;
640 }
641
642
643 if (!cmd->chanlist) {
644 dev_err(dev->class_dev, "NULL pointer to channel list\n");
645 return -EFAULT;
646 }
647
648
649 aref = CR_AREF(cmd->chanlist[0]);
650 for (i = 0; i < cmd->chanlist_len; i++) {
651 if (CR_AREF(cmd->chanlist[i]) != aref) {
652 dev_err(dev->class_dev,
653 "Mode is not equal for all entries\n");
654 return -EINVAL;
655 }
656 }
657
658
659 if (aref == SDF_DIFF) {
660 for (i = 0; i < cmd->chanlist_len; i++) {
661 if (CR_CHAN(cmd->chanlist[i]) >=
662 thisboard->ai_diff_nchan) {
663 dev_err(dev->class_dev,
664 "Channel number to high\n");
665 return -EINVAL;
666 }
667 }
668 } else {
669 for (i = 0; i < cmd->chanlist_len; i++) {
670 if (CR_CHAN(cmd->chanlist[i]) >= thisboard->ai_nchan) {
671 dev_err(dev->class_dev,
672 "Channel number to high\n");
673 return -EINVAL;
674 }
675 }
676 }
677
678
679 if (aref == SDF_DIFF) {
680 for (i = 0; i < cmd->chanlist_len; i++) {
681 if (CR_RANGE(cmd->chanlist[i]) != 1 &&
682 CR_RANGE(cmd->chanlist[i]) != 2) {
683 dev_err(dev->class_dev,
684 "Bipolar is not selected in differential mode\n");
685 return -EINVAL;
686 }
687 }
688 }
689
690 return 0;
691}
692
693static int ai_round_cmd_args(struct comedi_device *dev,
694 struct comedi_subdevice *s,
695 struct comedi_cmd *cmd,
696 unsigned int *init_ticks,
697 unsigned int *scan_ticks, unsigned int *chan_ticks)
698{
699
700 int rest;
701
702 *init_ticks = 0;
703 *scan_ticks = 0;
704 *chan_ticks = 0;
705
706 if (cmd->start_arg) {
707 *init_ticks = (cmd->start_arg * 33) / 1000;
708 rest = (cmd->start_arg * 33) % 1000;
709
710 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
711 if (rest > 33)
712 (*init_ticks)++;
713 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
714 if (rest)
715 (*init_ticks)++;
716 }
717 }
718
719 if (cmd->scan_begin_arg) {
720 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
721 rest = (cmd->scan_begin_arg * 33) % 1000;
722
723 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
724 if (rest > 33)
725 (*scan_ticks)++;
726 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
727 if (rest)
728 (*scan_ticks)++;
729 }
730 }
731
732 if (cmd->convert_arg) {
733 *chan_ticks = (cmd->convert_arg * 33) / 1000;
734 rest = (cmd->convert_arg * 33) % 1000;
735
736 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
737 if (rest > 33)
738 (*chan_ticks)++;
739 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
740 if (rest)
741 (*chan_ticks)++;
742 }
743 }
744
745 return 0;
746}
747
748static void ai_write_timer(struct comedi_device *dev,
749 unsigned int init_ticks,
750 unsigned int scan_ticks, unsigned int chan_ticks)
751{
752 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
753 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
754
755 if (scan_ticks) {
756 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
757 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
758 }
759
760 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
761 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
762}
763
764static int ai_write_chanlist(struct comedi_device *dev,
765 struct comedi_subdevice *s, struct comedi_cmd *cmd)
766{
767 unsigned int entry;
768 unsigned int chan;
769 unsigned int rang;
770 unsigned int aref;
771 int i;
772
773 for (i = 0; i < cmd->chanlist_len; i++) {
774 chan = CR_CHAN(cmd->chanlist[i]);
775 rang = CR_RANGE(cmd->chanlist[i]);
776 aref = CR_AREF(cmd->chanlist[i]);
777
778 entry = chan;
779
780 if (rang == 0)
781 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
782 else if (rang == 1)
783 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
784 else if (rang == 2)
785 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
786 else
787 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
788
789 if (aref == SDF_DIFF)
790 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
791 else
792 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
793
794 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
795 }
796
797 return 0;
798}
799
800static int ai_prepare(struct comedi_device *dev,
801 struct comedi_subdevice *s,
802 struct comedi_cmd *cmd,
803 unsigned int init_ticks,
804 unsigned int scan_ticks, unsigned int chan_ticks)
805{
806
807 unsigned long tmp = 0;
808
809
810 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
811
812
813 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
814
815
816 if ((cmd->start_src == TRIG_EXT &&
817 cmd->scan_begin_src == TRIG_TIMER &&
818 cmd->convert_src == TRIG_TIMER) ||
819 (cmd->start_src == TRIG_EXT &&
820 cmd->scan_begin_src == TRIG_FOLLOW &&
821 cmd->convert_src == TRIG_TIMER)) {
822 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
823 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
824 ME4000_AI_CTRL_BIT_DATA_FIFO;
825 } else if (cmd->start_src == TRIG_EXT &&
826 cmd->scan_begin_src == TRIG_EXT &&
827 cmd->convert_src == TRIG_TIMER) {
828 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
829 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
830 ME4000_AI_CTRL_BIT_DATA_FIFO;
831 } else if (cmd->start_src == TRIG_EXT &&
832 cmd->scan_begin_src == TRIG_EXT &&
833 cmd->convert_src == TRIG_EXT) {
834 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
835 ME4000_AI_CTRL_BIT_MODE_1 |
836 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
837 ME4000_AI_CTRL_BIT_DATA_FIFO;
838 } else {
839 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
840 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
841 ME4000_AI_CTRL_BIT_DATA_FIFO;
842 }
843
844
845 if (cmd->stop_src == TRIG_COUNT) {
846 outl(cmd->chanlist_len * cmd->stop_arg,
847 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
848 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
849 } else if (cmd->stop_src == TRIG_NONE &&
850 cmd->scan_end_src == TRIG_COUNT) {
851 outl(cmd->scan_end_arg,
852 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
853 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
854 } else {
855 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
856 }
857
858
859 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
860
861
862 ai_write_chanlist(dev, s, cmd);
863
864 return 0;
865}
866
867static int me4000_ai_do_cmd(struct comedi_device *dev,
868 struct comedi_subdevice *s)
869{
870 int err;
871 unsigned int init_ticks = 0;
872 unsigned int scan_ticks = 0;
873 unsigned int chan_ticks = 0;
874 struct comedi_cmd *cmd = &s->async->cmd;
875
876
877 err = me4000_ai_cancel(dev, s);
878 if (err)
879 return err;
880
881
882 err = ai_round_cmd_args(dev,
883 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
884 if (err)
885 return err;
886
887
888 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
889 if (err)
890 return err;
891
892
893 inl(dev->iobase + ME4000_AI_START_REG);
894
895 return 0;
896}
897
898static int me4000_ai_do_cmd_test(struct comedi_device *dev,
899 struct comedi_subdevice *s,
900 struct comedi_cmd *cmd)
901{
902
903 unsigned int init_ticks;
904 unsigned int chan_ticks;
905 unsigned int scan_ticks;
906 int err = 0;
907
908
909 cmd->flags &= TRIG_ROUND_NEAREST | TRIG_ROUND_UP | TRIG_ROUND_DOWN;
910
911
912 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
913
914
915
916 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
917 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
918 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
919 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
920 err |= cfc_check_trigger_src(&cmd->scan_end_src,
921 TRIG_NONE | TRIG_COUNT);
922 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
923
924 if (err)
925 return 1;
926
927
928
929 err |= cfc_check_trigger_is_unique(cmd->start_src);
930 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
931 err |= cfc_check_trigger_is_unique(cmd->convert_src);
932 err |= cfc_check_trigger_is_unique(cmd->scan_end_src);
933 err |= cfc_check_trigger_is_unique(cmd->stop_src);
934
935
936
937 if (cmd->start_src == TRIG_NOW &&
938 cmd->scan_begin_src == TRIG_TIMER &&
939 cmd->convert_src == TRIG_TIMER) {
940 } else if (cmd->start_src == TRIG_NOW &&
941 cmd->scan_begin_src == TRIG_FOLLOW &&
942 cmd->convert_src == TRIG_TIMER) {
943 } else if (cmd->start_src == TRIG_EXT &&
944 cmd->scan_begin_src == TRIG_TIMER &&
945 cmd->convert_src == TRIG_TIMER) {
946 } else if (cmd->start_src == TRIG_EXT &&
947 cmd->scan_begin_src == TRIG_FOLLOW &&
948 cmd->convert_src == TRIG_TIMER) {
949 } else if (cmd->start_src == TRIG_EXT &&
950 cmd->scan_begin_src == TRIG_EXT &&
951 cmd->convert_src == TRIG_TIMER) {
952 } else if (cmd->start_src == TRIG_EXT &&
953 cmd->scan_begin_src == TRIG_EXT &&
954 cmd->convert_src == TRIG_EXT) {
955 } else {
956 err |= -EINVAL;
957 }
958
959 if (cmd->stop_src == TRIG_NONE && cmd->scan_end_src == TRIG_NONE) {
960 } else if (cmd->stop_src == TRIG_COUNT &&
961 cmd->scan_end_src == TRIG_NONE) {
962 } else if (cmd->stop_src == TRIG_NONE &&
963 cmd->scan_end_src == TRIG_COUNT) {
964 } else if (cmd->stop_src == TRIG_COUNT &&
965 cmd->scan_end_src == TRIG_COUNT) {
966 } else {
967 err |= -EINVAL;
968 }
969
970 if (err)
971 return 2;
972
973
974
975 if (cmd->chanlist_len < 1) {
976 cmd->chanlist_len = 1;
977 err |= -EINVAL;
978 }
979 if (init_ticks < 66) {
980 cmd->start_arg = 2000;
981 err |= -EINVAL;
982 }
983 if (scan_ticks && scan_ticks < 67) {
984 cmd->scan_begin_arg = 2031;
985 err |= -EINVAL;
986 }
987 if (chan_ticks < 66) {
988 cmd->convert_arg = 2000;
989 err |= -EINVAL;
990 }
991
992 if (err)
993 return 3;
994
995
996
997
998 if (cmd->start_src == TRIG_NOW &&
999 cmd->scan_begin_src == TRIG_TIMER &&
1000 cmd->convert_src == TRIG_TIMER) {
1001
1002
1003 if (init_ticks < ME4000_AI_MIN_TICKS) {
1004 dev_err(dev->class_dev, "Invalid start arg\n");
1005 cmd->start_arg = 2000;
1006 err++;
1007 }
1008 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1009 dev_err(dev->class_dev, "Invalid convert arg\n");
1010 cmd->convert_arg = 2000;
1011 err++;
1012 }
1013 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1014 dev_err(dev->class_dev, "Invalid scan end arg\n");
1015
1016
1017 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1018 err++;
1019 }
1020 } else if (cmd->start_src == TRIG_NOW &&
1021 cmd->scan_begin_src == TRIG_FOLLOW &&
1022 cmd->convert_src == TRIG_TIMER) {
1023
1024
1025 if (init_ticks < ME4000_AI_MIN_TICKS) {
1026 dev_err(dev->class_dev, "Invalid start arg\n");
1027 cmd->start_arg = 2000;
1028 err++;
1029 }
1030 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1031 dev_err(dev->class_dev, "Invalid convert arg\n");
1032 cmd->convert_arg = 2000;
1033 err++;
1034 }
1035 } else if (cmd->start_src == TRIG_EXT &&
1036 cmd->scan_begin_src == TRIG_TIMER &&
1037 cmd->convert_src == TRIG_TIMER) {
1038
1039
1040 if (init_ticks < ME4000_AI_MIN_TICKS) {
1041 dev_err(dev->class_dev, "Invalid start arg\n");
1042 cmd->start_arg = 2000;
1043 err++;
1044 }
1045 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1046 dev_err(dev->class_dev, "Invalid convert arg\n");
1047 cmd->convert_arg = 2000;
1048 err++;
1049 }
1050 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1051 dev_err(dev->class_dev, "Invalid scan end arg\n");
1052
1053
1054 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1055 err++;
1056 }
1057 } else if (cmd->start_src == TRIG_EXT &&
1058 cmd->scan_begin_src == TRIG_FOLLOW &&
1059 cmd->convert_src == TRIG_TIMER) {
1060
1061
1062 if (init_ticks < ME4000_AI_MIN_TICKS) {
1063 dev_err(dev->class_dev, "Invalid start arg\n");
1064 cmd->start_arg = 2000;
1065 err++;
1066 }
1067 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1068 dev_err(dev->class_dev, "Invalid convert arg\n");
1069 cmd->convert_arg = 2000;
1070 err++;
1071 }
1072 } else if (cmd->start_src == TRIG_EXT &&
1073 cmd->scan_begin_src == TRIG_EXT &&
1074 cmd->convert_src == TRIG_TIMER) {
1075
1076
1077 if (init_ticks < ME4000_AI_MIN_TICKS) {
1078 dev_err(dev->class_dev, "Invalid start arg\n");
1079 cmd->start_arg = 2000;
1080 err++;
1081 }
1082 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1083 dev_err(dev->class_dev, "Invalid convert arg\n");
1084 cmd->convert_arg = 2000;
1085 err++;
1086 }
1087 } else if (cmd->start_src == TRIG_EXT &&
1088 cmd->scan_begin_src == TRIG_EXT &&
1089 cmd->convert_src == TRIG_EXT) {
1090
1091
1092 if (init_ticks < ME4000_AI_MIN_TICKS) {
1093 dev_err(dev->class_dev, "Invalid start arg\n");
1094 cmd->start_arg = 2000;
1095 err++;
1096 }
1097 }
1098 if (cmd->stop_src == TRIG_COUNT) {
1099 if (cmd->stop_arg == 0) {
1100 dev_err(dev->class_dev, "Invalid stop arg\n");
1101 cmd->stop_arg = 1;
1102 err++;
1103 }
1104 }
1105 if (cmd->scan_end_src == TRIG_COUNT) {
1106 if (cmd->scan_end_arg == 0) {
1107 dev_err(dev->class_dev, "Invalid scan end arg\n");
1108 cmd->scan_end_arg = 1;
1109 err++;
1110 }
1111 }
1112
1113 if (err)
1114 return 4;
1115
1116
1117
1118
1119 if (ai_check_chanlist(dev, s, cmd))
1120 return 5;
1121
1122 return 0;
1123}
1124
1125static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1126{
1127 unsigned int tmp;
1128 struct comedi_device *dev = dev_id;
1129 struct comedi_subdevice *s = &dev->subdevices[0];
1130 int i;
1131 int c = 0;
1132 long lval;
1133
1134 if (!dev->attached)
1135 return IRQ_NONE;
1136
1137
1138 s->async->events = 0;
1139
1140
1141 if (irq != dev->irq) {
1142 dev_err(dev->class_dev, "Incorrect interrupt num: %d\n", irq);
1143 return IRQ_HANDLED;
1144 }
1145
1146 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1147 ME4000_IRQ_STATUS_BIT_AI_HF) {
1148
1149 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1150
1151 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1152 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1153 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1154 c = ME4000_AI_FIFO_COUNT;
1155
1156
1157
1158
1159
1160 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1161 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1162 ME4000_AI_CTRL_BIT_SC_IRQ);
1163 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1164
1165 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1166
1167 dev_err(dev->class_dev, "FIFO overflow\n");
1168 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1169 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1170 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1171 s->async->events |= COMEDI_CB_BLOCK;
1172
1173 c = ME4000_AI_FIFO_COUNT / 2;
1174 } else {
1175 dev_err(dev->class_dev,
1176 "Can't determine state of fifo\n");
1177 c = 0;
1178
1179
1180
1181
1182
1183 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1184 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1185 ME4000_AI_CTRL_BIT_SC_IRQ);
1186 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1187
1188 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1189
1190 dev_err(dev->class_dev, "Undefined FIFO state\n");
1191 }
1192
1193 for (i = 0; i < c; i++) {
1194
1195 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1196 lval ^= 0x8000;
1197
1198 if (!comedi_buf_put(s->async, lval)) {
1199
1200
1201
1202
1203 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1204 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1205 ME4000_AI_CTRL_BIT_SC_IRQ);
1206 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1207
1208 s->async->events |= COMEDI_CB_OVERFLOW;
1209
1210 dev_err(dev->class_dev, "Buffer overflow\n");
1211
1212 break;
1213 }
1214 }
1215
1216
1217 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1218 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1219 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1220 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1221 }
1222
1223 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1224 ME4000_IRQ_STATUS_BIT_SC) {
1225 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOA;
1226
1227
1228
1229
1230
1231 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1232 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1233 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1234 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1235
1236
1237 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1238 ME4000_AI_STATUS_BIT_EF_DATA) {
1239
1240 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1241 lval ^= 0x8000;
1242
1243 if (!comedi_buf_put(s->async, lval)) {
1244 dev_err(dev->class_dev, "Buffer overflow\n");
1245 s->async->events |= COMEDI_CB_OVERFLOW;
1246 break;
1247 }
1248 }
1249
1250
1251 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1252 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1253 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1254 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1255 }
1256
1257 if (s->async->events)
1258 comedi_event(dev, s);
1259
1260 return IRQ_HANDLED;
1261}
1262
1263
1264
1265
1266
1267static int me4000_ao_insn_write(struct comedi_device *dev,
1268 struct comedi_subdevice *s,
1269 struct comedi_insn *insn, unsigned int *data)
1270{
1271 const struct me4000_board *thisboard = comedi_board(dev);
1272 struct me4000_info *info = dev->private;
1273 int chan = CR_CHAN(insn->chanspec);
1274 int rang = CR_RANGE(insn->chanspec);
1275 int aref = CR_AREF(insn->chanspec);
1276 unsigned long tmp;
1277
1278 if (insn->n == 0) {
1279 return 0;
1280 } else if (insn->n > 1) {
1281 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1282 insn->n);
1283 return -EINVAL;
1284 }
1285
1286 if (chan >= thisboard->ao_nchan) {
1287 dev_err(dev->class_dev, "Invalid channel %d\n", insn->n);
1288 return -EINVAL;
1289 }
1290
1291 if (rang != 0) {
1292 dev_err(dev->class_dev, "Invalid range %d\n", insn->n);
1293 return -EINVAL;
1294 }
1295
1296 if (aref != AREF_GROUND && aref != AREF_COMMON) {
1297 dev_err(dev->class_dev, "Invalid aref %d\n", insn->n);
1298 return -EINVAL;
1299 }
1300
1301
1302 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1303 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1304 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1305
1306
1307 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1308
1309
1310 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1311
1312
1313 info->ao_readback[chan] = data[0];
1314
1315 return 1;
1316}
1317
1318static int me4000_ao_insn_read(struct comedi_device *dev,
1319 struct comedi_subdevice *s,
1320 struct comedi_insn *insn, unsigned int *data)
1321{
1322 struct me4000_info *info = dev->private;
1323 int chan = CR_CHAN(insn->chanspec);
1324
1325 if (insn->n == 0) {
1326 return 0;
1327 } else if (insn->n > 1) {
1328 dev_err(dev->class_dev, "Invalid instruction length\n");
1329 return -EINVAL;
1330 }
1331
1332 data[0] = info->ao_readback[chan];
1333
1334 return 1;
1335}
1336
1337
1338
1339
1340
1341static int me4000_dio_insn_bits(struct comedi_device *dev,
1342 struct comedi_subdevice *s,
1343 struct comedi_insn *insn, unsigned int *data)
1344{
1345
1346
1347
1348
1349
1350
1351 if (data[0]) {
1352
1353 if ((s->io_bits & data[0]) != data[0])
1354 return -EIO;
1355
1356 s->state &= ~data[0];
1357 s->state |= data[0] & data[1];
1358
1359
1360 outl((s->state >> 0) & 0xFF,
1361 dev->iobase + ME4000_DIO_PORT_0_REG);
1362 outl((s->state >> 8) & 0xFF,
1363 dev->iobase + ME4000_DIO_PORT_1_REG);
1364 outl((s->state >> 16) & 0xFF,
1365 dev->iobase + ME4000_DIO_PORT_2_REG);
1366 outl((s->state >> 24) & 0xFF,
1367 dev->iobase + ME4000_DIO_PORT_3_REG);
1368 }
1369
1370
1371
1372 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1373 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1374 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1375 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1376
1377 return insn->n;
1378}
1379
1380static int me4000_dio_insn_config(struct comedi_device *dev,
1381 struct comedi_subdevice *s,
1382 struct comedi_insn *insn, unsigned int *data)
1383{
1384 unsigned long tmp;
1385 int chan = CR_CHAN(insn->chanspec);
1386
1387 switch (data[0]) {
1388 default:
1389 return -EINVAL;
1390 case INSN_CONFIG_DIO_QUERY:
1391 data[1] =
1392 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1393 return insn->n;
1394 case INSN_CONFIG_DIO_INPUT:
1395 case INSN_CONFIG_DIO_OUTPUT:
1396 break;
1397 }
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1408
1409 if (data[0] == INSN_CONFIG_DIO_OUTPUT) {
1410 if (chan < 8) {
1411 s->io_bits |= 0xFF;
1412 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1413 ME4000_DIO_CTRL_BIT_MODE_1);
1414 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1415 } else if (chan < 16) {
1416
1417
1418
1419
1420
1421 if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1422 return -ENODEV;
1423
1424 s->io_bits |= 0xFF00;
1425 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1426 ME4000_DIO_CTRL_BIT_MODE_3);
1427 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1428 } else if (chan < 24) {
1429 s->io_bits |= 0xFF0000;
1430 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1431 ME4000_DIO_CTRL_BIT_MODE_5);
1432 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1433 } else if (chan < 32) {
1434 s->io_bits |= 0xFF000000;
1435 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1436 ME4000_DIO_CTRL_BIT_MODE_7);
1437 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1438 } else {
1439 return -EINVAL;
1440 }
1441 } else {
1442 if (chan < 8) {
1443
1444
1445
1446
1447
1448 if (!inl(dev->iobase + ME4000_DIO_DIR_REG))
1449 return -ENODEV;
1450
1451 s->io_bits &= ~0xFF;
1452 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 |
1453 ME4000_DIO_CTRL_BIT_MODE_1);
1454 } else if (chan < 16) {
1455 s->io_bits &= ~0xFF00;
1456 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1457 ME4000_DIO_CTRL_BIT_MODE_3);
1458 } else if (chan < 24) {
1459 s->io_bits &= ~0xFF0000;
1460 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_4 |
1461 ME4000_DIO_CTRL_BIT_MODE_5);
1462 } else if (chan < 32) {
1463 s->io_bits &= ~0xFF000000;
1464 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_6 |
1465 ME4000_DIO_CTRL_BIT_MODE_7);
1466 } else {
1467 return -EINVAL;
1468 }
1469 }
1470
1471 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1472
1473 return 1;
1474}
1475
1476
1477
1478
1479
1480static int me4000_cnt_insn_config(struct comedi_device *dev,
1481 struct comedi_subdevice *s,
1482 struct comedi_insn *insn,
1483 unsigned int *data)
1484{
1485 struct me4000_info *info = dev->private;
1486 int err;
1487
1488 switch (data[0]) {
1489 case GPCT_RESET:
1490 if (insn->n != 1)
1491 return -EINVAL;
1492
1493 err = i8254_load(info->timer_regbase, 0, insn->chanspec, 0,
1494 I8254_MODE0 | I8254_BINARY);
1495 if (err)
1496 return err;
1497 break;
1498 case GPCT_SET_OPERATION:
1499 if (insn->n != 2)
1500 return -EINVAL;
1501
1502 err = i8254_set_mode(info->timer_regbase, 0, insn->chanspec,
1503 (data[1] << 1) | I8254_BINARY);
1504 if (err)
1505 return err;
1506 break;
1507 default:
1508 return -EINVAL;
1509 }
1510
1511 return insn->n;
1512}
1513
1514static int me4000_cnt_insn_read(struct comedi_device *dev,
1515 struct comedi_subdevice *s,
1516 struct comedi_insn *insn, unsigned int *data)
1517{
1518 struct me4000_info *info = dev->private;
1519
1520 if (insn->n == 0)
1521 return 0;
1522
1523 if (insn->n > 1) {
1524 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1525 insn->n);
1526 return -EINVAL;
1527 }
1528
1529 data[0] = i8254_read(info->timer_regbase, 0, insn->chanspec);
1530
1531 return 1;
1532}
1533
1534static int me4000_cnt_insn_write(struct comedi_device *dev,
1535 struct comedi_subdevice *s,
1536 struct comedi_insn *insn, unsigned int *data)
1537{
1538 struct me4000_info *info = dev->private;
1539
1540 if (insn->n == 0) {
1541 return 0;
1542 } else if (insn->n > 1) {
1543 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1544 insn->n);
1545 return -EINVAL;
1546 }
1547
1548 i8254_write(info->timer_regbase, 0, insn->chanspec, data[0]);
1549
1550 return 1;
1551}
1552
1553static const void *me4000_find_boardinfo(struct comedi_device *dev,
1554 struct pci_dev *pcidev)
1555{
1556 const struct me4000_board *thisboard;
1557 int i;
1558
1559 for (i = 0; i < ARRAY_SIZE(me4000_boards); i++) {
1560 thisboard = &me4000_boards[i];
1561 if (thisboard->device_id == pcidev->device)
1562 return thisboard;
1563 }
1564 return NULL;
1565}
1566
1567static int me4000_auto_attach(struct comedi_device *dev,
1568 unsigned long context_unused)
1569{
1570 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1571 const struct me4000_board *thisboard;
1572 struct me4000_info *info;
1573 struct comedi_subdevice *s;
1574 int result;
1575
1576 thisboard = me4000_find_boardinfo(dev, pcidev);
1577 if (!thisboard)
1578 return -ENODEV;
1579 dev->board_ptr = thisboard;
1580 dev->board_name = thisboard->name;
1581
1582 info = kzalloc(sizeof(*info), GFP_KERNEL);
1583 if (!info)
1584 return -ENOMEM;
1585 dev->private = info;
1586
1587 result = comedi_pci_enable(pcidev, dev->board_name);
1588 if (result)
1589 return result;
1590
1591 info->plx_regbase = pci_resource_start(pcidev, 1);
1592 dev->iobase = pci_resource_start(pcidev, 2);
1593 info->timer_regbase = pci_resource_start(pcidev, 3);
1594 if (!info->plx_regbase || !dev->iobase || !info->timer_regbase)
1595 return -ENODEV;
1596
1597 result = xilinx_download(dev);
1598 if (result)
1599 return result;
1600
1601 me4000_reset(dev);
1602
1603 result = comedi_alloc_subdevices(dev, 4);
1604 if (result)
1605 return result;
1606
1607
1608
1609
1610
1611 s = &dev->subdevices[0];
1612
1613 if (thisboard->ai_nchan) {
1614 s->type = COMEDI_SUBD_AI;
1615 s->subdev_flags =
1616 SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1617 s->n_chan = thisboard->ai_nchan;
1618 s->maxdata = 0xFFFF;
1619 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1620 s->range_table = &me4000_ai_range;
1621 s->insn_read = me4000_ai_insn_read;
1622
1623 if (pcidev->irq > 0) {
1624 if (request_irq(pcidev->irq, me4000_ai_isr,
1625 IRQF_SHARED, dev->board_name, dev)) {
1626 dev_warn(dev->class_dev,
1627 "request_irq failed\n");
1628 } else {
1629 dev->read_subdev = s;
1630 s->subdev_flags |= SDF_CMD_READ;
1631 s->cancel = me4000_ai_cancel;
1632 s->do_cmdtest = me4000_ai_do_cmd_test;
1633 s->do_cmd = me4000_ai_do_cmd;
1634
1635 dev->irq = pcidev->irq;
1636 }
1637 } else {
1638 dev_warn(dev->class_dev, "No interrupt available\n");
1639 }
1640 } else {
1641 s->type = COMEDI_SUBD_UNUSED;
1642 }
1643
1644
1645
1646
1647
1648 s = &dev->subdevices[1];
1649
1650 if (thisboard->ao_nchan) {
1651 s->type = COMEDI_SUBD_AO;
1652 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON | SDF_GROUND;
1653 s->n_chan = thisboard->ao_nchan;
1654 s->maxdata = 0xFFFF;
1655 s->range_table = &range_bipolar10;
1656 s->insn_write = me4000_ao_insn_write;
1657 s->insn_read = me4000_ao_insn_read;
1658 } else {
1659 s->type = COMEDI_SUBD_UNUSED;
1660 }
1661
1662
1663
1664
1665
1666 s = &dev->subdevices[2];
1667
1668 if (thisboard->dio_nchan) {
1669 s->type = COMEDI_SUBD_DIO;
1670 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1671 s->n_chan = thisboard->dio_nchan;
1672 s->maxdata = 1;
1673 s->range_table = &range_digital;
1674 s->insn_bits = me4000_dio_insn_bits;
1675 s->insn_config = me4000_dio_insn_config;
1676 } else {
1677 s->type = COMEDI_SUBD_UNUSED;
1678 }
1679
1680
1681
1682
1683
1684 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1685 s->io_bits |= 0xFF;
1686 outl(ME4000_DIO_CTRL_BIT_MODE_0,
1687 dev->iobase + ME4000_DIO_DIR_REG);
1688 }
1689
1690
1691
1692
1693
1694 s = &dev->subdevices[3];
1695
1696 if (thisboard->has_counter) {
1697 s->type = COMEDI_SUBD_COUNTER;
1698 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1699 s->n_chan = 3;
1700 s->maxdata = 0xFFFF;
1701 s->insn_read = me4000_cnt_insn_read;
1702 s->insn_write = me4000_cnt_insn_write;
1703 s->insn_config = me4000_cnt_insn_config;
1704 } else {
1705 s->type = COMEDI_SUBD_UNUSED;
1706 }
1707
1708 return 0;
1709}
1710
1711static void me4000_detach(struct comedi_device *dev)
1712{
1713 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1714
1715 if (dev->irq)
1716 free_irq(dev->irq, dev);
1717 if (pcidev) {
1718 if (dev->iobase) {
1719 me4000_reset(dev);
1720 comedi_pci_disable(pcidev);
1721 }
1722 }
1723}
1724
1725static struct comedi_driver me4000_driver = {
1726 .driver_name = "me4000",
1727 .module = THIS_MODULE,
1728 .auto_attach = me4000_auto_attach,
1729 .detach = me4000_detach,
1730};
1731
1732static int me4000_pci_probe(struct pci_dev *dev,
1733 const struct pci_device_id *ent)
1734{
1735 return comedi_pci_auto_config(dev, &me4000_driver);
1736}
1737
1738static DEFINE_PCI_DEVICE_TABLE(me4000_pci_table) = {
1739 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4650)},
1740 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660)},
1741 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660I)},
1742 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660S)},
1743 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4660IS)},
1744 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670)},
1745 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670I)},
1746 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670S)},
1747 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4670IS)},
1748 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680)},
1749 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680I)},
1750 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680S)},
1751 {PCI_DEVICE(PCI_VENDOR_ID_MEILHAUS, PCI_DEVICE_ID_MEILHAUS_ME4680IS)},
1752 {0}
1753};
1754MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1755
1756static struct pci_driver me4000_pci_driver = {
1757 .name = "me4000",
1758 .id_table = me4000_pci_table,
1759 .probe = me4000_pci_probe,
1760 .remove = comedi_pci_auto_unconfig,
1761};
1762module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1763
1764MODULE_AUTHOR("Comedi http://www.comedi.org");
1765MODULE_DESCRIPTION("Comedi low-level driver");
1766MODULE_LICENSE("GPL");
1767
