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18#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#include <linux/module.h>
23#include <linux/ioport.h>
24#include <linux/init.h>
25#include <linux/console.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/pci.h>
29#include <linux/serial_core.h>
30#include <linux/serial.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33
34#include <asm/io.h>
35
36static char *serial_version = "1.11";
37static char *serial_name = "TX39/49 Serial driver";
38
39#define PASS_LIMIT 256
40
41#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
42
43#define TXX9_TTY_NAME "ttyTX"
44#define TXX9_TTY_MINOR_START 196
45#define TXX9_TTY_MAJOR 204
46#else
47
48#define TXX9_TTY_NAME "ttyS"
49#define TXX9_TTY_MINOR_START 64
50#define TXX9_TTY_MAJOR TTY_MAJOR
51#endif
52
53
54#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
55#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
56
57#ifdef CONFIG_PCI
58
59#define ENABLE_SERIAL_TXX9_PCI
60#endif
61
62
63
64
65#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
66
67struct uart_txx9_port {
68 struct uart_port port;
69
70};
71
72#define TXX9_REGION_SIZE 0x24
73
74
75#define TXX9_SILCR 0x00
76#define TXX9_SIDICR 0x04
77#define TXX9_SIDISR 0x08
78#define TXX9_SICISR 0x0c
79#define TXX9_SIFCR 0x10
80#define TXX9_SIFLCR 0x14
81#define TXX9_SIBGR 0x18
82#define TXX9_SITFIFO 0x1c
83#define TXX9_SIRFIFO 0x20
84
85
86#define TXX9_SILCR_SCS_MASK 0x00000060
87#define TXX9_SILCR_SCS_IMCLK 0x00000000
88#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
89#define TXX9_SILCR_SCS_SCLK 0x00000040
90#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
91#define TXX9_SILCR_UEPS 0x00000010
92#define TXX9_SILCR_UPEN 0x00000008
93#define TXX9_SILCR_USBL_MASK 0x00000004
94#define TXX9_SILCR_USBL_1BIT 0x00000000
95#define TXX9_SILCR_USBL_2BIT 0x00000004
96#define TXX9_SILCR_UMODE_MASK 0x00000003
97#define TXX9_SILCR_UMODE_8BIT 0x00000000
98#define TXX9_SILCR_UMODE_7BIT 0x00000001
99
100
101#define TXX9_SIDICR_TDE 0x00008000
102#define TXX9_SIDICR_RDE 0x00004000
103#define TXX9_SIDICR_TIE 0x00002000
104#define TXX9_SIDICR_RIE 0x00001000
105#define TXX9_SIDICR_SPIE 0x00000800
106#define TXX9_SIDICR_CTSAC 0x00000600
107#define TXX9_SIDICR_STIE_MASK 0x0000003f
108#define TXX9_SIDICR_STIE_OERS 0x00000020
109#define TXX9_SIDICR_STIE_CTSS 0x00000010
110#define TXX9_SIDICR_STIE_RBRKD 0x00000008
111#define TXX9_SIDICR_STIE_TRDY 0x00000004
112#define TXX9_SIDICR_STIE_TXALS 0x00000002
113#define TXX9_SIDICR_STIE_UBRKD 0x00000001
114
115
116#define TXX9_SIDISR_UBRK 0x00008000
117#define TXX9_SIDISR_UVALID 0x00004000
118#define TXX9_SIDISR_UFER 0x00002000
119#define TXX9_SIDISR_UPER 0x00001000
120#define TXX9_SIDISR_UOER 0x00000800
121#define TXX9_SIDISR_ERI 0x00000400
122#define TXX9_SIDISR_TOUT 0x00000200
123#define TXX9_SIDISR_TDIS 0x00000100
124#define TXX9_SIDISR_RDIS 0x00000080
125#define TXX9_SIDISR_STIS 0x00000040
126#define TXX9_SIDISR_RFDN_MASK 0x0000001f
127
128
129#define TXX9_SICISR_OERS 0x00000020
130#define TXX9_SICISR_CTSS 0x00000010
131#define TXX9_SICISR_RBRKD 0x00000008
132#define TXX9_SICISR_TRDY 0x00000004
133#define TXX9_SICISR_TXALS 0x00000002
134#define TXX9_SICISR_UBRKD 0x00000001
135
136
137#define TXX9_SIFCR_SWRST 0x00008000
138#define TXX9_SIFCR_RDIL_MASK 0x00000180
139#define TXX9_SIFCR_RDIL_1 0x00000000
140#define TXX9_SIFCR_RDIL_4 0x00000080
141#define TXX9_SIFCR_RDIL_8 0x00000100
142#define TXX9_SIFCR_RDIL_12 0x00000180
143#define TXX9_SIFCR_RDIL_MAX 0x00000180
144#define TXX9_SIFCR_TDIL_MASK 0x00000018
145#define TXX9_SIFCR_TDIL_MASK 0x00000018
146#define TXX9_SIFCR_TDIL_1 0x00000000
147#define TXX9_SIFCR_TDIL_4 0x00000001
148#define TXX9_SIFCR_TDIL_8 0x00000010
149#define TXX9_SIFCR_TDIL_MAX 0x00000010
150#define TXX9_SIFCR_TFRST 0x00000004
151#define TXX9_SIFCR_RFRST 0x00000002
152#define TXX9_SIFCR_FRSTE 0x00000001
153#define TXX9_SIO_TX_FIFO 8
154#define TXX9_SIO_RX_FIFO 16
155
156
157#define TXX9_SIFLCR_RCS 0x00001000
158#define TXX9_SIFLCR_TES 0x00000800
159#define TXX9_SIFLCR_RTSSC 0x00000200
160#define TXX9_SIFLCR_RSDE 0x00000100
161#define TXX9_SIFLCR_TSDE 0x00000080
162#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
163#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
164#define TXX9_SIFLCR_TBRK 0x00000001
165
166
167#define TXX9_SIBGR_BCLK_MASK 0x00000300
168#define TXX9_SIBGR_BCLK_T0 0x00000000
169#define TXX9_SIBGR_BCLK_T2 0x00000100
170#define TXX9_SIBGR_BCLK_T4 0x00000200
171#define TXX9_SIBGR_BCLK_T6 0x00000300
172#define TXX9_SIBGR_BRD_MASK 0x000000ff
173
174static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
175{
176 switch (up->port.iotype) {
177 default:
178 return __raw_readl(up->port.membase + offset);
179 case UPIO_PORT:
180 return inl(up->port.iobase + offset);
181 }
182}
183
184static inline void
185sio_out(struct uart_txx9_port *up, int offset, int value)
186{
187 switch (up->port.iotype) {
188 default:
189 __raw_writel(value, up->port.membase + offset);
190 break;
191 case UPIO_PORT:
192 outl(value, up->port.iobase + offset);
193 break;
194 }
195}
196
197static inline void
198sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
199{
200 sio_out(up, offset, sio_in(up, offset) & ~value);
201}
202static inline void
203sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
204{
205 sio_out(up, offset, sio_in(up, offset) | value);
206}
207
208static inline void
209sio_quot_set(struct uart_txx9_port *up, int quot)
210{
211 quot >>= 1;
212 if (quot < 256)
213 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
214 else if (quot < (256 << 2))
215 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
216 else if (quot < (256 << 4))
217 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
218 else if (quot < (256 << 6))
219 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
220 else
221 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
222}
223
224static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port)
225{
226 return container_of(port, struct uart_txx9_port, port);
227}
228
229static void serial_txx9_stop_tx(struct uart_port *port)
230{
231 struct uart_txx9_port *up = to_uart_txx9_port(port);
232 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
233}
234
235static void serial_txx9_start_tx(struct uart_port *port)
236{
237 struct uart_txx9_port *up = to_uart_txx9_port(port);
238 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
239}
240
241static void serial_txx9_stop_rx(struct uart_port *port)
242{
243 struct uart_txx9_port *up = to_uart_txx9_port(port);
244 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
245}
246
247static void serial_txx9_enable_ms(struct uart_port *port)
248{
249
250}
251
252static void serial_txx9_initialize(struct uart_port *port)
253{
254 struct uart_txx9_port *up = to_uart_txx9_port(port);
255 unsigned int tmout = 10000;
256
257 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
258
259
260 mmiowb();
261 udelay(1);
262 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
263 udelay(1);
264
265 sio_set(up, TXX9_SIFCR,
266 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
267
268 sio_out(up, TXX9_SILCR,
269 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
270 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
271 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
272 sio_quot_set(up, uart_get_divisor(port, 9600));
273 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX );
274 sio_out(up, TXX9_SIDICR, 0);
275}
276
277static inline void
278receive_chars(struct uart_txx9_port *up, unsigned int *status)
279{
280 unsigned char ch;
281 unsigned int disr = *status;
282 int max_count = 256;
283 char flag;
284 unsigned int next_ignore_status_mask;
285
286 do {
287 ch = sio_in(up, TXX9_SIRFIFO);
288 flag = TTY_NORMAL;
289 up->port.icount.rx++;
290
291
292 next_ignore_status_mask =
293 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
294 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
295 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
296
297
298
299 if (disr & TXX9_SIDISR_UBRK) {
300 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
301 up->port.icount.brk++;
302
303
304
305
306
307
308 if (uart_handle_break(&up->port))
309 goto ignore_char;
310 } else if (disr & TXX9_SIDISR_UPER)
311 up->port.icount.parity++;
312 else if (disr & TXX9_SIDISR_UFER)
313 up->port.icount.frame++;
314 if (disr & TXX9_SIDISR_UOER) {
315 up->port.icount.overrun++;
316
317
318
319
320
321
322 next_ignore_status_mask |=
323 TXX9_SIDISR_RFDN_MASK;
324 }
325
326
327
328
329 disr &= up->port.read_status_mask;
330
331 if (disr & TXX9_SIDISR_UBRK) {
332 flag = TTY_BREAK;
333 } else if (disr & TXX9_SIDISR_UPER)
334 flag = TTY_PARITY;
335 else if (disr & TXX9_SIDISR_UFER)
336 flag = TTY_FRAME;
337 }
338 if (uart_handle_sysrq_char(&up->port, ch))
339 goto ignore_char;
340
341 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
342
343 ignore_char:
344 up->port.ignore_status_mask = next_ignore_status_mask;
345 disr = sio_in(up, TXX9_SIDISR);
346 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
347 spin_unlock(&up->port.lock);
348 tty_flip_buffer_push(&up->port.state->port);
349 spin_lock(&up->port.lock);
350 *status = disr;
351}
352
353static inline void transmit_chars(struct uart_txx9_port *up)
354{
355 struct circ_buf *xmit = &up->port.state->xmit;
356 int count;
357
358 if (up->port.x_char) {
359 sio_out(up, TXX9_SITFIFO, up->port.x_char);
360 up->port.icount.tx++;
361 up->port.x_char = 0;
362 return;
363 }
364 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
365 serial_txx9_stop_tx(&up->port);
366 return;
367 }
368
369 count = TXX9_SIO_TX_FIFO;
370 do {
371 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
372 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
373 up->port.icount.tx++;
374 if (uart_circ_empty(xmit))
375 break;
376 } while (--count > 0);
377
378 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
379 uart_write_wakeup(&up->port);
380
381 if (uart_circ_empty(xmit))
382 serial_txx9_stop_tx(&up->port);
383}
384
385static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
386{
387 int pass_counter = 0;
388 struct uart_txx9_port *up = dev_id;
389 unsigned int status;
390
391 while (1) {
392 spin_lock(&up->port.lock);
393 status = sio_in(up, TXX9_SIDISR);
394 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
395 status &= ~TXX9_SIDISR_TDIS;
396 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
397 TXX9_SIDISR_TOUT))) {
398 spin_unlock(&up->port.lock);
399 break;
400 }
401
402 if (status & TXX9_SIDISR_RDIS)
403 receive_chars(up, &status);
404 if (status & TXX9_SIDISR_TDIS)
405 transmit_chars(up);
406
407 sio_mask(up, TXX9_SIDISR,
408 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
409 TXX9_SIDISR_TOUT);
410 spin_unlock(&up->port.lock);
411
412 if (pass_counter++ > PASS_LIMIT)
413 break;
414 }
415
416 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
417}
418
419static unsigned int serial_txx9_tx_empty(struct uart_port *port)
420{
421 struct uart_txx9_port *up = to_uart_txx9_port(port);
422 unsigned long flags;
423 unsigned int ret;
424
425 spin_lock_irqsave(&up->port.lock, flags);
426 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
427 spin_unlock_irqrestore(&up->port.lock, flags);
428
429 return ret;
430}
431
432static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
433{
434 struct uart_txx9_port *up = to_uart_txx9_port(port);
435 unsigned int ret;
436
437
438 ret = TIOCM_CAR | TIOCM_DSR;
439 ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
440 ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
441
442 return ret;
443}
444
445static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
446{
447 struct uart_txx9_port *up = to_uart_txx9_port(port);
448
449 if (mctrl & TIOCM_RTS)
450 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
451 else
452 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
453}
454
455static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
456{
457 struct uart_txx9_port *up = to_uart_txx9_port(port);
458 unsigned long flags;
459
460 spin_lock_irqsave(&up->port.lock, flags);
461 if (break_state == -1)
462 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
463 else
464 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
465 spin_unlock_irqrestore(&up->port.lock, flags);
466}
467
468#if defined(CONFIG_SERIAL_TXX9_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
469
470
471
472static void wait_for_xmitr(struct uart_txx9_port *up)
473{
474 unsigned int tmout = 10000;
475
476
477 while (--tmout &&
478 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
479 udelay(1);
480
481
482 if (up->port.flags & UPF_CONS_FLOW) {
483 tmout = 1000000;
484 while (--tmout &&
485 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
486 udelay(1);
487 }
488}
489#endif
490
491#ifdef CONFIG_CONSOLE_POLL
492
493
494
495
496
497static int serial_txx9_get_poll_char(struct uart_port *port)
498{
499 unsigned int ier;
500 unsigned char c;
501 struct uart_txx9_port *up = to_uart_txx9_port(port);
502
503
504
505
506 ier = sio_in(up, TXX9_SIDICR);
507 sio_out(up, TXX9_SIDICR, 0);
508
509 while (sio_in(up, TXX9_SIDISR) & TXX9_SIDISR_UVALID)
510 ;
511
512 c = sio_in(up, TXX9_SIRFIFO);
513
514
515
516
517
518 sio_mask(up, TXX9_SIDISR, TXX9_SIDISR_RDIS);
519 sio_out(up, TXX9_SIDICR, ier);
520 return c;
521}
522
523
524static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
525{
526 unsigned int ier;
527 struct uart_txx9_port *up = to_uart_txx9_port(port);
528
529
530
531
532 ier = sio_in(up, TXX9_SIDICR);
533 sio_out(up, TXX9_SIDICR, 0);
534
535 wait_for_xmitr(up);
536
537
538
539
540 sio_out(up, TXX9_SITFIFO, c);
541 if (c == 10) {
542 wait_for_xmitr(up);
543 sio_out(up, TXX9_SITFIFO, 13);
544 }
545
546
547
548
549
550 wait_for_xmitr(up);
551 sio_out(up, TXX9_SIDICR, ier);
552}
553
554#endif
555
556static int serial_txx9_startup(struct uart_port *port)
557{
558 struct uart_txx9_port *up = to_uart_txx9_port(port);
559 unsigned long flags;
560 int retval;
561
562
563
564
565
566 sio_set(up, TXX9_SIFCR,
567 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
568
569 sio_mask(up, TXX9_SIFCR,
570 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
571 sio_out(up, TXX9_SIDICR, 0);
572
573
574
575
576 sio_out(up, TXX9_SIDISR, 0);
577
578 retval = request_irq(up->port.irq, serial_txx9_interrupt,
579 IRQF_SHARED, "serial_txx9", up);
580 if (retval)
581 return retval;
582
583
584
585
586 spin_lock_irqsave(&up->port.lock, flags);
587 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
588 spin_unlock_irqrestore(&up->port.lock, flags);
589
590
591 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
592
593
594
595
596 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
597
598 return 0;
599}
600
601static void serial_txx9_shutdown(struct uart_port *port)
602{
603 struct uart_txx9_port *up = to_uart_txx9_port(port);
604 unsigned long flags;
605
606
607
608
609 sio_out(up, TXX9_SIDICR, 0);
610
611 spin_lock_irqsave(&up->port.lock, flags);
612 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
613 spin_unlock_irqrestore(&up->port.lock, flags);
614
615
616
617
618 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
619
620#ifdef CONFIG_SERIAL_TXX9_CONSOLE
621 if (up->port.cons && up->port.line == up->port.cons->index) {
622 free_irq(up->port.irq, up);
623 return;
624 }
625#endif
626
627 sio_set(up, TXX9_SIFCR,
628 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
629
630 sio_mask(up, TXX9_SIFCR,
631 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
632
633
634 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
635
636 free_irq(up->port.irq, up);
637}
638
639static void
640serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
641 struct ktermios *old)
642{
643 struct uart_txx9_port *up = to_uart_txx9_port(port);
644 unsigned int cval, fcr = 0;
645 unsigned long flags;
646 unsigned int baud, quot;
647
648
649
650
651 termios->c_cflag &= ~(HUPCL | CMSPAR);
652 termios->c_cflag |= CLOCAL;
653
654 cval = sio_in(up, TXX9_SILCR);
655
656 cval &= ~TXX9_SILCR_UMODE_MASK;
657 switch (termios->c_cflag & CSIZE) {
658 case CS7:
659 cval |= TXX9_SILCR_UMODE_7BIT;
660 break;
661 default:
662 case CS5:
663 case CS6:
664 case CS8:
665 cval |= TXX9_SILCR_UMODE_8BIT;
666 break;
667 }
668
669 cval &= ~TXX9_SILCR_USBL_MASK;
670 if (termios->c_cflag & CSTOPB)
671 cval |= TXX9_SILCR_USBL_2BIT;
672 else
673 cval |= TXX9_SILCR_USBL_1BIT;
674 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
675 if (termios->c_cflag & PARENB)
676 cval |= TXX9_SILCR_UPEN;
677 if (!(termios->c_cflag & PARODD))
678 cval |= TXX9_SILCR_UEPS;
679
680
681
682
683 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
684 quot = uart_get_divisor(port, baud);
685
686
687
688 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
689
690
691
692
693
694 spin_lock_irqsave(&up->port.lock, flags);
695
696
697
698
699 uart_update_timeout(port, termios->c_cflag, baud);
700
701 up->port.read_status_mask = TXX9_SIDISR_UOER |
702 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
703 if (termios->c_iflag & INPCK)
704 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
705 if (termios->c_iflag & (BRKINT | PARMRK))
706 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
707
708
709
710
711 up->port.ignore_status_mask = 0;
712 if (termios->c_iflag & IGNPAR)
713 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
714 if (termios->c_iflag & IGNBRK) {
715 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
716
717
718
719
720 if (termios->c_iflag & IGNPAR)
721 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
722 }
723
724
725
726
727 if ((termios->c_cflag & CREAD) == 0)
728 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
729
730
731 if ((termios->c_cflag & CRTSCTS) &&
732 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
733 sio_set(up, TXX9_SIFLCR,
734 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
735 } else {
736 sio_mask(up, TXX9_SIFLCR,
737 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
738 }
739
740 sio_out(up, TXX9_SILCR, cval);
741 sio_quot_set(up, quot);
742 sio_out(up, TXX9_SIFCR, fcr);
743
744 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
745 spin_unlock_irqrestore(&up->port.lock, flags);
746}
747
748static void
749serial_txx9_pm(struct uart_port *port, unsigned int state,
750 unsigned int oldstate)
751{
752
753
754
755
756
757
758
759
760 if (state == 0 && oldstate != -1)
761 serial_txx9_initialize(port);
762}
763
764static int serial_txx9_request_resource(struct uart_txx9_port *up)
765{
766 unsigned int size = TXX9_REGION_SIZE;
767 int ret = 0;
768
769 switch (up->port.iotype) {
770 default:
771 if (!up->port.mapbase)
772 break;
773
774 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
775 ret = -EBUSY;
776 break;
777 }
778
779 if (up->port.flags & UPF_IOREMAP) {
780 up->port.membase = ioremap(up->port.mapbase, size);
781 if (!up->port.membase) {
782 release_mem_region(up->port.mapbase, size);
783 ret = -ENOMEM;
784 }
785 }
786 break;
787
788 case UPIO_PORT:
789 if (!request_region(up->port.iobase, size, "serial_txx9"))
790 ret = -EBUSY;
791 break;
792 }
793 return ret;
794}
795
796static void serial_txx9_release_resource(struct uart_txx9_port *up)
797{
798 unsigned int size = TXX9_REGION_SIZE;
799
800 switch (up->port.iotype) {
801 default:
802 if (!up->port.mapbase)
803 break;
804
805 if (up->port.flags & UPF_IOREMAP) {
806 iounmap(up->port.membase);
807 up->port.membase = NULL;
808 }
809
810 release_mem_region(up->port.mapbase, size);
811 break;
812
813 case UPIO_PORT:
814 release_region(up->port.iobase, size);
815 break;
816 }
817}
818
819static void serial_txx9_release_port(struct uart_port *port)
820{
821 struct uart_txx9_port *up = to_uart_txx9_port(port);
822 serial_txx9_release_resource(up);
823}
824
825static int serial_txx9_request_port(struct uart_port *port)
826{
827 struct uart_txx9_port *up = to_uart_txx9_port(port);
828 return serial_txx9_request_resource(up);
829}
830
831static void serial_txx9_config_port(struct uart_port *port, int uflags)
832{
833 struct uart_txx9_port *up = to_uart_txx9_port(port);
834 int ret;
835
836
837
838
839
840 ret = serial_txx9_request_resource(up);
841 if (ret < 0)
842 return;
843 port->type = PORT_TXX9;
844 up->port.fifosize = TXX9_SIO_TX_FIFO;
845
846#ifdef CONFIG_SERIAL_TXX9_CONSOLE
847 if (up->port.line == up->port.cons->index)
848 return;
849#endif
850 serial_txx9_initialize(port);
851}
852
853static const char *
854serial_txx9_type(struct uart_port *port)
855{
856 return "txx9";
857}
858
859static struct uart_ops serial_txx9_pops = {
860 .tx_empty = serial_txx9_tx_empty,
861 .set_mctrl = serial_txx9_set_mctrl,
862 .get_mctrl = serial_txx9_get_mctrl,
863 .stop_tx = serial_txx9_stop_tx,
864 .start_tx = serial_txx9_start_tx,
865 .stop_rx = serial_txx9_stop_rx,
866 .enable_ms = serial_txx9_enable_ms,
867 .break_ctl = serial_txx9_break_ctl,
868 .startup = serial_txx9_startup,
869 .shutdown = serial_txx9_shutdown,
870 .set_termios = serial_txx9_set_termios,
871 .pm = serial_txx9_pm,
872 .type = serial_txx9_type,
873 .release_port = serial_txx9_release_port,
874 .request_port = serial_txx9_request_port,
875 .config_port = serial_txx9_config_port,
876#ifdef CONFIG_CONSOLE_POLL
877 .poll_get_char = serial_txx9_get_poll_char,
878 .poll_put_char = serial_txx9_put_poll_char,
879#endif
880};
881
882static struct uart_txx9_port serial_txx9_ports[UART_NR];
883
884static void __init serial_txx9_register_ports(struct uart_driver *drv,
885 struct device *dev)
886{
887 int i;
888
889 for (i = 0; i < UART_NR; i++) {
890 struct uart_txx9_port *up = &serial_txx9_ports[i];
891
892 up->port.line = i;
893 up->port.ops = &serial_txx9_pops;
894 up->port.dev = dev;
895 if (up->port.iobase || up->port.mapbase)
896 uart_add_one_port(drv, &up->port);
897 }
898}
899
900#ifdef CONFIG_SERIAL_TXX9_CONSOLE
901
902static void serial_txx9_console_putchar(struct uart_port *port, int ch)
903{
904 struct uart_txx9_port *up = to_uart_txx9_port(port);
905
906 wait_for_xmitr(up);
907 sio_out(up, TXX9_SITFIFO, ch);
908}
909
910
911
912
913
914
915
916static void
917serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
918{
919 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
920 unsigned int ier, flcr;
921
922
923
924
925 ier = sio_in(up, TXX9_SIDICR);
926 sio_out(up, TXX9_SIDICR, 0);
927
928
929
930 flcr = sio_in(up, TXX9_SIFLCR);
931 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
932 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
933
934 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
935
936
937
938
939
940 wait_for_xmitr(up);
941 sio_out(up, TXX9_SIFLCR, flcr);
942 sio_out(up, TXX9_SIDICR, ier);
943}
944
945static int __init serial_txx9_console_setup(struct console *co, char *options)
946{
947 struct uart_port *port;
948 struct uart_txx9_port *up;
949 int baud = 9600;
950 int bits = 8;
951 int parity = 'n';
952 int flow = 'n';
953
954
955
956
957
958
959 if (co->index >= UART_NR)
960 co->index = 0;
961 up = &serial_txx9_ports[co->index];
962 port = &up->port;
963 if (!port->ops)
964 return -ENODEV;
965
966 serial_txx9_initialize(&up->port);
967
968 if (options)
969 uart_parse_options(options, &baud, &parity, &bits, &flow);
970
971 return uart_set_options(port, co, baud, parity, bits, flow);
972}
973
974static struct uart_driver serial_txx9_reg;
975static struct console serial_txx9_console = {
976 .name = TXX9_TTY_NAME,
977 .write = serial_txx9_console_write,
978 .device = uart_console_device,
979 .setup = serial_txx9_console_setup,
980 .flags = CON_PRINTBUFFER,
981 .index = -1,
982 .data = &serial_txx9_reg,
983};
984
985static int __init serial_txx9_console_init(void)
986{
987 register_console(&serial_txx9_console);
988 return 0;
989}
990console_initcall(serial_txx9_console_init);
991
992#define SERIAL_TXX9_CONSOLE &serial_txx9_console
993#else
994#define SERIAL_TXX9_CONSOLE NULL
995#endif
996
997static struct uart_driver serial_txx9_reg = {
998 .owner = THIS_MODULE,
999 .driver_name = "serial_txx9",
1000 .dev_name = TXX9_TTY_NAME,
1001 .major = TXX9_TTY_MAJOR,
1002 .minor = TXX9_TTY_MINOR_START,
1003 .nr = UART_NR,
1004 .cons = SERIAL_TXX9_CONSOLE,
1005};
1006
1007int __init early_serial_txx9_setup(struct uart_port *port)
1008{
1009 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
1010 return -ENODEV;
1011
1012 serial_txx9_ports[port->line].port = *port;
1013 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
1014 serial_txx9_ports[port->line].port.flags |=
1015 UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1016 return 0;
1017}
1018
1019static DEFINE_MUTEX(serial_txx9_mutex);
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032static int serial_txx9_register_port(struct uart_port *port)
1033{
1034 int i;
1035 struct uart_txx9_port *uart;
1036 int ret = -ENOSPC;
1037
1038 mutex_lock(&serial_txx9_mutex);
1039 for (i = 0; i < UART_NR; i++) {
1040 uart = &serial_txx9_ports[i];
1041 if (uart_match_port(&uart->port, port)) {
1042 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1043 break;
1044 }
1045 }
1046 if (i == UART_NR) {
1047
1048 for (i = 0; i < UART_NR; i++) {
1049 uart = &serial_txx9_ports[i];
1050 if (!(uart->port.iobase || uart->port.mapbase))
1051 break;
1052 }
1053 }
1054 if (i < UART_NR) {
1055 uart->port.iobase = port->iobase;
1056 uart->port.membase = port->membase;
1057 uart->port.irq = port->irq;
1058 uart->port.uartclk = port->uartclk;
1059 uart->port.iotype = port->iotype;
1060 uart->port.flags = port->flags
1061 | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1062 uart->port.mapbase = port->mapbase;
1063 if (port->dev)
1064 uart->port.dev = port->dev;
1065 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1066 if (ret == 0)
1067 ret = uart->port.line;
1068 }
1069 mutex_unlock(&serial_txx9_mutex);
1070 return ret;
1071}
1072
1073
1074
1075
1076
1077
1078
1079
1080static void serial_txx9_unregister_port(int line)
1081{
1082 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1083
1084 mutex_lock(&serial_txx9_mutex);
1085 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1086 uart->port.flags = 0;
1087 uart->port.type = PORT_UNKNOWN;
1088 uart->port.iobase = 0;
1089 uart->port.mapbase = 0;
1090 uart->port.membase = NULL;
1091 uart->port.dev = NULL;
1092 mutex_unlock(&serial_txx9_mutex);
1093}
1094
1095
1096
1097
1098static int serial_txx9_probe(struct platform_device *dev)
1099{
1100 struct uart_port *p = dev->dev.platform_data;
1101 struct uart_port port;
1102 int ret, i;
1103
1104 memset(&port, 0, sizeof(struct uart_port));
1105 for (i = 0; p && p->uartclk != 0; p++, i++) {
1106 port.iobase = p->iobase;
1107 port.membase = p->membase;
1108 port.irq = p->irq;
1109 port.uartclk = p->uartclk;
1110 port.iotype = p->iotype;
1111 port.flags = p->flags;
1112 port.mapbase = p->mapbase;
1113 port.dev = &dev->dev;
1114 ret = serial_txx9_register_port(&port);
1115 if (ret < 0) {
1116 dev_err(&dev->dev, "unable to register port at index %d "
1117 "(IO%lx MEM%llx IRQ%d): %d\n", i,
1118 p->iobase, (unsigned long long)p->mapbase,
1119 p->irq, ret);
1120 }
1121 }
1122 return 0;
1123}
1124
1125
1126
1127
1128static int serial_txx9_remove(struct platform_device *dev)
1129{
1130 int i;
1131
1132 for (i = 0; i < UART_NR; i++) {
1133 struct uart_txx9_port *up = &serial_txx9_ports[i];
1134
1135 if (up->port.dev == &dev->dev)
1136 serial_txx9_unregister_port(i);
1137 }
1138 return 0;
1139}
1140
1141#ifdef CONFIG_PM
1142static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1143{
1144 int i;
1145
1146 for (i = 0; i < UART_NR; i++) {
1147 struct uart_txx9_port *up = &serial_txx9_ports[i];
1148
1149 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1150 uart_suspend_port(&serial_txx9_reg, &up->port);
1151 }
1152
1153 return 0;
1154}
1155
1156static int serial_txx9_resume(struct platform_device *dev)
1157{
1158 int i;
1159
1160 for (i = 0; i < UART_NR; i++) {
1161 struct uart_txx9_port *up = &serial_txx9_ports[i];
1162
1163 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1164 uart_resume_port(&serial_txx9_reg, &up->port);
1165 }
1166
1167 return 0;
1168}
1169#endif
1170
1171static struct platform_driver serial_txx9_plat_driver = {
1172 .probe = serial_txx9_probe,
1173 .remove = serial_txx9_remove,
1174#ifdef CONFIG_PM
1175 .suspend = serial_txx9_suspend,
1176 .resume = serial_txx9_resume,
1177#endif
1178 .driver = {
1179 .name = "serial_txx9",
1180 .owner = THIS_MODULE,
1181 },
1182};
1183
1184#ifdef ENABLE_SERIAL_TXX9_PCI
1185
1186
1187
1188
1189static int
1190pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1191{
1192 struct uart_port port;
1193 int line;
1194 int rc;
1195
1196 rc = pci_enable_device(dev);
1197 if (rc)
1198 return rc;
1199
1200 memset(&port, 0, sizeof(port));
1201 port.ops = &serial_txx9_pops;
1202 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1203 port.uartclk = 66670000;
1204 port.irq = dev->irq;
1205 port.iotype = UPIO_PORT;
1206 port.iobase = pci_resource_start(dev, 1);
1207 port.dev = &dev->dev;
1208 line = serial_txx9_register_port(&port);
1209 if (line < 0) {
1210 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1211 pci_disable_device(dev);
1212 return line;
1213 }
1214 pci_set_drvdata(dev, &serial_txx9_ports[line]);
1215
1216 return 0;
1217}
1218
1219static void pciserial_txx9_remove_one(struct pci_dev *dev)
1220{
1221 struct uart_txx9_port *up = pci_get_drvdata(dev);
1222
1223 pci_set_drvdata(dev, NULL);
1224
1225 if (up) {
1226 serial_txx9_unregister_port(up->port.line);
1227 pci_disable_device(dev);
1228 }
1229}
1230
1231#ifdef CONFIG_PM
1232static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1233{
1234 struct uart_txx9_port *up = pci_get_drvdata(dev);
1235
1236 if (up)
1237 uart_suspend_port(&serial_txx9_reg, &up->port);
1238 pci_save_state(dev);
1239 pci_set_power_state(dev, pci_choose_state(dev, state));
1240 return 0;
1241}
1242
1243static int pciserial_txx9_resume_one(struct pci_dev *dev)
1244{
1245 struct uart_txx9_port *up = pci_get_drvdata(dev);
1246
1247 pci_set_power_state(dev, PCI_D0);
1248 pci_restore_state(dev);
1249 if (up)
1250 uart_resume_port(&serial_txx9_reg, &up->port);
1251 return 0;
1252}
1253#endif
1254
1255static const struct pci_device_id serial_txx9_pci_tbl[] = {
1256 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1257 { 0, }
1258};
1259
1260static struct pci_driver serial_txx9_pci_driver = {
1261 .name = "serial_txx9",
1262 .probe = pciserial_txx9_init_one,
1263 .remove = pciserial_txx9_remove_one,
1264#ifdef CONFIG_PM
1265 .suspend = pciserial_txx9_suspend_one,
1266 .resume = pciserial_txx9_resume_one,
1267#endif
1268 .id_table = serial_txx9_pci_tbl,
1269};
1270
1271MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1272#endif
1273
1274static struct platform_device *serial_txx9_plat_devs;
1275
1276static int __init serial_txx9_init(void)
1277{
1278 int ret;
1279
1280 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1281
1282 ret = uart_register_driver(&serial_txx9_reg);
1283 if (ret)
1284 goto out;
1285
1286 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1287 if (!serial_txx9_plat_devs) {
1288 ret = -ENOMEM;
1289 goto unreg_uart_drv;
1290 }
1291
1292 ret = platform_device_add(serial_txx9_plat_devs);
1293 if (ret)
1294 goto put_dev;
1295
1296 serial_txx9_register_ports(&serial_txx9_reg,
1297 &serial_txx9_plat_devs->dev);
1298
1299 ret = platform_driver_register(&serial_txx9_plat_driver);
1300 if (ret)
1301 goto del_dev;
1302
1303#ifdef ENABLE_SERIAL_TXX9_PCI
1304 ret = pci_register_driver(&serial_txx9_pci_driver);
1305#endif
1306 if (ret == 0)
1307 goto out;
1308
1309 del_dev:
1310 platform_device_del(serial_txx9_plat_devs);
1311 put_dev:
1312 platform_device_put(serial_txx9_plat_devs);
1313 unreg_uart_drv:
1314 uart_unregister_driver(&serial_txx9_reg);
1315 out:
1316 return ret;
1317}
1318
1319static void __exit serial_txx9_exit(void)
1320{
1321 int i;
1322
1323#ifdef ENABLE_SERIAL_TXX9_PCI
1324 pci_unregister_driver(&serial_txx9_pci_driver);
1325#endif
1326 platform_driver_unregister(&serial_txx9_plat_driver);
1327 platform_device_unregister(serial_txx9_plat_devs);
1328 for (i = 0; i < UART_NR; i++) {
1329 struct uart_txx9_port *up = &serial_txx9_ports[i];
1330 if (up->port.iobase || up->port.mapbase)
1331 uart_remove_one_port(&serial_txx9_reg, &up->port);
1332 }
1333
1334 uart_unregister_driver(&serial_txx9_reg);
1335}
1336
1337module_init(serial_txx9_init);
1338module_exit(serial_txx9_exit);
1339
1340MODULE_LICENSE("GPL");
1341MODULE_DESCRIPTION("TX39/49 serial driver");
1342
1343MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
1344
