1#ifndef __ALPHA_T2__H__
2#define __ALPHA_T2__H__
3
4
5#define T2_ONE_HAE_WINDOW 1
6
7#include <linux/types.h>
8#include <linux/spinlock.h>
9#include <asm/compiler.h>
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23
24#define T2_MEM_R1_MASK 0x07ffffff
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27
28#define _GAMMA_BIAS 0x8000000000UL
29
30#if defined(CONFIG_ALPHA_GENERIC)
31#define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias
32#elif defined(CONFIG_ALPHA_GAMMA)
33#define GAMMA_BIAS _GAMMA_BIAS
34#else
35#define GAMMA_BIAS 0
36#endif
37
38
39
40
41#define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
42#define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
43#define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
44#define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
45
46#define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
47#define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
48#define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
49#define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
50#define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
51#define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
52#define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
53#define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
54#define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
55#define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
56#define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
57#define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
58#define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
59#define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
60#define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
61#define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
62#define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
63#define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
64#define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
65#define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
66
67
68#define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
69#define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
70#define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
71
72#define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
73#define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
74#define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
75#define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
76#define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
77#define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
78#define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
79#define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
80
81#define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
82#define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
83#define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
84
85#define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
86#define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
87#define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
88#define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
89
90#ifndef T2_ONE_HAE_WINDOW
91#define T2_HAE_ADDRESS T2_HAE_1
92#endif
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127#define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
128#define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
129#define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
130#define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
131
132#define T2_CPUn_BASE(n) (T2_CPU0_BASE + (((n)&3) * 0x001000000L))
133
134#define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
135#define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
136#define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
137#define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
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148
149struct sable_cpu_csr {
150 unsigned long bcc; long fill_00[3];
151 unsigned long bcce; long fill_01[3];
152 unsigned long bccea; long fill_02[3];
153 unsigned long bcue; long fill_03[3];
154 unsigned long bcuea; long fill_04[3];
155 unsigned long dter; long fill_05[3];
156 unsigned long cbctl; long fill_06[3];
157 unsigned long cbe; long fill_07[3];
158 unsigned long cbeal; long fill_08[3];
159 unsigned long cbeah; long fill_09[3];
160 unsigned long pmbx; long fill_10[3];
161 unsigned long ipir; long fill_11[3];
162 unsigned long sic; long fill_12[3];
163 unsigned long adlk; long fill_13[3];
164 unsigned long madrl; long fill_14[3];
165 unsigned long rev; long fill_15[3];
166};
167
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170
171struct el_t2_frame_header {
172 unsigned int elcf_fid;
173 unsigned int elcf_size;
174};
175
176struct el_t2_procdata_mcheck {
177 unsigned long elfmc_paltemp[32];
178
179 unsigned long elfmc_exc_addr;
180 unsigned long elfmc_exc_sum;
181 unsigned long elfmc_exc_mask;
182 unsigned long elfmc_iccsr;
183 unsigned long elfmc_pal_base;
184 unsigned long elfmc_hier;
185 unsigned long elfmc_hirr;
186 unsigned long elfmc_mm_csr;
187 unsigned long elfmc_dc_stat;
188 unsigned long elfmc_dc_addr;
189 unsigned long elfmc_abox_ctl;
190 unsigned long elfmc_biu_stat;
191 unsigned long elfmc_biu_addr;
192 unsigned long elfmc_biu_ctl;
193 unsigned long elfmc_fill_syndrome;
194 unsigned long elfmc_fill_addr;
195 unsigned long elfmc_va;
196 unsigned long elfmc_bc_tag;
197};
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202
203struct el_t2_logout_header {
204 unsigned int elfl_size;
205 unsigned int elfl_sbz1:31;
206 unsigned int elfl_retry:1;
207 unsigned int elfl_procoffset;
208 unsigned int elfl_sysoffset;
209 unsigned int elfl_error_type;
210 unsigned int elfl_frame_rev;
211};
212struct el_t2_sysdata_mcheck {
213 unsigned long elcmc_bcc;
214 unsigned long elcmc_bcce;
215 unsigned long elcmc_bccea;
216 unsigned long elcmc_bcue;
217 unsigned long elcmc_bcuea;
218 unsigned long elcmc_dter;
219 unsigned long elcmc_cbctl;
220 unsigned long elcmc_cbe;
221 unsigned long elcmc_cbeal;
222 unsigned long elcmc_cbeah;
223 unsigned long elcmc_pmbx;
224 unsigned long elcmc_ipir;
225 unsigned long elcmc_sic;
226 unsigned long elcmc_adlk;
227 unsigned long elcmc_madrl;
228 unsigned long elcmc_crrev4;
229};
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233
234struct el_t2_data_memory {
235 struct el_t2_frame_header elcm_hdr;
236 unsigned int elcm_module;
237 unsigned int elcm_res04;
238 unsigned long elcm_merr;
239 unsigned long elcm_mcmd1;
240 unsigned long elcm_mcmd2;
241 unsigned long elcm_mconf;
242 unsigned long elcm_medc1;
243 unsigned long elcm_medc2;
244 unsigned long elcm_medcc;
245 unsigned long elcm_msctl;
246 unsigned long elcm_mref;
247 unsigned long elcm_filter;
248};
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253
254struct el_t2_data_other_cpu {
255 short elco_cpuid;
256 short elco_res02[3];
257 unsigned long elco_bcc;
258 unsigned long elco_bcce;
259 unsigned long elco_bccea;
260 unsigned long elco_bcue;
261 unsigned long elco_bcuea;
262 unsigned long elco_dter;
263 unsigned long elco_cbctl;
264 unsigned long elco_cbe;
265 unsigned long elco_cbeal;
266 unsigned long elco_cbeah;
267 unsigned long elco_pmbx;
268 unsigned long elco_ipir;
269 unsigned long elco_sic;
270 unsigned long elco_adlk;
271 unsigned long elco_madrl;
272 unsigned long elco_crrev4;
273};
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277
278struct el_t2_data_t2{
279 struct el_t2_frame_header elct_hdr;
280 unsigned long elct_iocsr;
281 unsigned long elct_cerr1;
282 unsigned long elct_cerr2;
283 unsigned long elct_cerr3;
284 unsigned long elct_perr1;
285 unsigned long elct_perr2;
286 unsigned long elct_hae0_1;
287 unsigned long elct_hae0_2;
288 unsigned long elct_hbase;
289 unsigned long elct_wbase1;
290 unsigned long elct_wmask1;
291 unsigned long elct_tbase1;
292 unsigned long elct_wbase2;
293 unsigned long elct_wmask2;
294 unsigned long elct_tbase2;
295 unsigned long elct_tdr0;
296 unsigned long elct_tdr1;
297 unsigned long elct_tdr2;
298 unsigned long elct_tdr3;
299 unsigned long elct_tdr4;
300 unsigned long elct_tdr5;
301 unsigned long elct_tdr6;
302 unsigned long elct_tdr7;
303};
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307
308struct el_t2_data_corrected {
309 unsigned long elcpb_biu_stat;
310 unsigned long elcpb_biu_addr;
311 unsigned long elcpb_biu_ctl;
312 unsigned long elcpb_fill_syndrome;
313 unsigned long elcpb_fill_addr;
314 unsigned long elcpb_bc_tag;
315};
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320
321struct el_t2_frame_mcheck {
322 struct el_t2_frame_header elfmc_header;
323 struct el_t2_logout_header elfmc_hdr;
324 struct el_t2_procdata_mcheck elfmc_procdata;
325 struct el_t2_sysdata_mcheck elfmc_sysdata;
326 struct el_t2_data_t2 elfmc_t2data;
327 struct el_t2_data_memory elfmc_memdata[4];
328 struct el_t2_frame_header elfmc_footer;
329};
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334
335struct el_t2_frame_corrected {
336 struct el_t2_frame_header elfcc_header;
337 struct el_t2_logout_header elfcc_hdr;
338 struct el_t2_data_corrected elfcc_procdata;
339
340
341 struct el_t2_frame_header elfcc_footer;
342};
343
344
345#ifdef __KERNEL__
346
347#ifndef __EXTERN_INLINE
348#define __EXTERN_INLINE extern inline
349#define __IO_EXTERN_INLINE
350#endif
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359
360#define vip volatile int *
361#define vuip volatile unsigned int *
362
363extern inline u8 t2_inb(unsigned long addr)
364{
365 long result = *(vip) ((addr << 5) + T2_IO + 0x00);
366 return __kernel_extbl(result, addr & 3);
367}
368
369extern inline void t2_outb(u8 b, unsigned long addr)
370{
371 unsigned long w;
372
373 w = __kernel_insbl(b, addr & 3);
374 *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
375 mb();
376}
377
378extern inline u16 t2_inw(unsigned long addr)
379{
380 long result = *(vip) ((addr << 5) + T2_IO + 0x08);
381 return __kernel_extwl(result, addr & 3);
382}
383
384extern inline void t2_outw(u16 b, unsigned long addr)
385{
386 unsigned long w;
387
388 w = __kernel_inswl(b, addr & 3);
389 *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
390 mb();
391}
392
393extern inline u32 t2_inl(unsigned long addr)
394{
395 return *(vuip) ((addr << 5) + T2_IO + 0x18);
396}
397
398extern inline void t2_outl(u32 b, unsigned long addr)
399{
400 *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
401 mb();
402}
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436#ifdef T2_ONE_HAE_WINDOW
437#define t2_set_hae
438#else
439#define t2_set_hae { \
440 unsigned long msb = addr >> 27; \
441 addr &= T2_MEM_R1_MASK; \
442 set_hae(msb); \
443}
444#endif
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451
452__EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
453{
454 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
455 unsigned long result;
456
457 t2_set_hae;
458
459 result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
460 return __kernel_extbl(result, addr & 3);
461}
462
463__EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
464{
465 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
466 unsigned long result;
467
468 t2_set_hae;
469
470 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
471 return __kernel_extwl(result, addr & 3);
472}
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477
478__EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
479{
480 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
481 unsigned long result;
482
483 t2_set_hae;
484
485 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
486 return result & 0xffffffffUL;
487}
488
489__EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
490{
491 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
492 unsigned long r0, r1, work;
493
494 t2_set_hae;
495
496 work = (addr << 5) + T2_SPARSE_MEM + 0x18;
497 r0 = *(vuip)(work);
498 r1 = *(vuip)(work + (4 << 5));
499 return r1 << 32 | r0;
500}
501
502__EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
503{
504 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
505 unsigned long w;
506
507 t2_set_hae;
508
509 w = __kernel_insbl(b, addr & 3);
510 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
511}
512
513__EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
514{
515 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
516 unsigned long w;
517
518 t2_set_hae;
519
520 w = __kernel_inswl(b, addr & 3);
521 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
522}
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527
528__EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
529{
530 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
531
532 t2_set_hae;
533
534 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
535}
536
537__EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
538{
539 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
540 unsigned long work;
541
542 t2_set_hae;
543
544 work = (addr << 5) + T2_SPARSE_MEM + 0x18;
545 *(vuip)work = b;
546 *(vuip)(work + (4 << 5)) = b >> 32;
547}
548
549__EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
550{
551 return (void __iomem *)(addr + T2_IO);
552}
553
554__EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr,
555 unsigned long size)
556{
557 return (void __iomem *)(addr + T2_DENSE_MEM);
558}
559
560__EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
561{
562 return (long)addr >= 0;
563}
564
565__EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
566{
567 return (unsigned long)addr >= T2_DENSE_MEM;
568}
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572
573#define IOPORT(OS, NS) \
574__EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr) \
575{ \
576 if (t2_is_mmio(xaddr)) \
577 return t2_read##OS(xaddr); \
578 else \
579 return t2_in##OS((unsigned long)xaddr - T2_IO); \
580} \
581__EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \
582{ \
583 if (t2_is_mmio(xaddr)) \
584 t2_write##OS(b, xaddr); \
585 else \
586 t2_out##OS(b, (unsigned long)xaddr - T2_IO); \
587}
588
589IOPORT(b, 8)
590IOPORT(w, 16)
591IOPORT(l, 32)
592
593#undef IOPORT
594
595#undef vip
596#undef vuip
597
598#undef __IO_PREFIX
599#define __IO_PREFIX t2
600#define t2_trivial_rw_bw 0
601#define t2_trivial_rw_lq 0
602#define t2_trivial_io_bw 0
603#define t2_trivial_io_lq 0
604#define t2_trivial_iounmap 1
605#include <asm/io_trivial.h>
606
607#ifdef __IO_EXTERN_INLINE
608#undef __EXTERN_INLINE
609#undef __IO_EXTERN_INLINE
610#endif
611
612#endif
613
614#endif
615