LXR linux/arch/mips/include/uapi/asm/inst.h

   1/*
   2 * Format of an instruction in memory.
   3 *
   4 * This file is subject to the terms and conditions of the GNU General Public
   5 * License.  See the file "COPYING" in the main directory of this archive
   6 * for more details.
   7 *
   8 * Copyright (C) 1996, 2000 by Ralf Baechle
   9 * Copyright (C) 2006 by Thiemo Seufer
  10 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  11 * Copyright (C) 2014 Imagination Technologies Ltd.
  12 */
  13#ifndef _UAPI_ASM_INST_H
  14#define _UAPI_ASM_INST_H
  15
  16#include <asm/bitfield.h>
  17
  18/*
  19 * Major opcodes; before MIPS IV cop1x was called cop3.
  20 */
  21enum major_op {
  22        spec_op, bcond_op, j_op, jal_op,
  23        beq_op, bne_op, blez_op, bgtz_op,
  24        addi_op, cbcond0_op = addi_op, addiu_op, slti_op, sltiu_op,
  25        andi_op, ori_op, xori_op, lui_op,
  26        cop0_op, cop1_op, cop2_op, cop1x_op,
  27        beql_op, bnel_op, blezl_op, bgtzl_op,
  28        daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
  29        spec2_op, jalx_op, mdmx_op, spec3_op,
  30        lb_op, lh_op, lwl_op, lw_op,
  31        lbu_op, lhu_op, lwr_op, lwu_op,
  32        sb_op, sh_op, swl_op, sw_op,
  33        sdl_op, sdr_op, swr_op, cache_op,
  34        ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
  35        lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
  36        sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
  37        scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
  38};
  39
  40/*
  41 * func field of spec opcode.
  42 */
  43enum spec_op {
  44        sll_op, movc_op, srl_op, sra_op,
  45        sllv_op, pmon_op, srlv_op, srav_op,
  46        jr_op, jalr_op, movz_op, movn_op,
  47        syscall_op, break_op, spim_op, sync_op,
  48        mfhi_op, mthi_op, mflo_op, mtlo_op,
  49        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  50        mult_op, multu_op, div_op, divu_op,
  51        dmult_op, dmultu_op, ddiv_op, ddivu_op,
  52        add_op, addu_op, sub_op, subu_op,
  53        and_op, or_op, xor_op, nor_op,
  54        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  55        dadd_op, daddu_op, dsub_op, dsubu_op,
  56        tge_op, tgeu_op, tlt_op, tltu_op,
  57        teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  58        dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  59        dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  60};
  61
  62/*
  63 * func field of spec2 opcode.
  64 */
  65enum spec2_op {
  66        madd_op, maddu_op, mul_op, spec2_3_unused_op,
  67        msub_op, msubu_op, /* more unused ops */
  68        clz_op = 0x20, clo_op,
  69        dclz_op = 0x24, dclo_op,
  70        sdbpp_op = 0x3f
  71};
  72
  73/*
  74 * func field of spec3 opcode.
  75 */
  76enum spec3_op {
  77        ext_op, dextm_op, dextu_op, dext_op,
  78        ins_op, dinsm_op, dinsu_op, dins_op,
  79        yield_op  = 0x09, lx_op     = 0x0a,
  80        lwle_op   = 0x19, lwre_op   = 0x1a,
  81        cachee_op = 0x1b, sbe_op    = 0x1c,
  82        she_op    = 0x1d, sce_op    = 0x1e,
  83        swe_op    = 0x1f, bshfl_op  = 0x20,
  84        swle_op   = 0x21, swre_op   = 0x22,
  85        prefe_op  = 0x23, dbshfl_op = 0x24,
  86        cache6_op = 0x25, sc6_op    = 0x26,
  87        scd6_op   = 0x27, lbue_op   = 0x28,
  88        lhue_op   = 0x29, lbe_op    = 0x2c,
  89        lhe_op    = 0x2d, lle_op    = 0x2e,
  90        lwe_op    = 0x2f, pref6_op  = 0x35,
  91        ll6_op    = 0x36, lld6_op   = 0x37,
  92        rdhwr_op  = 0x3b
  93};
  94
  95/*
  96 * rt field of bcond opcodes.
  97 */
  98enum rt_op {
  99        bltz_op, bgez_op, bltzl_op, bgezl_op,
 100        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
 101        tgei_op, tgeiu_op, tlti_op, tltiu_op,
 102        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
 103        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
 104        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
 105        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
 106        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
 107};
 108
 109/*
 110 * rs field of cop opcodes.
 111 */
 112enum cop_op {
 113        mfc_op        = 0x00, dmfc_op       = 0x01,
 114        cfc_op        = 0x02, mfhc0_op      = 0x02,
 115        mfhc_op       = 0x03, mtc_op        = 0x04,
 116        dmtc_op       = 0x05, ctc_op        = 0x06,
 117        mthc0_op      = 0x06, mthc_op       = 0x07,
 118        bc_op         = 0x08, bc1eqz_op     = 0x09,
 119        bc1nez_op     = 0x0d, cop_op        = 0x10,
 120        copm_op       = 0x18
 121};
 122
 123/*
 124 * rt field of cop.bc_op opcodes
 125 */
 126enum bcop_op {
 127        bcf_op, bct_op, bcfl_op, bctl_op
 128};
 129
 130/*
 131 * func field of cop0 coi opcodes.
 132 */
 133enum cop0_coi_func {
 134        tlbr_op       = 0x01, tlbwi_op      = 0x02,
 135        tlbwr_op      = 0x06, tlbp_op       = 0x08,
 136        rfe_op        = 0x10, eret_op       = 0x18,
 137        wait_op       = 0x20,
 138};
 139
 140/*
 141 * func field of cop0 com opcodes.
 142 */
 143enum cop0_com_func {
 144        tlbr1_op      = 0x01, tlbw_op       = 0x02,
 145        tlbp1_op      = 0x08, dctr_op       = 0x09,
 146        dctw_op       = 0x0a
 147};
 148
 149/*
 150 * fmt field of cop1 opcodes.
 151 */
 152enum cop1_fmt {
 153        s_fmt, d_fmt, e_fmt, q_fmt,
 154        w_fmt, l_fmt
 155};
 156
 157/*
 158 * func field of cop1 instructions using d, s or w format.
 159 */
 160enum cop1_sdw_func {
 161        fadd_op      =  0x00, fsub_op      =  0x01,
 162        fmul_op      =  0x02, fdiv_op      =  0x03,
 163        fsqrt_op     =  0x04, fabs_op      =  0x05,
 164        fmov_op      =  0x06, fneg_op      =  0x07,
 165        froundl_op   =  0x08, ftruncl_op   =  0x09,
 166        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 167        fround_op    =  0x0c, ftrunc_op    =  0x0d,
 168        fceil_op     =  0x0e, ffloor_op    =  0x0f,
 169        fmovc_op     =  0x11, fmovz_op     =  0x12,
 170        fmovn_op     =  0x13, frecip_op    =  0x15,
 171        frsqrt_op    =  0x16, fcvts_op     =  0x20,
 172        fcvtd_op     =  0x21, fcvte_op     =  0x22,
 173        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 174        fcmp_op      =  0x30
 175};
 176
 177/*
 178 * func field of cop1x opcodes (MIPS IV).
 179 */
 180enum cop1x_func {
 181        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 182        swxc1_op     =  0x08, sdxc1_op     =  0x09,
 183        pfetch_op    =  0x0f, madd_s_op    =  0x20,
 184        madd_d_op    =  0x21, madd_e_op    =  0x22,
 185        msub_s_op    =  0x28, msub_d_op    =  0x29,
 186        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 187        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 188        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 189        nmsub_e_op   =  0x3a
 190};
 191
 192/*
 193 * func field for mad opcodes (MIPS IV).
 194 */
 195enum mad_func {
 196        madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 197        nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 198};
 199
 200/*
 201 * func field for special3 lx opcodes (Cavium Octeon).
 202 */
 203enum lx_func {
 204        lwx_op  = 0x00,
 205        lhx_op  = 0x04,
 206        lbux_op = 0x06,
 207        ldx_op  = 0x08,
 208        lwux_op = 0x10,
 209        lhux_op = 0x14,
 210        lbx_op  = 0x16,
 211};
 212
 213/*
 214 * BSHFL opcodes
 215 */
 216enum bshfl_func {
 217        wsbh_op = 0x2,
 218        dshd_op = 0x5,
 219        seb_op  = 0x10,
 220        seh_op  = 0x18,
 221};
 222
 223/*
 224 * (microMIPS) Major opcodes.
 225 */
 226enum mm_major_op {
 227        mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 228        mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 229        mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 230        mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 231        mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 232        mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
 233        mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 234        mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
 235        mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 236        mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 237        mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
 238        mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 239        mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
 240        mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 241        mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
 242        mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
 243};
 244
 245/*
 246 * (microMIPS) POOL32I minor opcodes.
 247 */
 248enum mm_32i_minor_op {
 249        mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 250        mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 251        mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 252        mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
 253        mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
 254        mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
 255        mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
 256        mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
 257        mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
 258};
 259
 260/*
 261 * (microMIPS) POOL32A minor opcodes.
 262 */
 263enum mm_32a_minor_op {
 264        mm_sll32_op = 0x000,
 265        mm_ins_op = 0x00c,
 266        mm_sllv32_op = 0x010,
 267        mm_ext_op = 0x02c,
 268        mm_pool32axf_op = 0x03c,
 269        mm_srl32_op = 0x040,
 270        mm_sra_op = 0x080,
 271        mm_srlv32_op = 0x090,
 272        mm_rotr_op = 0x0c0,
 273        mm_lwxs_op = 0x118,
 274        mm_addu32_op = 0x150,
 275        mm_subu32_op = 0x1d0,
 276        mm_wsbh_op = 0x1ec,
 277        mm_mul_op = 0x210,
 278        mm_and_op = 0x250,
 279        mm_or32_op = 0x290,
 280        mm_xor32_op = 0x310,
 281        mm_slt_op = 0x350,
 282        mm_sltu_op = 0x390,
 283};
 284
 285/*
 286 * (microMIPS) POOL32B functions.
 287 */
 288enum mm_32b_func {
 289        mm_lwc2_func = 0x0,
 290        mm_lwp_func = 0x1,
 291        mm_ldc2_func = 0x2,
 292        mm_ldp_func = 0x4,
 293        mm_lwm32_func = 0x5,
 294        mm_cache_func = 0x6,
 295        mm_ldm_func = 0x7,
 296        mm_swc2_func = 0x8,
 297        mm_swp_func = 0x9,
 298        mm_sdc2_func = 0xa,
 299        mm_sdp_func = 0xc,
 300        mm_swm32_func = 0xd,
 301        mm_sdm_func = 0xf,
 302};
 303
 304/*
 305 * (microMIPS) POOL32C functions.
 306 */
 307enum mm_32c_func {
 308        mm_pref_func = 0x2,
 309        mm_ll_func = 0x3,
 310        mm_swr_func = 0x9,
 311        mm_sc_func = 0xb,
 312        mm_lwu_func = 0xe,
 313};
 314
 315/*
 316 * (microMIPS) POOL32AXF minor opcodes.
 317 */
 318enum mm_32axf_minor_op {
 319        mm_mfc0_op = 0x003,
 320        mm_mtc0_op = 0x00b,
 321        mm_tlbp_op = 0x00d,
 322        mm_mfhi32_op = 0x035,
 323        mm_jalr_op = 0x03c,
 324        mm_tlbr_op = 0x04d,
 325        mm_mflo32_op = 0x075,
 326        mm_jalrhb_op = 0x07c,
 327        mm_tlbwi_op = 0x08d,
 328        mm_tlbwr_op = 0x0cd,
 329        mm_jalrs_op = 0x13c,
 330        mm_jalrshb_op = 0x17c,
 331        mm_sync_op = 0x1ad,
 332        mm_syscall_op = 0x22d,
 333        mm_wait_op = 0x24d,
 334        mm_eret_op = 0x3cd,
 335        mm_divu_op = 0x5dc,
 336};
 337
 338/*
 339 * (microMIPS) POOL32F minor opcodes.
 340 */
 341enum mm_32f_minor_op {
 342        mm_32f_00_op = 0x00,
 343        mm_32f_01_op = 0x01,
 344        mm_32f_02_op = 0x02,
 345        mm_32f_10_op = 0x08,
 346        mm_32f_11_op = 0x09,
 347        mm_32f_12_op = 0x0a,
 348        mm_32f_20_op = 0x10,
 349        mm_32f_30_op = 0x18,
 350        mm_32f_40_op = 0x20,
 351        mm_32f_41_op = 0x21,
 352        mm_32f_42_op = 0x22,
 353        mm_32f_50_op = 0x28,
 354        mm_32f_51_op = 0x29,
 355        mm_32f_52_op = 0x2a,
 356        mm_32f_60_op = 0x30,
 357        mm_32f_70_op = 0x38,
 358        mm_32f_73_op = 0x3b,
 359        mm_32f_74_op = 0x3c,
 360};
 361
 362/*
 363 * (microMIPS) POOL32F secondary minor opcodes.
 364 */
 365enum mm_32f_10_minor_op {
 366        mm_lwxc1_op = 0x1,
 367        mm_swxc1_op,
 368        mm_ldxc1_op,
 369        mm_sdxc1_op,
 370        mm_luxc1_op,
 371        mm_suxc1_op,
 372};
 373
 374enum mm_32f_func {
 375        mm_lwxc1_func = 0x048,
 376        mm_swxc1_func = 0x088,
 377        mm_ldxc1_func = 0x0c8,
 378        mm_sdxc1_func = 0x108,
 379};
 380
 381/*
 382 * (microMIPS) POOL32F secondary minor opcodes.
 383 */
 384enum mm_32f_40_minor_op {
 385        mm_fmovf_op,
 386        mm_fmovt_op,
 387};
 388
 389/*
 390 * (microMIPS) POOL32F secondary minor opcodes.
 391 */
 392enum mm_32f_60_minor_op {
 393        mm_fadd_op,
 394        mm_fsub_op,
 395        mm_fmul_op,
 396        mm_fdiv_op,
 397};
 398
 399/*
 400 * (microMIPS) POOL32F secondary minor opcodes.
 401 */
 402enum mm_32f_70_minor_op {
 403        mm_fmovn_op,
 404        mm_fmovz_op,
 405};
 406
 407/*
 408 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
 409 */
 410enum mm_32f_73_minor_op {
 411        mm_fmov0_op = 0x01,
 412        mm_fcvtl_op = 0x04,
 413        mm_movf0_op = 0x05,
 414        mm_frsqrt_op = 0x08,
 415        mm_ffloorl_op = 0x0c,
 416        mm_fabs0_op = 0x0d,
 417        mm_fcvtw_op = 0x24,
 418        mm_movt0_op = 0x25,
 419        mm_fsqrt_op = 0x28,
 420        mm_ffloorw_op = 0x2c,
 421        mm_fneg0_op = 0x2d,
 422        mm_cfc1_op = 0x40,
 423        mm_frecip_op = 0x48,
 424        mm_fceill_op = 0x4c,
 425        mm_fcvtd0_op = 0x4d,
 426        mm_ctc1_op = 0x60,
 427        mm_fceilw_op = 0x6c,
 428        mm_fcvts0_op = 0x6d,
 429        mm_mfc1_op = 0x80,
 430        mm_fmov1_op = 0x81,
 431        mm_movf1_op = 0x85,
 432        mm_ftruncl_op = 0x8c,
 433        mm_fabs1_op = 0x8d,
 434        mm_mtc1_op = 0xa0,
 435        mm_movt1_op = 0xa5,
 436        mm_ftruncw_op = 0xac,
 437        mm_fneg1_op = 0xad,
 438        mm_mfhc1_op = 0xc0,
 439        mm_froundl_op = 0xcc,
 440        mm_fcvtd1_op = 0xcd,
 441        mm_mthc1_op = 0xe0,
 442        mm_froundw_op = 0xec,
 443        mm_fcvts1_op = 0xed,
 444};
 445
 446/*
 447 * (microMIPS) POOL16C minor opcodes.
 448 */
 449enum mm_16c_minor_op {
 450        mm_lwm16_op = 0x04,
 451        mm_swm16_op = 0x05,
 452        mm_jr16_op = 0x0c,
 453        mm_jrc_op = 0x0d,
 454        mm_jalr16_op = 0x0e,
 455        mm_jalrs16_op = 0x0f,
 456        mm_jraddiusp_op = 0x18,
 457};
 458
 459/*
 460 * (microMIPS) POOL16D minor opcodes.
 461 */
 462enum mm_16d_minor_op {
 463        mm_addius5_func,
 464        mm_addiusp_func,
 465};
 466
 467/*
 468 * (MIPS16e) opcodes.
 469 */
 470enum MIPS16e_ops {
 471        MIPS16e_jal_op = 003,
 472        MIPS16e_ld_op = 007,
 473        MIPS16e_i8_op = 014,
 474        MIPS16e_sd_op = 017,
 475        MIPS16e_lb_op = 020,
 476        MIPS16e_lh_op = 021,
 477        MIPS16e_lwsp_op = 022,
 478        MIPS16e_lw_op = 023,
 479        MIPS16e_lbu_op = 024,
 480        MIPS16e_lhu_op = 025,
 481        MIPS16e_lwpc_op = 026,
 482        MIPS16e_lwu_op = 027,
 483        MIPS16e_sb_op = 030,
 484        MIPS16e_sh_op = 031,
 485        MIPS16e_swsp_op = 032,
 486        MIPS16e_sw_op = 033,
 487        MIPS16e_rr_op = 035,
 488        MIPS16e_extend_op = 036,
 489        MIPS16e_i64_op = 037,
 490};
 491
 492enum MIPS16e_i64_func {
 493        MIPS16e_ldsp_func,
 494        MIPS16e_sdsp_func,
 495        MIPS16e_sdrasp_func,
 496        MIPS16e_dadjsp_func,
 497        MIPS16e_ldpc_func,
 498};
 499
 500enum MIPS16e_rr_func {
 501        MIPS16e_jr_func,
 502};
 503
 504enum MIPS6e_i8_func {
 505        MIPS16e_swrasp_func = 02,
 506};
 507
 508/*
 509 * (microMIPS & MIPS16e) NOP instruction.
 510 */
 511#define MM_NOP16        0x0c00
 512
 513struct j_format {
 514        __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
 515        __BITFIELD_FIELD(unsigned int target : 26,
 516        ;))
 517};
 518
 519struct i_format {                       /* signed immediate format */
 520        __BITFIELD_FIELD(unsigned int opcode : 6,
 521        __BITFIELD_FIELD(unsigned int rs : 5,
 522        __BITFIELD_FIELD(unsigned int rt : 5,
 523        __BITFIELD_FIELD(signed int simmediate : 16,
 524        ;))))
 525};
 526
 527struct u_format {                       /* unsigned immediate format */
 528        __BITFIELD_FIELD(unsigned int opcode : 6,
 529        __BITFIELD_FIELD(unsigned int rs : 5,
 530        __BITFIELD_FIELD(unsigned int rt : 5,
 531        __BITFIELD_FIELD(unsigned int uimmediate : 16,
 532        ;))))
 533};
 534
 535struct c_format {                       /* Cache (>= R6000) format */
 536        __BITFIELD_FIELD(unsigned int opcode : 6,
 537        __BITFIELD_FIELD(unsigned int rs : 5,
 538        __BITFIELD_FIELD(unsigned int c_op : 3,
 539        __BITFIELD_FIELD(unsigned int cache : 2,
 540        __BITFIELD_FIELD(unsigned int simmediate : 16,
 541        ;)))))
 542};
 543
 544struct r_format {                       /* Register format */
 545        __BITFIELD_FIELD(unsigned int opcode : 6,
 546        __BITFIELD_FIELD(unsigned int rs : 5,
 547        __BITFIELD_FIELD(unsigned int rt : 5,
 548        __BITFIELD_FIELD(unsigned int rd : 5,
 549        __BITFIELD_FIELD(unsigned int re : 5,
 550        __BITFIELD_FIELD(unsigned int func : 6,
 551        ;))))))
 552};
 553
 554struct p_format {               /* Performance counter format (R10000) */
 555        __BITFIELD_FIELD(unsigned int opcode : 6,
 556        __BITFIELD_FIELD(unsigned int rs : 5,
 557        __BITFIELD_FIELD(unsigned int rt : 5,
 558        __BITFIELD_FIELD(unsigned int rd : 5,
 559        __BITFIELD_FIELD(unsigned int re : 5,
 560        __BITFIELD_FIELD(unsigned int func : 6,
 561        ;))))))
 562};
 563
 564struct f_format {                       /* FPU register format */
 565        __BITFIELD_FIELD(unsigned int opcode : 6,
 566        __BITFIELD_FIELD(unsigned int : 1,
 567        __BITFIELD_FIELD(unsigned int fmt : 4,
 568        __BITFIELD_FIELD(unsigned int rt : 5,
 569        __BITFIELD_FIELD(unsigned int rd : 5,
 570        __BITFIELD_FIELD(unsigned int re : 5,
 571        __BITFIELD_FIELD(unsigned int func : 6,
 572        ;)))))))
 573};
 574
 575struct ma_format {              /* FPU multiply and add format (MIPS IV) */
 576        __BITFIELD_FIELD(unsigned int opcode : 6,
 577        __BITFIELD_FIELD(unsigned int fr : 5,
 578        __BITFIELD_FIELD(unsigned int ft : 5,
 579        __BITFIELD_FIELD(unsigned int fs : 5,
 580        __BITFIELD_FIELD(unsigned int fd : 5,
 581        __BITFIELD_FIELD(unsigned int func : 4,
 582        __BITFIELD_FIELD(unsigned int fmt : 2,
 583        ;)))))))
 584};
 585
 586struct b_format {                       /* BREAK and SYSCALL */
 587        __BITFIELD_FIELD(unsigned int opcode : 6,
 588        __BITFIELD_FIELD(unsigned int code : 20,
 589        __BITFIELD_FIELD(unsigned int func : 6,
 590        ;)))
 591};
 592
 593struct ps_format {                      /* MIPS-3D / paired single format */
 594        __BITFIELD_FIELD(unsigned int opcode : 6,
 595        __BITFIELD_FIELD(unsigned int rs : 5,
 596        __BITFIELD_FIELD(unsigned int ft : 5,
 597        __BITFIELD_FIELD(unsigned int fs : 5,
 598        __BITFIELD_FIELD(unsigned int fd : 5,
 599        __BITFIELD_FIELD(unsigned int func : 6,
 600        ;))))))
 601};
 602
 603struct v_format {                               /* MDMX vector format */
 604        __BITFIELD_FIELD(unsigned int opcode : 6,
 605        __BITFIELD_FIELD(unsigned int sel : 4,
 606        __BITFIELD_FIELD(unsigned int fmt : 1,
 607        __BITFIELD_FIELD(unsigned int vt : 5,
 608        __BITFIELD_FIELD(unsigned int vs : 5,
 609        __BITFIELD_FIELD(unsigned int vd : 5,
 610        __BITFIELD_FIELD(unsigned int func : 6,
 611        ;)))))))
 612};
 613
 614struct spec3_format {   /* SPEC3 */
 615        __BITFIELD_FIELD(unsigned int opcode:6,
 616        __BITFIELD_FIELD(unsigned int rs:5,
 617        __BITFIELD_FIELD(unsigned int rt:5,
 618        __BITFIELD_FIELD(signed int simmediate:9,
 619        __BITFIELD_FIELD(unsigned int func:7,
 620        ;)))))
 621};
 622
 623/*
 624 * microMIPS instruction formats (32-bit length)
 625 *
 626 * NOTE:
 627 *      Parenthesis denote whether the format is a microMIPS instruction or
 628 *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
 629 */
 630struct fb_format {              /* FPU branch format (MIPS32) */
 631        __BITFIELD_FIELD(unsigned int opcode : 6,
 632        __BITFIELD_FIELD(unsigned int bc : 5,
 633        __BITFIELD_FIELD(unsigned int cc : 3,
 634        __BITFIELD_FIELD(unsigned int flag : 2,
 635        __BITFIELD_FIELD(signed int simmediate : 16,
 636        ;)))))
 637};
 638
 639struct fp0_format {             /* FPU multiply and add format (MIPS32) */
 640        __BITFIELD_FIELD(unsigned int opcode : 6,
 641        __BITFIELD_FIELD(unsigned int fmt : 5,
 642        __BITFIELD_FIELD(unsigned int ft : 5,
 643        __BITFIELD_FIELD(unsigned int fs : 5,
 644        __BITFIELD_FIELD(unsigned int fd : 5,
 645        __BITFIELD_FIELD(unsigned int func : 6,
 646        ;))))))
 647};
 648
 649struct mm_fp0_format {          /* FPU multipy and add format (microMIPS) */
 650        __BITFIELD_FIELD(unsigned int opcode : 6,
 651        __BITFIELD_FIELD(unsigned int ft : 5,
 652        __BITFIELD_FIELD(unsigned int fs : 5,
 653        __BITFIELD_FIELD(unsigned int fd : 5,
 654        __BITFIELD_FIELD(unsigned int fmt : 3,
 655        __BITFIELD_FIELD(unsigned int op : 2,
 656        __BITFIELD_FIELD(unsigned int func : 6,
 657        ;)))))))
 658};
 659
 660struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 661        __BITFIELD_FIELD(unsigned int opcode : 6,
 662        __BITFIELD_FIELD(unsigned int op : 5,
 663        __BITFIELD_FIELD(unsigned int rt : 5,
 664        __BITFIELD_FIELD(unsigned int fs : 5,
 665        __BITFIELD_FIELD(unsigned int fd : 5,
 666        __BITFIELD_FIELD(unsigned int func : 6,
 667        ;))))))
 668};
 669
 670struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
 671        __BITFIELD_FIELD(unsigned int opcode : 6,
 672        __BITFIELD_FIELD(unsigned int rt : 5,
 673        __BITFIELD_FIELD(unsigned int fs : 5,
 674        __BITFIELD_FIELD(unsigned int fmt : 2,
 675        __BITFIELD_FIELD(unsigned int op : 8,
 676        __BITFIELD_FIELD(unsigned int func : 6,
 677        ;))))))
 678};
 679
 680struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
 681        __BITFIELD_FIELD(unsigned int opcode : 6,
 682        __BITFIELD_FIELD(unsigned int fd : 5,
 683        __BITFIELD_FIELD(unsigned int fs : 5,
 684        __BITFIELD_FIELD(unsigned int cc : 3,
 685        __BITFIELD_FIELD(unsigned int zero : 2,
 686        __BITFIELD_FIELD(unsigned int fmt : 2,
 687        __BITFIELD_FIELD(unsigned int op : 3,
 688        __BITFIELD_FIELD(unsigned int func : 6,
 689        ;))))))))
 690};
 691
 692struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
 693        __BITFIELD_FIELD(unsigned int opcode : 6,
 694        __BITFIELD_FIELD(unsigned int rt : 5,
 695        __BITFIELD_FIELD(unsigned int fs : 5,
 696        __BITFIELD_FIELD(unsigned int fmt : 3,
 697        __BITFIELD_FIELD(unsigned int op : 7,
 698        __BITFIELD_FIELD(unsigned int func : 6,
 699        ;))))))
 700};
 701
 702struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
 703        __BITFIELD_FIELD(unsigned int opcode : 6,
 704        __BITFIELD_FIELD(unsigned int rt : 5,
 705        __BITFIELD_FIELD(unsigned int fs : 5,
 706        __BITFIELD_FIELD(unsigned int cc : 3,
 707        __BITFIELD_FIELD(unsigned int fmt : 3,
 708        __BITFIELD_FIELD(unsigned int cond : 4,
 709        __BITFIELD_FIELD(unsigned int func : 6,
 710        ;)))))))
 711};
 712
 713struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
 714        __BITFIELD_FIELD(unsigned int opcode : 6,
 715        __BITFIELD_FIELD(unsigned int index : 5,
 716        __BITFIELD_FIELD(unsigned int base : 5,
 717        __BITFIELD_FIELD(unsigned int fd : 5,
 718        __BITFIELD_FIELD(unsigned int op : 5,
 719        __BITFIELD_FIELD(unsigned int func : 6,
 720        ;))))))
 721};
 722
 723struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 724        __BITFIELD_FIELD(unsigned int opcode : 6,
 725        __BITFIELD_FIELD(unsigned int fr : 5,
 726        __BITFIELD_FIELD(unsigned int ft : 5,
 727        __BITFIELD_FIELD(unsigned int fs : 5,
 728        __BITFIELD_FIELD(unsigned int fd : 5,
 729        __BITFIELD_FIELD(unsigned int func : 6,
 730        ;))))))
 731};
 732
 733struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
 734        __BITFIELD_FIELD(unsigned int opcode : 6,
 735        __BITFIELD_FIELD(unsigned int ft : 5,
 736        __BITFIELD_FIELD(unsigned int fs : 5,
 737        __BITFIELD_FIELD(unsigned int fd : 5,
 738        __BITFIELD_FIELD(unsigned int fr : 5,
 739        __BITFIELD_FIELD(unsigned int func : 6,
 740        ;))))))
 741};
 742
 743struct mm_i_format {            /* Immediate format (microMIPS) */
 744        __BITFIELD_FIELD(unsigned int opcode : 6,
 745        __BITFIELD_FIELD(unsigned int rt : 5,
 746        __BITFIELD_FIELD(unsigned int rs : 5,
 747        __BITFIELD_FIELD(signed int simmediate : 16,
 748        ;))))
 749};
 750
 751struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
 752        __BITFIELD_FIELD(unsigned int opcode : 6,
 753        __BITFIELD_FIELD(unsigned int rd : 5,
 754        __BITFIELD_FIELD(unsigned int base : 5,
 755        __BITFIELD_FIELD(unsigned int func : 4,
 756        __BITFIELD_FIELD(signed int simmediate : 12,
 757        ;)))))
 758};
 759
 760struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
 761        __BITFIELD_FIELD(unsigned int opcode : 6,
 762        __BITFIELD_FIELD(unsigned int index : 5,
 763        __BITFIELD_FIELD(unsigned int base : 5,
 764        __BITFIELD_FIELD(unsigned int rd : 5,
 765        __BITFIELD_FIELD(unsigned int func : 11,
 766        ;)))))
 767};
 768
 769/*
 770 * microMIPS instruction formats (16-bit length)
 771 */
 772struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
 773        __BITFIELD_FIELD(unsigned int opcode : 6,
 774        __BITFIELD_FIELD(signed int simmediate : 10,
 775        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 776        ;)))
 777};
 778
 779struct mm_b1_format {           /* Conditional branch format (microMIPS) */
 780        __BITFIELD_FIELD(unsigned int opcode : 6,
 781        __BITFIELD_FIELD(unsigned int rs : 3,
 782        __BITFIELD_FIELD(signed int simmediate : 7,
 783        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 784        ;))))
 785};
 786
 787struct mm16_m_format {          /* Multi-word load/store format */
 788        __BITFIELD_FIELD(unsigned int opcode : 6,
 789        __BITFIELD_FIELD(unsigned int func : 4,
 790        __BITFIELD_FIELD(unsigned int rlist : 2,
 791        __BITFIELD_FIELD(unsigned int imm : 4,
 792        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 793        ;)))))
 794};
 795
 796struct mm16_rb_format {         /* Signed immediate format */
 797        __BITFIELD_FIELD(unsigned int opcode : 6,
 798        __BITFIELD_FIELD(unsigned int rt : 3,
 799        __BITFIELD_FIELD(unsigned int base : 3,
 800        __BITFIELD_FIELD(signed int simmediate : 4,
 801        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 802        ;)))))
 803};
 804
 805struct mm16_r3_format {         /* Load from global pointer format */
 806        __BITFIELD_FIELD(unsigned int opcode : 6,
 807        __BITFIELD_FIELD(unsigned int rt : 3,
 808        __BITFIELD_FIELD(signed int simmediate : 7,
 809        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 810        ;))))
 811};
 812
 813struct mm16_r5_format {         /* Load/store from stack pointer format */
 814        __BITFIELD_FIELD(unsigned int opcode : 6,
 815        __BITFIELD_FIELD(unsigned int rt : 5,
 816        __BITFIELD_FIELD(signed int simmediate : 5,
 817        __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 818        ;))))
 819};
 820
 821/*
 822 * MIPS16e instruction formats (16-bit length)
 823 */
 824struct m16e_rr {
 825        __BITFIELD_FIELD(unsigned int opcode : 5,
 826        __BITFIELD_FIELD(unsigned int rx : 3,
 827        __BITFIELD_FIELD(unsigned int nd : 1,
 828        __BITFIELD_FIELD(unsigned int l : 1,
 829        __BITFIELD_FIELD(unsigned int ra : 1,
 830        __BITFIELD_FIELD(unsigned int func : 5,
 831        ;))))))
 832};
 833
 834struct m16e_jal {
 835        __BITFIELD_FIELD(unsigned int opcode : 5,
 836        __BITFIELD_FIELD(unsigned int x : 1,
 837        __BITFIELD_FIELD(unsigned int imm20_16 : 5,
 838        __BITFIELD_FIELD(signed int imm25_21 : 5,
 839        ;))))
 840};
 841
 842struct m16e_i64 {
 843        __BITFIELD_FIELD(unsigned int opcode : 5,
 844        __BITFIELD_FIELD(unsigned int func : 3,
 845        __BITFIELD_FIELD(unsigned int imm : 8,
 846        ;)))
 847};
 848
 849struct m16e_ri64 {
 850        __BITFIELD_FIELD(unsigned int opcode : 5,
 851        __BITFIELD_FIELD(unsigned int func : 3,
 852        __BITFIELD_FIELD(unsigned int ry : 3,
 853        __BITFIELD_FIELD(unsigned int imm : 5,
 854        ;))))
 855};
 856
 857struct m16e_ri {
 858        __BITFIELD_FIELD(unsigned int opcode : 5,
 859        __BITFIELD_FIELD(unsigned int rx : 3,
 860        __BITFIELD_FIELD(unsigned int imm : 8,
 861        ;)))
 862};
 863
 864struct m16e_rri {
 865        __BITFIELD_FIELD(unsigned int opcode : 5,
 866        __BITFIELD_FIELD(unsigned int rx : 3,
 867        __BITFIELD_FIELD(unsigned int ry : 3,
 868        __BITFIELD_FIELD(unsigned int imm : 5,
 869        ;))))
 870};
 871
 872struct m16e_i8 {
 873        __BITFIELD_FIELD(unsigned int opcode : 5,
 874        __BITFIELD_FIELD(unsigned int func : 3,
 875        __BITFIELD_FIELD(unsigned int imm : 8,
 876        ;)))
 877};
 878
 879union mips_instruction {
 880        unsigned int word;
 881        unsigned short halfword[2];
 882        unsigned char byte[4];
 883        struct j_format j_format;
 884        struct i_format i_format;
 885        struct u_format u_format;
 886        struct c_format c_format;
 887        struct r_format r_format;
 888        struct p_format p_format;
 889        struct f_format f_format;
 890        struct ma_format ma_format;
 891        struct b_format b_format;
 892        struct ps_format ps_format;
 893        struct v_format v_format;
 894        struct spec3_format spec3_format;
 895        struct fb_format fb_format;
 896        struct fp0_format fp0_format;
 897        struct mm_fp0_format mm_fp0_format;
 898        struct fp1_format fp1_format;
 899        struct mm_fp1_format mm_fp1_format;
 900        struct mm_fp2_format mm_fp2_format;
 901        struct mm_fp3_format mm_fp3_format;
 902        struct mm_fp4_format mm_fp4_format;
 903        struct mm_fp5_format mm_fp5_format;
 904        struct fp6_format fp6_format;
 905        struct mm_fp6_format mm_fp6_format;
 906        struct mm_i_format mm_i_format;
 907        struct mm_m_format mm_m_format;
 908        struct mm_x_format mm_x_format;
 909        struct mm_b0_format mm_b0_format;
 910        struct mm_b1_format mm_b1_format;
 911        struct mm16_m_format mm16_m_format ;
 912        struct mm16_rb_format mm16_rb_format;
 913        struct mm16_r3_format mm16_r3_format;
 914        struct mm16_r5_format mm16_r5_format;
 915};
 916
 917union mips16e_instruction {
 918        unsigned int full : 16;
 919        struct m16e_rr rr;
 920        struct m16e_jal jal;
 921        struct m16e_i64 i64;
 922        struct m16e_ri64 ri64;
 923        struct m16e_ri ri;
 924        struct m16e_rri rri;
 925        struct m16e_i8 i8;
 926};
 927
 928#endif /* _UAPI_ASM_INST_H */
 929