1#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H 2#define _ASM_POWERPC_PTE_FSL_BOOKE_H 3#ifdef __KERNEL__ 4 5/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based 6 * processors 7 * 8 MMU Assist Register 3: 9 10 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 11 RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR 12 13 - PRESENT *must* be in the bottom three bits because swap cache 14 entries use the top 29 bits. 15 16*/ 17 18/* Definitions for FSL Book-E Cores */ 19#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ 20#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ 21#define _PAGE_RW 0x00004 /* S: Write permission (SW) */ 22#define _PAGE_DIRTY 0x00008 /* S: Page dirty */ 23#define _PAGE_EXEC 0x00010 /* H: SX permission */ 24#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */ 25 26#define _PAGE_ENDIAN 0x00040 /* H: E bit */ 27#define _PAGE_GUARDED 0x00080 /* H: G bit */ 28#define _PAGE_COHERENT 0x00100 /* H: M bit */ 29#define _PAGE_NO_CACHE 0x00200 /* H: I bit */ 30#define _PAGE_WRITETHRU 0x00400 /* H: W bit */ 31#define _PAGE_SPECIAL 0x00800 /* S: Special page */ 32 33#define _PMD_PRESENT 0 34#define _PMD_PRESENT_MASK (PAGE_MASK) 35#define _PMD_BAD (~PAGE_MASK) 36 37#define PTE_WIMGE_SHIFT (6) 38 39#endif /* __KERNEL__ */ 40#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */ 41