LXR linux/arch/sparc/kernel/pci

   1/* pci_sabre.c: Sabre specific PCI controller support.
   2 *
   3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
   4 * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5 * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   6 */
   7
   8#include <linux/kernel.h>
   9#include <linux/types.h>
  10#include <linux/pci.h>
  11#include <linux/init.h>
  12#include <linux/export.h>
  13#include <linux/slab.h>
  14#include <linux/interrupt.h>
  15#include <linux/of_device.h>
  16
  17#include <asm/apb.h>
  18#include <asm/iommu.h>
  19#include <asm/irq.h>
  20#include <asm/prom.h>
  21#include <asm/upa.h>
  22
  23#include "pci_impl.h"
  24#include "iommu_common.h"
  25#include "psycho_common.h"
  26
  27#define DRIVER_NAME     "sabre"
  28#define PFX             DRIVER_NAME ": "
  29
  30/* SABRE PCI controller register offsets and definitions. */
  31#define SABRE_UE_AFSR           0x0030UL
  32#define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  33#define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  34#define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  35#define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  36#define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  37#define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  38#define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  39#define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  40#define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  41#define SABRE_UECE_AFAR         0x0038UL
  42#define SABRE_CE_AFSR           0x0040UL
  43#define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  44#define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  45#define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  46#define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  47#define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  48#define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  49#define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  50#define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  51#define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  52#define SABRE_IOMMU_CONTROL     0x0200UL
  53#define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  54#define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  55#define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  56#define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  57#define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  58#define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  59#define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  60#define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  61#define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  62#define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  63#define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  64#define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  65#define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  66#define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  67#define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  68#define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  69#define SABRE_IOMMU_TSBBASE     0x0208UL
  70#define SABRE_IOMMU_FLUSH       0x0210UL
  71#define SABRE_IMAP_A_SLOT0      0x0c00UL
  72#define SABRE_IMAP_B_SLOT0      0x0c20UL
  73#define SABRE_IMAP_SCSI         0x1000UL
  74#define SABRE_IMAP_ETH          0x1008UL
  75#define SABRE_IMAP_BPP          0x1010UL
  76#define SABRE_IMAP_AU_REC       0x1018UL
  77#define SABRE_IMAP_AU_PLAY      0x1020UL
  78#define SABRE_IMAP_PFAIL        0x1028UL
  79#define SABRE_IMAP_KMS          0x1030UL
  80#define SABRE_IMAP_FLPY         0x1038UL
  81#define SABRE_IMAP_SHW          0x1040UL
  82#define SABRE_IMAP_KBD          0x1048UL
  83#define SABRE_IMAP_MS           0x1050UL
  84#define SABRE_IMAP_SER          0x1058UL
  85#define SABRE_IMAP_UE           0x1070UL
  86#define SABRE_IMAP_CE           0x1078UL
  87#define SABRE_IMAP_PCIERR       0x1080UL
  88#define SABRE_IMAP_GFX          0x1098UL
  89#define SABRE_IMAP_EUPA         0x10a0UL
  90#define SABRE_ICLR_A_SLOT0      0x1400UL
  91#define SABRE_ICLR_B_SLOT0      0x1480UL
  92#define SABRE_ICLR_SCSI         0x1800UL
  93#define SABRE_ICLR_ETH          0x1808UL
  94#define SABRE_ICLR_BPP          0x1810UL
  95#define SABRE_ICLR_AU_REC       0x1818UL
  96#define SABRE_ICLR_AU_PLAY      0x1820UL
  97#define SABRE_ICLR_PFAIL        0x1828UL
  98#define SABRE_ICLR_KMS          0x1830UL
  99#define SABRE_ICLR_FLPY         0x1838UL
 100#define SABRE_ICLR_SHW          0x1840UL
 101#define SABRE_ICLR_KBD          0x1848UL
 102#define SABRE_ICLR_MS           0x1850UL
 103#define SABRE_ICLR_SER          0x1858UL
 104#define SABRE_ICLR_UE           0x1870UL
 105#define SABRE_ICLR_CE           0x1878UL
 106#define SABRE_ICLR_PCIERR       0x1880UL
 107#define SABRE_WRSYNC            0x1c20UL
 108#define SABRE_PCICTRL           0x2000UL
 109#define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 110#define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 111#define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 112#define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 113#define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 114#define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 115#define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 116#define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 117#define SABRE_PIOAFSR           0x2010UL
 118#define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 119#define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 120#define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 121#define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 122#define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 123#define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 124#define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 125#define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 126#define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 127#define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 128#define SABRE_PIOAFAR           0x2018UL
 129#define SABRE_PCIDIAG           0x2020UL
 130#define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 131#define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 132#define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 133#define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 134#define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 135#define SABRE_PCITASR           0x2028UL
 136#define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 137#define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 138#define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 139#define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 140#define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 141#define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 142#define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 143#define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 144#define SABRE_PIOBUF_DIAG       0x5000UL
 145#define SABRE_DMABUF_DIAGLO     0x5100UL
 146#define SABRE_DMABUF_DIAGHI     0x51c0UL
 147#define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 148#define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 149#define SABRE_IOMMU_VADIAG      0xa400UL
 150#define SABRE_IOMMU_TCDIAG      0xa408UL
 151#define SABRE_IOMMU_TAG         0xa580UL
 152#define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 153#define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 154#define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 155#define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 156#define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 157#define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 158#define SABRE_IOMMU_DATA        0xa600UL
 159#define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 160#define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 161#define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 162#define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 163#define SABRE_PCI_IRQSTATE      0xa800UL
 164#define SABRE_OBIO_IRQSTATE     0xa808UL
 165#define SABRE_FFBCFG            0xf000UL
 166#define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 167#define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 168#define SABRE_MCCTRL0           0xf010UL
 169#define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 170#define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 171#define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 172#define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 173#define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 174#define SABRE_MCCTRL1           0xf018UL
 175#define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 176#define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 177#define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 178#define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 179#define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 180#define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 181#define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 182#define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 183#define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 184#define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 185#define SABRE_RESETCTRL         0xf020UL
 186
 187#define SABRE_CONFIGSPACE       0x001000000UL
 188#define SABRE_IOSPACE           0x002000000UL
 189#define SABRE_IOSPACE_SIZE      0x000ffffffUL
 190#define SABRE_MEMSPACE          0x100000000UL
 191#define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 192
 193static int hummingbird_p;
 194static struct pci_bus *sabre_root_bus;
 195
 196static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
 197{
 198        struct pci_pbm_info *pbm = dev_id;
 199        unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
 200        unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
 201        unsigned long afsr, afar, error_bits;
 202        int reported;
 203
 204        /* Latch uncorrectable error status. */
 205        afar = upa_readq(afar_reg);
 206        afsr = upa_readq(afsr_reg);
 207
 208        /* Clear the primary/secondary error status bits. */
 209        error_bits = afsr &
 210                (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 211                 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 212                 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 213        if (!error_bits)
 214                return IRQ_NONE;
 215        upa_writeq(error_bits, afsr_reg);
 216
 217        /* Log the error. */
 218        printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
 219               pbm->name,
 220               ((error_bits & SABRE_UEAFSR_PDRD) ?
 221                "DMA Read" :
 222                ((error_bits & SABRE_UEAFSR_PDWR) ?
 223                 "DMA Write" : "???")),
 224               ((error_bits & SABRE_UEAFSR_PDTE) ?
 225                ":Translation Error" : ""));
 226        printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 227               pbm->name,
 228               (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 229               (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 230               ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 231        printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
 232        printk("%s: UE Secondary errors [", pbm->name);
 233        reported = 0;
 234        if (afsr & SABRE_UEAFSR_SDRD) {
 235                reported++;
 236                printk("(DMA Read)");
 237        }
 238        if (afsr & SABRE_UEAFSR_SDWR) {
 239                reported++;
 240                printk("(DMA Write)");
 241        }
 242        if (afsr & SABRE_UEAFSR_SDTE) {
 243                reported++;
 244                printk("(Translation Error)");
 245        }
 246        if (!reported)
 247                printk("(none)");
 248        printk("]\n");
 249
 250        /* Interrogate IOMMU for error status. */
 251        psycho_check_iommu_error(pbm, afsr, afar, UE_ERR);
 252
 253        return IRQ_HANDLED;
 254}
 255
 256static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
 257{
 258        struct pci_pbm_info *pbm = dev_id;
 259        unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
 260        unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
 261        unsigned long afsr, afar, error_bits;
 262        int reported;
 263
 264        /* Latch error status. */
 265        afar = upa_readq(afar_reg);
 266        afsr = upa_readq(afsr_reg);
 267
 268        /* Clear primary/secondary error status bits. */
 269        error_bits = afsr &
 270                (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 271                 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 272        if (!error_bits)
 273                return IRQ_NONE;
 274        upa_writeq(error_bits, afsr_reg);
 275
 276        /* Log the error. */
 277        printk("%s: Correctable Error, primary error type[%s]\n",
 278               pbm->name,
 279               ((error_bits & SABRE_CEAFSR_PDRD) ?
 280                "DMA Read" :
 281                ((error_bits & SABRE_CEAFSR_PDWR) ?
 282                 "DMA Write" : "???")));
 283
 284        /* XXX Use syndrome and afar to print out module string just like
 285         * XXX UDB CE trap handler does... -DaveM
 286         */
 287        printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 288               "was_block(%d)\n",
 289               pbm->name,
 290               (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 291               (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 292               (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 293               ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 294        printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
 295        printk("%s: CE Secondary errors [", pbm->name);
 296        reported = 0;
 297        if (afsr & SABRE_CEAFSR_SDRD) {
 298                reported++;
 299                printk("(DMA Read)");
 300        }
 301        if (afsr & SABRE_CEAFSR_SDWR) {
 302                reported++;
 303                printk("(DMA Write)");
 304        }
 305        if (!reported)
 306                printk("(none)");
 307        printk("]\n");
 308
 309        return IRQ_HANDLED;
 310}
 311
 312static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
 313{
 314        struct device_node *dp = pbm->op->dev.of_node;
 315        struct platform_device *op;
 316        unsigned long base = pbm->controller_regs;
 317        u64 tmp;
 318        int err;
 319
 320        if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
 321                dp = dp->parent;
 322
 323        op = of_find_device_by_node(dp);
 324        if (!op)
 325                return;
 326
 327        /* Sabre/Hummingbird IRQ property layout is:
 328         * 0: PCI ERR
 329         * 1: UE ERR
 330         * 2: CE ERR
 331         * 3: POWER FAIL
 332         */
 333        if (op->archdata.num_irqs < 4)
 334                return;
 335
 336        /* We clear the error bits in the appropriate AFSR before
 337         * registering the handler so that we don't get spurious
 338         * interrupts.
 339         */
 340        upa_writeq((SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 341                    SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 342                    SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE),
 343                   base + SABRE_UE_AFSR);
 344
 345        err = request_irq(op->archdata.irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
 346        if (err)
 347                printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
 348                       pbm->name, err);
 349
 350        upa_writeq((SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 351                    SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR),
 352                   base + SABRE_CE_AFSR);
 353
 354
 355        err = request_irq(op->archdata.irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
 356        if (err)
 357                printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
 358                       pbm->name, err);
 359        err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, 0,
 360                          "SABRE_PCIERR", pbm);
 361        if (err)
 362                printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
 363                       pbm->name, err);
 364
 365        tmp = upa_readq(base + SABRE_PCICTRL);
 366        tmp |= SABRE_PCICTRL_ERREN;
 367        upa_writeq(tmp, base + SABRE_PCICTRL);
 368}
 369
 370static void apb_init(struct pci_bus *sabre_bus)
 371{
 372        struct pci_dev *pdev;
 373
 374        list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
 375                if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 376                    pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
 377                        u16 word16;
 378
 379                        pci_read_config_word(pdev, PCI_COMMAND, &word16);
 380                        word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 381                                PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
 382                                PCI_COMMAND_IO;
 383                        pci_write_config_word(pdev, PCI_COMMAND, word16);
 384
 385                        /* Status register bits are "write 1 to clear". */
 386                        pci_write_config_word(pdev, PCI_STATUS, 0xffff);
 387                        pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
 388
 389                        /* Use a primary/seconday latency timer value
 390                         * of 64.
 391                         */
 392                        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
 393                        pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
 394
 395                        /* Enable reporting/forwarding of master aborts,
 396                         * parity, and SERR.
 397                         */
 398                        pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
 399                                              (PCI_BRIDGE_CTL_PARITY |
 400                                               PCI_BRIDGE_CTL_SERR |
 401                                               PCI_BRIDGE_CTL_MASTER_ABORT));
 402                }
 403        }
 404}
 405
 406static void sabre_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
 407{
 408        static int once;
 409
 410        /* The APB bridge speaks to the Sabre host PCI bridge
 411         * at 66Mhz, but the front side of APB runs at 33Mhz
 412         * for both segments.
 413         *
 414         * Hummingbird systems do not use APB, so they run
 415         * at 66MHZ.
 416         */
 417        if (hummingbird_p)
 418                pbm->is_66mhz_capable = 1;
 419        else
 420                pbm->is_66mhz_capable = 0;
 421
 422        /* This driver has not been verified to handle
 423         * multiple SABREs yet, so trap this.
 424         *
 425         * Also note that the SABRE host bridge is hardwired
 426         * to live at bus 0.
 427         */
 428        if (once != 0) {
 429                printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
 430                return;
 431        }
 432        once++;
 433
 434        pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
 435        if (!pbm->pci_bus)
 436                return;
 437
 438        sabre_root_bus = pbm->pci_bus;
 439
 440        apb_init(pbm->pci_bus);
 441
 442        sabre_register_error_handlers(pbm);
 443}
 444
 445static void sabre_pbm_init(struct pci_pbm_info *pbm,
 446                           struct platform_device *op)
 447{
 448        psycho_pbm_init_common(pbm, op, "SABRE", PBM_CHIP_TYPE_SABRE);
 449        pbm->pci_afsr = pbm->controller_regs + SABRE_PIOAFSR;
 450        pbm->pci_afar = pbm->controller_regs + SABRE_PIOAFAR;
 451        pbm->pci_csr = pbm->controller_regs + SABRE_PCICTRL;
 452        sabre_scan_bus(pbm, &op->dev);
 453}
 454
 455static const struct of_device_id sabre_match[];
 456static int sabre_probe(struct platform_device *op)
 457{
 458        const struct of_device_id *match;
 459        const struct linux_prom64_registers *pr_regs;
 460        struct device_node *dp = op->dev.of_node;
 461        struct pci_pbm_info *pbm;
 462        u32 upa_portid, dma_mask;
 463        struct iommu *iommu;
 464        int tsbsize, err;
 465        const u32 *vdma;
 466        u64 clear_irq;
 467
 468        match = of_match_device(sabre_match, &op->dev);
 469        hummingbird_p = match && (match->data != NULL);
 470        if (!hummingbird_p) {
 471                struct device_node *cpu_dp;
 472
 473                /* Of course, Sun has to encode things a thousand
 474                 * different ways, inconsistently.
 475                 */
 476                for_each_node_by_type(cpu_dp, "cpu") {
 477                        if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe"))
 478                                hummingbird_p = 1;
 479                }
 480        }
 481
 482        err = -ENOMEM;
 483        pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
 484        if (!pbm) {
 485                printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
 486                goto out_err;
 487        }
 488
 489        iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
 490        if (!iommu) {
 491                printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
 492                goto out_free_controller;
 493        }
 494
 495        pbm->iommu = iommu;
 496
 497        upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
 498
 499        pbm->portid = upa_portid;
 500
 501        /*
 502         * Map in SABRE register set and report the presence of this SABRE.
 503         */
 504        
 505        pr_regs = of_get_property(dp, "reg", NULL);
 506        err = -ENODEV;
 507        if (!pr_regs) {
 508                printk(KERN_ERR PFX "No reg property\n");
 509                goto out_free_iommu;
 510        }
 511
 512        /*
 513         * First REG in property is base of entire SABRE register space.
 514         */
 515        pbm->controller_regs = pr_regs[0].phys_addr;
 516
 517        /* Clear interrupts */
 518
 519        /* PCI first */
 520        for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
 521                upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
 522
 523        /* Then OBIO */
 524        for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
 525                upa_writeq(0x0UL, pbm->controller_regs + clear_irq);
 526
 527        /* Error interrupts are enabled later after the bus scan. */
 528        upa_writeq((SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
 529                    SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN),
 530                   pbm->controller_regs + SABRE_PCICTRL);
 531
 532        /* Now map in PCI config space for entire SABRE. */
 533        pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
 534
 535        vdma = of_get_property(dp, "virtual-dma", NULL);
 536        if (!vdma) {
 537                printk(KERN_ERR PFX "No virtual-dma property\n");
 538                goto out_free_iommu;
 539        }
 540
 541        dma_mask = vdma[0];
 542        switch(vdma[1]) {
 543                case 0x20000000:
 544                        dma_mask |= 0x1fffffff;
 545                        tsbsize = 64;
 546                        break;
 547                case 0x40000000:
 548                        dma_mask |= 0x3fffffff;
 549                        tsbsize = 128;
 550                        break;
 551
 552                case 0x80000000:
 553                        dma_mask |= 0x7fffffff;
 554                        tsbsize = 128;
 555                        break;
 556                default:
 557                        printk(KERN_ERR PFX "Strange virtual-dma size.\n");
 558                        goto out_free_iommu;
 559        }
 560
 561        err = psycho_iommu_init(pbm, tsbsize, vdma[0], dma_mask, SABRE_WRSYNC);
 562        if (err)
 563                goto out_free_iommu;
 564
 565        /*
 566         * Look for APB underneath.
 567         */
 568        sabre_pbm_init(pbm, op);
 569
 570        pbm->next = pci_pbm_root;
 571        pci_pbm_root = pbm;
 572
 573        dev_set_drvdata(&op->dev, pbm);
 574
 575        return 0;
 576
 577out_free_iommu:
 578        kfree(pbm->iommu);
 579
 580out_free_controller:
 581        kfree(pbm);
 582
 583out_err:
 584        return err;
 585}
 586
 587static const struct of_device_id sabre_match[] = {
 588        {
 589                .name = "pci",
 590                .compatible = "pci108e,a001",
 591                .data = (void *) 1,
 592        },
 593        {
 594                .name = "pci",
 595                .compatible = "pci108e,a000",
 596        },
 597        {},
 598};
 599
 600static struct platform_driver sabre_driver = {
 601        .driver = {
 602                .name = DRIVER_NAME,
 603                .of_match_table = sabre_match,
 604        },
 605        .probe          = sabre_probe,
 606};
 607
 608static int __init sabre_init(void)
 609{
 610        return platform_driver_register(&sabre_driver);
 611}
 612
 613subsys_initcall(sabre_init);
 614