1#ifndef _ASM_X86_PROCESSOR_H
2#define _ASM_X86_PROCESSOR_H
3
4#include <asm/processor-flags.h>
5
6
7struct task_struct;
8struct mm_struct;
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/types.h>
14#include <asm/sigcontext.h>
15#include <asm/current.h>
16#include <asm/cpufeature.h>
17#include <asm/page.h>
18#include <asm/pgtable_types.h>
19#include <asm/percpu.h>
20#include <asm/msr.h>
21#include <asm/desc_defs.h>
22#include <asm/nops.h>
23#include <asm/special_insns.h>
24
25#include <linux/personality.h>
26#include <linux/cpumask.h>
27#include <linux/cache.h>
28#include <linux/threads.h>
29#include <linux/math64.h>
30#include <linux/err.h>
31#include <linux/irqflags.h>
32
33
34
35
36
37
38
39#define NET_IP_ALIGN 0
40
41#define HBP_NUM 4
42
43
44
45
46static inline void *current_text_addr(void)
47{
48 void *pc;
49
50 asm volatile("mov $1f, %0; 1:":"=r" (pc));
51
52 return pc;
53}
54
55#ifdef CONFIG_X86_VSMP
56# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
57# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
58#else
59# define ARCH_MIN_TASKALIGN 16
60# define ARCH_MIN_MMSTRUCT_ALIGN 0
61#endif
62
63enum tlb_infos {
64 ENTRIES,
65 NR_INFO
66};
67
68extern u16 __read_mostly tlb_lli_4k[NR_INFO];
69extern u16 __read_mostly tlb_lli_2m[NR_INFO];
70extern u16 __read_mostly tlb_lli_4m[NR_INFO];
71extern u16 __read_mostly tlb_lld_4k[NR_INFO];
72extern u16 __read_mostly tlb_lld_2m[NR_INFO];
73extern u16 __read_mostly tlb_lld_4m[NR_INFO];
74extern u16 __read_mostly tlb_lld_1g[NR_INFO];
75
76
77
78
79
80
81
82struct cpuinfo_x86 {
83 __u8 x86;
84 __u8 x86_vendor;
85 __u8 x86_model;
86 __u8 x86_mask;
87#ifdef CONFIG_X86_32
88 char wp_works_ok;
89
90
91 char rfu;
92 char pad0;
93 char pad1;
94#else
95
96 int x86_tlbsize;
97#endif
98 __u8 x86_virt_bits;
99 __u8 x86_phys_bits;
100
101 __u8 x86_coreid_bits;
102
103 __u32 extended_cpuid_level;
104
105 int cpuid_level;
106 __u32 x86_capability[NCAPINTS + NBUGINTS];
107 char x86_vendor_id[16];
108 char x86_model_id[64];
109
110 int x86_cache_size;
111 int x86_cache_alignment;
112 int x86_power;
113 unsigned long loops_per_jiffy;
114
115 u16 x86_max_cores;
116 u16 apicid;
117 u16 initial_apicid;
118 u16 x86_clflush_size;
119
120 u16 booted_cores;
121
122 u16 phys_proc_id;
123
124 u16 cpu_core_id;
125
126 u8 compute_unit_id;
127
128 u16 cpu_index;
129 u32 microcode;
130};
131
132#define X86_VENDOR_INTEL 0
133#define X86_VENDOR_CYRIX 1
134#define X86_VENDOR_AMD 2
135#define X86_VENDOR_UMC 3
136#define X86_VENDOR_CENTAUR 5
137#define X86_VENDOR_TRANSMETA 7
138#define X86_VENDOR_NSC 8
139#define X86_VENDOR_NUM 9
140
141#define X86_VENDOR_UNKNOWN 0xff
142
143
144
145
146extern struct cpuinfo_x86 boot_cpu_data;
147extern struct cpuinfo_x86 new_cpu_data;
148
149extern struct tss_struct doublefault_tss;
150extern __u32 cpu_caps_cleared[NCAPINTS];
151extern __u32 cpu_caps_set[NCAPINTS];
152
153#ifdef CONFIG_SMP
154DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
155#define cpu_data(cpu) per_cpu(cpu_info, cpu)
156#else
157#define cpu_info boot_cpu_data
158#define cpu_data(cpu) boot_cpu_data
159#endif
160
161extern const struct seq_operations cpuinfo_op;
162
163#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
164
165extern void cpu_detect(struct cpuinfo_x86 *c);
166extern void fpu_detect(struct cpuinfo_x86 *c);
167
168extern void early_cpu_init(void);
169extern void identify_boot_cpu(void);
170extern void identify_secondary_cpu(struct cpuinfo_x86 *);
171extern void print_cpu_info(struct cpuinfo_x86 *);
172void print_cpu_msr(struct cpuinfo_x86 *);
173extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
174extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
175extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
176
177extern void detect_extended_topology(struct cpuinfo_x86 *c);
178extern void detect_ht(struct cpuinfo_x86 *c);
179
180#ifdef CONFIG_X86_32
181extern int have_cpuid_p(void);
182#else
183static inline int have_cpuid_p(void)
184{
185 return 1;
186}
187#endif
188static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
189 unsigned int *ecx, unsigned int *edx)
190{
191
192 asm volatile("cpuid"
193 : "=a" (*eax),
194 "=b" (*ebx),
195 "=c" (*ecx),
196 "=d" (*edx)
197 : "0" (*eax), "2" (*ecx)
198 : "memory");
199}
200
201static inline void load_cr3(pgd_t *pgdir)
202{
203 write_cr3(__pa(pgdir));
204}
205
206#ifdef CONFIG_X86_32
207
208struct x86_hw_tss {
209 unsigned short back_link, __blh;
210 unsigned long sp0;
211 unsigned short ss0, __ss0h;
212 unsigned long sp1;
213
214 unsigned short ss1, __ss1h;
215 unsigned long sp2;
216 unsigned short ss2, __ss2h;
217 unsigned long __cr3;
218 unsigned long ip;
219 unsigned long flags;
220 unsigned long ax;
221 unsigned long cx;
222 unsigned long dx;
223 unsigned long bx;
224 unsigned long sp;
225 unsigned long bp;
226 unsigned long si;
227 unsigned long di;
228 unsigned short es, __esh;
229 unsigned short cs, __csh;
230 unsigned short ss, __ssh;
231 unsigned short ds, __dsh;
232 unsigned short fs, __fsh;
233 unsigned short gs, __gsh;
234 unsigned short ldt, __ldth;
235 unsigned short trace;
236 unsigned short io_bitmap_base;
237
238} __attribute__((packed));
239#else
240struct x86_hw_tss {
241 u32 reserved1;
242 u64 sp0;
243 u64 sp1;
244 u64 sp2;
245 u64 reserved2;
246 u64 ist[7];
247 u32 reserved3;
248 u32 reserved4;
249 u16 reserved5;
250 u16 io_bitmap_base;
251
252} __attribute__((packed)) ____cacheline_aligned;
253#endif
254
255
256
257
258#define IO_BITMAP_BITS 65536
259#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
260#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
261#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
262#define INVALID_IO_BITMAP_OFFSET 0x8000
263
264struct tss_struct {
265
266
267
268 struct x86_hw_tss x86_tss;
269
270
271
272
273
274
275
276 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
277
278
279
280
281 unsigned long stack[64];
282
283} ____cacheline_aligned;
284
285DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
286
287
288
289
290struct orig_ist {
291 unsigned long ist[7];
292};
293
294#define MXCSR_DEFAULT 0x1f80
295
296struct i387_fsave_struct {
297 u32 cwd;
298 u32 swd;
299 u32 twd;
300 u32 fip;
301 u32 fcs;
302 u32 foo;
303 u32 fos;
304
305
306 u32 st_space[20];
307
308
309 u32 status;
310};
311
312struct i387_fxsave_struct {
313 u16 cwd;
314 u16 swd;
315 u16 twd;
316 u16 fop;
317 union {
318 struct {
319 u64 rip;
320 u64 rdp;
321 };
322 struct {
323 u32 fip;
324 u32 fcs;
325 u32 foo;
326 u32 fos;
327 };
328 };
329 u32 mxcsr;
330 u32 mxcsr_mask;
331
332
333 u32 st_space[32];
334
335
336 u32 xmm_space[64];
337
338 u32 padding[12];
339
340 union {
341 u32 padding1[12];
342 u32 sw_reserved[12];
343 };
344
345} __attribute__((aligned(16)));
346
347struct i387_soft_struct {
348 u32 cwd;
349 u32 swd;
350 u32 twd;
351 u32 fip;
352 u32 fcs;
353 u32 foo;
354 u32 fos;
355
356 u32 st_space[20];
357 u8 ftop;
358 u8 changed;
359 u8 lookahead;
360 u8 no_update;
361 u8 rm;
362 u8 alimit;
363 struct math_emu_info *info;
364 u32 entry_eip;
365};
366
367struct ymmh_struct {
368
369 u32 ymmh_space[64];
370};
371
372
373struct lwp_struct {
374 u8 reserved[128];
375};
376
377struct bndreg {
378 u64 lower_bound;
379 u64 upper_bound;
380} __packed;
381
382struct bndcsr {
383 u64 bndcfgu;
384 u64 bndstatus;
385} __packed;
386
387struct xsave_hdr_struct {
388 u64 xstate_bv;
389 u64 xcomp_bv;
390 u64 reserved[6];
391} __attribute__((packed));
392
393struct xsave_struct {
394 struct i387_fxsave_struct i387;
395 struct xsave_hdr_struct xsave_hdr;
396 struct ymmh_struct ymmh;
397 struct lwp_struct lwp;
398 struct bndreg bndreg[4];
399 struct bndcsr bndcsr;
400
401} __attribute__ ((packed, aligned (64)));
402
403union thread_xstate {
404 struct i387_fsave_struct fsave;
405 struct i387_fxsave_struct fxsave;
406 struct i387_soft_struct soft;
407 struct xsave_struct xsave;
408};
409
410struct fpu {
411 unsigned int last_cpu;
412 unsigned int has_fpu;
413 union thread_xstate *state;
414};
415
416#ifdef CONFIG_X86_64
417DECLARE_PER_CPU(struct orig_ist, orig_ist);
418
419union irq_stack_union {
420 char irq_stack[IRQ_STACK_SIZE];
421
422
423
424
425
426 struct {
427 char gs_base[40];
428 unsigned long stack_canary;
429 };
430};
431
432DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
433DECLARE_INIT_PER_CPU(irq_stack_union);
434
435DECLARE_PER_CPU(char *, irq_stack_ptr);
436DECLARE_PER_CPU(unsigned int, irq_count);
437extern asmlinkage void ignore_sysret(void);
438#else
439#ifdef CONFIG_CC_STACKPROTECTOR
440
441
442
443
444
445
446struct stack_canary {
447 char __pad[20];
448 unsigned long canary;
449};
450DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
451#endif
452
453
454
455struct irq_stack {
456 u32 stack[THREAD_SIZE/sizeof(u32)];
457} __aligned(THREAD_SIZE);
458
459DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
460DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
461#endif
462
463extern unsigned int xstate_size;
464extern void free_thread_xstate(struct task_struct *);
465extern struct kmem_cache *task_xstate_cachep;
466
467struct perf_event;
468
469struct thread_struct {
470
471 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
472 unsigned long sp0;
473 unsigned long sp;
474#ifdef CONFIG_X86_32
475 unsigned long sysenter_cs;
476#else
477 unsigned long usersp;
478 unsigned short es;
479 unsigned short ds;
480 unsigned short fsindex;
481 unsigned short gsindex;
482#endif
483#ifdef CONFIG_X86_32
484 unsigned long ip;
485#endif
486#ifdef CONFIG_X86_64
487 unsigned long fs;
488#endif
489 unsigned long gs;
490
491 struct perf_event *ptrace_bps[HBP_NUM];
492
493 unsigned long debugreg6;
494
495 unsigned long ptrace_dr7;
496
497 unsigned long cr2;
498 unsigned long trap_nr;
499 unsigned long error_code;
500
501 struct fpu fpu;
502#ifdef CONFIG_X86_32
503
504 struct vm86_struct __user *vm86_info;
505 unsigned long screen_bitmap;
506 unsigned long v86flags;
507 unsigned long v86mask;
508 unsigned long saved_sp0;
509 unsigned int saved_fs;
510 unsigned int saved_gs;
511#endif
512
513 unsigned long *io_bitmap_ptr;
514 unsigned long iopl;
515
516 unsigned io_bitmap_max;
517
518
519
520
521
522
523
524
525 unsigned char fpu_counter;
526};
527
528
529
530
531static inline void native_set_iopl_mask(unsigned mask)
532{
533#ifdef CONFIG_X86_32
534 unsigned int reg;
535
536 asm volatile ("pushfl;"
537 "popl %0;"
538 "andl %1, %0;"
539 "orl %2, %0;"
540 "pushl %0;"
541 "popfl"
542 : "=&r" (reg)
543 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
544#endif
545}
546
547static inline void
548native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
549{
550 tss->x86_tss.sp0 = thread->sp0;
551#ifdef CONFIG_X86_32
552
553 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
554 tss->x86_tss.ss1 = thread->sysenter_cs;
555 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
556 }
557#endif
558}
559
560static inline void native_swapgs(void)
561{
562#ifdef CONFIG_X86_64
563 asm volatile("swapgs" ::: "memory");
564#endif
565}
566
567#ifdef CONFIG_PARAVIRT
568#include <asm/paravirt.h>
569#else
570#define __cpuid native_cpuid
571#define paravirt_enabled() 0
572
573static inline void load_sp0(struct tss_struct *tss,
574 struct thread_struct *thread)
575{
576 native_load_sp0(tss, thread);
577}
578
579#define set_iopl_mask native_set_iopl_mask
580#endif
581
582typedef struct {
583 unsigned long seg;
584} mm_segment_t;
585
586
587
588extern void release_thread(struct task_struct *);
589
590unsigned long get_wchan(struct task_struct *p);
591
592
593
594
595
596
597static inline void cpuid(unsigned int op,
598 unsigned int *eax, unsigned int *ebx,
599 unsigned int *ecx, unsigned int *edx)
600{
601 *eax = op;
602 *ecx = 0;
603 __cpuid(eax, ebx, ecx, edx);
604}
605
606
607static inline void cpuid_count(unsigned int op, int count,
608 unsigned int *eax, unsigned int *ebx,
609 unsigned int *ecx, unsigned int *edx)
610{
611 *eax = op;
612 *ecx = count;
613 __cpuid(eax, ebx, ecx, edx);
614}
615
616
617
618
619static inline unsigned int cpuid_eax(unsigned int op)
620{
621 unsigned int eax, ebx, ecx, edx;
622
623 cpuid(op, &eax, &ebx, &ecx, &edx);
624
625 return eax;
626}
627
628static inline unsigned int cpuid_ebx(unsigned int op)
629{
630 unsigned int eax, ebx, ecx, edx;
631
632 cpuid(op, &eax, &ebx, &ecx, &edx);
633
634 return ebx;
635}
636
637static inline unsigned int cpuid_ecx(unsigned int op)
638{
639 unsigned int eax, ebx, ecx, edx;
640
641 cpuid(op, &eax, &ebx, &ecx, &edx);
642
643 return ecx;
644}
645
646static inline unsigned int cpuid_edx(unsigned int op)
647{
648 unsigned int eax, ebx, ecx, edx;
649
650 cpuid(op, &eax, &ebx, &ecx, &edx);
651
652 return edx;
653}
654
655
656static inline void rep_nop(void)
657{
658 asm volatile("rep; nop" ::: "memory");
659}
660
661static inline void cpu_relax(void)
662{
663 rep_nop();
664}
665
666#define cpu_relax_lowlatency() cpu_relax()
667
668
669static inline void sync_core(void)
670{
671 int tmp;
672
673#ifdef CONFIG_M486
674
675
676
677
678 asm volatile("cmpl %2,%1\n\t"
679 "jl 1f\n\t"
680 "cpuid\n"
681 "1:"
682 : "=a" (tmp)
683 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
684 : "ebx", "ecx", "edx", "memory");
685#else
686
687
688
689
690
691 asm volatile("cpuid"
692 : "=a" (tmp)
693 : "0" (1)
694 : "ebx", "ecx", "edx", "memory");
695#endif
696}
697
698extern void select_idle_routine(const struct cpuinfo_x86 *c);
699extern void init_amd_e400_c1e_mask(void);
700
701extern unsigned long boot_option_idle_override;
702extern bool amd_e400_c1e_detected;
703
704enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
705 IDLE_POLL};
706
707extern void enable_sep_cpu(void);
708extern int sysenter_setup(void);
709
710extern void early_trap_init(void);
711void early_trap_pf_init(void);
712
713
714extern struct desc_ptr early_gdt_descr;
715
716extern void cpu_set_gdt(int);
717extern void switch_to_new_gdt(int);
718extern void load_percpu_segment(int);
719extern void cpu_init(void);
720
721static inline unsigned long get_debugctlmsr(void)
722{
723 unsigned long debugctlmsr = 0;
724
725#ifndef CONFIG_X86_DEBUGCTLMSR
726 if (boot_cpu_data.x86 < 6)
727 return 0;
728#endif
729 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
730
731 return debugctlmsr;
732}
733
734static inline void update_debugctlmsr(unsigned long debugctlmsr)
735{
736#ifndef CONFIG_X86_DEBUGCTLMSR
737 if (boot_cpu_data.x86 < 6)
738 return;
739#endif
740 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
741}
742
743extern void set_task_blockstep(struct task_struct *task, bool on);
744
745
746
747
748
749extern unsigned int machine_id;
750extern unsigned int machine_submodel_id;
751extern unsigned int BIOS_revision;
752
753
754extern int bootloader_type;
755extern int bootloader_version;
756
757extern char ignore_fpu_irq;
758
759#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
760#define ARCH_HAS_PREFETCHW
761#define ARCH_HAS_SPINLOCK_PREFETCH
762
763#ifdef CONFIG_X86_32
764# define BASE_PREFETCH ASM_NOP4
765# define ARCH_HAS_PREFETCH
766#else
767# define BASE_PREFETCH "prefetcht0 (%1)"
768#endif
769
770
771
772
773
774
775
776static inline void prefetch(const void *x)
777{
778 alternative_input(BASE_PREFETCH,
779 "prefetchnta (%1)",
780 X86_FEATURE_XMM,
781 "r" (x));
782}
783
784
785
786
787
788
789static inline void prefetchw(const void *x)
790{
791 alternative_input(BASE_PREFETCH,
792 "prefetchw (%1)",
793 X86_FEATURE_3DNOW,
794 "r" (x));
795}
796
797static inline void spin_lock_prefetch(const void *x)
798{
799 prefetchw(x);
800}
801
802#ifdef CONFIG_X86_32
803
804
805
806#define TASK_SIZE PAGE_OFFSET
807#define TASK_SIZE_MAX TASK_SIZE
808#define STACK_TOP TASK_SIZE
809#define STACK_TOP_MAX STACK_TOP
810
811#define INIT_THREAD { \
812 .sp0 = sizeof(init_stack) + (long)&init_stack, \
813 .vm86_info = NULL, \
814 .sysenter_cs = __KERNEL_CS, \
815 .io_bitmap_ptr = NULL, \
816}
817
818
819
820
821
822
823
824#define INIT_TSS { \
825 .x86_tss = { \
826 .sp0 = sizeof(init_stack) + (long)&init_stack, \
827 .ss0 = __KERNEL_DS, \
828 .ss1 = __KERNEL_CS, \
829 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
830 }, \
831 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
832}
833
834extern unsigned long thread_saved_pc(struct task_struct *tsk);
835
836#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
837#define KSTK_TOP(info) \
838({ \
839 unsigned long *__ptr = (unsigned long *)(info); \
840 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
841})
842
843
844
845
846
847
848
849
850
851
852
853#define task_pt_regs(task) \
854({ \
855 struct pt_regs *__regs__; \
856 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
857 __regs__ - 1; \
858})
859
860#define KSTK_ESP(task) (task_pt_regs(task)->sp)
861
862#else
863
864
865
866
867
868
869
870
871
872#define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
873
874
875
876
877#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
878 0xc0000000 : 0xFFFFe000)
879
880#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
881 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
882#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
883 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
884
885#define STACK_TOP TASK_SIZE
886#define STACK_TOP_MAX TASK_SIZE_MAX
887
888#define INIT_THREAD { \
889 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
890}
891
892#define INIT_TSS { \
893 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
894}
895
896
897
898
899
900#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
901
902#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
903extern unsigned long KSTK_ESP(struct task_struct *task);
904
905
906
907
908DECLARE_PER_CPU(unsigned long, old_rsp);
909
910#endif
911
912extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
913 unsigned long new_sp);
914
915
916
917
918
919#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
920
921#define KSTK_EIP(task) (task_pt_regs(task)->ip)
922
923
924#define GET_TSC_CTL(adr) get_tsc_mode((adr))
925#define SET_TSC_CTL(val) set_tsc_mode((val))
926
927extern int get_tsc_mode(unsigned long adr);
928extern int set_tsc_mode(unsigned int val);
929
930
931#define MPX_ENABLE_MANAGEMENT(tsk) mpx_enable_management((tsk))
932#define MPX_DISABLE_MANAGEMENT(tsk) mpx_disable_management((tsk))
933
934#ifdef CONFIG_X86_INTEL_MPX
935extern int mpx_enable_management(struct task_struct *tsk);
936extern int mpx_disable_management(struct task_struct *tsk);
937#else
938static inline int mpx_enable_management(struct task_struct *tsk)
939{
940 return -EINVAL;
941}
942static inline int mpx_disable_management(struct task_struct *tsk)
943{
944 return -EINVAL;
945}
946#endif
947
948extern u16 amd_get_nb_id(int cpu);
949
950static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
951{
952 uint32_t base, eax, signature[3];
953
954 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
955 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
956
957 if (!memcmp(sig, signature, 12) &&
958 (leaves == 0 || ((eax - base) >= leaves)))
959 return base;
960 }
961
962 return 0;
963}
964
965extern unsigned long arch_align_stack(unsigned long sp);
966extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
967
968void default_idle(void);
969#ifdef CONFIG_XEN
970bool xen_set_default_idle(void);
971#else
972#define xen_set_default_idle 0
973#endif
974
975void stop_this_cpu(void *dummy);
976void df_debug(struct pt_regs *regs, long error_code);
977#endif
978