LXR linux/drivers/block/rsxx/rsxx

   1/*
   2* Filename: rsxx_priv.h
   3*
   4*
   5* Authors: Joshua Morris <josh.h.morris@us.ibm.com>
   6*       Philip Kelleher <pjk1939@linux.vnet.ibm.com>
   7*
   8* (C) Copyright 2013 IBM Corporation
   9*
  10* This program is free software; you can redistribute it and/or
  11* modify it under the terms of the GNU General Public License as
  12* published by the Free Software Foundation; either version 2 of the
  13* License, or (at your option) any later version.
  14*
  15* This program is distributed in the hope that it will be useful, but
  16* WITHOUT ANY WARRANTY; without even the implied warranty of
  17* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18* General Public License for more details.
  19*
  20* You should have received a copy of the GNU General Public License
  21* along with this program; if not, write to the Free Software Foundation,
  22* Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23*/
  24
  25#ifndef __RSXX_PRIV_H__
  26#define __RSXX_PRIV_H__
  27
  28#include <linux/version.h>
  29#include <linux/semaphore.h>
  30
  31#include <linux/fs.h>
  32#include <linux/interrupt.h>
  33#include <linux/mutex.h>
  34#include <linux/pci.h>
  35#include <linux/spinlock.h>
  36#include <linux/sysfs.h>
  37#include <linux/workqueue.h>
  38#include <linux/bio.h>
  39#include <linux/vmalloc.h>
  40#include <linux/timer.h>
  41#include <linux/ioctl.h>
  42#include <linux/delay.h>
  43
  44#include "rsxx.h"
  45#include "rsxx_cfg.h"
  46
  47struct proc_cmd;
  48
  49#define PCI_DEVICE_ID_FS70_FLASH        0x04A9
  50#define PCI_DEVICE_ID_FS80_FLASH        0x04AA
  51
  52#define RS70_PCI_REV_SUPPORTED  4
  53
  54#define DRIVER_NAME "rsxx"
  55#define DRIVER_VERSION "4.0.3.2516"
  56
  57/* Block size is 4096 */
  58#define RSXX_HW_BLK_SHIFT               12
  59#define RSXX_HW_BLK_SIZE                (1 << RSXX_HW_BLK_SHIFT)
  60#define RSXX_HW_BLK_MASK                (RSXX_HW_BLK_SIZE - 1)
  61
  62#define MAX_CREG_DATA8  32
  63#define LOG_BUF_SIZE8   128
  64
  65#define RSXX_MAX_OUTSTANDING_CMDS       255
  66#define RSXX_CS_IDX_MASK                0xff
  67
  68#define STATUS_BUFFER_SIZE8     4096
  69#define COMMAND_BUFFER_SIZE8    4096
  70
  71#define RSXX_MAX_TARGETS        8
  72
  73struct dma_tracker_list;
  74
  75/* DMA Command/Status Buffer structure */
  76struct rsxx_cs_buffer {
  77        dma_addr_t      dma_addr;
  78        void            *buf;
  79        u32             idx;
  80};
  81
  82struct rsxx_dma_stats {
  83        u32 crc_errors;
  84        u32 hard_errors;
  85        u32 soft_errors;
  86        u32 writes_issued;
  87        u32 writes_failed;
  88        u32 reads_issued;
  89        u32 reads_failed;
  90        u32 reads_retried;
  91        u32 discards_issued;
  92        u32 discards_failed;
  93        u32 done_rescheduled;
  94        u32 issue_rescheduled;
  95        u32 dma_sw_err;
  96        u32 dma_hw_fault;
  97        u32 dma_cancelled;
  98        u32 sw_q_depth;         /* Number of DMAs on the SW queue. */
  99        atomic_t hw_q_depth;    /* Number of DMAs queued to HW. */
 100};
 101
 102struct rsxx_dma_ctrl {
 103        struct rsxx_cardinfo            *card;
 104        int                             id;
 105        void                            __iomem *regmap;
 106        struct rsxx_cs_buffer           status;
 107        struct rsxx_cs_buffer           cmd;
 108        u16                             e_cnt;
 109        spinlock_t                      queue_lock;
 110        struct list_head                queue;
 111        struct workqueue_struct         *issue_wq;
 112        struct work_struct              issue_dma_work;
 113        struct workqueue_struct         *done_wq;
 114        struct work_struct              dma_done_work;
 115        struct timer_list               activity_timer;
 116        struct dma_tracker_list         *trackers;
 117        struct rsxx_dma_stats           stats;
 118        struct mutex                    work_lock;
 119};
 120
 121struct rsxx_cardinfo {
 122        struct pci_dev          *dev;
 123        unsigned int            halt;
 124        unsigned int            eeh_state;
 125
 126        void                    __iomem *regmap;
 127        spinlock_t              irq_lock;
 128        unsigned int            isr_mask;
 129        unsigned int            ier_mask;
 130
 131        struct rsxx_card_cfg    config;
 132        int                     config_valid;
 133
 134        /* Embedded CPU Communication */
 135        struct {
 136                spinlock_t              lock;
 137                bool                    active;
 138                struct creg_cmd         *active_cmd;
 139                struct workqueue_struct *creg_wq;
 140                struct work_struct      done_work;
 141                struct list_head        queue;
 142                unsigned int            q_depth;
 143                /* Cache the creg status to prevent ioreads */
 144                struct {
 145                        u32             stat;
 146                        u32             failed_cancel_timer;
 147                        u32             creg_timeout;
 148                } creg_stats;
 149                struct timer_list       cmd_timer;
 150                struct mutex            reset_lock;
 151                int                     reset;
 152        } creg_ctrl;
 153
 154        struct {
 155                char tmp[MAX_CREG_DATA8];
 156                char buf[LOG_BUF_SIZE8]; /* terminated */
 157                int buf_len;
 158        } log;
 159
 160        struct workqueue_struct *event_wq;
 161        struct work_struct      event_work;
 162        unsigned int            state;
 163        u64                     size8;
 164
 165        /* Lock the device attach/detach function */
 166        struct mutex            dev_lock;
 167
 168        /* Block Device Variables */
 169        bool                    bdev_attached;
 170        int                     disk_id;
 171        int                     major;
 172        struct request_queue    *queue;
 173        struct gendisk          *gendisk;
 174        struct {
 175                /* Used to convert a byte address to a device address. */
 176                u64 lower_mask;
 177                u64 upper_shift;
 178                u64 upper_mask;
 179                u64 target_mask;
 180                u64 target_shift;
 181        } _stripe;
 182        unsigned int            dma_fault;
 183
 184        int                     scrub_hard;
 185
 186        int                     n_targets;
 187        struct rsxx_dma_ctrl    *ctrl;
 188
 189        struct dentry           *debugfs_dir;
 190};
 191
 192enum rsxx_pci_regmap {
 193        HWID            = 0x00, /* Hardware Identification Register */
 194        SCRATCH         = 0x04, /* Scratch/Debug Register */
 195        RESET           = 0x08, /* Reset Register */
 196        ISR             = 0x10, /* Interrupt Status Register */
 197        IER             = 0x14, /* Interrupt Enable Register */
 198        IPR             = 0x18, /* Interrupt Poll Register */
 199        CB_ADD_LO       = 0x20, /* Command Host Buffer Address [31:0] */
 200        CB_ADD_HI       = 0x24, /* Command Host Buffer Address [63:32]*/
 201        HW_CMD_IDX      = 0x28, /* Hardware Processed Command Index */
 202        SW_CMD_IDX      = 0x2C, /* Software Processed Command Index */
 203        SB_ADD_LO       = 0x30, /* Status Host Buffer Address [31:0] */
 204        SB_ADD_HI       = 0x34, /* Status Host Buffer Address [63:32] */
 205        HW_STATUS_CNT   = 0x38, /* Hardware Status Counter */
 206        SW_STATUS_CNT   = 0x3C, /* Deprecated */
 207        CREG_CMD        = 0x40, /* CPU Command Register */
 208        CREG_ADD        = 0x44, /* CPU Address Register */
 209        CREG_CNT        = 0x48, /* CPU Count Register */
 210        CREG_STAT       = 0x4C, /* CPU Status Register */
 211        CREG_DATA0      = 0x50, /* CPU Data Registers */
 212        CREG_DATA1      = 0x54,
 213        CREG_DATA2      = 0x58,
 214        CREG_DATA3      = 0x5C,
 215        CREG_DATA4      = 0x60,
 216        CREG_DATA5      = 0x64,
 217        CREG_DATA6      = 0x68,
 218        CREG_DATA7      = 0x6c,
 219        INTR_COAL       = 0x70, /* Interrupt Coalescing Register */
 220        HW_ERROR        = 0x74, /* Card Error Register */
 221        PCI_DEBUG0      = 0x78, /* PCI Debug Registers */
 222        PCI_DEBUG1      = 0x7C,
 223        PCI_DEBUG2      = 0x80,
 224        PCI_DEBUG3      = 0x84,
 225        PCI_DEBUG4      = 0x88,
 226        PCI_DEBUG5      = 0x8C,
 227        PCI_DEBUG6      = 0x90,
 228        PCI_DEBUG7      = 0x94,
 229        PCI_POWER_THROTTLE = 0x98,
 230        PERF_CTRL       = 0x9c,
 231        PERF_TIMER_LO   = 0xa0,
 232        PERF_TIMER_HI   = 0xa4,
 233        PERF_RD512_LO   = 0xa8,
 234        PERF_RD512_HI   = 0xac,
 235        PERF_WR512_LO   = 0xb0,
 236        PERF_WR512_HI   = 0xb4,
 237        PCI_RECONFIG    = 0xb8,
 238};
 239
 240enum rsxx_intr {
 241        CR_INTR_DMA0    = 0x00000001,
 242        CR_INTR_CREG    = 0x00000002,
 243        CR_INTR_DMA1    = 0x00000004,
 244        CR_INTR_EVENT   = 0x00000008,
 245        CR_INTR_DMA2    = 0x00000010,
 246        CR_INTR_DMA3    = 0x00000020,
 247        CR_INTR_DMA4    = 0x00000040,
 248        CR_INTR_DMA5    = 0x00000080,
 249        CR_INTR_DMA6    = 0x00000100,
 250        CR_INTR_DMA7    = 0x00000200,
 251        CR_INTR_ALL_C   = 0x0000003f,
 252        CR_INTR_ALL_G   = 0x000003ff,
 253        CR_INTR_DMA_ALL = 0x000003f5,
 254        CR_INTR_ALL     = 0xffffffff,
 255};
 256
 257static inline int CR_INTR_DMA(int N)
 258{
 259        static const unsigned int _CR_INTR_DMA[] = {
 260                CR_INTR_DMA0, CR_INTR_DMA1, CR_INTR_DMA2, CR_INTR_DMA3,
 261                CR_INTR_DMA4, CR_INTR_DMA5, CR_INTR_DMA6, CR_INTR_DMA7
 262        };
 263        return _CR_INTR_DMA[N];
 264}
 265enum rsxx_pci_reset {
 266        DMA_QUEUE_RESET         = 0x00000001,
 267};
 268
 269enum rsxx_hw_fifo_flush {
 270        RSXX_FLUSH_BUSY         = 0x00000002,
 271        RSXX_FLUSH_TIMEOUT      = 0x00000004,
 272};
 273
 274enum rsxx_pci_revision {
 275        RSXX_DISCARD_SUPPORT = 2,
 276        RSXX_EEH_SUPPORT     = 3,
 277};
 278
 279enum rsxx_creg_cmd {
 280        CREG_CMD_TAG_MASK       = 0x0000FF00,
 281        CREG_OP_WRITE           = 0x000000C0,
 282        CREG_OP_READ            = 0x000000E0,
 283};
 284
 285enum rsxx_creg_addr {
 286        CREG_ADD_CARD_CMD               = 0x80001000,
 287        CREG_ADD_CARD_STATE             = 0x80001004,
 288        CREG_ADD_CARD_SIZE              = 0x8000100c,
 289        CREG_ADD_CAPABILITIES           = 0x80001050,
 290        CREG_ADD_LOG                    = 0x80002000,
 291        CREG_ADD_NUM_TARGETS            = 0x80003000,
 292        CREG_ADD_CRAM                   = 0xA0000000,
 293        CREG_ADD_CONFIG                 = 0xB0000000,
 294};
 295
 296enum rsxx_creg_card_cmd {
 297        CARD_CMD_STARTUP                = 1,
 298        CARD_CMD_SHUTDOWN               = 2,
 299        CARD_CMD_LOW_LEVEL_FORMAT       = 3,
 300        CARD_CMD_FPGA_RECONFIG_BR       = 4,
 301        CARD_CMD_FPGA_RECONFIG_MAIN     = 5,
 302        CARD_CMD_BACKUP                 = 6,
 303        CARD_CMD_RESET                  = 7,
 304        CARD_CMD_deprecated             = 8,
 305        CARD_CMD_UNINITIALIZE           = 9,
 306        CARD_CMD_DSTROY_EMERGENCY       = 10,
 307        CARD_CMD_DSTROY_NORMAL          = 11,
 308        CARD_CMD_DSTROY_EXTENDED        = 12,
 309        CARD_CMD_DSTROY_ABORT           = 13,
 310};
 311
 312enum rsxx_card_state {
 313        CARD_STATE_SHUTDOWN             = 0x00000001,
 314        CARD_STATE_STARTING             = 0x00000002,
 315        CARD_STATE_FORMATTING           = 0x00000004,
 316        CARD_STATE_UNINITIALIZED        = 0x00000008,
 317        CARD_STATE_GOOD                 = 0x00000010,
 318        CARD_STATE_SHUTTING_DOWN        = 0x00000020,
 319        CARD_STATE_FAULT                = 0x00000040,
 320        CARD_STATE_RD_ONLY_FAULT        = 0x00000080,
 321        CARD_STATE_DSTROYING            = 0x00000100,
 322};
 323
 324enum rsxx_led {
 325        LED_DEFAULT     = 0x0,
 326        LED_IDENTIFY    = 0x1,
 327        LED_SOAK        = 0x2,
 328};
 329
 330enum rsxx_creg_flash_lock {
 331        CREG_FLASH_LOCK         = 1,
 332        CREG_FLASH_UNLOCK       = 2,
 333};
 334
 335enum rsxx_card_capabilities {
 336        CARD_CAP_SUBPAGE_WRITES = 0x00000080,
 337};
 338
 339enum rsxx_creg_stat {
 340        CREG_STAT_STATUS_MASK   = 0x00000003,
 341        CREG_STAT_SUCCESS       = 0x1,
 342        CREG_STAT_ERROR         = 0x2,
 343        CREG_STAT_CHAR_PENDING  = 0x00000004, /* Character I/O pending bit */
 344        CREG_STAT_LOG_PENDING   = 0x00000008, /* HW log message pending bit */
 345        CREG_STAT_TAG_MASK      = 0x0000ff00,
 346};
 347
 348enum rsxx_dma_finish {
 349        FREE_DMA        = 0x0,
 350        COMPLETE_DMA    = 0x1,
 351};
 352
 353static inline unsigned int CREG_DATA(int N)
 354{
 355        return CREG_DATA0 + (N << 2);
 356}
 357
 358/*----------------- Convenient Log Wrappers -------------------*/
 359#define CARD_TO_DEV(__CARD)     (&(__CARD)->dev->dev)
 360
 361/***** config.c *****/
 362int rsxx_load_config(struct rsxx_cardinfo *card);
 363
 364/***** core.c *****/
 365void rsxx_enable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 366void rsxx_disable_ier(struct rsxx_cardinfo *card, unsigned int intr);
 367void rsxx_enable_ier_and_isr(struct rsxx_cardinfo *card,
 368                                 unsigned int intr);
 369void rsxx_disable_ier_and_isr(struct rsxx_cardinfo *card,
 370                                  unsigned int intr);
 371
 372/***** dev.c *****/
 373int rsxx_attach_dev(struct rsxx_cardinfo *card);
 374void rsxx_detach_dev(struct rsxx_cardinfo *card);
 375int rsxx_setup_dev(struct rsxx_cardinfo *card);
 376void rsxx_destroy_dev(struct rsxx_cardinfo *card);
 377int rsxx_dev_init(void);
 378void rsxx_dev_cleanup(void);
 379
 380/***** dma.c ****/
 381typedef void (*rsxx_dma_cb)(struct rsxx_cardinfo *card,
 382                                void *cb_data,
 383                                unsigned int status);
 384int rsxx_dma_setup(struct rsxx_cardinfo *card);
 385void rsxx_dma_destroy(struct rsxx_cardinfo *card);
 386int rsxx_dma_init(void);
 387int rsxx_cleanup_dma_queue(struct rsxx_dma_ctrl *ctrl,
 388                                struct list_head *q,
 389                                unsigned int done);
 390int rsxx_dma_cancel(struct rsxx_dma_ctrl *ctrl);
 391void rsxx_dma_cleanup(void);
 392void rsxx_dma_queue_reset(struct rsxx_cardinfo *card);
 393int rsxx_dma_configure(struct rsxx_cardinfo *card);
 394int rsxx_dma_queue_bio(struct rsxx_cardinfo *card,
 395                           struct bio *bio,
 396                           atomic_t *n_dmas,
 397                           rsxx_dma_cb cb,
 398                           void *cb_data);
 399int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl);
 400int rsxx_eeh_save_issued_dmas(struct rsxx_cardinfo *card);
 401int rsxx_eeh_remap_dmas(struct rsxx_cardinfo *card);
 402
 403/***** cregs.c *****/
 404int rsxx_creg_write(struct rsxx_cardinfo *card, u32 addr,
 405                        unsigned int size8,
 406                        void *data,
 407                        int byte_stream);
 408int rsxx_creg_read(struct rsxx_cardinfo *card,
 409                       u32 addr,
 410                       unsigned int size8,
 411                       void *data,
 412                       int byte_stream);
 413int rsxx_read_hw_log(struct rsxx_cardinfo *card);
 414int rsxx_get_card_state(struct rsxx_cardinfo *card,
 415                            unsigned int *state);
 416int rsxx_get_card_size8(struct rsxx_cardinfo *card, u64 *size8);
 417int rsxx_get_num_targets(struct rsxx_cardinfo *card,
 418                             unsigned int *n_targets);
 419int rsxx_get_card_capabilities(struct rsxx_cardinfo *card,
 420                                   u32 *capabilities);
 421int rsxx_issue_card_cmd(struct rsxx_cardinfo *card, u32 cmd);
 422int rsxx_creg_setup(struct rsxx_cardinfo *card);
 423void rsxx_creg_destroy(struct rsxx_cardinfo *card);
 424int rsxx_creg_init(void);
 425void rsxx_creg_cleanup(void);
 426int rsxx_reg_access(struct rsxx_cardinfo *card,
 427                        struct rsxx_reg_access __user *ucmd,
 428                        int read);
 429void rsxx_eeh_save_issued_creg(struct rsxx_cardinfo *card);
 430void rsxx_kick_creg_queue(struct rsxx_cardinfo *card);
 431
 432
 433
 434#endif /* __DRIVERS_BLOCK_RSXX_H__ */
 435