LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.c

   1/*
   2 * Copyright 2013 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "nv40.h"
  25
  26static void
  27nv40_perfctr_init(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
  28                  struct nvkm_perfctr *ctr)
  29{
  30        struct nv40_pm_priv *priv = (void *)ppm;
  31        struct nv40_pm_cntr *cntr = (void *)ctr;
  32        u32 log = ctr->logic_op;
  33        u32 src = 0x00000000;
  34        int i;
  35
  36        for (i = 0; i < 4 && ctr->signal[i]; i++)
  37                src |= (ctr->signal[i] - dom->signal) << (i * 8);
  38
  39        nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001);
  40        nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
  41        nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
  42}
  43
  44static void
  45nv40_perfctr_read(struct nvkm_pm *ppm, struct nvkm_perfdom *dom,
  46                  struct nvkm_perfctr *ctr)
  47{
  48        struct nv40_pm_priv *priv = (void *)ppm;
  49        struct nv40_pm_cntr *cntr = (void *)ctr;
  50
  51        switch (cntr->base.slot) {
  52        case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break;
  53        case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break;
  54        case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break;
  55        case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break;
  56        }
  57        cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr);
  58}
  59
  60static void
  61nv40_perfctr_next(struct nvkm_pm *ppm, struct nvkm_perfdom *dom)
  62{
  63        struct nv40_pm_priv *priv = (void *)ppm;
  64        if (priv->sequence != ppm->sequence) {
  65                nv_wr32(priv, 0x400084, 0x00000020);
  66                priv->sequence = ppm->sequence;
  67        }
  68}
  69
  70const struct nvkm_funcdom
  71nv40_perfctr_func = {
  72        .init = nv40_perfctr_init,
  73        .read = nv40_perfctr_read,
  74        .next = nv40_perfctr_next,
  75};
  76
  77static const struct nvkm_specdom
  78nv40_pm[] = {
  79        { 0x20, (const struct nvkm_specsig[]) {
  80                        {}
  81                }, &nv40_perfctr_func },
  82        { 0x20, (const struct nvkm_specsig[]) {
  83                        {}
  84                }, &nv40_perfctr_func },
  85        { 0x20, (const struct nvkm_specsig[]) {
  86                        {}
  87                }, &nv40_perfctr_func },
  88        { 0x20, (const struct nvkm_specsig[]) {
  89                        {}
  90                }, &nv40_perfctr_func },
  91        { 0x20, (const struct nvkm_specsig[]) {
  92                        {}
  93                }, &nv40_perfctr_func },
  94        {}
  95};
  96
  97int
  98nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  99             struct nvkm_oclass *oclass, void *data, u32 size,
 100             struct nvkm_object **pobject)
 101{
 102        struct nv40_pm_oclass *mclass = (void *)oclass;
 103        struct nv40_pm_priv *priv;
 104        int ret;
 105
 106        ret = nvkm_pm_create(parent, engine, oclass, &priv);
 107        *pobject = nv_object(priv);
 108        if (ret)
 109                return ret;
 110
 111        ret = nvkm_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
 112        if (ret)
 113                return ret;
 114
 115        nv_engine(priv)->cclass = &nvkm_pm_cclass;
 116        nv_engine(priv)->sclass =  nvkm_pm_sclass;
 117        return 0;
 118}
 119
 120struct nvkm_oclass *
 121nv40_pm_oclass = &(struct nv40_pm_oclass) {
 122        .base.handle = NV_ENGINE(PM, 0x40),
 123        .base.ofuncs = &(struct nvkm_ofuncs) {
 124                .ctor = nv40_pm_ctor,
 125                .dtor = _nvkm_pm_dtor,
 126                .init = _nvkm_pm_init,
 127                .fini = _nvkm_pm_fini,
 128        },
 129        .doms = nv40_pm,
 130}.base;
 131