LXR linux/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c

   1/*
   2 * Copyright 2012 Nouveau Community
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Martin Peres <martin.peres@labri.fr>
  23 *          Ben Skeggs
  24 */
  25#include "nv04.h"
  26
  27static void
  28nv31_bus_intr(struct nvkm_subdev *subdev)
  29{
  30        struct nvkm_bus *pbus = nvkm_bus(subdev);
  31        u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
  32        u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
  33
  34        if (gpio) {
  35                subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_GPIO);
  36                if (subdev && subdev->intr)
  37                        subdev->intr(subdev);
  38        }
  39
  40        if (stat & 0x00000008) {  /* NV41- */
  41                u32 addr = nv_rd32(pbus, 0x009084);
  42                u32 data = nv_rd32(pbus, 0x009088);
  43
  44                nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
  45                         (addr & 0x00000002) ? "write" : "read", data,
  46                         (addr & 0x00fffffc));
  47
  48                stat &= ~0x00000008;
  49                nv_wr32(pbus, 0x001100, 0x00000008);
  50        }
  51
  52        if (stat & 0x00070000) {
  53                subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
  54                if (subdev && subdev->intr)
  55                        subdev->intr(subdev);
  56                stat &= ~0x00070000;
  57                nv_wr32(pbus, 0x001100, 0x00070000);
  58        }
  59
  60        if (stat) {
  61                nv_error(pbus, "unknown intr 0x%08x\n", stat);
  62                nv_mask(pbus, 0x001140, stat, 0x00000000);
  63        }
  64}
  65
  66static int
  67nv31_bus_init(struct nvkm_object *object)
  68{
  69        struct nv04_bus_priv *priv = (void *)object;
  70        int ret;
  71
  72        ret = nvkm_bus_init(&priv->base);
  73        if (ret)
  74                return ret;
  75
  76        nv_wr32(priv, 0x001100, 0xffffffff);
  77        nv_wr32(priv, 0x001140, 0x00070008);
  78        return 0;
  79}
  80
  81struct nvkm_oclass *
  82nv31_bus_oclass = &(struct nv04_bus_impl) {
  83        .base.handle = NV_SUBDEV(BUS, 0x31),
  84        .base.ofuncs = &(struct nvkm_ofuncs) {
  85                .ctor = nv04_bus_ctor,
  86                .dtor = _nvkm_bus_dtor,
  87                .init = nv31_bus_init,
  88                .fini = _nvkm_bus_fini,
  89        },
  90        .intr = nv31_bus_intr,
  91}.base;
  92