LXR linux/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "nv50.h"
  25
  26void
  27gk104_aux_stat(struct nvkm_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx)
  28{
  29        u32 intr = nv_rd32(i2c, 0x00dc60);
  30        u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i;
  31        for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) {
  32                if ((stat & (1 << (i * 4)))) *hi |= 1 << i;
  33                if ((stat & (2 << (i * 4)))) *lo |= 1 << i;
  34                if ((stat & (4 << (i * 4)))) *rq |= 1 << i;
  35                if ((stat & (8 << (i * 4)))) *tx |= 1 << i;
  36        }
  37        nv_wr32(i2c, 0x00dc60, intr);
  38}
  39
  40void
  41gk104_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data)
  42{
  43        u32 temp = nv_rd32(i2c, 0x00dc68), i;
  44        for (i = 0; i < 8; i++) {
  45                if (mask & (1 << i)) {
  46                        if (!(data & (1 << i))) {
  47                                temp &= ~(type << (i * 4));
  48                                continue;
  49                        }
  50                        temp |= type << (i * 4);
  51                }
  52        }
  53        nv_wr32(i2c, 0x00dc68, temp);
  54}
  55
  56struct nvkm_oclass *
  57gk104_i2c_oclass = &(struct nvkm_i2c_impl) {
  58        .base.handle = NV_SUBDEV(I2C, 0xe0),
  59        .base.ofuncs = &(struct nvkm_ofuncs) {
  60                .ctor = _nvkm_i2c_ctor,
  61                .dtor = _nvkm_i2c_dtor,
  62                .init = _nvkm_i2c_init,
  63                .fini = _nvkm_i2c_fini,
  64        },
  65        .sclass = gf110_i2c_sclass,
  66        .pad_x = &nv04_i2c_pad_oclass,
  67        .pad_s = &g94_i2c_pad_oclass,
  68        .aux = 4,
  69        .aux_stat = gk104_aux_stat,
  70        .aux_mask = gk104_aux_mask,
  71}.base;
  72