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15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23
24#include <asm/exception.h>
25#include <asm/hardirq.h>
26
27#include "irqchip.h"
28
29#define MAX_ICU_NR 16
30
31#define PJ1_INT_SEL 0x10c
32#define PJ4_INT_SEL 0x104
33
34
35#define SEL_INT_PENDING (1 << 6)
36#define SEL_INT_NUM_MASK 0x3f
37
38struct icu_chip_data {
39 int nr_irqs;
40 unsigned int virq_base;
41 unsigned int cascade_irq;
42 void __iomem *reg_status;
43 void __iomem *reg_mask;
44 unsigned int conf_enable;
45 unsigned int conf_disable;
46 unsigned int conf_mask;
47 unsigned int clr_mfp_irq_base;
48 unsigned int clr_mfp_hwirq;
49 struct irq_domain *domain;
50};
51
52struct mmp_intc_conf {
53 unsigned int conf_enable;
54 unsigned int conf_disable;
55 unsigned int conf_mask;
56};
57
58static void __iomem *mmp_icu_base;
59static struct icu_chip_data icu_data[MAX_ICU_NR];
60static int max_icu_nr;
61
62extern void mmp2_clear_pmic_int(void);
63
64static void icu_mask_ack_irq(struct irq_data *d)
65{
66 struct irq_domain *domain = d->domain;
67 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
68 int hwirq;
69 u32 r;
70
71 hwirq = d->irq - data->virq_base;
72 if (data == &icu_data[0]) {
73 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
74 r &= ~data->conf_mask;
75 r |= data->conf_disable;
76 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
77 } else {
78#ifdef CONFIG_CPU_MMP2
79 if ((data->virq_base == data->clr_mfp_irq_base)
80 && (hwirq == data->clr_mfp_hwirq))
81 mmp2_clear_pmic_int();
82#endif
83 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
84 writel_relaxed(r, data->reg_mask);
85 }
86}
87
88static void icu_mask_irq(struct irq_data *d)
89{
90 struct irq_domain *domain = d->domain;
91 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
92 int hwirq;
93 u32 r;
94
95 hwirq = d->irq - data->virq_base;
96 if (data == &icu_data[0]) {
97 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
98 r &= ~data->conf_mask;
99 r |= data->conf_disable;
100 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
101 } else {
102 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
103 writel_relaxed(r, data->reg_mask);
104 }
105}
106
107static void icu_unmask_irq(struct irq_data *d)
108{
109 struct irq_domain *domain = d->domain;
110 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
111 int hwirq;
112 u32 r;
113
114 hwirq = d->irq - data->virq_base;
115 if (data == &icu_data[0]) {
116 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
117 r &= ~data->conf_mask;
118 r |= data->conf_enable;
119 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
120 } else {
121 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
122 writel_relaxed(r, data->reg_mask);
123 }
124}
125
126struct irq_chip icu_irq_chip = {
127 .name = "icu_irq",
128 .irq_mask = icu_mask_irq,
129 .irq_mask_ack = icu_mask_ack_irq,
130 .irq_unmask = icu_unmask_irq,
131};
132
133static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
134{
135 struct irq_domain *domain;
136 struct icu_chip_data *data;
137 int i;
138 unsigned long mask, status, n;
139
140 for (i = 1; i < max_icu_nr; i++) {
141 if (irq == icu_data[i].cascade_irq) {
142 domain = icu_data[i].domain;
143 data = (struct icu_chip_data *)domain->host_data;
144 break;
145 }
146 }
147 if (i >= max_icu_nr) {
148 pr_err("Spurious irq %d in MMP INTC\n", irq);
149 return;
150 }
151
152 mask = readl_relaxed(data->reg_mask);
153 while (1) {
154 status = readl_relaxed(data->reg_status) & ~mask;
155 if (status == 0)
156 break;
157 for_each_set_bit(n, &status, BITS_PER_LONG) {
158 generic_handle_irq(icu_data[i].virq_base + n);
159 }
160 }
161}
162
163static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
164 irq_hw_number_t hw)
165{
166 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
167 set_irq_flags(irq, IRQF_VALID);
168 return 0;
169}
170
171static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
172 const u32 *intspec, unsigned int intsize,
173 unsigned long *out_hwirq,
174 unsigned int *out_type)
175{
176 *out_hwirq = intspec[0];
177 return 0;
178}
179
180const struct irq_domain_ops mmp_irq_domain_ops = {
181 .map = mmp_irq_domain_map,
182 .xlate = mmp_irq_domain_xlate,
183};
184
185static struct mmp_intc_conf mmp_conf = {
186 .conf_enable = 0x51,
187 .conf_disable = 0x0,
188 .conf_mask = 0x7f,
189};
190
191static struct mmp_intc_conf mmp2_conf = {
192 .conf_enable = 0x20,
193 .conf_disable = 0x0,
194 .conf_mask = 0x7f,
195};
196
197static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
198{
199 int hwirq;
200
201 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
202 if (!(hwirq & SEL_INT_PENDING))
203 return;
204 hwirq &= SEL_INT_NUM_MASK;
205 handle_domain_irq(icu_data[0].domain, hwirq, regs);
206}
207
208static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs)
209{
210 int hwirq;
211
212 hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
213 if (!(hwirq & SEL_INT_PENDING))
214 return;
215 hwirq &= SEL_INT_NUM_MASK;
216 handle_domain_irq(icu_data[0].domain, hwirq, regs);
217}
218
219
220void __init icu_init_irq(void)
221{
222 int irq;
223
224 max_icu_nr = 1;
225 mmp_icu_base = ioremap(0xd4282000, 0x1000);
226 icu_data[0].conf_enable = mmp_conf.conf_enable;
227 icu_data[0].conf_disable = mmp_conf.conf_disable;
228 icu_data[0].conf_mask = mmp_conf.conf_mask;
229 icu_data[0].nr_irqs = 64;
230 icu_data[0].virq_base = 0;
231 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
232 &irq_domain_simple_ops,
233 &icu_data[0]);
234 for (irq = 0; irq < 64; irq++) {
235 icu_mask_irq(irq_get_irq_data(irq));
236 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
237 set_irq_flags(irq, IRQF_VALID);
238 }
239 irq_set_default_host(icu_data[0].domain);
240 set_handle_irq(mmp_handle_irq);
241}
242
243
244void __init mmp2_init_icu(void)
245{
246 int irq, end;
247
248 max_icu_nr = 8;
249 mmp_icu_base = ioremap(0xd4282000, 0x1000);
250 icu_data[0].conf_enable = mmp2_conf.conf_enable;
251 icu_data[0].conf_disable = mmp2_conf.conf_disable;
252 icu_data[0].conf_mask = mmp2_conf.conf_mask;
253 icu_data[0].nr_irqs = 64;
254 icu_data[0].virq_base = 0;
255 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
256 &irq_domain_simple_ops,
257 &icu_data[0]);
258 icu_data[1].reg_status = mmp_icu_base + 0x150;
259 icu_data[1].reg_mask = mmp_icu_base + 0x168;
260 icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
261 icu_data[0].nr_irqs;
262 icu_data[1].clr_mfp_hwirq = 1;
263 icu_data[1].nr_irqs = 2;
264 icu_data[1].cascade_irq = 4;
265 icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
266 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
267 icu_data[1].virq_base, 0,
268 &irq_domain_simple_ops,
269 &icu_data[1]);
270 icu_data[2].reg_status = mmp_icu_base + 0x154;
271 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
272 icu_data[2].nr_irqs = 2;
273 icu_data[2].cascade_irq = 5;
274 icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
275 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
276 icu_data[2].virq_base, 0,
277 &irq_domain_simple_ops,
278 &icu_data[2]);
279 icu_data[3].reg_status = mmp_icu_base + 0x180;
280 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
281 icu_data[3].nr_irqs = 3;
282 icu_data[3].cascade_irq = 9;
283 icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
284 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
285 icu_data[3].virq_base, 0,
286 &irq_domain_simple_ops,
287 &icu_data[3]);
288 icu_data[4].reg_status = mmp_icu_base + 0x158;
289 icu_data[4].reg_mask = mmp_icu_base + 0x170;
290 icu_data[4].nr_irqs = 5;
291 icu_data[4].cascade_irq = 17;
292 icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
293 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
294 icu_data[4].virq_base, 0,
295 &irq_domain_simple_ops,
296 &icu_data[4]);
297 icu_data[5].reg_status = mmp_icu_base + 0x15c;
298 icu_data[5].reg_mask = mmp_icu_base + 0x174;
299 icu_data[5].nr_irqs = 15;
300 icu_data[5].cascade_irq = 35;
301 icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
302 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
303 icu_data[5].virq_base, 0,
304 &irq_domain_simple_ops,
305 &icu_data[5]);
306 icu_data[6].reg_status = mmp_icu_base + 0x160;
307 icu_data[6].reg_mask = mmp_icu_base + 0x178;
308 icu_data[6].nr_irqs = 2;
309 icu_data[6].cascade_irq = 51;
310 icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
311 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
312 icu_data[6].virq_base, 0,
313 &irq_domain_simple_ops,
314 &icu_data[6]);
315 icu_data[7].reg_status = mmp_icu_base + 0x188;
316 icu_data[7].reg_mask = mmp_icu_base + 0x184;
317 icu_data[7].nr_irqs = 2;
318 icu_data[7].cascade_irq = 55;
319 icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
320 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
321 icu_data[7].virq_base, 0,
322 &irq_domain_simple_ops,
323 &icu_data[7]);
324 end = icu_data[7].virq_base + icu_data[7].nr_irqs;
325 for (irq = 0; irq < end; irq++) {
326 icu_mask_irq(irq_get_irq_data(irq));
327 if (irq == icu_data[1].cascade_irq ||
328 irq == icu_data[2].cascade_irq ||
329 irq == icu_data[3].cascade_irq ||
330 irq == icu_data[4].cascade_irq ||
331 irq == icu_data[5].cascade_irq ||
332 irq == icu_data[6].cascade_irq ||
333 irq == icu_data[7].cascade_irq) {
334 irq_set_chip(irq, &icu_irq_chip);
335 irq_set_chained_handler(irq, icu_mux_irq_demux);
336 } else {
337 irq_set_chip_and_handler(irq, &icu_irq_chip,
338 handle_level_irq);
339 }
340 set_irq_flags(irq, IRQF_VALID);
341 }
342 irq_set_default_host(icu_data[0].domain);
343 set_handle_irq(mmp2_handle_irq);
344}
345
346#ifdef CONFIG_OF
347static int __init mmp_init_bases(struct device_node *node)
348{
349 int ret, nr_irqs, irq, i = 0;
350
351 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
352 if (ret) {
353 pr_err("Not found mrvl,intc-nr-irqs property\n");
354 return ret;
355 }
356
357 mmp_icu_base = of_iomap(node, 0);
358 if (!mmp_icu_base) {
359 pr_err("Failed to get interrupt controller register\n");
360 return -ENOMEM;
361 }
362
363 icu_data[0].virq_base = 0;
364 icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
365 &mmp_irq_domain_ops,
366 &icu_data[0]);
367 for (irq = 0; irq < nr_irqs; irq++) {
368 ret = irq_create_mapping(icu_data[0].domain, irq);
369 if (!ret) {
370 pr_err("Failed to mapping hwirq\n");
371 goto err;
372 }
373 if (!irq)
374 icu_data[0].virq_base = ret;
375 }
376 icu_data[0].nr_irqs = nr_irqs;
377 return 0;
378err:
379 if (icu_data[0].virq_base) {
380 for (i = 0; i < irq; i++)
381 irq_dispose_mapping(icu_data[0].virq_base + i);
382 }
383 irq_domain_remove(icu_data[0].domain);
384 iounmap(mmp_icu_base);
385 return -EINVAL;
386}
387
388static int __init mmp_of_init(struct device_node *node,
389 struct device_node *parent)
390{
391 int ret;
392
393 ret = mmp_init_bases(node);
394 if (ret < 0)
395 return ret;
396
397 icu_data[0].conf_enable = mmp_conf.conf_enable;
398 icu_data[0].conf_disable = mmp_conf.conf_disable;
399 icu_data[0].conf_mask = mmp_conf.conf_mask;
400 irq_set_default_host(icu_data[0].domain);
401 set_handle_irq(mmp_handle_irq);
402 max_icu_nr = 1;
403 return 0;
404}
405IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
406
407static int __init mmp2_of_init(struct device_node *node,
408 struct device_node *parent)
409{
410 int ret;
411
412 ret = mmp_init_bases(node);
413 if (ret < 0)
414 return ret;
415
416 icu_data[0].conf_enable = mmp2_conf.conf_enable;
417 icu_data[0].conf_disable = mmp2_conf.conf_disable;
418 icu_data[0].conf_mask = mmp2_conf.conf_mask;
419 irq_set_default_host(icu_data[0].domain);
420 set_handle_irq(mmp2_handle_irq);
421 max_icu_nr = 1;
422 return 0;
423}
424IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
425
426static int __init mmp2_mux_of_init(struct device_node *node,
427 struct device_node *parent)
428{
429 struct resource res;
430 int i, ret, irq, j = 0;
431 u32 nr_irqs, mfp_irq;
432
433 if (!parent)
434 return -ENODEV;
435
436 i = max_icu_nr;
437 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
438 &nr_irqs);
439 if (ret) {
440 pr_err("Not found mrvl,intc-nr-irqs property\n");
441 return -EINVAL;
442 }
443 ret = of_address_to_resource(node, 0, &res);
444 if (ret < 0) {
445 pr_err("Not found reg property\n");
446 return -EINVAL;
447 }
448 icu_data[i].reg_status = mmp_icu_base + res.start;
449 ret = of_address_to_resource(node, 1, &res);
450 if (ret < 0) {
451 pr_err("Not found reg property\n");
452 return -EINVAL;
453 }
454 icu_data[i].reg_mask = mmp_icu_base + res.start;
455 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
456 if (!icu_data[i].cascade_irq)
457 return -EINVAL;
458
459 icu_data[i].virq_base = 0;
460 icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
461 &mmp_irq_domain_ops,
462 &icu_data[i]);
463 for (irq = 0; irq < nr_irqs; irq++) {
464 ret = irq_create_mapping(icu_data[i].domain, irq);
465 if (!ret) {
466 pr_err("Failed to mapping hwirq\n");
467 goto err;
468 }
469 if (!irq)
470 icu_data[i].virq_base = ret;
471 }
472 icu_data[i].nr_irqs = nr_irqs;
473 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
474 &mfp_irq)) {
475 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
476 icu_data[i].clr_mfp_hwirq = mfp_irq;
477 }
478 irq_set_chained_handler(icu_data[i].cascade_irq,
479 icu_mux_irq_demux);
480 max_icu_nr++;
481 return 0;
482err:
483 if (icu_data[i].virq_base) {
484 for (j = 0; j < irq; j++)
485 irq_dispose_mapping(icu_data[i].virq_base + j);
486 }
487 irq_domain_remove(icu_data[i].domain);
488 return -EINVAL;
489}
490IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
491#endif
492
