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23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/delay.h>
31#include <linux/firmware.h>
32#include <linux/i2c.h>
33#include <linux/hardirq.h>
34#include <asm/div64.h>
35
36#include "dvb_frontend.h"
37#include "drxk.h"
38#include "drxk_hard.h"
39#include "dvb_math.h"
40
41static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
42static int power_down_qam(struct drxk_state *state);
43static int set_dvbt_standard(struct drxk_state *state,
44 enum operation_mode o_mode);
45static int set_qam_standard(struct drxk_state *state,
46 enum operation_mode o_mode);
47static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
48 s32 tuner_freq_offset);
49static int set_dvbt_standard(struct drxk_state *state,
50 enum operation_mode o_mode);
51static int dvbt_start(struct drxk_state *state);
52static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
53 s32 tuner_freq_offset);
54static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
55static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
56static int switch_antenna_to_qam(struct drxk_state *state);
57static int switch_antenna_to_dvbt(struct drxk_state *state);
58
59static bool is_dvbt(struct drxk_state *state)
60{
61 return state->m_operation_mode == OM_DVBT;
62}
63
64static bool is_qam(struct drxk_state *state)
65{
66 return state->m_operation_mode == OM_QAM_ITU_A ||
67 state->m_operation_mode == OM_QAM_ITU_B ||
68 state->m_operation_mode == OM_QAM_ITU_C;
69}
70
71#define NOA1ROM 0
72
73#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
74#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
75
76#define DEFAULT_MER_83 165
77#define DEFAULT_MER_93 250
78
79#ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
80#define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
81#endif
82
83#ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
84#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
85#endif
86
87#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
88#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
89
90#ifndef DRXK_KI_RAGC_ATV
91#define DRXK_KI_RAGC_ATV 4
92#endif
93#ifndef DRXK_KI_IAGC_ATV
94#define DRXK_KI_IAGC_ATV 6
95#endif
96#ifndef DRXK_KI_DAGC_ATV
97#define DRXK_KI_DAGC_ATV 7
98#endif
99
100#ifndef DRXK_KI_RAGC_QAM
101#define DRXK_KI_RAGC_QAM 3
102#endif
103#ifndef DRXK_KI_IAGC_QAM
104#define DRXK_KI_IAGC_QAM 4
105#endif
106#ifndef DRXK_KI_DAGC_QAM
107#define DRXK_KI_DAGC_QAM 7
108#endif
109#ifndef DRXK_KI_RAGC_DVBT
110#define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
111#endif
112#ifndef DRXK_KI_IAGC_DVBT
113#define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
114#endif
115#ifndef DRXK_KI_DAGC_DVBT
116#define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
117#endif
118
119#ifndef DRXK_AGC_DAC_OFFSET
120#define DRXK_AGC_DAC_OFFSET (0x800)
121#endif
122
123#ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
124#define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
125#endif
126
127#ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
128#define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
129#endif
130
131#ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
132#define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
133#endif
134
135#ifndef DRXK_QAM_SYMBOLRATE_MAX
136#define DRXK_QAM_SYMBOLRATE_MAX (7233000)
137#endif
138
139#define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
140#define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
141#define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
142#define DRXK_BL_ROM_OFFSET_TAPS_BG 24
143#define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
144#define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
145#define DRXK_BL_ROM_OFFSET_TAPS_FM 48
146#define DRXK_BL_ROM_OFFSET_UCODE 0
147
148#define DRXK_BLC_TIMEOUT 100
149
150#define DRXK_BLCC_NR_ELEMENTS_TAPS 2
151#define DRXK_BLCC_NR_ELEMENTS_UCODE 6
152
153#define DRXK_BLDC_NR_ELEMENTS_TAPS 28
154
155#ifndef DRXK_OFDM_NE_NOTCH_WIDTH
156#define DRXK_OFDM_NE_NOTCH_WIDTH (4)
157#endif
158
159#define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
160#define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
161#define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
162#define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
163#define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
164
165static unsigned int debug;
166module_param(debug, int, 0644);
167MODULE_PARM_DESC(debug, "enable debug messages");
168
169#define dprintk(level, fmt, arg...) do { \
170if (debug >= level) \
171 printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \
172} while (0)
173
174
175static inline u32 MulDiv32(u32 a, u32 b, u32 c)
176{
177 u64 tmp64;
178
179 tmp64 = (u64) a * (u64) b;
180 do_div(tmp64, c);
181
182 return (u32) tmp64;
183}
184
185static inline u32 Frac28a(u32 a, u32 c)
186{
187 int i = 0;
188 u32 Q1 = 0;
189 u32 R0 = 0;
190
191 R0 = (a % c) << 4;
192 Q1 = a / c;
193
194
195
196
197
198 for (i = 0; i < 7; i++) {
199 Q1 = (Q1 << 4) | (R0 / c);
200 R0 = (R0 % c) << 4;
201 }
202
203 if ((R0 >> 3) >= c)
204 Q1++;
205
206 return Q1;
207}
208
209static inline u32 log10times100(u32 value)
210{
211 return (100L * intlog10(value)) >> 24;
212}
213
214
215
216
217
218static int drxk_i2c_lock(struct drxk_state *state)
219{
220 i2c_lock_adapter(state->i2c);
221 state->drxk_i2c_exclusive_lock = true;
222
223 return 0;
224}
225
226static void drxk_i2c_unlock(struct drxk_state *state)
227{
228 if (!state->drxk_i2c_exclusive_lock)
229 return;
230
231 i2c_unlock_adapter(state->i2c);
232 state->drxk_i2c_exclusive_lock = false;
233}
234
235static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
236 unsigned len)
237{
238 if (state->drxk_i2c_exclusive_lock)
239 return __i2c_transfer(state->i2c, msgs, len);
240 else
241 return i2c_transfer(state->i2c, msgs, len);
242}
243
244static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
245{
246 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
247 .buf = val, .len = 1}
248 };
249
250 return drxk_i2c_transfer(state, msgs, 1);
251}
252
253static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
254{
255 int status;
256 struct i2c_msg msg = {
257 .addr = adr, .flags = 0, .buf = data, .len = len };
258
259 dprintk(3, ":");
260 if (debug > 2) {
261 int i;
262 for (i = 0; i < len; i++)
263 pr_cont(" %02x", data[i]);
264 pr_cont("\n");
265 }
266 status = drxk_i2c_transfer(state, &msg, 1);
267 if (status >= 0 && status != 1)
268 status = -EIO;
269
270 if (status < 0)
271 pr_err("i2c write error at addr 0x%02x\n", adr);
272
273 return status;
274}
275
276static int i2c_read(struct drxk_state *state,
277 u8 adr, u8 *msg, int len, u8 *answ, int alen)
278{
279 int status;
280 struct i2c_msg msgs[2] = {
281 {.addr = adr, .flags = 0,
282 .buf = msg, .len = len},
283 {.addr = adr, .flags = I2C_M_RD,
284 .buf = answ, .len = alen}
285 };
286
287 status = drxk_i2c_transfer(state, msgs, 2);
288 if (status != 2) {
289 if (debug > 2)
290 pr_cont(": ERROR!\n");
291 if (status >= 0)
292 status = -EIO;
293
294 pr_err("i2c read error at addr 0x%02x\n", adr);
295 return status;
296 }
297 if (debug > 2) {
298 int i;
299 dprintk(2, ": read from");
300 for (i = 0; i < len; i++)
301 pr_cont(" %02x", msg[i]);
302 pr_cont(", value = ");
303 for (i = 0; i < alen; i++)
304 pr_cont(" %02x", answ[i]);
305 pr_cont("\n");
306 }
307 return 0;
308}
309
310static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
311{
312 int status;
313 u8 adr = state->demod_address, mm1[4], mm2[2], len;
314
315 if (state->single_master)
316 flags |= 0xC0;
317
318 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
319 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
320 mm1[1] = ((reg >> 16) & 0xFF);
321 mm1[2] = ((reg >> 24) & 0xFF) | flags;
322 mm1[3] = ((reg >> 7) & 0xFF);
323 len = 4;
324 } else {
325 mm1[0] = ((reg << 1) & 0xFF);
326 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
327 len = 2;
328 }
329 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
330 status = i2c_read(state, adr, mm1, len, mm2, 2);
331 if (status < 0)
332 return status;
333 if (data)
334 *data = mm2[0] | (mm2[1] << 8);
335
336 return 0;
337}
338
339static int read16(struct drxk_state *state, u32 reg, u16 *data)
340{
341 return read16_flags(state, reg, data, 0);
342}
343
344static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
345{
346 int status;
347 u8 adr = state->demod_address, mm1[4], mm2[4], len;
348
349 if (state->single_master)
350 flags |= 0xC0;
351
352 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
353 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
354 mm1[1] = ((reg >> 16) & 0xFF);
355 mm1[2] = ((reg >> 24) & 0xFF) | flags;
356 mm1[3] = ((reg >> 7) & 0xFF);
357 len = 4;
358 } else {
359 mm1[0] = ((reg << 1) & 0xFF);
360 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
361 len = 2;
362 }
363 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
364 status = i2c_read(state, adr, mm1, len, mm2, 4);
365 if (status < 0)
366 return status;
367 if (data)
368 *data = mm2[0] | (mm2[1] << 8) |
369 (mm2[2] << 16) | (mm2[3] << 24);
370
371 return 0;
372}
373
374static int read32(struct drxk_state *state, u32 reg, u32 *data)
375{
376 return read32_flags(state, reg, data, 0);
377}
378
379static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
380{
381 u8 adr = state->demod_address, mm[6], len;
382
383 if (state->single_master)
384 flags |= 0xC0;
385 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
386 mm[0] = (((reg << 1) & 0xFF) | 0x01);
387 mm[1] = ((reg >> 16) & 0xFF);
388 mm[2] = ((reg >> 24) & 0xFF) | flags;
389 mm[3] = ((reg >> 7) & 0xFF);
390 len = 4;
391 } else {
392 mm[0] = ((reg << 1) & 0xFF);
393 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
394 len = 2;
395 }
396 mm[len] = data & 0xff;
397 mm[len + 1] = (data >> 8) & 0xff;
398
399 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
400 return i2c_write(state, adr, mm, len + 2);
401}
402
403static int write16(struct drxk_state *state, u32 reg, u16 data)
404{
405 return write16_flags(state, reg, data, 0);
406}
407
408static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
409{
410 u8 adr = state->demod_address, mm[8], len;
411
412 if (state->single_master)
413 flags |= 0xC0;
414 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
415 mm[0] = (((reg << 1) & 0xFF) | 0x01);
416 mm[1] = ((reg >> 16) & 0xFF);
417 mm[2] = ((reg >> 24) & 0xFF) | flags;
418 mm[3] = ((reg >> 7) & 0xFF);
419 len = 4;
420 } else {
421 mm[0] = ((reg << 1) & 0xFF);
422 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
423 len = 2;
424 }
425 mm[len] = data & 0xff;
426 mm[len + 1] = (data >> 8) & 0xff;
427 mm[len + 2] = (data >> 16) & 0xff;
428 mm[len + 3] = (data >> 24) & 0xff;
429 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
430
431 return i2c_write(state, adr, mm, len + 4);
432}
433
434static int write32(struct drxk_state *state, u32 reg, u32 data)
435{
436 return write32_flags(state, reg, data, 0);
437}
438
439static int write_block(struct drxk_state *state, u32 address,
440 const int block_size, const u8 p_block[])
441{
442 int status = 0, blk_size = block_size;
443 u8 flags = 0;
444
445 if (state->single_master)
446 flags |= 0xC0;
447
448 while (blk_size > 0) {
449 int chunk = blk_size > state->m_chunk_size ?
450 state->m_chunk_size : blk_size;
451 u8 *adr_buf = &state->chunk[0];
452 u32 adr_length = 0;
453
454 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
455 adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
456 adr_buf[1] = ((address >> 16) & 0xFF);
457 adr_buf[2] = ((address >> 24) & 0xFF);
458 adr_buf[3] = ((address >> 7) & 0xFF);
459 adr_buf[2] |= flags;
460 adr_length = 4;
461 if (chunk == state->m_chunk_size)
462 chunk -= 2;
463 } else {
464 adr_buf[0] = ((address << 1) & 0xFF);
465 adr_buf[1] = (((address >> 16) & 0x0F) |
466 ((address >> 18) & 0xF0));
467 adr_length = 2;
468 }
469 memcpy(&state->chunk[adr_length], p_block, chunk);
470 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
471 if (debug > 1) {
472 int i;
473 if (p_block)
474 for (i = 0; i < chunk; i++)
475 pr_cont(" %02x", p_block[i]);
476 pr_cont("\n");
477 }
478 status = i2c_write(state, state->demod_address,
479 &state->chunk[0], chunk + adr_length);
480 if (status < 0) {
481 pr_err("%s: i2c write error at addr 0x%02x\n",
482 __func__, address);
483 break;
484 }
485 p_block += chunk;
486 address += (chunk >> 1);
487 blk_size -= chunk;
488 }
489 return status;
490}
491
492#ifndef DRXK_MAX_RETRIES_POWERUP
493#define DRXK_MAX_RETRIES_POWERUP 20
494#endif
495
496static int power_up_device(struct drxk_state *state)
497{
498 int status;
499 u8 data = 0;
500 u16 retry_count = 0;
501
502 dprintk(1, "\n");
503
504 status = i2c_read1(state, state->demod_address, &data);
505 if (status < 0) {
506 do {
507 data = 0;
508 status = i2c_write(state, state->demod_address,
509 &data, 1);
510 usleep_range(10000, 11000);
511 retry_count++;
512 if (status < 0)
513 continue;
514 status = i2c_read1(state, state->demod_address,
515 &data);
516 } while (status < 0 &&
517 (retry_count < DRXK_MAX_RETRIES_POWERUP));
518 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
519 goto error;
520 }
521
522
523 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
524 if (status < 0)
525 goto error;
526 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
527 if (status < 0)
528 goto error;
529
530 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
531 if (status < 0)
532 goto error;
533
534 state->m_current_power_mode = DRX_POWER_UP;
535
536error:
537 if (status < 0)
538 pr_err("Error %d on %s\n", status, __func__);
539
540 return status;
541}
542
543
544static int init_state(struct drxk_state *state)
545{
546
547
548
549
550 u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
551 u32 ul_vsb_if_agc_output_level = 0;
552 u32 ul_vsb_if_agc_min_level = 0;
553 u32 ul_vsb_if_agc_max_level = 0x7FFF;
554 u32 ul_vsb_if_agc_speed = 3;
555
556 u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
557 u32 ul_vsb_rf_agc_output_level = 0;
558 u32 ul_vsb_rf_agc_min_level = 0;
559 u32 ul_vsb_rf_agc_max_level = 0x7FFF;
560 u32 ul_vsb_rf_agc_speed = 3;
561 u32 ul_vsb_rf_agc_top = 9500;
562 u32 ul_vsb_rf_agc_cut_off_current = 4000;
563
564 u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
565 u32 ul_atv_if_agc_output_level = 0;
566 u32 ul_atv_if_agc_min_level = 0;
567 u32 ul_atv_if_agc_max_level = 0;
568 u32 ul_atv_if_agc_speed = 3;
569
570 u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
571 u32 ul_atv_rf_agc_output_level = 0;
572 u32 ul_atv_rf_agc_min_level = 0;
573 u32 ul_atv_rf_agc_max_level = 0;
574 u32 ul_atv_rf_agc_top = 9500;
575 u32 ul_atv_rf_agc_cut_off_current = 4000;
576 u32 ul_atv_rf_agc_speed = 3;
577
578 u32 ulQual83 = DEFAULT_MER_83;
579 u32 ulQual93 = DEFAULT_MER_93;
580
581 u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
582 u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
583
584
585
586
587 u32 ul_gpio_cfg = 0x0113;
588 u32 ul_invert_ts_clock = 0;
589 u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
590 u32 ul_dvbt_bitrate = 50000000;
591 u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
592
593 u32 ul_insert_rs_byte = 0;
594
595 u32 ul_rf_mirror = 1;
596 u32 ul_power_down = 0;
597
598 dprintk(1, "\n");
599
600 state->m_has_lna = false;
601 state->m_has_dvbt = false;
602 state->m_has_dvbc = false;
603 state->m_has_atv = false;
604 state->m_has_oob = false;
605 state->m_has_audio = false;
606
607 if (!state->m_chunk_size)
608 state->m_chunk_size = 124;
609
610 state->m_osc_clock_freq = 0;
611 state->m_smart_ant_inverted = false;
612 state->m_b_p_down_open_bridge = false;
613
614
615 state->m_sys_clock_freq = 151875;
616
617
618 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
619 HI_I2C_DELAY) / 1000;
620
621 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
622 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
623 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
624
625 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
626
627 state->m_b_power_down = (ul_power_down != 0);
628
629 state->m_drxk_a3_patch_code = false;
630
631
632
633 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
634 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
635 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
636 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
637 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
638 state->m_vsb_pga_cfg = 140;
639
640
641 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
642 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
643 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
644 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
645 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
646 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
647 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
648 state->m_vsb_pre_saw_cfg.reference = 0x07;
649 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
650
651 state->m_Quality83percent = DEFAULT_MER_83;
652 state->m_Quality93percent = DEFAULT_MER_93;
653 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
654 state->m_Quality83percent = ulQual83;
655 state->m_Quality93percent = ulQual93;
656 }
657
658
659 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
660 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
661 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
662 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
663 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
664
665
666 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
667 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
668 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
669 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
670 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
671 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
672 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
673 state->m_atv_pre_saw_cfg.reference = 0x04;
674 state->m_atv_pre_saw_cfg.use_pre_saw = true;
675
676
677
678 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
679 state->m_dvbt_rf_agc_cfg.output_level = 0;
680 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
681 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
682 state->m_dvbt_rf_agc_cfg.top = 0x2100;
683 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
684 state->m_dvbt_rf_agc_cfg.speed = 1;
685
686
687
688 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
689 state->m_dvbt_if_agc_cfg.output_level = 0;
690 state->m_dvbt_if_agc_cfg.min_output_level = 0;
691 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
692 state->m_dvbt_if_agc_cfg.top = 13424;
693 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
694 state->m_dvbt_if_agc_cfg.speed = 3;
695 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
696 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
697
698
699 state->m_dvbt_pre_saw_cfg.reference = 4;
700 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
701
702
703 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
704 state->m_qam_rf_agc_cfg.output_level = 0;
705 state->m_qam_rf_agc_cfg.min_output_level = 6023;
706 state->m_qam_rf_agc_cfg.max_output_level = 27000;
707 state->m_qam_rf_agc_cfg.top = 0x2380;
708 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
709 state->m_qam_rf_agc_cfg.speed = 3;
710
711
712 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
713 state->m_qam_if_agc_cfg.output_level = 0;
714 state->m_qam_if_agc_cfg.min_output_level = 0;
715 state->m_qam_if_agc_cfg.max_output_level = 9000;
716 state->m_qam_if_agc_cfg.top = 0x0511;
717 state->m_qam_if_agc_cfg.cut_off_current = 0;
718 state->m_qam_if_agc_cfg.speed = 3;
719 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
720 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
721
722 state->m_qam_pga_cfg = 140;
723 state->m_qam_pre_saw_cfg.reference = 4;
724 state->m_qam_pre_saw_cfg.use_pre_saw = false;
725
726 state->m_operation_mode = OM_NONE;
727 state->m_drxk_state = DRXK_UNINITIALIZED;
728
729
730 state->m_enable_mpeg_output = true;
731 state->m_insert_rs_byte = false;
732 state->m_invert_data = false;
733 state->m_invert_err = false;
734 state->m_invert_str = false;
735 state->m_invert_val = false;
736 state->m_invert_clk = (ul_invert_ts_clock != 0);
737
738
739
740
741 state->m_dvbt_bitrate = ul_dvbt_bitrate;
742 state->m_dvbc_bitrate = ul_dvbc_bitrate;
743
744 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
745
746
747 state->m_mpeg_ts_static_bitrate = 19392658;
748 state->m_disable_te_ihandling = false;
749
750 if (ul_insert_rs_byte)
751 state->m_insert_rs_byte = true;
752
753 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
754 if (ul_mpeg_lock_time_out < 10000)
755 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
756 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
757 if (ul_demod_lock_time_out < 10000)
758 state->m_demod_lock_time_out = ul_demod_lock_time_out;
759
760
761 state->m_constellation = DRX_CONSTELLATION_AUTO;
762 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
763 state->m_fec_rs_plen = 204 * 8;
764 state->m_fec_rs_prescale = 1;
765
766 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
767 state->m_agcfast_clip_ctrl_delay = 0;
768
769 state->m_gpio_cfg = ul_gpio_cfg;
770
771 state->m_b_power_down = false;
772 state->m_current_power_mode = DRX_POWER_DOWN;
773
774 state->m_rfmirror = (ul_rf_mirror == 0);
775 state->m_if_agc_pol = false;
776 return 0;
777}
778
779static int drxx_open(struct drxk_state *state)
780{
781 int status = 0;
782 u32 jtag = 0;
783 u16 bid = 0;
784 u16 key = 0;
785
786 dprintk(1, "\n");
787
788 status = write16(state, SCU_RAM_GPIO__A,
789 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
790 if (status < 0)
791 goto error;
792
793 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
794 if (status < 0)
795 goto error;
796 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
797 if (status < 0)
798 goto error;
799 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
800 if (status < 0)
801 goto error;
802 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
803 if (status < 0)
804 goto error;
805 status = write16(state, SIO_TOP_COMM_KEY__A, key);
806error:
807 if (status < 0)
808 pr_err("Error %d on %s\n", status, __func__);
809 return status;
810}
811
812static int get_device_capabilities(struct drxk_state *state)
813{
814 u16 sio_pdr_ohw_cfg = 0;
815 u32 sio_top_jtagid_lo = 0;
816 int status;
817 const char *spin = "";
818
819 dprintk(1, "\n");
820
821
822
823 status = write16(state, SCU_RAM_GPIO__A,
824 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
825 if (status < 0)
826 goto error;
827 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
828 if (status < 0)
829 goto error;
830 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
831 if (status < 0)
832 goto error;
833 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
834 if (status < 0)
835 goto error;
836
837 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
838 case 0:
839
840 break;
841 case 1:
842
843 state->m_osc_clock_freq = 27000;
844 break;
845 case 2:
846
847 state->m_osc_clock_freq = 20250;
848 break;
849 case 3:
850
851 state->m_osc_clock_freq = 20250;
852 break;
853 default:
854 pr_err("Clock Frequency is unknown\n");
855 return -EINVAL;
856 }
857
858
859
860
861 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
862 if (status < 0)
863 goto error;
864
865 pr_info("status = 0x%08x\n", sio_top_jtagid_lo);
866
867
868 switch ((sio_top_jtagid_lo >> 29) & 0xF) {
869 case 0:
870 state->m_device_spin = DRXK_SPIN_A1;
871 spin = "A1";
872 break;
873 case 2:
874 state->m_device_spin = DRXK_SPIN_A2;
875 spin = "A2";
876 break;
877 case 3:
878 state->m_device_spin = DRXK_SPIN_A3;
879 spin = "A3";
880 break;
881 default:
882 state->m_device_spin = DRXK_SPIN_UNKNOWN;
883 status = -EINVAL;
884 pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF);
885 goto error2;
886 }
887 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
888 case 0x13:
889
890 state->m_has_lna = false;
891 state->m_has_oob = false;
892 state->m_has_atv = false;
893 state->m_has_audio = false;
894 state->m_has_dvbt = true;
895 state->m_has_dvbc = true;
896 state->m_has_sawsw = true;
897 state->m_has_gpio2 = false;
898 state->m_has_gpio1 = false;
899 state->m_has_irqn = false;
900 break;
901 case 0x15:
902
903 state->m_has_lna = false;
904 state->m_has_oob = false;
905 state->m_has_atv = true;
906 state->m_has_audio = false;
907 state->m_has_dvbt = true;
908 state->m_has_dvbc = false;
909 state->m_has_sawsw = true;
910 state->m_has_gpio2 = true;
911 state->m_has_gpio1 = true;
912 state->m_has_irqn = false;
913 break;
914 case 0x16:
915
916 state->m_has_lna = false;
917 state->m_has_oob = false;
918 state->m_has_atv = true;
919 state->m_has_audio = false;
920 state->m_has_dvbt = true;
921 state->m_has_dvbc = false;
922 state->m_has_sawsw = true;
923 state->m_has_gpio2 = true;
924 state->m_has_gpio1 = true;
925 state->m_has_irqn = false;
926 break;
927 case 0x18:
928
929 state->m_has_lna = false;
930 state->m_has_oob = false;
931 state->m_has_atv = true;
932 state->m_has_audio = true;
933 state->m_has_dvbt = true;
934 state->m_has_dvbc = false;
935 state->m_has_sawsw = true;
936 state->m_has_gpio2 = true;
937 state->m_has_gpio1 = true;
938 state->m_has_irqn = false;
939 break;
940 case 0x21:
941
942 state->m_has_lna = false;
943 state->m_has_oob = false;
944 state->m_has_atv = true;
945 state->m_has_audio = true;
946 state->m_has_dvbt = true;
947 state->m_has_dvbc = true;
948 state->m_has_sawsw = true;
949 state->m_has_gpio2 = true;
950 state->m_has_gpio1 = true;
951 state->m_has_irqn = false;
952 break;
953 case 0x23:
954
955 state->m_has_lna = false;
956 state->m_has_oob = false;
957 state->m_has_atv = true;
958 state->m_has_audio = true;
959 state->m_has_dvbt = true;
960 state->m_has_dvbc = true;
961 state->m_has_sawsw = true;
962 state->m_has_gpio2 = true;
963 state->m_has_gpio1 = true;
964 state->m_has_irqn = false;
965 break;
966 case 0x25:
967
968 state->m_has_lna = false;
969 state->m_has_oob = false;
970 state->m_has_atv = true;
971 state->m_has_audio = true;
972 state->m_has_dvbt = true;
973 state->m_has_dvbc = true;
974 state->m_has_sawsw = true;
975 state->m_has_gpio2 = true;
976 state->m_has_gpio1 = true;
977 state->m_has_irqn = false;
978 break;
979 case 0x26:
980
981 state->m_has_lna = false;
982 state->m_has_oob = false;
983 state->m_has_atv = true;
984 state->m_has_audio = false;
985 state->m_has_dvbt = true;
986 state->m_has_dvbc = true;
987 state->m_has_sawsw = true;
988 state->m_has_gpio2 = true;
989 state->m_has_gpio1 = true;
990 state->m_has_irqn = false;
991 break;
992 default:
993 pr_err("DeviceID 0x%02x not supported\n",
994 ((sio_top_jtagid_lo >> 12) & 0xFF));
995 status = -EINVAL;
996 goto error2;
997 }
998
999 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1000 ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
1001 state->m_osc_clock_freq / 1000,
1002 state->m_osc_clock_freq % 1000);
1003
1004error:
1005 if (status < 0)
1006 pr_err("Error %d on %s\n", status, __func__);
1007
1008error2:
1009 return status;
1010}
1011
1012static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
1013{
1014 int status;
1015 bool powerdown_cmd;
1016
1017 dprintk(1, "\n");
1018
1019
1020 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1021 if (status < 0)
1022 goto error;
1023 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1024 usleep_range(1000, 2000);
1025
1026 powerdown_cmd =
1027 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1028 ((state->m_hi_cfg_ctrl) &
1029 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1030 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1031 if (!powerdown_cmd) {
1032
1033 u32 retry_count = 0;
1034 u16 wait_cmd;
1035
1036 do {
1037 usleep_range(1000, 2000);
1038 retry_count += 1;
1039 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1040 &wait_cmd);
1041 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1042 && (wait_cmd != 0));
1043 if (status < 0)
1044 goto error;
1045 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1046 }
1047error:
1048 if (status < 0)
1049 pr_err("Error %d on %s\n", status, __func__);
1050
1051 return status;
1052}
1053
1054static int hi_cfg_command(struct drxk_state *state)
1055{
1056 int status;
1057
1058 dprintk(1, "\n");
1059
1060 mutex_lock(&state->mutex);
1061
1062 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1063 state->m_hi_cfg_timeout);
1064 if (status < 0)
1065 goto error;
1066 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1067 state->m_hi_cfg_ctrl);
1068 if (status < 0)
1069 goto error;
1070 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1071 state->m_hi_cfg_wake_up_key);
1072 if (status < 0)
1073 goto error;
1074 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1075 state->m_hi_cfg_bridge_delay);
1076 if (status < 0)
1077 goto error;
1078 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1079 state->m_hi_cfg_timing_div);
1080 if (status < 0)
1081 goto error;
1082 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1083 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1084 if (status < 0)
1085 goto error;
1086 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1087 if (status < 0)
1088 goto error;
1089
1090 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1091error:
1092 mutex_unlock(&state->mutex);
1093 if (status < 0)
1094 pr_err("Error %d on %s\n", status, __func__);
1095 return status;
1096}
1097
1098static int init_hi(struct drxk_state *state)
1099{
1100 dprintk(1, "\n");
1101
1102 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1103 state->m_hi_cfg_timeout = 0x96FF;
1104
1105 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1106
1107 return hi_cfg_command(state);
1108}
1109
1110static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1111{
1112 int status = -1;
1113 u16 sio_pdr_mclk_cfg = 0;
1114 u16 sio_pdr_mdx_cfg = 0;
1115 u16 err_cfg = 0;
1116
1117 dprintk(1, ": mpeg %s, %s mode\n",
1118 mpeg_enable ? "enable" : "disable",
1119 state->m_enable_parallel ? "parallel" : "serial");
1120
1121
1122 status = write16(state, SCU_RAM_GPIO__A,
1123 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1124 if (status < 0)
1125 goto error;
1126
1127
1128 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1129 if (status < 0)
1130 goto error;
1131
1132 if (!mpeg_enable) {
1133
1134 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1135 if (status < 0)
1136 goto error;
1137 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1138 if (status < 0)
1139 goto error;
1140 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1141 if (status < 0)
1142 goto error;
1143 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1144 if (status < 0)
1145 goto error;
1146 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1147 if (status < 0)
1148 goto error;
1149 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1150 if (status < 0)
1151 goto error;
1152 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1153 if (status < 0)
1154 goto error;
1155 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1156 if (status < 0)
1157 goto error;
1158 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1159 if (status < 0)
1160 goto error;
1161 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1162 if (status < 0)
1163 goto error;
1164 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1165 if (status < 0)
1166 goto error;
1167 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1168 if (status < 0)
1169 goto error;
1170 } else {
1171
1172 sio_pdr_mdx_cfg =
1173 ((state->m_ts_data_strength <<
1174 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1175 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1176 SIO_PDR_MCLK_CFG_DRIVE__B) |
1177 0x0003);
1178
1179 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1180 if (status < 0)
1181 goto error;
1182
1183 if (state->enable_merr_cfg)
1184 err_cfg = sio_pdr_mdx_cfg;
1185
1186 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1187 if (status < 0)
1188 goto error;
1189 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1190 if (status < 0)
1191 goto error;
1192
1193 if (state->m_enable_parallel) {
1194
1195 status = write16(state, SIO_PDR_MD1_CFG__A,
1196 sio_pdr_mdx_cfg);
1197 if (status < 0)
1198 goto error;
1199 status = write16(state, SIO_PDR_MD2_CFG__A,
1200 sio_pdr_mdx_cfg);
1201 if (status < 0)
1202 goto error;
1203 status = write16(state, SIO_PDR_MD3_CFG__A,
1204 sio_pdr_mdx_cfg);
1205 if (status < 0)
1206 goto error;
1207 status = write16(state, SIO_PDR_MD4_CFG__A,
1208 sio_pdr_mdx_cfg);
1209 if (status < 0)
1210 goto error;
1211 status = write16(state, SIO_PDR_MD5_CFG__A,
1212 sio_pdr_mdx_cfg);
1213 if (status < 0)
1214 goto error;
1215 status = write16(state, SIO_PDR_MD6_CFG__A,
1216 sio_pdr_mdx_cfg);
1217 if (status < 0)
1218 goto error;
1219 status = write16(state, SIO_PDR_MD7_CFG__A,
1220 sio_pdr_mdx_cfg);
1221 if (status < 0)
1222 goto error;
1223 } else {
1224 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1225 SIO_PDR_MD0_CFG_DRIVE__B)
1226 | 0x0003);
1227
1228 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1229 if (status < 0)
1230 goto error;
1231 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1232 if (status < 0)
1233 goto error;
1234 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1235 if (status < 0)
1236 goto error;
1237 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1238 if (status < 0)
1239 goto error;
1240 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1241 if (status < 0)
1242 goto error;
1243 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1244 if (status < 0)
1245 goto error;
1246 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1247 if (status < 0)
1248 goto error;
1249 }
1250 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1251 if (status < 0)
1252 goto error;
1253 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1254 if (status < 0)
1255 goto error;
1256 }
1257
1258 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1259 if (status < 0)
1260 goto error;
1261
1262 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1263error:
1264 if (status < 0)
1265 pr_err("Error %d on %s\n", status, __func__);
1266 return status;
1267}
1268
1269static int mpegts_disable(struct drxk_state *state)
1270{
1271 dprintk(1, "\n");
1272
1273 return mpegts_configure_pins(state, false);
1274}
1275
1276static int bl_chain_cmd(struct drxk_state *state,
1277 u16 rom_offset, u16 nr_of_elements, u32 time_out)
1278{
1279 u16 bl_status = 0;
1280 int status;
1281 unsigned long end;
1282
1283 dprintk(1, "\n");
1284 mutex_lock(&state->mutex);
1285 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1286 if (status < 0)
1287 goto error;
1288 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1289 if (status < 0)
1290 goto error;
1291 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1292 if (status < 0)
1293 goto error;
1294 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1295 if (status < 0)
1296 goto error;
1297
1298 end = jiffies + msecs_to_jiffies(time_out);
1299 do {
1300 usleep_range(1000, 2000);
1301 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1302 if (status < 0)
1303 goto error;
1304 } while ((bl_status == 0x1) &&
1305 ((time_is_after_jiffies(end))));
1306
1307 if (bl_status == 0x1) {
1308 pr_err("SIO not ready\n");
1309 status = -EINVAL;
1310 goto error2;
1311 }
1312error:
1313 if (status < 0)
1314 pr_err("Error %d on %s\n", status, __func__);
1315error2:
1316 mutex_unlock(&state->mutex);
1317 return status;
1318}
1319
1320
1321static int download_microcode(struct drxk_state *state,
1322 const u8 p_mc_image[], u32 length)
1323{
1324 const u8 *p_src = p_mc_image;
1325 u32 address;
1326 u16 n_blocks;
1327 u16 block_size;
1328 u32 offset = 0;
1329 u32 i;
1330 int status = 0;
1331
1332 dprintk(1, "\n");
1333
1334
1335#if 0
1336
1337 drain = (p_src[0] << 8) | p_src[1];
1338#endif
1339 p_src += sizeof(u16);
1340 offset += sizeof(u16);
1341 n_blocks = (p_src[0] << 8) | p_src[1];
1342 p_src += sizeof(u16);
1343 offset += sizeof(u16);
1344
1345 for (i = 0; i < n_blocks; i += 1) {
1346 address = (p_src[0] << 24) | (p_src[1] << 16) |
1347 (p_src[2] << 8) | p_src[3];
1348 p_src += sizeof(u32);
1349 offset += sizeof(u32);
1350
1351 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1352 p_src += sizeof(u16);
1353 offset += sizeof(u16);
1354
1355#if 0
1356
1357 flags = (p_src[0] << 8) | p_src[1];
1358#endif
1359 p_src += sizeof(u16);
1360 offset += sizeof(u16);
1361
1362#if 0
1363
1364 block_crc = (p_src[0] << 8) | p_src[1];
1365#endif
1366 p_src += sizeof(u16);
1367 offset += sizeof(u16);
1368
1369 if (offset + block_size > length) {
1370 pr_err("Firmware is corrupted.\n");
1371 return -EINVAL;
1372 }
1373
1374 status = write_block(state, address, block_size, p_src);
1375 if (status < 0) {
1376 pr_err("Error %d while loading firmware\n", status);
1377 break;
1378 }
1379 p_src += block_size;
1380 offset += block_size;
1381 }
1382 return status;
1383}
1384
1385static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1386{
1387 int status;
1388 u16 data = 0;
1389 u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1390 u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1391 unsigned long end;
1392
1393 dprintk(1, "\n");
1394
1395 if (!enable) {
1396 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1397 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1398 }
1399
1400 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1401 if (status >= 0 && data == desired_status) {
1402
1403 return status;
1404 }
1405
1406 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1407
1408 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1409 do {
1410 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1411 if ((status >= 0 && data == desired_status)
1412 || time_is_after_jiffies(end))
1413 break;
1414 usleep_range(1000, 2000);
1415 } while (1);
1416 if (data != desired_status) {
1417 pr_err("SIO not ready\n");
1418 return -EINVAL;
1419 }
1420 return status;
1421}
1422
1423static int mpegts_stop(struct drxk_state *state)
1424{
1425 int status = 0;
1426 u16 fec_oc_snc_mode = 0;
1427 u16 fec_oc_ipr_mode = 0;
1428
1429 dprintk(1, "\n");
1430
1431
1432 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1433 if (status < 0)
1434 goto error;
1435 fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1436 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1437 if (status < 0)
1438 goto error;
1439
1440
1441 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1442 if (status < 0)
1443 goto error;
1444 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1445 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1446
1447error:
1448 if (status < 0)
1449 pr_err("Error %d on %s\n", status, __func__);
1450
1451 return status;
1452}
1453
1454static int scu_command(struct drxk_state *state,
1455 u16 cmd, u8 parameter_len,
1456 u16 *parameter, u8 result_len, u16 *result)
1457{
1458#if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1459#error DRXK register mapping no longer compatible with this routine!
1460#endif
1461 u16 cur_cmd = 0;
1462 int status = -EINVAL;
1463 unsigned long end;
1464 u8 buffer[34];
1465 int cnt = 0, ii;
1466 const char *p;
1467 char errname[30];
1468
1469 dprintk(1, "\n");
1470
1471 if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1472 ((result_len > 0) && (result == NULL))) {
1473 pr_err("Error %d on %s\n", status, __func__);
1474 return status;
1475 }
1476
1477 mutex_lock(&state->mutex);
1478
1479
1480
1481 for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1482 buffer[cnt++] = (parameter[ii] & 0xFF);
1483 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1484 }
1485 buffer[cnt++] = (cmd & 0xFF);
1486 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1487
1488 write_block(state, SCU_RAM_PARAM_0__A -
1489 (parameter_len - 1), cnt, buffer);
1490
1491 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1492 do {
1493 usleep_range(1000, 2000);
1494 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1495 if (status < 0)
1496 goto error;
1497 } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1498 if (cur_cmd != DRX_SCU_READY) {
1499 pr_err("SCU not ready\n");
1500 status = -EIO;
1501 goto error2;
1502 }
1503
1504 if ((result_len > 0) && (result != NULL)) {
1505 s16 err;
1506 int ii;
1507
1508 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1509 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1510 &result[ii]);
1511 if (status < 0)
1512 goto error;
1513 }
1514
1515
1516 err = (s16)result[0];
1517 if (err >= 0)
1518 goto error;
1519
1520
1521 switch (err) {
1522 case SCU_RESULT_UNKCMD:
1523 p = "SCU_RESULT_UNKCMD";
1524 break;
1525 case SCU_RESULT_UNKSTD:
1526 p = "SCU_RESULT_UNKSTD";
1527 break;
1528 case SCU_RESULT_SIZE:
1529 p = "SCU_RESULT_SIZE";
1530 break;
1531 case SCU_RESULT_INVPAR:
1532 p = "SCU_RESULT_INVPAR";
1533 break;
1534 default:
1535 sprintf(errname, "ERROR: %d\n", err);
1536 p = errname;
1537 }
1538 pr_err("%s while sending cmd 0x%04x with params:", p, cmd);
1539 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1540 status = -EINVAL;
1541 goto error2;
1542 }
1543
1544error:
1545 if (status < 0)
1546 pr_err("Error %d on %s\n", status, __func__);
1547error2:
1548 mutex_unlock(&state->mutex);
1549 return status;
1550}
1551
1552static int set_iqm_af(struct drxk_state *state, bool active)
1553{
1554 u16 data = 0;
1555 int status;
1556
1557 dprintk(1, "\n");
1558
1559
1560 status = read16(state, IQM_AF_STDBY__A, &data);
1561 if (status < 0)
1562 goto error;
1563
1564 if (!active) {
1565 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1566 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1567 | IQM_AF_STDBY_STDBY_PD_STANDBY
1568 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1569 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1570 } else {
1571 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1572 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1573 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1574 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1575 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1576 );
1577 }
1578 status = write16(state, IQM_AF_STDBY__A, data);
1579
1580error:
1581 if (status < 0)
1582 pr_err("Error %d on %s\n", status, __func__);
1583 return status;
1584}
1585
1586static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1587{
1588 int status = 0;
1589 u16 sio_cc_pwd_mode = 0;
1590
1591 dprintk(1, "\n");
1592
1593
1594 if (mode == NULL)
1595 return -EINVAL;
1596
1597 switch (*mode) {
1598 case DRX_POWER_UP:
1599 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1600 break;
1601 case DRXK_POWER_DOWN_OFDM:
1602 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1603 break;
1604 case DRXK_POWER_DOWN_CORE:
1605 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1606 break;
1607 case DRXK_POWER_DOWN_PLL:
1608 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1609 break;
1610 case DRX_POWER_DOWN:
1611 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1612 break;
1613 default:
1614
1615 return -EINVAL;
1616 }
1617
1618
1619 if (state->m_current_power_mode == *mode)
1620 return 0;
1621
1622
1623 if (state->m_current_power_mode != DRX_POWER_UP) {
1624 status = power_up_device(state);
1625 if (status < 0)
1626 goto error;
1627 status = dvbt_enable_ofdm_token_ring(state, true);
1628 if (status < 0)
1629 goto error;
1630 }
1631
1632 if (*mode == DRX_POWER_UP) {
1633
1634 } else {
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644 switch (state->m_operation_mode) {
1645 case OM_DVBT:
1646 status = mpegts_stop(state);
1647 if (status < 0)
1648 goto error;
1649 status = power_down_dvbt(state, false);
1650 if (status < 0)
1651 goto error;
1652 break;
1653 case OM_QAM_ITU_A:
1654 case OM_QAM_ITU_C:
1655 status = mpegts_stop(state);
1656 if (status < 0)
1657 goto error;
1658 status = power_down_qam(state);
1659 if (status < 0)
1660 goto error;
1661 break;
1662 default:
1663 break;
1664 }
1665 status = dvbt_enable_ofdm_token_ring(state, false);
1666 if (status < 0)
1667 goto error;
1668 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1669 if (status < 0)
1670 goto error;
1671 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1672 if (status < 0)
1673 goto error;
1674
1675 if (*mode != DRXK_POWER_DOWN_OFDM) {
1676 state->m_hi_cfg_ctrl |=
1677 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1678 status = hi_cfg_command(state);
1679 if (status < 0)
1680 goto error;
1681 }
1682 }
1683 state->m_current_power_mode = *mode;
1684
1685error:
1686 if (status < 0)
1687 pr_err("Error %d on %s\n", status, __func__);
1688
1689 return status;
1690}
1691
1692static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1693{
1694 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1695 u16 cmd_result = 0;
1696 u16 data = 0;
1697 int status;
1698
1699 dprintk(1, "\n");
1700
1701 status = read16(state, SCU_COMM_EXEC__A, &data);
1702 if (status < 0)
1703 goto error;
1704 if (data == SCU_COMM_EXEC_ACTIVE) {
1705
1706 status = scu_command(state,
1707 SCU_RAM_COMMAND_STANDARD_OFDM
1708 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1709 0, NULL, 1, &cmd_result);
1710 if (status < 0)
1711 goto error;
1712
1713 status = scu_command(state,
1714 SCU_RAM_COMMAND_STANDARD_OFDM
1715 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1716 0, NULL, 1, &cmd_result);
1717 if (status < 0)
1718 goto error;
1719 }
1720
1721
1722 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1723 if (status < 0)
1724 goto error;
1725 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1726 if (status < 0)
1727 goto error;
1728 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1729 if (status < 0)
1730 goto error;
1731
1732
1733 status = set_iqm_af(state, false);
1734 if (status < 0)
1735 goto error;
1736
1737
1738 if (set_power_mode) {
1739 status = ctrl_power_mode(state, &power_mode);
1740 if (status < 0)
1741 goto error;
1742 }
1743error:
1744 if (status < 0)
1745 pr_err("Error %d on %s\n", status, __func__);
1746 return status;
1747}
1748
1749static int setoperation_mode(struct drxk_state *state,
1750 enum operation_mode o_mode)
1751{
1752 int status = 0;
1753
1754 dprintk(1, "\n");
1755
1756
1757
1758
1759
1760
1761
1762 status = write16(state, SCU_RAM_GPIO__A,
1763 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1764 if (status < 0)
1765 goto error;
1766
1767
1768 if (state->m_operation_mode == o_mode)
1769 return 0;
1770
1771 switch (state->m_operation_mode) {
1772
1773 case OM_NONE:
1774 break;
1775 case OM_DVBT:
1776 status = mpegts_stop(state);
1777 if (status < 0)
1778 goto error;
1779 status = power_down_dvbt(state, true);
1780 if (status < 0)
1781 goto error;
1782 state->m_operation_mode = OM_NONE;
1783 break;
1784 case OM_QAM_ITU_A:
1785 case OM_QAM_ITU_C:
1786 status = mpegts_stop(state);
1787 if (status < 0)
1788 goto error;
1789 status = power_down_qam(state);
1790 if (status < 0)
1791 goto error;
1792 state->m_operation_mode = OM_NONE;
1793 break;
1794 case OM_QAM_ITU_B:
1795 default:
1796 status = -EINVAL;
1797 goto error;
1798 }
1799
1800
1801
1802
1803 switch (o_mode) {
1804 case OM_DVBT:
1805 dprintk(1, ": DVB-T\n");
1806 state->m_operation_mode = o_mode;
1807 status = set_dvbt_standard(state, o_mode);
1808 if (status < 0)
1809 goto error;
1810 break;
1811 case OM_QAM_ITU_A:
1812 case OM_QAM_ITU_C:
1813 dprintk(1, ": DVB-C Annex %c\n",
1814 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1815 state->m_operation_mode = o_mode;
1816 status = set_qam_standard(state, o_mode);
1817 if (status < 0)
1818 goto error;
1819 break;
1820 case OM_QAM_ITU_B:
1821 default:
1822 status = -EINVAL;
1823 }
1824error:
1825 if (status < 0)
1826 pr_err("Error %d on %s\n", status, __func__);
1827 return status;
1828}
1829
1830static int start(struct drxk_state *state, s32 offset_freq,
1831 s32 intermediate_frequency)
1832{
1833 int status = -EINVAL;
1834
1835 u16 i_freqk_hz;
1836 s32 offsetk_hz = offset_freq / 1000;
1837
1838 dprintk(1, "\n");
1839 if (state->m_drxk_state != DRXK_STOPPED &&
1840 state->m_drxk_state != DRXK_DTV_STARTED)
1841 goto error;
1842
1843 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1844
1845 if (intermediate_frequency < 0) {
1846 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1847 intermediate_frequency = -intermediate_frequency;
1848 }
1849
1850 switch (state->m_operation_mode) {
1851 case OM_QAM_ITU_A:
1852 case OM_QAM_ITU_C:
1853 i_freqk_hz = (intermediate_frequency / 1000);
1854 status = set_qam(state, i_freqk_hz, offsetk_hz);
1855 if (status < 0)
1856 goto error;
1857 state->m_drxk_state = DRXK_DTV_STARTED;
1858 break;
1859 case OM_DVBT:
1860 i_freqk_hz = (intermediate_frequency / 1000);
1861 status = mpegts_stop(state);
1862 if (status < 0)
1863 goto error;
1864 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1865 if (status < 0)
1866 goto error;
1867 status = dvbt_start(state);
1868 if (status < 0)
1869 goto error;
1870 state->m_drxk_state = DRXK_DTV_STARTED;
1871 break;
1872 default:
1873 break;
1874 }
1875error:
1876 if (status < 0)
1877 pr_err("Error %d on %s\n", status, __func__);
1878 return status;
1879}
1880
1881static int shut_down(struct drxk_state *state)
1882{
1883 dprintk(1, "\n");
1884
1885 mpegts_stop(state);
1886 return 0;
1887}
1888
1889static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1890{
1891 int status = -EINVAL;
1892
1893 dprintk(1, "\n");
1894
1895 if (p_lock_status == NULL)
1896 goto error;
1897
1898 *p_lock_status = NOT_LOCKED;
1899
1900
1901 switch (state->m_operation_mode) {
1902 case OM_QAM_ITU_A:
1903 case OM_QAM_ITU_B:
1904 case OM_QAM_ITU_C:
1905 status = get_qam_lock_status(state, p_lock_status);
1906 break;
1907 case OM_DVBT:
1908 status = get_dvbt_lock_status(state, p_lock_status);
1909 break;
1910 default:
1911 break;
1912 }
1913error:
1914 if (status < 0)
1915 pr_err("Error %d on %s\n", status, __func__);
1916 return status;
1917}
1918
1919static int mpegts_start(struct drxk_state *state)
1920{
1921 int status;
1922
1923 u16 fec_oc_snc_mode = 0;
1924
1925
1926 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1927 if (status < 0)
1928 goto error;
1929 fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1930 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1931 if (status < 0)
1932 goto error;
1933 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1934error:
1935 if (status < 0)
1936 pr_err("Error %d on %s\n", status, __func__);
1937 return status;
1938}
1939
1940static int mpegts_dto_init(struct drxk_state *state)
1941{
1942 int status;
1943
1944 dprintk(1, "\n");
1945
1946
1947 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1948 if (status < 0)
1949 goto error;
1950 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1951 if (status < 0)
1952 goto error;
1953 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1954 if (status < 0)
1955 goto error;
1956 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1957 if (status < 0)
1958 goto error;
1959 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1960 if (status < 0)
1961 goto error;
1962 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1963 if (status < 0)
1964 goto error;
1965 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1966 if (status < 0)
1967 goto error;
1968 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1969 if (status < 0)
1970 goto error;
1971
1972
1973 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1974 if (status < 0)
1975 goto error;
1976 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1977 if (status < 0)
1978 goto error;
1979 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1980error:
1981 if (status < 0)
1982 pr_err("Error %d on %s\n", status, __func__);
1983
1984 return status;
1985}
1986
1987static int mpegts_dto_setup(struct drxk_state *state,
1988 enum operation_mode o_mode)
1989{
1990 int status;
1991
1992 u16 fec_oc_reg_mode = 0;
1993 u16 fec_oc_reg_ipr_mode = 0;
1994 u16 fec_oc_dto_mode = 0;
1995 u16 fec_oc_fct_mode = 0;
1996 u16 fec_oc_dto_period = 2;
1997 u16 fec_oc_dto_burst_len = 188;
1998 u32 fec_oc_rcn_ctl_rate = 0;
1999 u16 fec_oc_tmd_mode = 0;
2000 u16 fec_oc_tmd_int_upd_rate = 0;
2001 u32 max_bit_rate = 0;
2002 bool static_clk = false;
2003
2004 dprintk(1, "\n");
2005
2006
2007 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
2008 if (status < 0)
2009 goto error;
2010 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
2011 if (status < 0)
2012 goto error;
2013 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2014 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2015 if (state->m_insert_rs_byte) {
2016
2017 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2018
2019 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2020
2021 fec_oc_dto_burst_len = 204;
2022 }
2023
2024
2025 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2026 if (!state->m_enable_parallel) {
2027
2028 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2029 }
2030
2031 switch (o_mode) {
2032 case OM_DVBT:
2033 max_bit_rate = state->m_dvbt_bitrate;
2034 fec_oc_tmd_mode = 3;
2035 fec_oc_rcn_ctl_rate = 0xC00000;
2036 static_clk = state->m_dvbt_static_clk;
2037 break;
2038 case OM_QAM_ITU_A:
2039 case OM_QAM_ITU_C:
2040 fec_oc_tmd_mode = 0x0004;
2041 fec_oc_rcn_ctl_rate = 0xD2B4EE;
2042 max_bit_rate = state->m_dvbc_bitrate;
2043 static_clk = state->m_dvbc_static_clk;
2044 break;
2045 default:
2046 status = -EINVAL;
2047 }
2048 if (status < 0)
2049 goto error;
2050
2051
2052 if (static_clk) {
2053 u32 bit_rate = 0;
2054
2055
2056
2057
2058
2059 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2060 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2061 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2062 FEC_OC_FCT_MODE_VIRT_ENA__M);
2063
2064
2065 bit_rate = max_bit_rate;
2066 if (bit_rate > 75900000UL) {
2067 bit_rate = 75900000UL;
2068 }
2069
2070
2071
2072
2073
2074
2075 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2076 * 1000) / bit_rate);
2077 if (fec_oc_dto_period <= 2)
2078 fec_oc_dto_period = 0;
2079 else
2080 fec_oc_dto_period -= 2;
2081 fec_oc_tmd_int_upd_rate = 8;
2082 } else {
2083
2084 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2085 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2086 fec_oc_tmd_int_upd_rate = 5;
2087 }
2088
2089
2090 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2091 if (status < 0)
2092 goto error;
2093 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2094 if (status < 0)
2095 goto error;
2096 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2097 if (status < 0)
2098 goto error;
2099 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2100 if (status < 0)
2101 goto error;
2102 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2103 if (status < 0)
2104 goto error;
2105 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2106 if (status < 0)
2107 goto error;
2108
2109
2110 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2111 if (status < 0)
2112 goto error;
2113 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2114 fec_oc_tmd_int_upd_rate);
2115 if (status < 0)
2116 goto error;
2117 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2118error:
2119 if (status < 0)
2120 pr_err("Error %d on %s\n", status, __func__);
2121 return status;
2122}
2123
2124static int mpegts_configure_polarity(struct drxk_state *state)
2125{
2126 u16 fec_oc_reg_ipr_invert = 0;
2127
2128
2129 u16 invert_data_mask =
2130 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2131 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2132 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2133 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2134
2135 dprintk(1, "\n");
2136
2137
2138 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2139 if (state->m_invert_data)
2140 fec_oc_reg_ipr_invert |= invert_data_mask;
2141 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2142 if (state->m_invert_err)
2143 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2144 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2145 if (state->m_invert_str)
2146 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2147 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2148 if (state->m_invert_val)
2149 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2150 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2151 if (state->m_invert_clk)
2152 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2153
2154 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2155}
2156
2157#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2158
2159static int set_agc_rf(struct drxk_state *state,
2160 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2161{
2162 int status = -EINVAL;
2163 u16 data = 0;
2164 struct s_cfg_agc *p_if_agc_settings;
2165
2166 dprintk(1, "\n");
2167
2168 if (p_agc_cfg == NULL)
2169 goto error;
2170
2171 switch (p_agc_cfg->ctrl_mode) {
2172 case DRXK_AGC_CTRL_AUTO:
2173
2174 status = read16(state, IQM_AF_STDBY__A, &data);
2175 if (status < 0)
2176 goto error;
2177 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2178 status = write16(state, IQM_AF_STDBY__A, data);
2179 if (status < 0)
2180 goto error;
2181 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2182 if (status < 0)
2183 goto error;
2184
2185
2186 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2187
2188
2189 if (state->m_rf_agc_pol)
2190 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2191 else
2192 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2193 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2194 if (status < 0)
2195 goto error;
2196
2197
2198 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2199 if (status < 0)
2200 goto error;
2201
2202 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2203 data |= (~(p_agc_cfg->speed <<
2204 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2205 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2206
2207 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2208 if (status < 0)
2209 goto error;
2210
2211 if (is_dvbt(state))
2212 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2213 else if (is_qam(state))
2214 p_if_agc_settings = &state->m_qam_if_agc_cfg;
2215 else
2216 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2217 if (p_if_agc_settings == NULL) {
2218 status = -EINVAL;
2219 goto error;
2220 }
2221
2222
2223 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) {
2224 status = write16(state,
2225 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2226 p_agc_cfg->top);
2227 if (status < 0)
2228 goto error;
2229 }
2230
2231
2232 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2233 p_agc_cfg->cut_off_current);
2234 if (status < 0)
2235 goto error;
2236
2237
2238 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2239 p_agc_cfg->max_output_level);
2240 if (status < 0)
2241 goto error;
2242
2243 break;
2244
2245 case DRXK_AGC_CTRL_USER:
2246
2247 status = read16(state, IQM_AF_STDBY__A, &data);
2248 if (status < 0)
2249 goto error;
2250 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2251 status = write16(state, IQM_AF_STDBY__A, data);
2252 if (status < 0)
2253 goto error;
2254
2255
2256 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2257 if (status < 0)
2258 goto error;
2259 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2260 if (state->m_rf_agc_pol)
2261 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2262 else
2263 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2264 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2265 if (status < 0)
2266 goto error;
2267
2268
2269 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2270 if (status < 0)
2271 goto error;
2272
2273
2274 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2275 p_agc_cfg->output_level);
2276 if (status < 0)
2277 goto error;
2278 break;
2279
2280 case DRXK_AGC_CTRL_OFF:
2281
2282 status = read16(state, IQM_AF_STDBY__A, &data);
2283 if (status < 0)
2284 goto error;
2285 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2286 status = write16(state, IQM_AF_STDBY__A, data);
2287 if (status < 0)
2288 goto error;
2289
2290
2291 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2292 if (status < 0)
2293 goto error;
2294 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2295 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2296 if (status < 0)
2297 goto error;
2298 break;
2299
2300 default:
2301 status = -EINVAL;
2302
2303 }
2304error:
2305 if (status < 0)
2306 pr_err("Error %d on %s\n", status, __func__);
2307 return status;
2308}
2309
2310#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2311
2312static int set_agc_if(struct drxk_state *state,
2313 struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2314{
2315 u16 data = 0;
2316 int status = 0;
2317 struct s_cfg_agc *p_rf_agc_settings;
2318
2319 dprintk(1, "\n");
2320
2321 switch (p_agc_cfg->ctrl_mode) {
2322 case DRXK_AGC_CTRL_AUTO:
2323
2324
2325 status = read16(state, IQM_AF_STDBY__A, &data);
2326 if (status < 0)
2327 goto error;
2328 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2329 status = write16(state, IQM_AF_STDBY__A, data);
2330 if (status < 0)
2331 goto error;
2332
2333 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2334 if (status < 0)
2335 goto error;
2336
2337
2338 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2339
2340
2341 if (state->m_if_agc_pol)
2342 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2343 else
2344 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2345 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2346 if (status < 0)
2347 goto error;
2348
2349
2350 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2351 if (status < 0)
2352 goto error;
2353 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2354 data |= (~(p_agc_cfg->speed <<
2355 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2356 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2357
2358 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2359 if (status < 0)
2360 goto error;
2361
2362 if (is_qam(state))
2363 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2364 else
2365 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2366 if (p_rf_agc_settings == NULL)
2367 return -1;
2368
2369 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2370 p_rf_agc_settings->top);
2371 if (status < 0)
2372 goto error;
2373 break;
2374
2375 case DRXK_AGC_CTRL_USER:
2376
2377
2378 status = read16(state, IQM_AF_STDBY__A, &data);
2379 if (status < 0)
2380 goto error;
2381 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2382 status = write16(state, IQM_AF_STDBY__A, data);
2383 if (status < 0)
2384 goto error;
2385
2386 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2387 if (status < 0)
2388 goto error;
2389
2390
2391 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2392
2393
2394 if (state->m_if_agc_pol)
2395 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2396 else
2397 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2398 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2399 if (status < 0)
2400 goto error;
2401
2402
2403 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2404 p_agc_cfg->output_level);
2405 if (status < 0)
2406 goto error;
2407 break;
2408
2409 case DRXK_AGC_CTRL_OFF:
2410
2411
2412 status = read16(state, IQM_AF_STDBY__A, &data);
2413 if (status < 0)
2414 goto error;
2415 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2416 status = write16(state, IQM_AF_STDBY__A, data);
2417 if (status < 0)
2418 goto error;
2419
2420
2421 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2422 if (status < 0)
2423 goto error;
2424 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2425 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2426 if (status < 0)
2427 goto error;
2428 break;
2429 }
2430
2431
2432
2433 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2434error:
2435 if (status < 0)
2436 pr_err("Error %d on %s\n", status, __func__);
2437 return status;
2438}
2439
2440static int get_qam_signal_to_noise(struct drxk_state *state,
2441 s32 *p_signal_to_noise)
2442{
2443 int status = 0;
2444 u16 qam_sl_err_power = 0;
2445
2446 u32 qam_sl_sig_power = 0;
2447
2448 u32 qam_sl_mer = 0;
2449
2450 dprintk(1, "\n");
2451
2452
2453
2454
2455 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2456 if (status < 0) {
2457 pr_err("Error %d on %s\n", status, __func__);
2458 return -EINVAL;
2459 }
2460
2461 switch (state->props.modulation) {
2462 case QAM_16:
2463 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2464 break;
2465 case QAM_32:
2466 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2467 break;
2468 case QAM_64:
2469 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2470 break;
2471 case QAM_128:
2472 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2473 break;
2474 default:
2475 case QAM_256:
2476 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2477 break;
2478 }
2479
2480 if (qam_sl_err_power > 0) {
2481 qam_sl_mer = log10times100(qam_sl_sig_power) -
2482 log10times100((u32) qam_sl_err_power);
2483 }
2484 *p_signal_to_noise = qam_sl_mer;
2485
2486 return status;
2487}
2488
2489static int get_dvbt_signal_to_noise(struct drxk_state *state,
2490 s32 *p_signal_to_noise)
2491{
2492 int status;
2493 u16 reg_data = 0;
2494 u32 eq_reg_td_sqr_err_i = 0;
2495 u32 eq_reg_td_sqr_err_q = 0;
2496 u16 eq_reg_td_sqr_err_exp = 0;
2497 u16 eq_reg_td_tps_pwr_ofs = 0;
2498 u16 eq_reg_td_req_smb_cnt = 0;
2499 u32 tps_cnt = 0;
2500 u32 sqr_err_iq = 0;
2501 u32 a = 0;
2502 u32 b = 0;
2503 u32 c = 0;
2504 u32 i_mer = 0;
2505 u16 transmission_params = 0;
2506
2507 dprintk(1, "\n");
2508
2509 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2510 &eq_reg_td_tps_pwr_ofs);
2511 if (status < 0)
2512 goto error;
2513 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2514 &eq_reg_td_req_smb_cnt);
2515 if (status < 0)
2516 goto error;
2517 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2518 &eq_reg_td_sqr_err_exp);
2519 if (status < 0)
2520 goto error;
2521 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2522 ®_data);
2523 if (status < 0)
2524 goto error;
2525
2526 eq_reg_td_sqr_err_i = (u32) reg_data;
2527 if ((eq_reg_td_sqr_err_exp > 11) &&
2528 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2529 eq_reg_td_sqr_err_i += 0x00010000UL;
2530 }
2531 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2532 if (status < 0)
2533 goto error;
2534
2535 eq_reg_td_sqr_err_q = (u32) reg_data;
2536 if ((eq_reg_td_sqr_err_exp > 11) &&
2537 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2538 eq_reg_td_sqr_err_q += 0x00010000UL;
2539
2540 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2541 &transmission_params);
2542 if (status < 0)
2543 goto error;
2544
2545
2546
2547
2548 if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2549 i_mer = 0;
2550 else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2551
2552
2553
2554 i_mer = 0;
2555 } else {
2556 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2557 eq_reg_td_sqr_err_exp;
2558 if ((transmission_params &
2559 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2560 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2561 tps_cnt = 17;
2562 else
2563 tps_cnt = 68;
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576 a = log10times100(eq_reg_td_tps_pwr_ofs *
2577 eq_reg_td_tps_pwr_ofs);
2578
2579 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2580
2581 c = log10times100(sqr_err_iq);
2582
2583 i_mer = a + b - c;
2584 }
2585 *p_signal_to_noise = i_mer;
2586
2587error:
2588 if (status < 0)
2589 pr_err("Error %d on %s\n", status, __func__);
2590 return status;
2591}
2592
2593static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2594{
2595 dprintk(1, "\n");
2596
2597 *p_signal_to_noise = 0;
2598 switch (state->m_operation_mode) {
2599 case OM_DVBT:
2600 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2601 case OM_QAM_ITU_A:
2602 case OM_QAM_ITU_C:
2603 return get_qam_signal_to_noise(state, p_signal_to_noise);
2604 default:
2605 break;
2606 }
2607 return 0;
2608}
2609
2610#if 0
2611static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2612{
2613
2614 int status = 0;
2615
2616 dprintk(1, "\n");
2617
2618 static s32 QE_SN[] = {
2619 51,
2620 69,
2621 79,
2622 89,
2623 97,
2624 108,
2625 131,
2626 146,
2627 156,
2628 160,
2629 165,
2630 187,
2631 202,
2632 216,
2633 225,
2634 };
2635
2636 *p_quality = 0;
2637
2638 do {
2639 s32 signal_to_noise = 0;
2640 u16 constellation = 0;
2641 u16 code_rate = 0;
2642 u32 signal_to_noise_rel;
2643 u32 ber_quality;
2644
2645 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2646 if (status < 0)
2647 break;
2648 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2649 &constellation);
2650 if (status < 0)
2651 break;
2652 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2653
2654 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2655 &code_rate);
2656 if (status < 0)
2657 break;
2658 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2659
2660 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2661 code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2662 break;
2663 signal_to_noise_rel = signal_to_noise -
2664 QE_SN[constellation * 5 + code_rate];
2665 ber_quality = 100;
2666
2667 if (signal_to_noise_rel < -70)
2668 *p_quality = 0;
2669 else if (signal_to_noise_rel < 30)
2670 *p_quality = ((signal_to_noise_rel + 70) *
2671 ber_quality) / 100;
2672 else
2673 *p_quality = ber_quality;
2674 } while (0);
2675 return 0;
2676};
2677
2678static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2679{
2680 int status = 0;
2681 *p_quality = 0;
2682
2683 dprintk(1, "\n");
2684
2685 do {
2686 u32 signal_to_noise = 0;
2687 u32 ber_quality = 100;
2688 u32 signal_to_noise_rel = 0;
2689
2690 status = get_qam_signal_to_noise(state, &signal_to_noise);
2691 if (status < 0)
2692 break;
2693
2694 switch (state->props.modulation) {
2695 case QAM_16:
2696 signal_to_noise_rel = signal_to_noise - 200;
2697 break;
2698 case QAM_32:
2699 signal_to_noise_rel = signal_to_noise - 230;
2700 break;
2701 case QAM_64:
2702 signal_to_noise_rel = signal_to_noise - 260;
2703 break;
2704 case QAM_128:
2705 signal_to_noise_rel = signal_to_noise - 290;
2706 break;
2707 default:
2708 case QAM_256:
2709 signal_to_noise_rel = signal_to_noise - 320;
2710 break;
2711 }
2712
2713 if (signal_to_noise_rel < -70)
2714 *p_quality = 0;
2715 else if (signal_to_noise_rel < 30)
2716 *p_quality = ((signal_to_noise_rel + 70) *
2717 ber_quality) / 100;
2718 else
2719 *p_quality = ber_quality;
2720 } while (0);
2721
2722 return status;
2723}
2724
2725static int get_quality(struct drxk_state *state, s32 *p_quality)
2726{
2727 dprintk(1, "\n");
2728
2729 switch (state->m_operation_mode) {
2730 case OM_DVBT:
2731 return get_dvbt_quality(state, p_quality);
2732 case OM_QAM_ITU_A:
2733 return get_dvbc_quality(state, p_quality);
2734 default:
2735 break;
2736 }
2737
2738 return 0;
2739}
2740#endif
2741
2742
2743#define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2744#define SIO_HI_RA_RAM_USR_END__A 0x420060
2745
2746#define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2747#define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2748#define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2749#define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2750
2751#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2752#define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2753#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2754
2755static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2756{
2757 int status = -EINVAL;
2758
2759 dprintk(1, "\n");
2760
2761 if (state->m_drxk_state == DRXK_UNINITIALIZED)
2762 return 0;
2763 if (state->m_drxk_state == DRXK_POWERED_DOWN)
2764 goto error;
2765
2766 if (state->no_i2c_bridge)
2767 return 0;
2768
2769 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2770 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2771 if (status < 0)
2772 goto error;
2773 if (b_enable_bridge) {
2774 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2775 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2776 if (status < 0)
2777 goto error;
2778 } else {
2779 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2780 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2781 if (status < 0)
2782 goto error;
2783 }
2784
2785 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2786
2787error:
2788 if (status < 0)
2789 pr_err("Error %d on %s\n", status, __func__);
2790 return status;
2791}
2792
2793static int set_pre_saw(struct drxk_state *state,
2794 struct s_cfg_pre_saw *p_pre_saw_cfg)
2795{
2796 int status = -EINVAL;
2797
2798 dprintk(1, "\n");
2799
2800 if ((p_pre_saw_cfg == NULL)
2801 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2802 goto error;
2803
2804 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2805error:
2806 if (status < 0)
2807 pr_err("Error %d on %s\n", status, __func__);
2808 return status;
2809}
2810
2811static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2812 u16 rom_offset, u16 nr_of_elements, u32 time_out)
2813{
2814 u16 bl_status = 0;
2815 u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2816 u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2817 int status;
2818 unsigned long end;
2819
2820 dprintk(1, "\n");
2821
2822 mutex_lock(&state->mutex);
2823 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2824 if (status < 0)
2825 goto error;
2826 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2827 if (status < 0)
2828 goto error;
2829 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2830 if (status < 0)
2831 goto error;
2832 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2833 if (status < 0)
2834 goto error;
2835 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2836 if (status < 0)
2837 goto error;
2838 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2839 if (status < 0)
2840 goto error;
2841
2842 end = jiffies + msecs_to_jiffies(time_out);
2843 do {
2844 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2845 if (status < 0)
2846 goto error;
2847 } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2848 if (bl_status == 0x1) {
2849 pr_err("SIO not ready\n");
2850 status = -EINVAL;
2851 goto error2;
2852 }
2853error:
2854 if (status < 0)
2855 pr_err("Error %d on %s\n", status, __func__);
2856error2:
2857 mutex_unlock(&state->mutex);
2858 return status;
2859
2860}
2861
2862static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2863{
2864 u16 data = 0;
2865 int status;
2866
2867 dprintk(1, "\n");
2868
2869
2870 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2871 if (status < 0)
2872 goto error;
2873 status = write16(state, IQM_AF_START_LOCK__A, 1);
2874 if (status < 0)
2875 goto error;
2876
2877 *count = 0;
2878 status = read16(state, IQM_AF_PHASE0__A, &data);
2879 if (status < 0)
2880 goto error;
2881 if (data == 127)
2882 *count = *count + 1;
2883 status = read16(state, IQM_AF_PHASE1__A, &data);
2884 if (status < 0)
2885 goto error;
2886 if (data == 127)
2887 *count = *count + 1;
2888 status = read16(state, IQM_AF_PHASE2__A, &data);
2889 if (status < 0)
2890 goto error;
2891 if (data == 127)
2892 *count = *count + 1;
2893
2894error:
2895 if (status < 0)
2896 pr_err("Error %d on %s\n", status, __func__);
2897 return status;
2898}
2899
2900static int adc_synchronization(struct drxk_state *state)
2901{
2902 u16 count = 0;
2903 int status;
2904
2905 dprintk(1, "\n");
2906
2907 status = adc_sync_measurement(state, &count);
2908 if (status < 0)
2909 goto error;
2910
2911 if (count == 1) {
2912
2913 u16 clk_neg = 0;
2914
2915 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2916 if (status < 0)
2917 goto error;
2918 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2919 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2920 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2921 clk_neg |=
2922 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2923 } else {
2924 clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2925 clk_neg |=
2926 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2927 }
2928 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2929 if (status < 0)
2930 goto error;
2931 status = adc_sync_measurement(state, &count);
2932 if (status < 0)
2933 goto error;
2934 }
2935
2936 if (count < 2)
2937 status = -EINVAL;
2938error:
2939 if (status < 0)
2940 pr_err("Error %d on %s\n", status, __func__);
2941 return status;
2942}
2943
2944static int set_frequency_shifter(struct drxk_state *state,
2945 u16 intermediate_freqk_hz,
2946 s32 tuner_freq_offset, bool is_dtv)
2947{
2948 bool select_pos_image = false;
2949 u32 rf_freq_residual = tuner_freq_offset;
2950 u32 fm_frequency_shift = 0;
2951 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2952 u32 adc_freq;
2953 bool adc_flip;
2954 int status;
2955 u32 if_freq_actual;
2956 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2957 u32 frequency_shift;
2958 bool image_to_select;
2959
2960 dprintk(1, "\n");
2961
2962
2963
2964
2965
2966 if (is_dtv) {
2967 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2968 (state->m_operation_mode == OM_QAM_ITU_C) ||
2969 (state->m_operation_mode == OM_DVBT))
2970 select_pos_image = true;
2971 else
2972 select_pos_image = false;
2973 }
2974 if (tuner_mirror)
2975
2976 if_freq_actual = intermediate_freqk_hz +
2977 rf_freq_residual + fm_frequency_shift;
2978 else
2979
2980 if_freq_actual = intermediate_freqk_hz -
2981 rf_freq_residual - fm_frequency_shift;
2982 if (if_freq_actual > sampling_frequency / 2) {
2983
2984 adc_freq = sampling_frequency - if_freq_actual;
2985 adc_flip = true;
2986 } else {
2987
2988 adc_freq = if_freq_actual;
2989 adc_flip = false;
2990 }
2991
2992 frequency_shift = adc_freq;
2993 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2994 adc_flip ^ select_pos_image;
2995 state->m_iqm_fs_rate_ofs =
2996 Frac28a((frequency_shift), sampling_frequency);
2997
2998 if (image_to_select)
2999 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
3000
3001
3002
3003 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3004 state->m_iqm_fs_rate_ofs);
3005 if (status < 0)
3006 pr_err("Error %d on %s\n", status, __func__);
3007 return status;
3008}
3009
3010static int init_agc(struct drxk_state *state, bool is_dtv)
3011{
3012 u16 ingain_tgt = 0;
3013 u16 ingain_tgt_min = 0;
3014 u16 ingain_tgt_max = 0;
3015 u16 clp_cyclen = 0;
3016 u16 clp_sum_min = 0;
3017 u16 clp_dir_to = 0;
3018 u16 sns_sum_min = 0;
3019 u16 sns_sum_max = 0;
3020 u16 clp_sum_max = 0;
3021 u16 sns_dir_to = 0;
3022 u16 ki_innergain_min = 0;
3023 u16 if_iaccu_hi_tgt = 0;
3024 u16 if_iaccu_hi_tgt_min = 0;
3025 u16 if_iaccu_hi_tgt_max = 0;
3026 u16 data = 0;
3027 u16 fast_clp_ctrl_delay = 0;
3028 u16 clp_ctrl_mode = 0;
3029 int status = 0;
3030
3031 dprintk(1, "\n");
3032
3033
3034 sns_sum_max = 1023;
3035 if_iaccu_hi_tgt_min = 2047;
3036 clp_cyclen = 500;
3037 clp_sum_max = 1023;
3038
3039
3040 if (!is_qam(state)) {
3041 pr_err("%s: mode %d is not DVB-C\n",
3042 __func__, state->m_operation_mode);
3043 return -EINVAL;
3044 }
3045
3046
3047
3048
3049 clp_sum_min = 8;
3050 clp_dir_to = (u16) -9;
3051 clp_ctrl_mode = 0;
3052 sns_sum_min = 8;
3053 sns_dir_to = (u16) -9;
3054 ki_innergain_min = (u16) -1030;
3055 if_iaccu_hi_tgt_max = 0x2380;
3056 if_iaccu_hi_tgt = 0x2380;
3057 ingain_tgt_min = 0x0511;
3058 ingain_tgt = 0x0511;
3059 ingain_tgt_max = 5119;
3060 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3061
3062 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3063 fast_clp_ctrl_delay);
3064 if (status < 0)
3065 goto error;
3066
3067 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3068 if (status < 0)
3069 goto error;
3070 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3071 if (status < 0)
3072 goto error;
3073 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3074 if (status < 0)
3075 goto error;
3076 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3077 if (status < 0)
3078 goto error;
3079 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3080 if_iaccu_hi_tgt_min);
3081 if (status < 0)
3082 goto error;
3083 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3084 if_iaccu_hi_tgt_max);
3085 if (status < 0)
3086 goto error;
3087 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3088 if (status < 0)
3089 goto error;
3090 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3091 if (status < 0)
3092 goto error;
3093 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3094 if (status < 0)
3095 goto error;
3096 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3097 if (status < 0)
3098 goto error;
3099 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3100 if (status < 0)
3101 goto error;
3102 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3103 if (status < 0)
3104 goto error;
3105
3106 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3107 ki_innergain_min);
3108 if (status < 0)
3109 goto error;
3110 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3111 if_iaccu_hi_tgt);
3112 if (status < 0)
3113 goto error;
3114 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3115 if (status < 0)
3116 goto error;
3117
3118 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3119 if (status < 0)
3120 goto error;
3121 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3122 if (status < 0)
3123 goto error;
3124 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3125 if (status < 0)
3126 goto error;
3127
3128 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3129 if (status < 0)
3130 goto error;
3131 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3132 if (status < 0)
3133 goto error;
3134 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3135 if (status < 0)
3136 goto error;
3137 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3138 if (status < 0)
3139 goto error;
3140 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3141 if (status < 0)
3142 goto error;
3143 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3144 if (status < 0)
3145 goto error;
3146 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3147 if (status < 0)
3148 goto error;
3149 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3150 if (status < 0)
3151 goto error;
3152 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3153 if (status < 0)
3154 goto error;
3155 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3156 if (status < 0)
3157 goto error;
3158 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3159 if (status < 0)
3160 goto error;
3161 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3162 if (status < 0)
3163 goto error;
3164 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3165 if (status < 0)
3166 goto error;
3167 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3168 if (status < 0)
3169 goto error;
3170 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3171 if (status < 0)
3172 goto error;
3173 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3174 if (status < 0)
3175 goto error;
3176 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3177 if (status < 0)
3178 goto error;
3179 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3180 if (status < 0)
3181 goto error;
3182 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3183 if (status < 0)
3184 goto error;
3185
3186
3187 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3188 if (status < 0)
3189 goto error;
3190
3191 data = 0x0657;
3192 data &= ~SCU_RAM_AGC_KI_RF__M;
3193 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3194 data &= ~SCU_RAM_AGC_KI_IF__M;
3195 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3196
3197 status = write16(state, SCU_RAM_AGC_KI__A, data);
3198error:
3199 if (status < 0)
3200 pr_err("Error %d on %s\n", status, __func__);
3201 return status;
3202}
3203
3204static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3205{
3206 int status;
3207
3208 dprintk(1, "\n");
3209 if (packet_err == NULL)
3210 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3211 else
3212 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3213 packet_err);
3214 if (status < 0)
3215 pr_err("Error %d on %s\n", status, __func__);
3216 return status;
3217}
3218
3219static int dvbt_sc_command(struct drxk_state *state,
3220 u16 cmd, u16 subcmd,
3221 u16 param0, u16 param1, u16 param2,
3222 u16 param3, u16 param4)
3223{
3224 u16 cur_cmd = 0;
3225 u16 err_code = 0;
3226 u16 retry_cnt = 0;
3227 u16 sc_exec = 0;
3228 int status;
3229
3230 dprintk(1, "\n");
3231 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3232 if (sc_exec != 1) {
3233
3234 status = -EINVAL;
3235 }
3236 if (status < 0)
3237 goto error;
3238
3239
3240 retry_cnt = 0;
3241 do {
3242 usleep_range(1000, 2000);
3243 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3244 retry_cnt++;
3245 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3246 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3247 goto error;
3248
3249
3250 switch (cmd) {
3251
3252 case OFDM_SC_RA_RAM_CMD_PROC_START:
3253 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3254 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3255 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3256 if (status < 0)
3257 goto error;
3258 break;
3259 default:
3260
3261 break;
3262 }
3263
3264
3265 switch (cmd) {
3266
3267
3268
3269
3270 case OFDM_SC_RA_RAM_CMD_PROC_START:
3271 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3272 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3273 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3274
3275 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3276 case OFDM_SC_RA_RAM_CMD_USER_IO:
3277 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3278
3279 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3280 case OFDM_SC_RA_RAM_CMD_NULL:
3281
3282 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3283 break;
3284 default:
3285
3286 status = -EINVAL;
3287 }
3288 if (status < 0)
3289 goto error;
3290
3291
3292 retry_cnt = 0;
3293 do {
3294 usleep_range(1000, 2000);
3295 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3296 retry_cnt++;
3297 } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3298 if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3299 goto error;
3300
3301
3302 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3303 if (err_code == 0xFFFF) {
3304
3305 status = -EINVAL;
3306 }
3307 if (status < 0)
3308 goto error;
3309
3310
3311 switch (cmd) {
3312
3313
3314
3315
3316
3317 case OFDM_SC_RA_RAM_CMD_USER_IO:
3318 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3319 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3320
3321 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3322 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3323 case OFDM_SC_RA_RAM_CMD_PROC_START:
3324 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3325 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3326 case OFDM_SC_RA_RAM_CMD_NULL:
3327 break;
3328 default:
3329
3330 status = -EINVAL;
3331 break;
3332 }
3333error:
3334 if (status < 0)
3335 pr_err("Error %d on %s\n", status, __func__);
3336 return status;
3337}
3338
3339static int power_up_dvbt(struct drxk_state *state)
3340{
3341 enum drx_power_mode power_mode = DRX_POWER_UP;
3342 int status;
3343
3344 dprintk(1, "\n");
3345 status = ctrl_power_mode(state, &power_mode);
3346 if (status < 0)
3347 pr_err("Error %d on %s\n", status, __func__);
3348 return status;
3349}
3350
3351static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3352{
3353 int status;
3354
3355 dprintk(1, "\n");
3356 if (*enabled)
3357 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3358 else
3359 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3360 if (status < 0)
3361 pr_err("Error %d on %s\n", status, __func__);
3362 return status;
3363}
3364
3365#define DEFAULT_FR_THRES_8K 4000
3366static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3367{
3368
3369 int status;
3370
3371 dprintk(1, "\n");
3372 if (*enabled) {
3373
3374 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3375 DEFAULT_FR_THRES_8K);
3376 } else {
3377
3378 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3379 }
3380 if (status < 0)
3381 pr_err("Error %d on %s\n", status, __func__);
3382
3383 return status;
3384}
3385
3386static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3387 struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3388{
3389 u16 data = 0;
3390 int status;
3391
3392 dprintk(1, "\n");
3393 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3394 if (status < 0)
3395 goto error;
3396
3397 switch (echo_thres->fft_mode) {
3398 case DRX_FFTMODE_2K:
3399 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3400 data |= ((echo_thres->threshold <<
3401 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3402 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3403 break;
3404 case DRX_FFTMODE_8K:
3405 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3406 data |= ((echo_thres->threshold <<
3407 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3408 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3409 break;
3410 default:
3411 return -EINVAL;
3412 }
3413
3414 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3415error:
3416 if (status < 0)
3417 pr_err("Error %d on %s\n", status, __func__);
3418 return status;
3419}
3420
3421static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3422 enum drxk_cfg_dvbt_sqi_speed *speed)
3423{
3424 int status = -EINVAL;
3425
3426 dprintk(1, "\n");
3427
3428 switch (*speed) {
3429 case DRXK_DVBT_SQI_SPEED_FAST:
3430 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3431 case DRXK_DVBT_SQI_SPEED_SLOW:
3432 break;
3433 default:
3434 goto error;
3435 }
3436 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3437 (u16) *speed);
3438error:
3439 if (status < 0)
3440 pr_err("Error %d on %s\n", status, __func__);
3441 return status;
3442}
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454static int dvbt_activate_presets(struct drxk_state *state)
3455{
3456 int status;
3457 bool setincenable = false;
3458 bool setfrenable = true;
3459
3460 struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3461 struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3462
3463 dprintk(1, "\n");
3464 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3465 if (status < 0)
3466 goto error;
3467 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3468 if (status < 0)
3469 goto error;
3470 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3471 if (status < 0)
3472 goto error;
3473 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3474 if (status < 0)
3475 goto error;
3476 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3477 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3478error:
3479 if (status < 0)
3480 pr_err("Error %d on %s\n", status, __func__);
3481 return status;
3482}
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494static int set_dvbt_standard(struct drxk_state *state,
3495 enum operation_mode o_mode)
3496{
3497 u16 cmd_result = 0;
3498 u16 data = 0;
3499 int status;
3500
3501 dprintk(1, "\n");
3502
3503 power_up_dvbt(state);
3504
3505 switch_antenna_to_dvbt(state);
3506
3507 status = scu_command(state,
3508 SCU_RAM_COMMAND_STANDARD_OFDM
3509 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
3510 0, NULL, 1, &cmd_result);
3511 if (status < 0)
3512 goto error;
3513
3514
3515 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3516 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
3517 0, NULL, 1, &cmd_result);
3518 if (status < 0)
3519 goto error;
3520
3521
3522 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3523 if (status < 0)
3524 goto error;
3525 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3526 if (status < 0)
3527 goto error;
3528 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3529 if (status < 0)
3530 goto error;
3531
3532
3533
3534 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3535 if (status < 0)
3536 goto error;
3537
3538 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3539 if (status < 0)
3540 goto error;
3541
3542 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3543 if (status < 0)
3544 goto error;
3545
3546 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3547 if (status < 0)
3548 goto error;
3549 status = set_iqm_af(state, true);
3550 if (status < 0)
3551 goto error;
3552
3553 status = write16(state, IQM_AF_AGC_RF__A, 0);
3554 if (status < 0)
3555 goto error;
3556
3557
3558 status = write16(state, IQM_AF_INC_LCT__A, 0);
3559 if (status < 0)
3560 goto error;
3561 status = write16(state, IQM_CF_DET_LCT__A, 0);
3562 if (status < 0)
3563 goto error;
3564 status = write16(state, IQM_CF_WND_LEN__A, 3);
3565 if (status < 0)
3566 goto error;
3567
3568 status = write16(state, IQM_RC_STRETCH__A, 16);
3569 if (status < 0)
3570 goto error;
3571 status = write16(state, IQM_CF_OUT_ENA__A, 0x4);
3572 if (status < 0)
3573 goto error;
3574 status = write16(state, IQM_CF_DS_ENA__A, 0x4);
3575 if (status < 0)
3576 goto error;
3577 status = write16(state, IQM_CF_SCALE__A, 1600);
3578 if (status < 0)
3579 goto error;
3580 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3581 if (status < 0)
3582 goto error;
3583
3584
3585 status = write16(state, IQM_AF_CLP_TH__A, 448);
3586 if (status < 0)
3587 goto error;
3588 status = write16(state, IQM_CF_DATATH__A, 495);
3589 if (status < 0)
3590 goto error;
3591
3592 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3593 DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3594 if (status < 0)
3595 goto error;
3596
3597 status = write16(state, IQM_CF_PKDTH__A, 2);
3598 if (status < 0)
3599 goto error;
3600 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3601 if (status < 0)
3602 goto error;
3603
3604 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3605 if (status < 0)
3606 goto error;
3607 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3608 if (status < 0)
3609 goto error;
3610
3611
3612 status = adc_synchronization(state);
3613 if (status < 0)
3614 goto error;
3615 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3616 if (status < 0)
3617 goto error;
3618
3619
3620 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3621 if (status < 0)
3622 goto error;
3623
3624 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3625 if (status < 0)
3626 goto error;
3627 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3628 if (status < 0)
3629 goto error;
3630
3631
3632 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3633 if (status < 0)
3634 goto error;
3635 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3636 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3637 if (status < 0)
3638 goto error;
3639
3640
3641 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3642 if (status < 0)
3643 goto error;
3644
3645 if (!state->m_drxk_a3_rom_code) {
3646
3647 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3648 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3649 if (status < 0)
3650 goto error;
3651 }
3652
3653
3654#ifdef COMPILE_FOR_NONRT
3655 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3656 if (status < 0)
3657 goto error;
3658 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3659 if (status < 0)
3660 goto error;
3661#endif
3662
3663
3664 status = write16(state, FEC_DI_INPUT_CTL__A, 1);
3665 if (status < 0)
3666 goto error;
3667
3668
3669#ifdef COMPILE_FOR_NONRT
3670 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3671 if (status < 0)
3672 goto error;
3673#else
3674 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3675 if (status < 0)
3676 goto error;
3677#endif
3678 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3679 if (status < 0)
3680 goto error;
3681
3682
3683 status = mpegts_dto_setup(state, OM_DVBT);
3684 if (status < 0)
3685 goto error;
3686
3687 status = dvbt_activate_presets(state);
3688 if (status < 0)
3689 goto error;
3690
3691error:
3692 if (status < 0)
3693 pr_err("Error %d on %s\n", status, __func__);
3694 return status;
3695}
3696
3697
3698
3699
3700
3701
3702
3703static int dvbt_start(struct drxk_state *state)
3704{
3705 u16 param1;
3706 int status;
3707
3708
3709 dprintk(1, "\n");
3710
3711
3712 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3713 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3714 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
3715 0, 0, 0);
3716 if (status < 0)
3717 goto error;
3718
3719 status = mpegts_start(state);
3720 if (status < 0)
3721 goto error;
3722 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3723 if (status < 0)
3724 goto error;
3725error:
3726 if (status < 0)
3727 pr_err("Error %d on %s\n", status, __func__);
3728 return status;
3729}
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3741 s32 tuner_freq_offset)
3742{
3743 u16 cmd_result = 0;
3744 u16 transmission_params = 0;
3745 u16 operation_mode = 0;
3746 u32 iqm_rc_rate_ofs = 0;
3747 u32 bandwidth = 0;
3748 u16 param1;
3749 int status;
3750
3751 dprintk(1, "IF =%d, TFO = %d\n",
3752 intermediate_freqk_hz, tuner_freq_offset);
3753
3754 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3755 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
3756 0, NULL, 1, &cmd_result);
3757 if (status < 0)
3758 goto error;
3759
3760
3761 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3762 if (status < 0)
3763 goto error;
3764
3765
3766 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3767 if (status < 0)
3768 goto error;
3769 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3770 if (status < 0)
3771 goto error;
3772
3773
3774
3775 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3776 if (status < 0)
3777 goto error;
3778
3779
3780
3781
3782 switch (state->props.transmission_mode) {
3783 case TRANSMISSION_MODE_AUTO:
3784 default:
3785 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3786
3787 case TRANSMISSION_MODE_8K:
3788 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3789 break;
3790 case TRANSMISSION_MODE_2K:
3791 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3792 break;
3793 }
3794
3795
3796 switch (state->props.guard_interval) {
3797 default:
3798 case GUARD_INTERVAL_AUTO:
3799 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3800
3801 case GUARD_INTERVAL_1_4:
3802 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3803 break;
3804 case GUARD_INTERVAL_1_32:
3805 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3806 break;
3807 case GUARD_INTERVAL_1_16:
3808 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3809 break;
3810 case GUARD_INTERVAL_1_8:
3811 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3812 break;
3813 }
3814
3815
3816 switch (state->props.hierarchy) {
3817 case HIERARCHY_AUTO:
3818 case HIERARCHY_NONE:
3819 default:
3820 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3821
3822
3823
3824 case HIERARCHY_1:
3825 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3826 break;
3827 case HIERARCHY_2:
3828 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3829 break;
3830 case HIERARCHY_4:
3831 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3832 break;
3833 }
3834
3835
3836
3837 switch (state->props.modulation) {
3838 case QAM_AUTO:
3839 default:
3840 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3841
3842 case QAM_64:
3843 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3844 break;
3845 case QPSK:
3846 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3847 break;
3848 case QAM_16:
3849 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3850 break;
3851 }
3852#if 0
3853
3854
3855 switch (channel->priority) {
3856 case DRX_PRIORITY_LOW:
3857 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3858 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3859 OFDM_EC_SB_PRIOR_LO);
3860 break;
3861 case DRX_PRIORITY_HIGH:
3862 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3863 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3864 OFDM_EC_SB_PRIOR_HI));
3865 break;
3866 case DRX_PRIORITY_UNKNOWN:
3867 default:
3868 status = -EINVAL;
3869 goto error;
3870 }
3871#else
3872
3873 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3874 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3875 if (status < 0)
3876 goto error;
3877#endif
3878
3879
3880 switch (state->props.code_rate_HP) {
3881 case FEC_AUTO:
3882 default:
3883 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3884
3885 case FEC_2_3:
3886 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3887 break;
3888 case FEC_1_2:
3889 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3890 break;
3891 case FEC_3_4:
3892 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3893 break;
3894 case FEC_5_6:
3895 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3896 break;
3897 case FEC_7_8:
3898 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3899 break;
3900 }
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915 switch (state->props.bandwidth_hz) {
3916 case 0:
3917 state->props.bandwidth_hz = 8000000;
3918
3919 case 8000000:
3920 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3921 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3922 3052);
3923 if (status < 0)
3924 goto error;
3925
3926 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3927 7);
3928 if (status < 0)
3929 goto error;
3930 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3931 7);
3932 if (status < 0)
3933 goto error;
3934 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3935 7);
3936 if (status < 0)
3937 goto error;
3938 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3939 1);
3940 if (status < 0)
3941 goto error;
3942 break;
3943 case 7000000:
3944 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3945 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3946 3491);
3947 if (status < 0)
3948 goto error;
3949
3950 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3951 8);
3952 if (status < 0)
3953 goto error;
3954 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3955 8);
3956 if (status < 0)
3957 goto error;
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3959 4);
3960 if (status < 0)
3961 goto error;
3962 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3963 1);
3964 if (status < 0)
3965 goto error;
3966 break;
3967 case 6000000:
3968 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3969 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3970 4073);
3971 if (status < 0)
3972 goto error;
3973
3974 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3975 19);
3976 if (status < 0)
3977 goto error;
3978 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3979 19);
3980 if (status < 0)
3981 goto error;
3982 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3983 14);
3984 if (status < 0)
3985 goto error;
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3987 1);
3988 if (status < 0)
3989 goto error;
3990 break;
3991 default:
3992 status = -EINVAL;
3993 goto error;
3994 }
3995
3996 if (iqm_rc_rate_ofs == 0) {
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009 iqm_rc_rate_ofs = Frac28a((u32)
4010 ((state->m_sys_clock_freq *
4011 1000) / 3), bandwidth);
4012
4013 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
4014 iqm_rc_rate_ofs += 0x80L;
4015 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
4016
4017 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
4018 }
4019
4020 iqm_rc_rate_ofs &=
4021 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4022 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4023 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
4024 if (status < 0)
4025 goto error;
4026
4027
4028
4029#if 0
4030 status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
4031 if (status < 0)
4032 goto error;
4033#endif
4034 status = set_frequency_shifter(state, intermediate_freqk_hz,
4035 tuner_freq_offset, true);
4036 if (status < 0)
4037 goto error;
4038
4039
4040
4041
4042 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4043 if (status < 0)
4044 goto error;
4045
4046
4047 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4048 if (status < 0)
4049 goto error;
4050 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4051 if (status < 0)
4052 goto error;
4053
4054
4055 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4056 | SCU_RAM_COMMAND_CMD_DEMOD_START,
4057 0, NULL, 1, &cmd_result);
4058 if (status < 0)
4059 goto error;
4060
4061
4062 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4063 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4064 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4065 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4066 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4067 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4068 0, transmission_params, param1, 0, 0, 0);
4069 if (status < 0)
4070 goto error;
4071
4072 if (!state->m_drxk_a3_rom_code)
4073 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4074error:
4075 if (status < 0)
4076 pr_err("Error %d on %s\n", status, __func__);
4077
4078 return status;
4079}
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4092{
4093 int status;
4094 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4095 OFDM_SC_RA_RAM_LOCK_FEC__M);
4096 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4097 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4098
4099 u16 sc_ra_ram_lock = 0;
4100 u16 sc_comm_exec = 0;
4101
4102 dprintk(1, "\n");
4103
4104 *p_lock_status = NOT_LOCKED;
4105
4106
4107 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4108 if (status < 0)
4109 goto end;
4110 if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4111 goto end;
4112
4113 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4114 if (status < 0)
4115 goto end;
4116
4117 if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4118 *p_lock_status = MPEG_LOCK;
4119 else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4120 *p_lock_status = FEC_LOCK;
4121 else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4122 *p_lock_status = DEMOD_LOCK;
4123 else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4124 *p_lock_status = NEVER_LOCK;
4125end:
4126 if (status < 0)
4127 pr_err("Error %d on %s\n", status, __func__);
4128
4129 return status;
4130}
4131
4132static int power_up_qam(struct drxk_state *state)
4133{
4134 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4135 int status;
4136
4137 dprintk(1, "\n");
4138 status = ctrl_power_mode(state, &power_mode);
4139 if (status < 0)
4140 pr_err("Error %d on %s\n", status, __func__);
4141
4142 return status;
4143}
4144
4145
4146
4147static int power_down_qam(struct drxk_state *state)
4148{
4149 u16 data = 0;
4150 u16 cmd_result;
4151 int status = 0;
4152
4153 dprintk(1, "\n");
4154 status = read16(state, SCU_COMM_EXEC__A, &data);
4155 if (status < 0)
4156 goto error;
4157 if (data == SCU_COMM_EXEC_ACTIVE) {
4158
4159
4160
4161
4162
4163 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4164 if (status < 0)
4165 goto error;
4166 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4167 | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
4168 0, NULL, 1, &cmd_result);
4169 if (status < 0)
4170 goto error;
4171 }
4172
4173 status = set_iqm_af(state, false);
4174
4175error:
4176 if (status < 0)
4177 pr_err("Error %d on %s\n", status, __func__);
4178
4179 return status;
4180}
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195static int set_qam_measurement(struct drxk_state *state,
4196 enum e_drxk_constellation modulation,
4197 u32 symbol_rate)
4198{
4199 u32 fec_bits_desired = 0;
4200 u32 fec_rs_period_total = 0;
4201 u16 fec_rs_prescale = 0;
4202 u16 fec_rs_period = 0;
4203 int status = 0;
4204
4205 dprintk(1, "\n");
4206
4207 fec_rs_prescale = 1;
4208
4209
4210
4211
4212
4213
4214 switch (modulation) {
4215 case DRX_CONSTELLATION_QAM16:
4216 fec_bits_desired = 4 * symbol_rate;
4217 break;
4218 case DRX_CONSTELLATION_QAM32:
4219 fec_bits_desired = 5 * symbol_rate;
4220 break;
4221 case DRX_CONSTELLATION_QAM64:
4222 fec_bits_desired = 6 * symbol_rate;
4223 break;
4224 case DRX_CONSTELLATION_QAM128:
4225 fec_bits_desired = 7 * symbol_rate;
4226 break;
4227 case DRX_CONSTELLATION_QAM256:
4228 fec_bits_desired = 8 * symbol_rate;
4229 break;
4230 default:
4231 status = -EINVAL;
4232 }
4233 if (status < 0)
4234 goto error;
4235
4236 fec_bits_desired /= 1000;
4237 fec_bits_desired *= 500;
4238
4239
4240
4241 fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;
4242
4243
4244 fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4245 if (fec_rs_prescale == 0) {
4246
4247 status = -EINVAL;
4248 if (status < 0)
4249 goto error;
4250 }
4251 fec_rs_period =
4252 ((u16) fec_rs_period_total +
4253 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4254
4255
4256 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4257 if (status < 0)
4258 goto error;
4259 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4260 fec_rs_prescale);
4261 if (status < 0)
4262 goto error;
4263 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4264error:
4265 if (status < 0)
4266 pr_err("Error %d on %s\n", status, __func__);
4267 return status;
4268}
4269
4270static int set_qam16(struct drxk_state *state)
4271{
4272 int status = 0;
4273
4274 dprintk(1, "\n");
4275
4276
4277 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4278 if (status < 0)
4279 goto error;
4280 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4281 if (status < 0)
4282 goto error;
4283 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4284 if (status < 0)
4285 goto error;
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4287 if (status < 0)
4288 goto error;
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4290 if (status < 0)
4291 goto error;
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4293 if (status < 0)
4294 goto error;
4295
4296 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4297 if (status < 0)
4298 goto error;
4299 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4300 if (status < 0)
4301 goto error;
4302 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4303 if (status < 0)
4304 goto error;
4305 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4306 if (status < 0)
4307 goto error;
4308 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4309 if (status < 0)
4310 goto error;
4311 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4312 if (status < 0)
4313 goto error;
4314
4315 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4316 if (status < 0)
4317 goto error;
4318 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4319 if (status < 0)
4320 goto error;
4321 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4322 if (status < 0)
4323 goto error;
4324
4325
4326 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4327 DRXK_QAM_SL_SIG_POWER_QAM16);
4328 if (status < 0)
4329 goto error;
4330
4331
4332 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4333 if (status < 0)
4334 goto error;
4335 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4336 if (status < 0)
4337 goto error;
4338 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4339 if (status < 0)
4340 goto error;
4341 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4342 if (status < 0)
4343 goto error;
4344 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4345 if (status < 0)
4346 goto error;
4347 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4348 if (status < 0)
4349 goto error;
4350 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4351 if (status < 0)
4352 goto error;
4353 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4354 if (status < 0)
4355 goto error;
4356
4357 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4358 if (status < 0)
4359 goto error;
4360 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4361 if (status < 0)
4362 goto error;
4363 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4364 if (status < 0)
4365 goto error;
4366 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4367 if (status < 0)
4368 goto error;
4369 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4370 if (status < 0)
4371 goto error;
4372 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4373 if (status < 0)
4374 goto error;
4375 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4376 if (status < 0)
4377 goto error;
4378 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4379 if (status < 0)
4380 goto error;
4381 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4382 if (status < 0)
4383 goto error;
4384 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4385 if (status < 0)
4386 goto error;
4387 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4388 if (status < 0)
4389 goto error;
4390 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4391 if (status < 0)
4392 goto error;
4393
4394
4395
4396
4397 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4398 if (status < 0)
4399 goto error;
4400 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4401 if (status < 0)
4402 goto error;
4403 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4404 if (status < 0)
4405 goto error;
4406 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4407 if (status < 0)
4408 goto error;
4409 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4410 if (status < 0)
4411 goto error;
4412 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4413 if (status < 0)
4414 goto error;
4415
4416 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4417 if (status < 0)
4418 goto error;
4419 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4420 if (status < 0)
4421 goto error;
4422 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4423 if (status < 0)
4424 goto error;
4425
4426
4427
4428
4429 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4430 if (status < 0)
4431 goto error;
4432 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4433 if (status < 0)
4434 goto error;
4435 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4436 if (status < 0)
4437 goto error;
4438 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4439 if (status < 0)
4440 goto error;
4441 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4442 if (status < 0)
4443 goto error;
4444 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4445 if (status < 0)
4446 goto error;
4447 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4448 if (status < 0)
4449 goto error;
4450
4451error:
4452 if (status < 0)
4453 pr_err("Error %d on %s\n", status, __func__);
4454 return status;
4455}
4456
4457
4458
4459
4460
4461
4462
4463
4464static int set_qam32(struct drxk_state *state)
4465{
4466 int status = 0;
4467
4468 dprintk(1, "\n");
4469
4470
4471
4472 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4473 if (status < 0)
4474 goto error;
4475 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4476 if (status < 0)
4477 goto error;
4478 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4479 if (status < 0)
4480 goto error;
4481 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4482 if (status < 0)
4483 goto error;
4484 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4485 if (status < 0)
4486 goto error;
4487 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4488 if (status < 0)
4489 goto error;
4490
4491
4492 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4493 if (status < 0)
4494 goto error;
4495 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4496 if (status < 0)
4497 goto error;
4498 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4499 if (status < 0)
4500 goto error;
4501 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4502 if (status < 0)
4503 goto error;
4504 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4505 if (status < 0)
4506 goto error;
4507 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4508 if (status < 0)
4509 goto error;
4510
4511 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4512 if (status < 0)
4513 goto error;
4514 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4515 if (status < 0)
4516 goto error;
4517 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4518 if (status < 0)
4519 goto error;
4520
4521
4522
4523 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4524 DRXK_QAM_SL_SIG_POWER_QAM32);
4525 if (status < 0)
4526 goto error;
4527
4528
4529
4530
4531 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4532 if (status < 0)
4533 goto error;
4534 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4535 if (status < 0)
4536 goto error;
4537 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4538 if (status < 0)
4539 goto error;
4540 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4541 if (status < 0)
4542 goto error;
4543 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4544 if (status < 0)
4545 goto error;
4546 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4547 if (status < 0)
4548 goto error;
4549 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4550 if (status < 0)
4551 goto error;
4552 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4553 if (status < 0)
4554 goto error;
4555
4556 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4557 if (status < 0)
4558 goto error;
4559 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4560 if (status < 0)
4561 goto error;
4562 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4563 if (status < 0)
4564 goto error;
4565 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4566 if (status < 0)
4567 goto error;
4568 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4569 if (status < 0)
4570 goto error;
4571 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4572 if (status < 0)
4573 goto error;
4574 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4575 if (status < 0)
4576 goto error;
4577 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4578 if (status < 0)
4579 goto error;
4580 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4581 if (status < 0)
4582 goto error;
4583 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4584 if (status < 0)
4585 goto error;
4586 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4587 if (status < 0)
4588 goto error;
4589 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4590 if (status < 0)
4591 goto error;
4592
4593
4594
4595
4596 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4597 if (status < 0)
4598 goto error;
4599 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4600 if (status < 0)
4601 goto error;
4602 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4603 if (status < 0)
4604 goto error;
4605 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4606 if (status < 0)
4607 goto error;
4608 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4609 if (status < 0)
4610 goto error;
4611 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4612 if (status < 0)
4613 goto error;
4614
4615 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4616 if (status < 0)
4617 goto error;
4618 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4619 if (status < 0)
4620 goto error;
4621 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4622 if (status < 0)
4623 goto error;
4624
4625
4626
4627
4628 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4629 if (status < 0)
4630 goto error;
4631 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4632 if (status < 0)
4633 goto error;
4634 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4635 if (status < 0)
4636 goto error;
4637 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4638 if (status < 0)
4639 goto error;
4640 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4641 if (status < 0)
4642 goto error;
4643 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4644 if (status < 0)
4645 goto error;
4646 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4647error:
4648 if (status < 0)
4649 pr_err("Error %d on %s\n", status, __func__);
4650 return status;
4651}
4652
4653
4654
4655
4656
4657
4658
4659
4660static int set_qam64(struct drxk_state *state)
4661{
4662 int status = 0;
4663
4664 dprintk(1, "\n");
4665
4666
4667 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4668 if (status < 0)
4669 goto error;
4670 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4671 if (status < 0)
4672 goto error;
4673 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4674 if (status < 0)
4675 goto error;
4676 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4677 if (status < 0)
4678 goto error;
4679 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4680 if (status < 0)
4681 goto error;
4682 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4683 if (status < 0)
4684 goto error;
4685
4686
4687 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4688 if (status < 0)
4689 goto error;
4690 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4691 if (status < 0)
4692 goto error;
4693 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4694 if (status < 0)
4695 goto error;
4696 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4697 if (status < 0)
4698 goto error;
4699 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4700 if (status < 0)
4701 goto error;
4702 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4703 if (status < 0)
4704 goto error;
4705
4706 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4707 if (status < 0)
4708 goto error;
4709 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4710 if (status < 0)
4711 goto error;
4712 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4713 if (status < 0)
4714 goto error;
4715
4716
4717 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4718 DRXK_QAM_SL_SIG_POWER_QAM64);
4719 if (status < 0)
4720 goto error;
4721
4722
4723
4724
4725 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4726 if (status < 0)
4727 goto error;
4728 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4729 if (status < 0)
4730 goto error;
4731 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4732 if (status < 0)
4733 goto error;
4734 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4735 if (status < 0)
4736 goto error;
4737 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4738 if (status < 0)
4739 goto error;
4740 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4741 if (status < 0)
4742 goto error;
4743 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4744 if (status < 0)
4745 goto error;
4746 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4747 if (status < 0)
4748 goto error;
4749
4750 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4751 if (status < 0)
4752 goto error;
4753 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4754 if (status < 0)
4755 goto error;
4756 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4757 if (status < 0)
4758 goto error;
4759 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4760 if (status < 0)
4761 goto error;
4762 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4763 if (status < 0)
4764 goto error;
4765 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4766 if (status < 0)
4767 goto error;
4768 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4769 if (status < 0)
4770 goto error;
4771 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4772 if (status < 0)
4773 goto error;
4774 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4775 if (status < 0)
4776 goto error;
4777 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4778 if (status < 0)
4779 goto error;
4780 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4781 if (status < 0)
4782 goto error;
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4784 if (status < 0)
4785 goto error;
4786
4787
4788
4789
4790 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4791 if (status < 0)
4792 goto error;
4793 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4794 if (status < 0)
4795 goto error;
4796 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4797 if (status < 0)
4798 goto error;
4799 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4800 if (status < 0)
4801 goto error;
4802 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4803 if (status < 0)
4804 goto error;
4805 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4806 if (status < 0)
4807 goto error;
4808
4809 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4810 if (status < 0)
4811 goto error;
4812 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4813 if (status < 0)
4814 goto error;
4815 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4816 if (status < 0)
4817 goto error;
4818
4819
4820
4821
4822 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4823 if (status < 0)
4824 goto error;
4825 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4826 if (status < 0)
4827 goto error;
4828 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4829 if (status < 0)
4830 goto error;
4831 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4832 if (status < 0)
4833 goto error;
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4835 if (status < 0)
4836 goto error;
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4838 if (status < 0)
4839 goto error;
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4841error:
4842 if (status < 0)
4843 pr_err("Error %d on %s\n", status, __func__);
4844
4845 return status;
4846}
4847
4848
4849
4850
4851
4852
4853
4854
4855static int set_qam128(struct drxk_state *state)
4856{
4857 int status = 0;
4858
4859 dprintk(1, "\n");
4860
4861
4862 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4863 if (status < 0)
4864 goto error;
4865 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4866 if (status < 0)
4867 goto error;
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4869 if (status < 0)
4870 goto error;
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4872 if (status < 0)
4873 goto error;
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4875 if (status < 0)
4876 goto error;
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4878 if (status < 0)
4879 goto error;
4880
4881
4882 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4883 if (status < 0)
4884 goto error;
4885 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4886 if (status < 0)
4887 goto error;
4888 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4889 if (status < 0)
4890 goto error;
4891 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4892 if (status < 0)
4893 goto error;
4894 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4895 if (status < 0)
4896 goto error;
4897 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4898 if (status < 0)
4899 goto error;
4900
4901 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4902 if (status < 0)
4903 goto error;
4904 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4905 if (status < 0)
4906 goto error;
4907 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4908 if (status < 0)
4909 goto error;
4910
4911
4912
4913
4914 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4915 DRXK_QAM_SL_SIG_POWER_QAM128);
4916 if (status < 0)
4917 goto error;
4918
4919
4920
4921
4922 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4923 if (status < 0)
4924 goto error;
4925 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4926 if (status < 0)
4927 goto error;
4928 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4929 if (status < 0)
4930 goto error;
4931 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4932 if (status < 0)
4933 goto error;
4934 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4935 if (status < 0)
4936 goto error;
4937 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4938 if (status < 0)
4939 goto error;
4940 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4941 if (status < 0)
4942 goto error;
4943 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4944 if (status < 0)
4945 goto error;
4946
4947 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4948 if (status < 0)
4949 goto error;
4950 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4951 if (status < 0)
4952 goto error;
4953 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4954 if (status < 0)
4955 goto error;
4956 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4957 if (status < 0)
4958 goto error;
4959 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4960 if (status < 0)
4961 goto error;
4962 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4963 if (status < 0)
4964 goto error;
4965 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4966 if (status < 0)
4967 goto error;
4968 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4969 if (status < 0)
4970 goto error;
4971 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4972 if (status < 0)
4973 goto error;
4974 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4975 if (status < 0)
4976 goto error;
4977 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4978 if (status < 0)
4979 goto error;
4980 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4981 if (status < 0)
4982 goto error;
4983
4984
4985
4986
4987 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4988 if (status < 0)
4989 goto error;
4990 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4991 if (status < 0)
4992 goto error;
4993 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4994 if (status < 0)
4995 goto error;
4996 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4997 if (status < 0)
4998 goto error;
4999 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5000 if (status < 0)
5001 goto error;
5002 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5003 if (status < 0)
5004 goto error;
5005
5006 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5007 if (status < 0)
5008 goto error;
5009 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5010 if (status < 0)
5011 goto error;
5012
5013 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5014 if (status < 0)
5015 goto error;
5016
5017
5018
5019 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5020 if (status < 0)
5021 goto error;
5022 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5023 if (status < 0)
5024 goto error;
5025 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5026 if (status < 0)
5027 goto error;
5028 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5029 if (status < 0)
5030 goto error;
5031 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5032 if (status < 0)
5033 goto error;
5034 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5035 if (status < 0)
5036 goto error;
5037 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5038error:
5039 if (status < 0)
5040 pr_err("Error %d on %s\n", status, __func__);
5041
5042 return status;
5043}
5044
5045
5046
5047
5048
5049
5050
5051
5052static int set_qam256(struct drxk_state *state)
5053{
5054 int status = 0;
5055
5056 dprintk(1, "\n");
5057
5058
5059 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5060 if (status < 0)
5061 goto error;
5062 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5063 if (status < 0)
5064 goto error;
5065 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5066 if (status < 0)
5067 goto error;
5068 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5069 if (status < 0)
5070 goto error;
5071 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5072 if (status < 0)
5073 goto error;
5074 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5075 if (status < 0)
5076 goto error;
5077
5078
5079 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5080 if (status < 0)
5081 goto error;
5082 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5083 if (status < 0)
5084 goto error;
5085 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5086 if (status < 0)
5087 goto error;
5088 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5089 if (status < 0)
5090 goto error;
5091 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5092 if (status < 0)
5093 goto error;
5094 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5095 if (status < 0)
5096 goto error;
5097
5098 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5099 if (status < 0)
5100 goto error;
5101 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5102 if (status < 0)
5103 goto error;
5104 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5105 if (status < 0)
5106 goto error;
5107
5108
5109
5110 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5111 DRXK_QAM_SL_SIG_POWER_QAM256);
5112 if (status < 0)
5113 goto error;
5114
5115
5116
5117
5118 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5119 if (status < 0)
5120 goto error;
5121 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5122 if (status < 0)
5123 goto error;
5124 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5125 if (status < 0)
5126 goto error;
5127 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5128 if (status < 0)
5129 goto error;
5130 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5131 if (status < 0)
5132 goto error;
5133 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5134 if (status < 0)
5135 goto error;
5136 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5137 if (status < 0)
5138 goto error;
5139 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5140 if (status < 0)
5141 goto error;
5142
5143 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5144 if (status < 0)
5145 goto error;
5146 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5147 if (status < 0)
5148 goto error;
5149 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5150 if (status < 0)
5151 goto error;
5152 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5153 if (status < 0)
5154 goto error;
5155 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5156 if (status < 0)
5157 goto error;
5158 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5159 if (status < 0)
5160 goto error;
5161 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5162 if (status < 0)
5163 goto error;
5164 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5165 if (status < 0)
5166 goto error;
5167 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5168 if (status < 0)
5169 goto error;
5170 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5171 if (status < 0)
5172 goto error;
5173 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5174 if (status < 0)
5175 goto error;
5176 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5177 if (status < 0)
5178 goto error;
5179
5180
5181
5182
5183 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5184 if (status < 0)
5185 goto error;
5186 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5187 if (status < 0)
5188 goto error;
5189 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5190 if (status < 0)
5191 goto error;
5192 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5193 if (status < 0)
5194 goto error;
5195 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5196 if (status < 0)
5197 goto error;
5198 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5199 if (status < 0)
5200 goto error;
5201
5202 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5203 if (status < 0)
5204 goto error;
5205 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5206 if (status < 0)
5207 goto error;
5208 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5209 if (status < 0)
5210 goto error;
5211
5212
5213
5214
5215 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5216 if (status < 0)
5217 goto error;
5218 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5219 if (status < 0)
5220 goto error;
5221 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5222 if (status < 0)
5223 goto error;
5224 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5225 if (status < 0)
5226 goto error;
5227 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5228 if (status < 0)
5229 goto error;
5230 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5231 if (status < 0)
5232 goto error;
5233 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5234error:
5235 if (status < 0)
5236 pr_err("Error %d on %s\n", status, __func__);
5237 return status;
5238}
5239
5240
5241
5242
5243
5244
5245
5246
5247
5248static int qam_reset_qam(struct drxk_state *state)
5249{
5250 int status;
5251 u16 cmd_result;
5252
5253 dprintk(1, "\n");
5254
5255 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5256 if (status < 0)
5257 goto error;
5258
5259 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5260 | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
5261 0, NULL, 1, &cmd_result);
5262error:
5263 if (status < 0)
5264 pr_err("Error %d on %s\n", status, __func__);
5265 return status;
5266}
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276static int qam_set_symbolrate(struct drxk_state *state)
5277{
5278 u32 adc_frequency = 0;
5279 u32 symb_freq = 0;
5280 u32 iqm_rc_rate = 0;
5281 u16 ratesel = 0;
5282 u32 lc_symb_rate = 0;
5283 int status;
5284
5285 dprintk(1, "\n");
5286
5287 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5288 ratesel = 0;
5289
5290 if (state->props.symbol_rate <= 1188750)
5291 ratesel = 3;
5292 else if (state->props.symbol_rate <= 2377500)
5293 ratesel = 2;
5294 else if (state->props.symbol_rate <= 4755000)
5295 ratesel = 1;
5296 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5297 if (status < 0)
5298 goto error;
5299
5300
5301
5302
5303 symb_freq = state->props.symbol_rate * (1 << ratesel);
5304 if (symb_freq == 0) {
5305
5306 status = -EINVAL;
5307 goto error;
5308 }
5309 iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5310 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5311 (1 << 23);
5312 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5313 if (status < 0)
5314 goto error;
5315 state->m_iqm_rc_rate = iqm_rc_rate;
5316
5317
5318
5319 symb_freq = state->props.symbol_rate;
5320 if (adc_frequency == 0) {
5321
5322 status = -EINVAL;
5323 goto error;
5324 }
5325 lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5326 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5327 16);
5328 if (lc_symb_rate > 511)
5329 lc_symb_rate = 511;
5330 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5331
5332error:
5333 if (status < 0)
5334 pr_err("Error %d on %s\n", status, __func__);
5335 return status;
5336}
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5348{
5349 int status;
5350 u16 result[2] = { 0, 0 };
5351
5352 dprintk(1, "\n");
5353 *p_lock_status = NOT_LOCKED;
5354 status = scu_command(state,
5355 SCU_RAM_COMMAND_STANDARD_QAM |
5356 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5357 result);
5358 if (status < 0)
5359 pr_err("Error %d on %s\n", status, __func__);
5360
5361 if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5362
5363 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5364
5365 *p_lock_status = DEMOD_LOCK;
5366 } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5367
5368 *p_lock_status = MPEG_LOCK;
5369 } else {
5370
5371
5372
5373
5374
5375
5376 *p_lock_status = NEVER_LOCK;
5377 }
5378 return status;
5379}
5380
5381#define QAM_MIRROR__M 0x03
5382#define QAM_MIRROR_NORMAL 0x00
5383#define QAM_MIRRORED 0x01
5384#define QAM_MIRROR_AUTO_ON 0x02
5385#define QAM_LOCKRANGE__M 0x10
5386#define QAM_LOCKRANGE_NORMAL 0x10
5387
5388static int qam_demodulator_command(struct drxk_state *state,
5389 int number_of_parameters)
5390{
5391 int status;
5392 u16 cmd_result;
5393 u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5394
5395 set_param_parameters[0] = state->m_constellation;
5396 set_param_parameters[1] = DRXK_QAM_I12_J17;
5397
5398 if (number_of_parameters == 2) {
5399 u16 set_env_parameters[1] = { 0 };
5400
5401 if (state->m_operation_mode == OM_QAM_ITU_C)
5402 set_env_parameters[0] = QAM_TOP_ANNEX_C;
5403 else
5404 set_env_parameters[0] = QAM_TOP_ANNEX_A;
5405
5406 status = scu_command(state,
5407 SCU_RAM_COMMAND_STANDARD_QAM
5408 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5409 1, set_env_parameters, 1, &cmd_result);
5410 if (status < 0)
5411 goto error;
5412
5413 status = scu_command(state,
5414 SCU_RAM_COMMAND_STANDARD_QAM
5415 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5416 number_of_parameters, set_param_parameters,
5417 1, &cmd_result);
5418 } else if (number_of_parameters == 4) {
5419 if (state->m_operation_mode == OM_QAM_ITU_C)
5420 set_param_parameters[2] = QAM_TOP_ANNEX_C;
5421 else
5422 set_param_parameters[2] = QAM_TOP_ANNEX_A;
5423
5424 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5425
5426
5427
5428
5429 status = scu_command(state,
5430 SCU_RAM_COMMAND_STANDARD_QAM
5431 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5432 number_of_parameters, set_param_parameters,
5433 1, &cmd_result);
5434 } else {
5435 pr_warn("Unknown QAM demodulator parameter count %d\n",
5436 number_of_parameters);
5437 status = -EINVAL;
5438 }
5439
5440error:
5441 if (status < 0)
5442 pr_warn("Warning %d on %s\n", status, __func__);
5443 return status;
5444}
5445
5446static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5447 s32 tuner_freq_offset)
5448{
5449 int status;
5450 u16 cmd_result;
5451 int qam_demod_param_count = state->qam_demod_parameter_count;
5452
5453 dprintk(1, "\n");
5454
5455
5456
5457
5458
5459
5460 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5461 if (status < 0)
5462 goto error;
5463 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5464 if (status < 0)
5465 goto error;
5466 status = qam_reset_qam(state);
5467 if (status < 0)
5468 goto error;
5469
5470
5471
5472
5473
5474
5475 status = qam_set_symbolrate(state);
5476 if (status < 0)
5477 goto error;
5478
5479
5480 switch (state->props.modulation) {
5481 case QAM_256:
5482 state->m_constellation = DRX_CONSTELLATION_QAM256;
5483 break;
5484 case QAM_AUTO:
5485 case QAM_64:
5486 state->m_constellation = DRX_CONSTELLATION_QAM64;
5487 break;
5488 case QAM_16:
5489 state->m_constellation = DRX_CONSTELLATION_QAM16;
5490 break;
5491 case QAM_32:
5492 state->m_constellation = DRX_CONSTELLATION_QAM32;
5493 break;
5494 case QAM_128:
5495 state->m_constellation = DRX_CONSTELLATION_QAM128;
5496 break;
5497 default:
5498 status = -EINVAL;
5499 break;
5500 }
5501 if (status < 0)
5502 goto error;
5503
5504
5505
5506 if (state->qam_demod_parameter_count == 4
5507 || !state->qam_demod_parameter_count) {
5508 qam_demod_param_count = 4;
5509 status = qam_demodulator_command(state, qam_demod_param_count);
5510 }
5511
5512
5513
5514
5515 if (state->qam_demod_parameter_count == 2
5516 || (!state->qam_demod_parameter_count && status < 0)) {
5517 qam_demod_param_count = 2;
5518 status = qam_demodulator_command(state, qam_demod_param_count);
5519 }
5520
5521 if (status < 0) {
5522 dprintk(1, "Could not set demodulator parameters.\n");
5523 dprintk(1,
5524 "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n",
5525 state->qam_demod_parameter_count,
5526 state->microcode_name);
5527 goto error;
5528 } else if (!state->qam_demod_parameter_count) {
5529 dprintk(1,
5530 "Auto-probing the QAM command parameters was successful - using %d parameters.\n",
5531 qam_demod_param_count);
5532
5533
5534
5535
5536
5537 state->qam_demod_parameter_count = qam_demod_param_count;
5538 }
5539
5540
5541
5542
5543
5544#if 0
5545 status = set_frequency(channel, tuner_freq_offset));
5546 if (status < 0)
5547 goto error;
5548#endif
5549 status = set_frequency_shifter(state, intermediate_freqk_hz,
5550 tuner_freq_offset, true);
5551 if (status < 0)
5552 goto error;
5553
5554
5555 status = set_qam_measurement(state, state->m_constellation,
5556 state->props.symbol_rate);
5557 if (status < 0)
5558 goto error;
5559
5560
5561 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5562 if (status < 0)
5563 goto error;
5564 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5565 if (status < 0)
5566 goto error;
5567
5568
5569 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5570 if (status < 0)
5571 goto error;
5572 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5573 if (status < 0)
5574 goto error;
5575 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5576 if (status < 0)
5577 goto error;
5578 status = write16(state, QAM_LC_MODE__A, 7);
5579 if (status < 0)
5580 goto error;
5581
5582 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5583 if (status < 0)
5584 goto error;
5585 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5586 if (status < 0)
5587 goto error;
5588 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5589 if (status < 0)
5590 goto error;
5591 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5592 if (status < 0)
5593 goto error;
5594 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5595 if (status < 0)
5596 goto error;
5597 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5598 if (status < 0)
5599 goto error;
5600 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5601 if (status < 0)
5602 goto error;
5603 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5604 if (status < 0)
5605 goto error;
5606 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5607 if (status < 0)
5608 goto error;
5609 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5610 if (status < 0)
5611 goto error;
5612 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5613 if (status < 0)
5614 goto error;
5615 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5616 if (status < 0)
5617 goto error;
5618 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5619 if (status < 0)
5620 goto error;
5621 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5622 if (status < 0)
5623 goto error;
5624 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5625 if (status < 0)
5626 goto error;
5627
5628
5629 status = write16(state, QAM_SY_SP_INV__A,
5630 QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5631 if (status < 0)
5632 goto error;
5633
5634
5635 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5636 if (status < 0)
5637 goto error;
5638
5639
5640 switch (state->props.modulation) {
5641 case QAM_16:
5642 status = set_qam16(state);
5643 break;
5644 case QAM_32:
5645 status = set_qam32(state);
5646 break;
5647 case QAM_AUTO:
5648 case QAM_64:
5649 status = set_qam64(state);
5650 break;
5651 case QAM_128:
5652 status = set_qam128(state);
5653 break;
5654 case QAM_256:
5655 status = set_qam256(state);
5656 break;
5657 default:
5658 status = -EINVAL;
5659 break;
5660 }
5661 if (status < 0)
5662 goto error;
5663
5664
5665 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5666 if (status < 0)
5667 goto error;
5668
5669
5670
5671
5672 status = mpegts_dto_setup(state, state->m_operation_mode);
5673 if (status < 0)
5674 goto error;
5675
5676
5677 status = mpegts_start(state);
5678 if (status < 0)
5679 goto error;
5680 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5681 if (status < 0)
5682 goto error;
5683 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5684 if (status < 0)
5685 goto error;
5686 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5687 if (status < 0)
5688 goto error;
5689
5690
5691 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5692 | SCU_RAM_COMMAND_CMD_DEMOD_START,
5693 0, NULL, 1, &cmd_result);
5694 if (status < 0)
5695 goto error;
5696
5697
5698
5699
5700error:
5701 if (status < 0)
5702 pr_err("Error %d on %s\n", status, __func__);
5703 return status;
5704}
5705
5706static int set_qam_standard(struct drxk_state *state,
5707 enum operation_mode o_mode)
5708{
5709 int status;
5710#ifdef DRXK_QAM_TAPS
5711#define DRXK_QAMA_TAPS_SELECT
5712#include "drxk_filters.h"
5713#undef DRXK_QAMA_TAPS_SELECT
5714#endif
5715
5716 dprintk(1, "\n");
5717
5718
5719 switch_antenna_to_qam(state);
5720
5721
5722 status = power_up_qam(state);
5723 if (status < 0)
5724 goto error;
5725
5726 status = qam_reset_qam(state);
5727 if (status < 0)
5728 goto error;
5729
5730
5731
5732 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5733 if (status < 0)
5734 goto error;
5735 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5736 if (status < 0)
5737 goto error;
5738
5739
5740
5741 switch (o_mode) {
5742 case OM_QAM_ITU_A:
5743 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5744 DRXK_BLCC_NR_ELEMENTS_TAPS,
5745 DRXK_BLC_TIMEOUT);
5746 break;
5747 case OM_QAM_ITU_C:
5748 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5749 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5750 DRXK_BLDC_NR_ELEMENTS_TAPS,
5751 DRXK_BLC_TIMEOUT);
5752 if (status < 0)
5753 goto error;
5754 status = bl_direct_cmd(state,
5755 IQM_CF_TAP_IM0__A,
5756 DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
5757 DRXK_BLDC_NR_ELEMENTS_TAPS,
5758 DRXK_BLC_TIMEOUT);
5759 break;
5760 default:
5761 status = -EINVAL;
5762 }
5763 if (status < 0)
5764 goto error;
5765
5766 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5767 if (status < 0)
5768 goto error;
5769 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5770 if (status < 0)
5771 goto error;
5772 status = write16(state, IQM_CF_MIDTAP__A,
5773 ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5774 if (status < 0)
5775 goto error;
5776
5777 status = write16(state, IQM_RC_STRETCH__A, 21);
5778 if (status < 0)
5779 goto error;
5780 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5781 if (status < 0)
5782 goto error;
5783 status = write16(state, IQM_AF_CLP_TH__A, 448);
5784 if (status < 0)
5785 goto error;
5786 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5787 if (status < 0)
5788 goto error;
5789 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5790 if (status < 0)
5791 goto error;
5792
5793 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5794 if (status < 0)
5795 goto error;
5796 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5797 if (status < 0)
5798 goto error;
5799 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5800 if (status < 0)
5801 goto error;
5802 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5803 if (status < 0)
5804 goto error;
5805
5806
5807 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5808 if (status < 0)
5809 goto error;
5810 status = write16(state, IQM_CF_DATATH__A, 1000);
5811 if (status < 0)
5812 goto error;
5813 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5814 if (status < 0)
5815 goto error;
5816 status = write16(state, IQM_CF_DET_LCT__A, 0);
5817 if (status < 0)
5818 goto error;
5819 status = write16(state, IQM_CF_WND_LEN__A, 1);
5820 if (status < 0)
5821 goto error;
5822 status = write16(state, IQM_CF_PKDTH__A, 1);
5823 if (status < 0)
5824 goto error;
5825 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5826 if (status < 0)
5827 goto error;
5828
5829
5830 status = set_iqm_af(state, true);
5831 if (status < 0)
5832 goto error;
5833 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5834 if (status < 0)
5835 goto error;
5836
5837
5838 status = adc_synchronization(state);
5839 if (status < 0)
5840 goto error;
5841
5842
5843 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5844 if (status < 0)
5845 goto error;
5846
5847
5848 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5849 if (status < 0)
5850 goto error;
5851
5852
5853
5854
5855 status = init_agc(state, true);
5856 if (status < 0)
5857 goto error;
5858 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5859 if (status < 0)
5860 goto error;
5861
5862
5863 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5864 if (status < 0)
5865 goto error;
5866 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5867 if (status < 0)
5868 goto error;
5869
5870
5871 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5872error:
5873 if (status < 0)
5874 pr_err("Error %d on %s\n", status, __func__);
5875 return status;
5876}
5877
5878static int write_gpio(struct drxk_state *state)
5879{
5880 int status;
5881 u16 value = 0;
5882
5883 dprintk(1, "\n");
5884
5885 status = write16(state, SCU_RAM_GPIO__A,
5886 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5887 if (status < 0)
5888 goto error;
5889
5890
5891 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5892 if (status < 0)
5893 goto error;
5894
5895 if (state->m_has_sawsw) {
5896 if (state->uio_mask & 0x0001) {
5897
5898 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5899 state->m_gpio_cfg);
5900 if (status < 0)
5901 goto error;
5902
5903
5904 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5905 if (status < 0)
5906 goto error;
5907 if ((state->m_gpio & 0x0001) == 0)
5908 value &= 0x7FFF;
5909 else
5910 value |= 0x8000;
5911
5912 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5913 if (status < 0)
5914 goto error;
5915 }
5916 if (state->uio_mask & 0x0002) {
5917
5918 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5919 state->m_gpio_cfg);
5920 if (status < 0)
5921 goto error;
5922
5923
5924 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5925 if (status < 0)
5926 goto error;
5927 if ((state->m_gpio & 0x0002) == 0)
5928 value &= 0xBFFF;
5929 else
5930 value |= 0x4000;
5931
5932 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5933 if (status < 0)
5934 goto error;
5935 }
5936 if (state->uio_mask & 0x0004) {
5937
5938 status = write16(state, SIO_PDR_GPIO_CFG__A,
5939 state->m_gpio_cfg);
5940 if (status < 0)
5941 goto error;
5942
5943
5944 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5945 if (status < 0)
5946 goto error;
5947 if ((state->m_gpio & 0x0004) == 0)
5948 value &= 0xFFFB;
5949 else
5950 value |= 0x0004;
5951
5952 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5953 if (status < 0)
5954 goto error;
5955 }
5956 }
5957
5958 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5959error:
5960 if (status < 0)
5961 pr_err("Error %d on %s\n", status, __func__);
5962 return status;
5963}
5964
5965static int switch_antenna_to_qam(struct drxk_state *state)
5966{
5967 int status = 0;
5968 bool gpio_state;
5969
5970 dprintk(1, "\n");
5971
5972 if (!state->antenna_gpio)
5973 return 0;
5974
5975 gpio_state = state->m_gpio & state->antenna_gpio;
5976
5977 if (state->antenna_dvbt ^ gpio_state) {
5978
5979 if (state->antenna_dvbt)
5980 state->m_gpio &= ~state->antenna_gpio;
5981 else
5982 state->m_gpio |= state->antenna_gpio;
5983 status = write_gpio(state);
5984 }
5985 if (status < 0)
5986 pr_err("Error %d on %s\n", status, __func__);
5987 return status;
5988}
5989
5990static int switch_antenna_to_dvbt(struct drxk_state *state)
5991{
5992 int status = 0;
5993 bool gpio_state;
5994
5995 dprintk(1, "\n");
5996
5997 if (!state->antenna_gpio)
5998 return 0;
5999
6000 gpio_state = state->m_gpio & state->antenna_gpio;
6001
6002 if (!(state->antenna_dvbt ^ gpio_state)) {
6003
6004 if (state->antenna_dvbt)
6005 state->m_gpio |= state->antenna_gpio;
6006 else
6007 state->m_gpio &= ~state->antenna_gpio;
6008 status = write_gpio(state);
6009 }
6010 if (status < 0)
6011 pr_err("Error %d on %s\n", status, __func__);
6012 return status;
6013}
6014
6015
6016static int power_down_device(struct drxk_state *state)
6017{
6018
6019
6020
6021
6022
6023
6024 int status;
6025
6026 dprintk(1, "\n");
6027 if (state->m_b_p_down_open_bridge) {
6028
6029 status = ConfigureI2CBridge(state, true);
6030 if (status < 0)
6031 goto error;
6032 }
6033
6034 status = dvbt_enable_ofdm_token_ring(state, false);
6035 if (status < 0)
6036 goto error;
6037
6038 status = write16(state, SIO_CC_PWD_MODE__A,
6039 SIO_CC_PWD_MODE_LEVEL_CLOCK);
6040 if (status < 0)
6041 goto error;
6042 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6043 if (status < 0)
6044 goto error;
6045 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
6046 status = hi_cfg_command(state);
6047error:
6048 if (status < 0)
6049 pr_err("Error %d on %s\n", status, __func__);
6050
6051 return status;
6052}
6053
6054static int init_drxk(struct drxk_state *state)
6055{
6056 int status = 0, n = 0;
6057 enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
6058 u16 driver_version;
6059
6060 dprintk(1, "\n");
6061 if ((state->m_drxk_state == DRXK_UNINITIALIZED)) {
6062 drxk_i2c_lock(state);
6063 status = power_up_device(state);
6064 if (status < 0)
6065 goto error;
6066 status = drxx_open(state);
6067 if (status < 0)
6068 goto error;
6069
6070 status = write16(state, SIO_CC_SOFT_RST__A,
6071 SIO_CC_SOFT_RST_OFDM__M
6072 | SIO_CC_SOFT_RST_SYS__M
6073 | SIO_CC_SOFT_RST_OSC__M);
6074 if (status < 0)
6075 goto error;
6076 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6077 if (status < 0)
6078 goto error;
6079
6080
6081
6082
6083 usleep_range(1000, 2000);
6084 state->m_drxk_a3_patch_code = true;
6085 status = get_device_capabilities(state);
6086 if (status < 0)
6087 goto error;
6088
6089
6090
6091
6092 state->m_hi_cfg_bridge_delay =
6093 (u16) ((state->m_osc_clock_freq / 1000) *
6094 HI_I2C_BRIDGE_DELAY) / 1000;
6095
6096 if (state->m_hi_cfg_bridge_delay >
6097 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6098 state->m_hi_cfg_bridge_delay =
6099 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6100 }
6101
6102 state->m_hi_cfg_bridge_delay +=
6103 state->m_hi_cfg_bridge_delay <<
6104 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6105
6106 status = init_hi(state);
6107 if (status < 0)
6108 goto error;
6109
6110#if NOA1ROM
6111 if (!(state->m_DRXK_A1_ROM_CODE)
6112 && !(state->m_DRXK_A2_ROM_CODE))
6113#endif
6114 {
6115 status = write16(state, SCU_RAM_GPIO__A,
6116 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6117 if (status < 0)
6118 goto error;
6119 }
6120
6121
6122 status = mpegts_disable(state);
6123 if (status < 0)
6124 goto error;
6125
6126
6127 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6128 if (status < 0)
6129 goto error;
6130 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6131 if (status < 0)
6132 goto error;
6133
6134
6135 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6136 SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6137 if (status < 0)
6138 goto error;
6139
6140
6141 status = write16(state, SIO_BL_COMM_EXEC__A,
6142 SIO_BL_COMM_EXEC_ACTIVE);
6143 if (status < 0)
6144 goto error;
6145 status = bl_chain_cmd(state, 0, 6, 100);
6146 if (status < 0)
6147 goto error;
6148
6149 if (state->fw) {
6150 status = download_microcode(state, state->fw->data,
6151 state->fw->size);
6152 if (status < 0)
6153 goto error;
6154 }
6155
6156
6157 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6158 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6159 if (status < 0)
6160 goto error;
6161
6162
6163 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6164 if (status < 0)
6165 goto error;
6166 status = drxx_open(state);
6167 if (status < 0)
6168 goto error;
6169
6170 msleep(30);
6171
6172 power_mode = DRXK_POWER_DOWN_OFDM;
6173 status = ctrl_power_mode(state, &power_mode);
6174 if (status < 0)
6175 goto error;
6176
6177
6178
6179
6180
6181
6182
6183 driver_version =
6184 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6185 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6186 ((DRXK_VERSION_MAJOR % 10) << 4) +
6187 (DRXK_VERSION_MINOR % 10);
6188 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6189 driver_version);
6190 if (status < 0)
6191 goto error;
6192 driver_version =
6193 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6194 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6195 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6196 (DRXK_VERSION_PATCH % 10);
6197 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6198 driver_version);
6199 if (status < 0)
6200 goto error;
6201
6202 pr_info("DRXK driver version %d.%d.%d\n",
6203 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6204 DRXK_VERSION_PATCH);
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214
6215
6216
6217 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6218 if (status < 0)
6219 goto error;
6220
6221
6222
6223 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6224 if (status < 0)
6225 goto error;
6226
6227 status = mpegts_dto_init(state);
6228 if (status < 0)
6229 goto error;
6230 status = mpegts_stop(state);
6231 if (status < 0)
6232 goto error;
6233 status = mpegts_configure_polarity(state);
6234 if (status < 0)
6235 goto error;
6236 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6237 if (status < 0)
6238 goto error;
6239
6240 status = write_gpio(state);
6241 if (status < 0)
6242 goto error;
6243
6244 state->m_drxk_state = DRXK_STOPPED;
6245
6246 if (state->m_b_power_down) {
6247 status = power_down_device(state);
6248 if (status < 0)
6249 goto error;
6250 state->m_drxk_state = DRXK_POWERED_DOWN;
6251 } else
6252 state->m_drxk_state = DRXK_STOPPED;
6253
6254
6255 n = 0;
6256 if (state->m_has_dvbc) {
6257 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6258 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6259 strlcat(state->frontend.ops.info.name, " DVB-C",
6260 sizeof(state->frontend.ops.info.name));
6261 }
6262 if (state->m_has_dvbt) {
6263 state->frontend.ops.delsys[n++] = SYS_DVBT;
6264 strlcat(state->frontend.ops.info.name, " DVB-T",
6265 sizeof(state->frontend.ops.info.name));
6266 }
6267 drxk_i2c_unlock(state);
6268 }
6269error:
6270 if (status < 0) {
6271 state->m_drxk_state = DRXK_NO_DEV;
6272 drxk_i2c_unlock(state);
6273 pr_err("Error %d on %s\n", status, __func__);
6274 }
6275
6276 return status;
6277}
6278
6279static void load_firmware_cb(const struct firmware *fw,
6280 void *context)
6281{
6282 struct drxk_state *state = context;
6283
6284 dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6285 if (!fw) {
6286 pr_err("Could not load firmware file %s.\n",
6287 state->microcode_name);
6288 pr_info("Copy %s to your hotplug directory!\n",
6289 state->microcode_name);
6290 state->microcode_name = NULL;
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301
6302 }
6303 state->fw = fw;
6304
6305 init_drxk(state);
6306}
6307
6308static void drxk_release(struct dvb_frontend *fe)
6309{
6310 struct drxk_state *state = fe->demodulator_priv;
6311
6312 dprintk(1, "\n");
6313 release_firmware(state->fw);
6314
6315 kfree(state);
6316}
6317
6318static int drxk_sleep(struct dvb_frontend *fe)
6319{
6320 struct drxk_state *state = fe->demodulator_priv;
6321
6322 dprintk(1, "\n");
6323
6324 if (state->m_drxk_state == DRXK_NO_DEV)
6325 return -ENODEV;
6326 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6327 return 0;
6328
6329 shut_down(state);
6330 return 0;
6331}
6332
6333static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6334{
6335 struct drxk_state *state = fe->demodulator_priv;
6336
6337 dprintk(1, ": %s\n", enable ? "enable" : "disable");
6338
6339 if (state->m_drxk_state == DRXK_NO_DEV)
6340 return -ENODEV;
6341
6342 return ConfigureI2CBridge(state, enable ? true : false);
6343}
6344
6345static int drxk_set_parameters(struct dvb_frontend *fe)
6346{
6347 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6348 u32 delsys = p->delivery_system, old_delsys;
6349 struct drxk_state *state = fe->demodulator_priv;
6350 u32 IF;
6351
6352 dprintk(1, "\n");
6353
6354 if (state->m_drxk_state == DRXK_NO_DEV)
6355 return -ENODEV;
6356
6357 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6358 return -EAGAIN;
6359
6360 if (!fe->ops.tuner_ops.get_if_frequency) {
6361 pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6362 return -EINVAL;
6363 }
6364
6365 if (fe->ops.i2c_gate_ctrl)
6366 fe->ops.i2c_gate_ctrl(fe, 1);
6367 if (fe->ops.tuner_ops.set_params)
6368 fe->ops.tuner_ops.set_params(fe);
6369 if (fe->ops.i2c_gate_ctrl)
6370 fe->ops.i2c_gate_ctrl(fe, 0);
6371
6372 old_delsys = state->props.delivery_system;
6373 state->props = *p;
6374
6375 if (old_delsys != delsys) {
6376 shut_down(state);
6377 switch (delsys) {
6378 case SYS_DVBC_ANNEX_A:
6379 case SYS_DVBC_ANNEX_C:
6380 if (!state->m_has_dvbc)
6381 return -EINVAL;
6382 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6383 true : false;
6384 if (state->m_itut_annex_c)
6385 setoperation_mode(state, OM_QAM_ITU_C);
6386 else
6387 setoperation_mode(state, OM_QAM_ITU_A);
6388 break;
6389 case SYS_DVBT:
6390 if (!state->m_has_dvbt)
6391 return -EINVAL;
6392 setoperation_mode(state, OM_DVBT);
6393 break;
6394 default:
6395 return -EINVAL;
6396 }
6397 }
6398
6399 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6400 start(state, 0, IF);
6401
6402
6403 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6404 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6405 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6406 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6407 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6408 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6409 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6410 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6411
6412
6413
6414 return 0;
6415}
6416
6417static int get_strength(struct drxk_state *state, u64 *strength)
6418{
6419 int status;
6420 struct s_cfg_agc rf_agc, if_agc;
6421 u32 total_gain = 0;
6422 u32 atten = 0;
6423 u32 agc_range = 0;
6424 u16 scu_lvl = 0;
6425 u16 scu_coc = 0;
6426
6427 u16 tuner_rf_gain = 50;
6428 u16 tuner_if_gain = 40;
6429
6430 *strength = 0;
6431
6432 if (is_dvbt(state)) {
6433 rf_agc = state->m_dvbt_rf_agc_cfg;
6434 if_agc = state->m_dvbt_if_agc_cfg;
6435 } else if (is_qam(state)) {
6436 rf_agc = state->m_qam_rf_agc_cfg;
6437 if_agc = state->m_qam_if_agc_cfg;
6438 } else {
6439 rf_agc = state->m_atv_rf_agc_cfg;
6440 if_agc = state->m_atv_if_agc_cfg;
6441 }
6442
6443 if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6444
6445 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6446 if (status < 0)
6447 return status;
6448
6449
6450 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6451 if (status < 0)
6452 return status;
6453
6454 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6455 rf_agc.output_level = scu_lvl + scu_coc;
6456 else
6457 rf_agc.output_level = 0xffff;
6458
6459
6460 total_gain += tuner_rf_gain;
6461
6462
6463 if (rf_agc.output_level < rf_agc.min_output_level)
6464 rf_agc.output_level = rf_agc.min_output_level;
6465 if (rf_agc.output_level > rf_agc.max_output_level)
6466 rf_agc.output_level = rf_agc.max_output_level;
6467
6468 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6469 if (agc_range > 0) {
6470 atten += 100UL *
6471 ((u32)(tuner_rf_gain)) *
6472 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6473 / agc_range;
6474 }
6475 }
6476
6477 if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6478 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6479 &if_agc.output_level);
6480 if (status < 0)
6481 return status;
6482
6483 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6484 &if_agc.top);
6485 if (status < 0)
6486 return status;
6487
6488
6489 total_gain += (u32) tuner_if_gain;
6490
6491
6492 if (if_agc.output_level < if_agc.min_output_level)
6493 if_agc.output_level = if_agc.min_output_level;
6494 if (if_agc.output_level > if_agc.max_output_level)
6495 if_agc.output_level = if_agc.max_output_level;
6496
6497 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
6498 if (agc_range > 0) {
6499 atten += 100UL *
6500 ((u32)(tuner_if_gain)) *
6501 ((u32)(if_agc.output_level - if_agc.min_output_level))
6502 / agc_range;
6503 }
6504 }
6505
6506
6507
6508
6509
6510 if (total_gain > 0)
6511 *strength = (65535UL * atten / total_gain / 100);
6512 else
6513 *strength = 65535;
6514
6515 return 0;
6516}
6517
6518static int drxk_get_stats(struct dvb_frontend *fe)
6519{
6520 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6521 struct drxk_state *state = fe->demodulator_priv;
6522 int status;
6523 u32 stat;
6524 u16 reg16;
6525 u32 post_bit_count;
6526 u32 post_bit_err_count;
6527 u32 post_bit_error_scale;
6528 u32 pre_bit_err_count;
6529 u32 pre_bit_count;
6530 u32 pkt_count;
6531 u32 pkt_error_count;
6532 s32 cnr;
6533
6534 if (state->m_drxk_state == DRXK_NO_DEV)
6535 return -ENODEV;
6536 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6537 return -EAGAIN;
6538
6539
6540 state->fe_status = 0;
6541 get_lock_status(state, &stat);
6542 if (stat == MPEG_LOCK)
6543 state->fe_status |= 0x1f;
6544 if (stat == FEC_LOCK)
6545 state->fe_status |= 0x0f;
6546 if (stat == DEMOD_LOCK)
6547 state->fe_status |= 0x07;
6548
6549
6550
6551
6552 get_strength(state, &c->strength.stat[0].uvalue);
6553 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6554
6555
6556 if (stat >= DEMOD_LOCK) {
6557 get_signal_to_noise(state, &cnr);
6558 c->cnr.stat[0].svalue = cnr * 100;
6559 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6560 } else {
6561 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6562 }
6563
6564 if (stat < FEC_LOCK) {
6565 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6566 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6567 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6568 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6569 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6570 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6571 return 0;
6572 }
6573
6574
6575
6576
6577
6578
6579
6580
6581
6582
6583
6584
6585 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6586 if (status < 0)
6587 goto error;
6588 pre_bit_err_count = reg16;
6589
6590 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6591 if (status < 0)
6592 goto error;
6593 pre_bit_count = reg16;
6594
6595
6596 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6597 if (status < 0)
6598 goto error;
6599 post_bit_err_count = reg16;
6600
6601 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6602 if (status < 0)
6603 goto error;
6604 post_bit_error_scale = reg16;
6605
6606 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6607 if (status < 0)
6608 goto error;
6609 pkt_count = reg16;
6610
6611 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6612 if (status < 0)
6613 goto error;
6614 pkt_error_count = reg16;
6615 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6616
6617 post_bit_err_count *= post_bit_error_scale;
6618
6619 post_bit_count = pkt_count * 204 * 8;
6620
6621
6622 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6623 c->block_error.stat[0].uvalue += pkt_error_count;
6624 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6625 c->block_count.stat[0].uvalue += pkt_count;
6626
6627 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6628 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6629 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6630 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6631
6632 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6633 c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6634 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6635 c->post_bit_count.stat[0].uvalue += post_bit_count;
6636
6637error:
6638 return status;
6639}
6640
6641
6642static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6643{
6644 struct drxk_state *state = fe->demodulator_priv;
6645 int rc;
6646
6647 dprintk(1, "\n");
6648
6649 rc = drxk_get_stats(fe);
6650 if (rc < 0)
6651 return rc;
6652
6653 *status = state->fe_status;
6654
6655 return 0;
6656}
6657
6658static int drxk_read_signal_strength(struct dvb_frontend *fe,
6659 u16 *strength)
6660{
6661 struct drxk_state *state = fe->demodulator_priv;
6662 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6663
6664 dprintk(1, "\n");
6665
6666 if (state->m_drxk_state == DRXK_NO_DEV)
6667 return -ENODEV;
6668 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6669 return -EAGAIN;
6670
6671 *strength = c->strength.stat[0].uvalue;
6672 return 0;
6673}
6674
6675static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6676{
6677 struct drxk_state *state = fe->demodulator_priv;
6678 s32 snr2;
6679
6680 dprintk(1, "\n");
6681
6682 if (state->m_drxk_state == DRXK_NO_DEV)
6683 return -ENODEV;
6684 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6685 return -EAGAIN;
6686
6687 get_signal_to_noise(state, &snr2);
6688
6689
6690 if (snr2 < 0)
6691 snr2 = 0;
6692 *snr = snr2 & 0xffff;
6693 return 0;
6694}
6695
6696static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6697{
6698 struct drxk_state *state = fe->demodulator_priv;
6699 u16 err;
6700
6701 dprintk(1, "\n");
6702
6703 if (state->m_drxk_state == DRXK_NO_DEV)
6704 return -ENODEV;
6705 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6706 return -EAGAIN;
6707
6708 dvbtqam_get_acc_pkt_err(state, &err);
6709 *ucblocks = (u32) err;
6710 return 0;
6711}
6712
6713static int drxk_get_tune_settings(struct dvb_frontend *fe,
6714 struct dvb_frontend_tune_settings *sets)
6715{
6716 struct drxk_state *state = fe->demodulator_priv;
6717 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6718
6719 dprintk(1, "\n");
6720
6721 if (state->m_drxk_state == DRXK_NO_DEV)
6722 return -ENODEV;
6723 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6724 return -EAGAIN;
6725
6726 switch (p->delivery_system) {
6727 case SYS_DVBC_ANNEX_A:
6728 case SYS_DVBC_ANNEX_C:
6729 case SYS_DVBT:
6730 sets->min_delay_ms = 3000;
6731 sets->max_drift = 0;
6732 sets->step_size = 0;
6733 return 0;
6734 default:
6735 return -EINVAL;
6736 }
6737}
6738
6739static struct dvb_frontend_ops drxk_ops = {
6740
6741 .info = {
6742 .name = "DRXK",
6743 .frequency_min = 47000000,
6744 .frequency_max = 865000000,
6745
6746 .symbol_rate_min = 870000,
6747 .symbol_rate_max = 11700000,
6748
6749 .frequency_stepsize = 166667,
6750
6751 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6752 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6753 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6754 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6755 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6756 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6757 },
6758
6759 .release = drxk_release,
6760 .sleep = drxk_sleep,
6761 .i2c_gate_ctrl = drxk_gate_ctrl,
6762
6763 .set_frontend = drxk_set_parameters,
6764 .get_tune_settings = drxk_get_tune_settings,
6765
6766 .read_status = drxk_read_status,
6767 .read_signal_strength = drxk_read_signal_strength,
6768 .read_snr = drxk_read_snr,
6769 .read_ucblocks = drxk_read_ucblocks,
6770};
6771
6772struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6773 struct i2c_adapter *i2c)
6774{
6775 struct dtv_frontend_properties *p;
6776 struct drxk_state *state = NULL;
6777 u8 adr = config->adr;
6778 int status;
6779
6780 dprintk(1, "\n");
6781 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6782 if (!state)
6783 return NULL;
6784
6785 state->i2c = i2c;
6786 state->demod_address = adr;
6787 state->single_master = config->single_master;
6788 state->microcode_name = config->microcode_name;
6789 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6790 state->no_i2c_bridge = config->no_i2c_bridge;
6791 state->antenna_gpio = config->antenna_gpio;
6792 state->antenna_dvbt = config->antenna_dvbt;
6793 state->m_chunk_size = config->chunk_size;
6794 state->enable_merr_cfg = config->enable_merr_cfg;
6795
6796 if (config->dynamic_clk) {
6797 state->m_dvbt_static_clk = false;
6798 state->m_dvbc_static_clk = false;
6799 } else {
6800 state->m_dvbt_static_clk = true;
6801 state->m_dvbc_static_clk = true;
6802 }
6803
6804
6805 if (config->mpeg_out_clk_strength)
6806 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6807 else
6808 state->m_ts_clockk_strength = 0x06;
6809
6810 if (config->parallel_ts)
6811 state->m_enable_parallel = true;
6812 else
6813 state->m_enable_parallel = false;
6814
6815
6816 state->uio_mask = config->antenna_gpio;
6817
6818
6819 if (!state->antenna_dvbt && state->antenna_gpio)
6820 state->m_gpio |= state->antenna_gpio;
6821 else
6822 state->m_gpio &= ~state->antenna_gpio;
6823
6824 mutex_init(&state->mutex);
6825
6826 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6827 state->frontend.demodulator_priv = state;
6828
6829 init_state(state);
6830
6831
6832 if (state->microcode_name) {
6833 const struct firmware *fw = NULL;
6834
6835 status = request_firmware(&fw, state->microcode_name,
6836 state->i2c->dev.parent);
6837 if (status < 0)
6838 fw = NULL;
6839 load_firmware_cb(fw, state);
6840 } else if (init_drxk(state) < 0)
6841 goto error;
6842
6843
6844
6845 p = &state->frontend.dtv_property_cache;
6846 p->strength.len = 1;
6847 p->cnr.len = 1;
6848 p->block_error.len = 1;
6849 p->block_count.len = 1;
6850 p->pre_bit_error.len = 1;
6851 p->pre_bit_count.len = 1;
6852 p->post_bit_error.len = 1;
6853 p->post_bit_count.len = 1;
6854
6855 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6856 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6857 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6858 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6859 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6860 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6861 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6862 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6863
6864 pr_info("frontend initialized.\n");
6865 return &state->frontend;
6866
6867error:
6868 pr_err("not found\n");
6869 kfree(state);
6870 return NULL;
6871}
6872EXPORT_SYMBOL(drxk_attach);
6873
6874MODULE_DESCRIPTION("DRX-K driver");
6875MODULE_AUTHOR("Ralph Metzler");
6876MODULE_LICENSE("GPL");
6877
