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10#include <linux/interrupt.h>
11#include <linux/workqueue.h>
12#include <linux/sched.h>
13#include <linux/wait.h>
14#include <linux/slab.h>
15#include <linux/pid.h>
16#include <asm/cputable.h>
17#include <misc/cxl.h>
18
19#include "cxl.h"
20#include "trace.h"
21
22
23static irqreturn_t handle_psl_slice_error(struct cxl_context *ctx, u64 dsisr, u64 errstat)
24{
25 u64 fir1, fir2, fir_slice, serr, afu_debug;
26
27 fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1);
28 fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2);
29 fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An);
30 serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
31 afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An);
32
33 dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%.16llx\n", errstat);
34 dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%.16llx\n", fir1);
35 dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%.16llx\n", fir2);
36 dev_crit(&ctx->afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr);
37 dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice);
38 dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug);
39
40 dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n");
41 cxl_stop_trace(ctx->afu->adapter);
42
43 return cxl_ack_irq(ctx, 0, errstat);
44}
45
46irqreturn_t cxl_slice_irq_err(int irq, void *data)
47{
48 struct cxl_afu *afu = data;
49 u64 fir_slice, errstat, serr, afu_debug;
50
51 WARN(irq, "CXL SLICE ERROR interrupt %i\n", irq);
52
53 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
54 fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An);
55 errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
56 afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An);
57 dev_crit(&afu->dev, "PSL_SERR_An: 0x%.16llx\n", serr);
58 dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%.16llx\n", fir_slice);
59 dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%.16llx\n", errstat);
60 dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%.16llx\n", afu_debug);
61
62 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
63
64 return IRQ_HANDLED;
65}
66
67static irqreturn_t cxl_irq_err(int irq, void *data)
68{
69 struct cxl *adapter = data;
70 u64 fir1, fir2, err_ivte;
71
72 WARN(1, "CXL ERROR interrupt %i\n", irq);
73
74 err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE);
75 dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%.16llx\n", err_ivte);
76
77 dev_crit(&adapter->dev, "STOPPING CXL TRACE\n");
78 cxl_stop_trace(adapter);
79
80 fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
81 fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
82
83 dev_crit(&adapter->dev, "PSL_FIR1: 0x%.16llx\nPSL_FIR2: 0x%.16llx\n", fir1, fir2);
84
85 return IRQ_HANDLED;
86}
87
88static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
89{
90 ctx->dsisr = dsisr;
91 ctx->dar = dar;
92 schedule_work(&ctx->fault_work);
93 return IRQ_HANDLED;
94}
95
96static irqreturn_t cxl_irq(int irq, void *data, struct cxl_irq_info *irq_info)
97{
98 struct cxl_context *ctx = data;
99 u64 dsisr, dar;
100
101 dsisr = irq_info->dsisr;
102 dar = irq_info->dar;
103
104 trace_cxl_psl_irq(ctx, irq, dsisr, dar);
105
106 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
107
108 if (dsisr & CXL_PSL_DSISR_An_DS) {
109
110
111
112
113
114
115
116
117
118
119 pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe);
120 return schedule_cxl_fault(ctx, dsisr, dar);
121 }
122
123 if (dsisr & CXL_PSL_DSISR_An_M)
124 pr_devel("CXL interrupt: PTE not found\n");
125 if (dsisr & CXL_PSL_DSISR_An_P)
126 pr_devel("CXL interrupt: Storage protection violation\n");
127 if (dsisr & CXL_PSL_DSISR_An_A)
128 pr_devel("CXL interrupt: AFU lock access to write through or cache inhibited storage\n");
129 if (dsisr & CXL_PSL_DSISR_An_S)
130 pr_devel("CXL interrupt: Access was afu_wr or afu_zero\n");
131 if (dsisr & CXL_PSL_DSISR_An_K)
132 pr_devel("CXL interrupt: Access not permitted by virtual page class key protection\n");
133
134 if (dsisr & CXL_PSL_DSISR_An_DM) {
135
136
137
138
139
140 pr_devel("Scheduling page fault handling for later pe: %i\n", ctx->pe);
141 return schedule_cxl_fault(ctx, dsisr, dar);
142 }
143 if (dsisr & CXL_PSL_DSISR_An_ST)
144 WARN(1, "CXL interrupt: Segment Table PTE not found\n");
145 if (dsisr & CXL_PSL_DSISR_An_UR)
146 pr_devel("CXL interrupt: AURP PTE not found\n");
147 if (dsisr & CXL_PSL_DSISR_An_PE)
148 return handle_psl_slice_error(ctx, dsisr, irq_info->errstat);
149 if (dsisr & CXL_PSL_DSISR_An_AE) {
150 pr_devel("CXL interrupt: AFU Error %.llx\n", irq_info->afu_err);
151
152 if (ctx->pending_afu_err) {
153
154
155
156
157
158
159
160 dev_err_ratelimited(&ctx->afu->dev, "CXL AFU Error "
161 "undelivered to pe %i: %.llx\n",
162 ctx->pe, irq_info->afu_err);
163 } else {
164 spin_lock(&ctx->lock);
165 ctx->afu_err = irq_info->afu_err;
166 ctx->pending_afu_err = 1;
167 spin_unlock(&ctx->lock);
168
169 wake_up_all(&ctx->wq);
170 }
171
172 cxl_ack_irq(ctx, CXL_PSL_TFC_An_A, 0);
173 return IRQ_HANDLED;
174 }
175 if (dsisr & CXL_PSL_DSISR_An_OC)
176 pr_devel("CXL interrupt: OS Context Warning\n");
177
178 WARN(1, "Unhandled CXL PSL IRQ\n");
179 return IRQ_HANDLED;
180}
181
182static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info)
183{
184 if (irq_info->dsisr & CXL_PSL_DSISR_TRANS)
185 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
186 else
187 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
188
189 return IRQ_HANDLED;
190}
191
192static irqreturn_t cxl_irq_multiplexed(int irq, void *data)
193{
194 struct cxl_afu *afu = data;
195 struct cxl_context *ctx;
196 struct cxl_irq_info irq_info;
197 int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff;
198 int ret;
199
200 if ((ret = cxl_get_irq(afu, &irq_info))) {
201 WARN(1, "Unable to get CXL IRQ Info: %i\n", ret);
202 return fail_psl_irq(afu, &irq_info);
203 }
204
205 rcu_read_lock();
206 ctx = idr_find(&afu->contexts_idr, ph);
207 if (ctx) {
208 ret = cxl_irq(irq, ctx, &irq_info);
209 rcu_read_unlock();
210 return ret;
211 }
212 rcu_read_unlock();
213
214 WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %.16llx DAR"
215 " %.16llx\n(Possible AFU HW issue - was a term/remove acked"
216 " with outstanding transactions?)\n", ph, irq_info.dsisr,
217 irq_info.dar);
218 return fail_psl_irq(afu, &irq_info);
219}
220
221static irqreturn_t cxl_irq_afu(int irq, void *data)
222{
223 struct cxl_context *ctx = data;
224 irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq));
225 int irq_off, afu_irq = 1;
226 __u16 range;
227 int r;
228
229 for (r = 1; r < CXL_IRQ_RANGES; r++) {
230 irq_off = hwirq - ctx->irqs.offset[r];
231 range = ctx->irqs.range[r];
232 if (irq_off >= 0 && irq_off < range) {
233 afu_irq += irq_off;
234 break;
235 }
236 afu_irq += range;
237 }
238 if (unlikely(r >= CXL_IRQ_RANGES)) {
239 WARN(1, "Recieved AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n",
240 ctx->pe, irq, hwirq);
241 return IRQ_HANDLED;
242 }
243
244 trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq);
245 pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n",
246 afu_irq, ctx->pe, irq, hwirq);
247
248 if (unlikely(!ctx->irq_bitmap)) {
249 WARN(1, "Recieved AFU IRQ for context with no IRQ bitmap\n");
250 return IRQ_HANDLED;
251 }
252 spin_lock(&ctx->lock);
253 set_bit(afu_irq - 1, ctx->irq_bitmap);
254 ctx->pending_irq = true;
255 spin_unlock(&ctx->lock);
256
257 wake_up_all(&ctx->wq);
258
259 return IRQ_HANDLED;
260}
261
262unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
263 irq_handler_t handler, void *cookie, const char *name)
264{
265 unsigned int virq;
266 int result;
267
268
269 virq = irq_create_mapping(NULL, hwirq);
270 if (!virq) {
271 dev_warn(&adapter->dev, "cxl_map_irq: irq_create_mapping failed\n");
272 return 0;
273 }
274
275 cxl_setup_irq(adapter, hwirq, virq);
276
277 pr_devel("hwirq %#lx mapped to virq %u\n", hwirq, virq);
278
279 result = request_irq(virq, handler, 0, name, cookie);
280 if (result) {
281 dev_warn(&adapter->dev, "cxl_map_irq: request_irq failed: %i\n", result);
282 return 0;
283 }
284
285 return virq;
286}
287
288void cxl_unmap_irq(unsigned int virq, void *cookie)
289{
290 free_irq(virq, cookie);
291 irq_dispose_mapping(virq);
292}
293
294static int cxl_register_one_irq(struct cxl *adapter,
295 irq_handler_t handler,
296 void *cookie,
297 irq_hw_number_t *dest_hwirq,
298 unsigned int *dest_virq,
299 const char *name)
300{
301 int hwirq, virq;
302
303 if ((hwirq = cxl_alloc_one_irq(adapter)) < 0)
304 return hwirq;
305
306 if (!(virq = cxl_map_irq(adapter, hwirq, handler, cookie, name)))
307 goto err;
308
309 *dest_hwirq = hwirq;
310 *dest_virq = virq;
311
312 return 0;
313
314err:
315 cxl_release_one_irq(adapter, hwirq);
316 return -ENOMEM;
317}
318
319int cxl_register_psl_err_irq(struct cxl *adapter)
320{
321 int rc;
322
323 adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
324 dev_name(&adapter->dev));
325 if (!adapter->irq_name)
326 return -ENOMEM;
327
328 if ((rc = cxl_register_one_irq(adapter, cxl_irq_err, adapter,
329 &adapter->err_hwirq,
330 &adapter->err_virq,
331 adapter->irq_name))) {
332 kfree(adapter->irq_name);
333 adapter->irq_name = NULL;
334 return rc;
335 }
336
337 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->err_hwirq & 0xffff);
338
339 return 0;
340}
341
342void cxl_release_psl_err_irq(struct cxl *adapter)
343{
344 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000);
345 cxl_unmap_irq(adapter->err_virq, adapter);
346 cxl_release_one_irq(adapter, adapter->err_hwirq);
347 kfree(adapter->irq_name);
348}
349
350int cxl_register_serr_irq(struct cxl_afu *afu)
351{
352 u64 serr;
353 int rc;
354
355 afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err",
356 dev_name(&afu->dev));
357 if (!afu->err_irq_name)
358 return -ENOMEM;
359
360 if ((rc = cxl_register_one_irq(afu->adapter, cxl_slice_irq_err, afu,
361 &afu->serr_hwirq,
362 &afu->serr_virq, afu->err_irq_name))) {
363 kfree(afu->err_irq_name);
364 afu->err_irq_name = NULL;
365 return rc;
366 }
367
368 serr = cxl_p1n_read(afu, CXL_PSL_SERR_An);
369 serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff);
370 cxl_p1n_write(afu, CXL_PSL_SERR_An, serr);
371
372 return 0;
373}
374
375void cxl_release_serr_irq(struct cxl_afu *afu)
376{
377 cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000);
378 cxl_unmap_irq(afu->serr_virq, afu);
379 cxl_release_one_irq(afu->adapter, afu->serr_hwirq);
380 kfree(afu->err_irq_name);
381}
382
383int cxl_register_psl_irq(struct cxl_afu *afu)
384{
385 int rc;
386
387 afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s",
388 dev_name(&afu->dev));
389 if (!afu->psl_irq_name)
390 return -ENOMEM;
391
392 if ((rc = cxl_register_one_irq(afu->adapter, cxl_irq_multiplexed, afu,
393 &afu->psl_hwirq, &afu->psl_virq,
394 afu->psl_irq_name))) {
395 kfree(afu->psl_irq_name);
396 afu->psl_irq_name = NULL;
397 }
398 return rc;
399}
400
401void cxl_release_psl_irq(struct cxl_afu *afu)
402{
403 cxl_unmap_irq(afu->psl_virq, afu);
404 cxl_release_one_irq(afu->adapter, afu->psl_hwirq);
405 kfree(afu->psl_irq_name);
406}
407
408void afu_irq_name_free(struct cxl_context *ctx)
409{
410 struct cxl_irq_name *irq_name, *tmp;
411
412 list_for_each_entry_safe(irq_name, tmp, &ctx->irq_names, list) {
413 kfree(irq_name->name);
414 list_del(&irq_name->list);
415 kfree(irq_name);
416 }
417}
418
419int afu_register_irqs(struct cxl_context *ctx, u32 count)
420{
421 irq_hw_number_t hwirq;
422 int rc, r, i, j = 1;
423 struct cxl_irq_name *irq_name;
424
425 if ((rc = cxl_alloc_irq_ranges(&ctx->irqs, ctx->afu->adapter, count)))
426 return rc;
427
428
429 ctx->irqs.offset[0] = ctx->afu->psl_hwirq;
430 ctx->irqs.range[0] = 1;
431
432 ctx->irq_count = count;
433 ctx->irq_bitmap = kcalloc(BITS_TO_LONGS(count),
434 sizeof(*ctx->irq_bitmap), GFP_KERNEL);
435 if (!ctx->irq_bitmap)
436 return -ENOMEM;
437
438
439
440
441
442 INIT_LIST_HEAD(&ctx->irq_names);
443 for (r = 1; r < CXL_IRQ_RANGES; r++) {
444 for (i = 0; i < ctx->irqs.range[r]; i++) {
445 irq_name = kmalloc(sizeof(struct cxl_irq_name),
446 GFP_KERNEL);
447 if (!irq_name)
448 goto out;
449 irq_name->name = kasprintf(GFP_KERNEL, "cxl-%s-pe%i-%i",
450 dev_name(&ctx->afu->dev),
451 ctx->pe, j);
452 if (!irq_name->name) {
453 kfree(irq_name);
454 goto out;
455 }
456
457 list_add_tail(&irq_name->list, &ctx->irq_names);
458 j++;
459 }
460 }
461
462
463 irq_name = list_first_entry(&ctx->irq_names, struct cxl_irq_name, list);
464 for (r = 1; r < CXL_IRQ_RANGES; r++) {
465 hwirq = ctx->irqs.offset[r];
466 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
467 cxl_map_irq(ctx->afu->adapter, hwirq,
468 cxl_irq_afu, ctx, irq_name->name);
469 irq_name = list_next_entry(irq_name, list);
470 }
471 }
472
473 return 0;
474
475out:
476 afu_irq_name_free(ctx);
477 return -ENOMEM;
478}
479
480void afu_release_irqs(struct cxl_context *ctx)
481{
482 irq_hw_number_t hwirq;
483 unsigned int virq;
484 int r, i;
485
486 for (r = 1; r < CXL_IRQ_RANGES; r++) {
487 hwirq = ctx->irqs.offset[r];
488 for (i = 0; i < ctx->irqs.range[r]; hwirq++, i++) {
489 virq = irq_find_mapping(NULL, hwirq);
490 if (virq)
491 cxl_unmap_irq(virq, ctx);
492 }
493 }
494
495 afu_irq_name_free(ctx);
496 cxl_release_irq_ranges(&ctx->irqs, ctx->afu->adapter);
497}
498
