linux/drivers/mtd/devices/st_spi_fsm.c
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   1/*
   2 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
   3 *
   4 * Author: Angus Clark <angus.clark@st.com>
   5 *
   6 * Copyright (C) 2010-2014 STMicroelectronics Limited
   7 *
   8 * JEDEC probe based on drivers/mtd/devices/m25p80.c
   9 *
  10 * This code is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 *
  14 */
  15#include <linux/kernel.h>
  16#include <linux/module.h>
  17#include <linux/regmap.h>
  18#include <linux/platform_device.h>
  19#include <linux/mfd/syscon.h>
  20#include <linux/mtd/mtd.h>
  21#include <linux/mtd/partitions.h>
  22#include <linux/mtd/spi-nor.h>
  23#include <linux/sched.h>
  24#include <linux/delay.h>
  25#include <linux/io.h>
  26#include <linux/of.h>
  27#include <linux/clk.h>
  28
  29#include "serial_flash_cmds.h"
  30
  31/*
  32 * FSM SPI Controller Registers
  33 */
  34#define SPI_CLOCKDIV                    0x0010
  35#define SPI_MODESELECT                  0x0018
  36#define SPI_CONFIGDATA                  0x0020
  37#define SPI_STA_MODE_CHANGE             0x0028
  38#define SPI_FAST_SEQ_TRANSFER_SIZE      0x0100
  39#define SPI_FAST_SEQ_ADD1               0x0104
  40#define SPI_FAST_SEQ_ADD2               0x0108
  41#define SPI_FAST_SEQ_ADD_CFG            0x010c
  42#define SPI_FAST_SEQ_OPC1               0x0110
  43#define SPI_FAST_SEQ_OPC2               0x0114
  44#define SPI_FAST_SEQ_OPC3               0x0118
  45#define SPI_FAST_SEQ_OPC4               0x011c
  46#define SPI_FAST_SEQ_OPC5               0x0120
  47#define SPI_MODE_BITS                   0x0124
  48#define SPI_DUMMY_BITS                  0x0128
  49#define SPI_FAST_SEQ_FLASH_STA_DATA     0x012c
  50#define SPI_FAST_SEQ_1                  0x0130
  51#define SPI_FAST_SEQ_2                  0x0134
  52#define SPI_FAST_SEQ_3                  0x0138
  53#define SPI_FAST_SEQ_4                  0x013c
  54#define SPI_FAST_SEQ_CFG                0x0140
  55#define SPI_FAST_SEQ_STA                0x0144
  56#define SPI_QUAD_BOOT_SEQ_INIT_1        0x0148
  57#define SPI_QUAD_BOOT_SEQ_INIT_2        0x014c
  58#define SPI_QUAD_BOOT_READ_SEQ_1        0x0150
  59#define SPI_QUAD_BOOT_READ_SEQ_2        0x0154
  60#define SPI_PROGRAM_ERASE_TIME          0x0158
  61#define SPI_MULT_PAGE_REPEAT_SEQ_1      0x015c
  62#define SPI_MULT_PAGE_REPEAT_SEQ_2      0x0160
  63#define SPI_STATUS_WR_TIME_REG          0x0164
  64#define SPI_FAST_SEQ_DATA_REG           0x0300
  65
  66/*
  67 * Register: SPI_MODESELECT
  68 */
  69#define SPI_MODESELECT_CONTIG           0x01
  70#define SPI_MODESELECT_FASTREAD         0x02
  71#define SPI_MODESELECT_DUALIO           0x04
  72#define SPI_MODESELECT_FSM              0x08
  73#define SPI_MODESELECT_QUADBOOT         0x10
  74
  75/*
  76 * Register: SPI_CONFIGDATA
  77 */
  78#define SPI_CFG_DEVICE_ST               0x1
  79#define SPI_CFG_DEVICE_ATMEL            0x4
  80#define SPI_CFG_MIN_CS_HIGH(x)          (((x) & 0xfff) << 4)
  81#define SPI_CFG_CS_SETUPHOLD(x)         (((x) & 0xff) << 16)
  82#define SPI_CFG_DATA_HOLD(x)            (((x) & 0xff) << 24)
  83
  84#define SPI_CFG_DEFAULT_MIN_CS_HIGH    SPI_CFG_MIN_CS_HIGH(0x0AA)
  85#define SPI_CFG_DEFAULT_CS_SETUPHOLD   SPI_CFG_CS_SETUPHOLD(0xA0)
  86#define SPI_CFG_DEFAULT_DATA_HOLD      SPI_CFG_DATA_HOLD(0x00)
  87
  88/*
  89 * Register: SPI_FAST_SEQ_TRANSFER_SIZE
  90 */
  91#define TRANSFER_SIZE(x)                ((x) * 8)
  92
  93/*
  94 * Register: SPI_FAST_SEQ_ADD_CFG
  95 */
  96#define ADR_CFG_CYCLES_ADD1(x)          ((x) << 0)
  97#define ADR_CFG_PADS_1_ADD1             (0x0 << 6)
  98#define ADR_CFG_PADS_2_ADD1             (0x1 << 6)
  99#define ADR_CFG_PADS_4_ADD1             (0x3 << 6)
 100#define ADR_CFG_CSDEASSERT_ADD1         (1   << 8)
 101#define ADR_CFG_CYCLES_ADD2(x)          ((x) << (0+16))
 102#define ADR_CFG_PADS_1_ADD2             (0x0 << (6+16))
 103#define ADR_CFG_PADS_2_ADD2             (0x1 << (6+16))
 104#define ADR_CFG_PADS_4_ADD2             (0x3 << (6+16))
 105#define ADR_CFG_CSDEASSERT_ADD2         (1   << (8+16))
 106
 107/*
 108 * Register: SPI_FAST_SEQ_n
 109 */
 110#define SEQ_OPC_OPCODE(x)               ((x) << 0)
 111#define SEQ_OPC_CYCLES(x)               ((x) << 8)
 112#define SEQ_OPC_PADS_1                  (0x0 << 14)
 113#define SEQ_OPC_PADS_2                  (0x1 << 14)
 114#define SEQ_OPC_PADS_4                  (0x3 << 14)
 115#define SEQ_OPC_CSDEASSERT              (1   << 16)
 116
 117/*
 118 * Register: SPI_FAST_SEQ_CFG
 119 */
 120#define SEQ_CFG_STARTSEQ                (1 << 0)
 121#define SEQ_CFG_SWRESET                 (1 << 5)
 122#define SEQ_CFG_CSDEASSERT              (1 << 6)
 123#define SEQ_CFG_READNOTWRITE            (1 << 7)
 124#define SEQ_CFG_ERASE                   (1 << 8)
 125#define SEQ_CFG_PADS_1                  (0x0 << 16)
 126#define SEQ_CFG_PADS_2                  (0x1 << 16)
 127#define SEQ_CFG_PADS_4                  (0x3 << 16)
 128
 129/*
 130 * Register: SPI_MODE_BITS
 131 */
 132#define MODE_DATA(x)                    (x & 0xff)
 133#define MODE_CYCLES(x)                  ((x & 0x3f) << 16)
 134#define MODE_PADS_1                     (0x0 << 22)
 135#define MODE_PADS_2                     (0x1 << 22)
 136#define MODE_PADS_4                     (0x3 << 22)
 137#define DUMMY_CSDEASSERT                (1   << 24)
 138
 139/*
 140 * Register: SPI_DUMMY_BITS
 141 */
 142#define DUMMY_CYCLES(x)                 ((x & 0x3f) << 16)
 143#define DUMMY_PADS_1                    (0x0 << 22)
 144#define DUMMY_PADS_2                    (0x1 << 22)
 145#define DUMMY_PADS_4                    (0x3 << 22)
 146#define DUMMY_CSDEASSERT                (1   << 24)
 147
 148/*
 149 * Register: SPI_FAST_SEQ_FLASH_STA_DATA
 150 */
 151#define STA_DATA_BYTE1(x)               ((x & 0xff) << 0)
 152#define STA_DATA_BYTE2(x)               ((x & 0xff) << 8)
 153#define STA_PADS_1                      (0x0 << 16)
 154#define STA_PADS_2                      (0x1 << 16)
 155#define STA_PADS_4                      (0x3 << 16)
 156#define STA_CSDEASSERT                  (0x1 << 20)
 157#define STA_RDNOTWR                     (0x1 << 21)
 158
 159/*
 160 * FSM SPI Instruction Opcodes
 161 */
 162#define STFSM_OPC_CMD                   0x1
 163#define STFSM_OPC_ADD                   0x2
 164#define STFSM_OPC_STA                   0x3
 165#define STFSM_OPC_MODE                  0x4
 166#define STFSM_OPC_DUMMY         0x5
 167#define STFSM_OPC_DATA                  0x6
 168#define STFSM_OPC_WAIT                  0x7
 169#define STFSM_OPC_JUMP                  0x8
 170#define STFSM_OPC_GOTO                  0x9
 171#define STFSM_OPC_STOP                  0xF
 172
 173/*
 174 * FSM SPI Instructions (== opcode + operand).
 175 */
 176#define STFSM_INSTR(cmd, op)            ((cmd) | ((op) << 4))
 177
 178#define STFSM_INST_CMD1                 STFSM_INSTR(STFSM_OPC_CMD,      1)
 179#define STFSM_INST_CMD2                 STFSM_INSTR(STFSM_OPC_CMD,      2)
 180#define STFSM_INST_CMD3                 STFSM_INSTR(STFSM_OPC_CMD,      3)
 181#define STFSM_INST_CMD4                 STFSM_INSTR(STFSM_OPC_CMD,      4)
 182#define STFSM_INST_CMD5                 STFSM_INSTR(STFSM_OPC_CMD,      5)
 183#define STFSM_INST_ADD1                 STFSM_INSTR(STFSM_OPC_ADD,      1)
 184#define STFSM_INST_ADD2                 STFSM_INSTR(STFSM_OPC_ADD,      2)
 185
 186#define STFSM_INST_DATA_WRITE           STFSM_INSTR(STFSM_OPC_DATA,     1)
 187#define STFSM_INST_DATA_READ            STFSM_INSTR(STFSM_OPC_DATA,     2)
 188
 189#define STFSM_INST_STA_RD1              STFSM_INSTR(STFSM_OPC_STA,      0x1)
 190#define STFSM_INST_STA_WR1              STFSM_INSTR(STFSM_OPC_STA,      0x1)
 191#define STFSM_INST_STA_RD2              STFSM_INSTR(STFSM_OPC_STA,      0x2)
 192#define STFSM_INST_STA_WR1_2            STFSM_INSTR(STFSM_OPC_STA,      0x3)
 193
 194#define STFSM_INST_MODE                 STFSM_INSTR(STFSM_OPC_MODE,     0)
 195#define STFSM_INST_DUMMY                STFSM_INSTR(STFSM_OPC_DUMMY,    0)
 196#define STFSM_INST_WAIT                 STFSM_INSTR(STFSM_OPC_WAIT,     0)
 197#define STFSM_INST_STOP                 STFSM_INSTR(STFSM_OPC_STOP,     0)
 198
 199#define STFSM_DEFAULT_EMI_FREQ 100000000UL                        /* 100 MHz */
 200#define STFSM_DEFAULT_WR_TIME  (STFSM_DEFAULT_EMI_FREQ * (15/1000)) /* 15ms */
 201
 202#define STFSM_FLASH_SAFE_FREQ  10000000UL                         /* 10 MHz */
 203
 204#define STFSM_MAX_WAIT_SEQ_MS  1000     /* FSM execution time */
 205
 206/* S25FLxxxS commands */
 207#define S25FL_CMD_WRITE4_1_1_4 0x34
 208#define S25FL_CMD_SE4          0xdc
 209#define S25FL_CMD_CLSR         0x30
 210#define S25FL_CMD_DYBWR                0xe1
 211#define S25FL_CMD_DYBRD                0xe0
 212#define S25FL_CMD_WRITE4       0x12    /* Note, opcode clashes with
 213                                        * 'SPINOR_OP_WRITE_1_4_4'
 214                                        * as found on N25Qxxx devices! */
 215
 216/* Status register */
 217#define FLASH_STATUS_BUSY      0x01
 218#define FLASH_STATUS_WEL       0x02
 219#define FLASH_STATUS_BP0       0x04
 220#define FLASH_STATUS_BP1       0x08
 221#define FLASH_STATUS_BP2       0x10
 222#define FLASH_STATUS_SRWP0     0x80
 223#define FLASH_STATUS_TIMEOUT   0xff
 224/* S25FL Error Flags */
 225#define S25FL_STATUS_E_ERR     0x20
 226#define S25FL_STATUS_P_ERR     0x40
 227
 228#define N25Q_CMD_WRVCR         0x81
 229#define N25Q_CMD_RDVCR         0x85
 230#define N25Q_CMD_RDVECR        0x65
 231#define N25Q_CMD_RDNVCR        0xb5
 232#define N25Q_CMD_WRNVCR        0xb1
 233
 234#define FLASH_PAGESIZE         256                      /* In Bytes    */
 235#define FLASH_PAGESIZE_32      (FLASH_PAGESIZE / 4)     /* In uint32_t */
 236#define FLASH_MAX_BUSY_WAIT    (300 * HZ)       /* Maximum 'CHIPERASE' time */
 237
 238/*
 239 * Flags to tweak operation of default read/write/erase routines
 240 */
 241#define CFG_READ_TOGGLE_32BIT_ADDR     0x00000001
 242#define CFG_WRITE_TOGGLE_32BIT_ADDR    0x00000002
 243#define CFG_ERASESEC_TOGGLE_32BIT_ADDR 0x00000008
 244#define CFG_S25FL_CHECK_ERROR_FLAGS    0x00000010
 245
 246struct stfsm_seq {
 247        uint32_t data_size;
 248        uint32_t addr1;
 249        uint32_t addr2;
 250        uint32_t addr_cfg;
 251        uint32_t seq_opc[5];
 252        uint32_t mode;
 253        uint32_t dummy;
 254        uint32_t status;
 255        uint8_t  seq[16];
 256        uint32_t seq_cfg;
 257} __packed __aligned(4);
 258
 259struct stfsm {
 260        struct device           *dev;
 261        void __iomem            *base;
 262        struct resource         *region;
 263        struct mtd_info         mtd;
 264        struct mutex            lock;
 265        struct flash_info       *info;
 266        struct clk              *clk;
 267
 268        uint32_t                configuration;
 269        uint32_t                fifo_dir_delay;
 270        bool                    booted_from_spi;
 271        bool                    reset_signal;
 272        bool                    reset_por;
 273
 274        struct stfsm_seq stfsm_seq_read;
 275        struct stfsm_seq stfsm_seq_write;
 276        struct stfsm_seq stfsm_seq_en_32bit_addr;
 277};
 278
 279/* Parameters to configure a READ or WRITE FSM sequence */
 280struct seq_rw_config {
 281        uint32_t        flags;          /* flags to support config */
 282        uint8_t         cmd;            /* FLASH command */
 283        int             write;          /* Write Sequence */
 284        uint8_t         addr_pads;      /* No. of addr pads (MODE & DUMMY) */
 285        uint8_t         data_pads;      /* No. of data pads */
 286        uint8_t         mode_data;      /* MODE data */
 287        uint8_t         mode_cycles;    /* No. of MODE cycles */
 288        uint8_t         dummy_cycles;   /* No. of DUMMY cycles */
 289};
 290
 291/* SPI Flash Device Table */
 292struct flash_info {
 293        char            *name;
 294        /*
 295         * JEDEC id zero means "no ID" (most older chips); otherwise it has
 296         * a high byte of zero plus three data bytes: the manufacturer id,
 297         * then a two byte device id.
 298         */
 299        u32             jedec_id;
 300        u16             ext_id;
 301        /*
 302         * The size listed here is what works with SPINOR_OP_SE, which isn't
 303         * necessarily called a "sector" by the vendor.
 304         */
 305        unsigned        sector_size;
 306        u16             n_sectors;
 307        u32             flags;
 308        /*
 309         * Note, where FAST_READ is supported, freq_max specifies the
 310         * FAST_READ frequency, not the READ frequency.
 311         */
 312        u32             max_freq;
 313        int             (*config)(struct stfsm *);
 314};
 315
 316static int stfsm_n25q_config(struct stfsm *fsm);
 317static int stfsm_mx25_config(struct stfsm *fsm);
 318static int stfsm_s25fl_config(struct stfsm *fsm);
 319static int stfsm_w25q_config(struct stfsm *fsm);
 320
 321static struct flash_info flash_types[] = {
 322        /*
 323         * ST Microelectronics/Numonyx --
 324         * (newer production versions may have feature updates
 325         * (eg faster operating frequency)
 326         */
 327#define M25P_FLAG (FLASH_FLAG_READ_WRITE | FLASH_FLAG_READ_FAST)
 328        { "m25p40",  0x202013, 0,  64 * 1024,   8, M25P_FLAG, 25, NULL },
 329        { "m25p80",  0x202014, 0,  64 * 1024,  16, M25P_FLAG, 25, NULL },
 330        { "m25p16",  0x202015, 0,  64 * 1024,  32, M25P_FLAG, 25, NULL },
 331        { "m25p32",  0x202016, 0,  64 * 1024,  64, M25P_FLAG, 50, NULL },
 332        { "m25p64",  0x202017, 0,  64 * 1024, 128, M25P_FLAG, 50, NULL },
 333        { "m25p128", 0x202018, 0, 256 * 1024,  64, M25P_FLAG, 50, NULL },
 334
 335#define M25PX_FLAG (FLASH_FLAG_READ_WRITE      |        \
 336                    FLASH_FLAG_READ_FAST        |       \
 337                    FLASH_FLAG_READ_1_1_2       |       \
 338                    FLASH_FLAG_WRITE_1_1_2)
 339        { "m25px32", 0x207116, 0,  64 * 1024,  64, M25PX_FLAG, 75, NULL },
 340        { "m25px64", 0x207117, 0,  64 * 1024, 128, M25PX_FLAG, 75, NULL },
 341
 342        /* Macronix MX25xxx
 343         *     - Support for 'FLASH_FLAG_WRITE_1_4_4' is omitted for devices
 344         *       where operating frequency must be reduced.
 345         */
 346#define MX25_FLAG (FLASH_FLAG_READ_WRITE       |        \
 347                   FLASH_FLAG_READ_FAST         |       \
 348                   FLASH_FLAG_READ_1_1_2        |       \
 349                   FLASH_FLAG_READ_1_2_2        |       \
 350                   FLASH_FLAG_READ_1_1_4        |       \
 351                   FLASH_FLAG_SE_4K             |       \
 352                   FLASH_FLAG_SE_32K)
 353        { "mx25l3255e",  0xc29e16, 0, 64 * 1024, 64,
 354          (MX25_FLAG | FLASH_FLAG_WRITE_1_4_4), 86,
 355          stfsm_mx25_config},
 356        { "mx25l25635e", 0xc22019, 0, 64*1024, 512,
 357          (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70,
 358          stfsm_mx25_config },
 359        { "mx25l25655e", 0xc22619, 0, 64*1024, 512,
 360          (MX25_FLAG | FLASH_FLAG_32BIT_ADDR | FLASH_FLAG_RESET), 70,
 361          stfsm_mx25_config},
 362
 363#define N25Q_FLAG (FLASH_FLAG_READ_WRITE       |        \
 364                   FLASH_FLAG_READ_FAST         |       \
 365                   FLASH_FLAG_READ_1_1_2        |       \
 366                   FLASH_FLAG_READ_1_2_2        |       \
 367                   FLASH_FLAG_READ_1_1_4        |       \
 368                   FLASH_FLAG_READ_1_4_4        |       \
 369                   FLASH_FLAG_WRITE_1_1_2       |       \
 370                   FLASH_FLAG_WRITE_1_2_2       |       \
 371                   FLASH_FLAG_WRITE_1_1_4       |       \
 372                   FLASH_FLAG_WRITE_1_4_4)
 373        { "n25q128", 0x20ba18, 0, 64 * 1024,  256, N25Q_FLAG, 108,
 374          stfsm_n25q_config },
 375        { "n25q256", 0x20ba19, 0, 64 * 1024,  512,
 376          N25Q_FLAG | FLASH_FLAG_32BIT_ADDR, 108, stfsm_n25q_config },
 377
 378        /*
 379         * Spansion S25FLxxxP
 380         *     - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
 381         */
 382#define S25FLXXXP_FLAG (FLASH_FLAG_READ_WRITE  |        \
 383                        FLASH_FLAG_READ_1_1_2   |       \
 384                        FLASH_FLAG_READ_1_2_2   |       \
 385                        FLASH_FLAG_READ_1_1_4   |       \
 386                        FLASH_FLAG_READ_1_4_4   |       \
 387                        FLASH_FLAG_WRITE_1_1_4  |       \
 388                        FLASH_FLAG_READ_FAST)
 389        { "s25fl032p",  0x010215, 0x4d00,  64 * 1024,  64, S25FLXXXP_FLAG, 80,
 390          stfsm_s25fl_config},
 391        { "s25fl129p0", 0x012018, 0x4d00, 256 * 1024,  64, S25FLXXXP_FLAG, 80,
 392          stfsm_s25fl_config },
 393        { "s25fl129p1", 0x012018, 0x4d01,  64 * 1024, 256, S25FLXXXP_FLAG, 80,
 394          stfsm_s25fl_config },
 395
 396        /*
 397         * Spansion S25FLxxxS
 398         *     - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
 399         *     - RESET# signal supported by die but not bristled out on all
 400         *       package types.  The package type is a function of board design,
 401         *       so this information is captured in the board's flags.
 402         *     - Supports 'DYB' sector protection. Depending on variant, sectors
 403         *       may default to locked state on power-on.
 404         */
 405#define S25FLXXXS_FLAG (S25FLXXXP_FLAG         |        \
 406                        FLASH_FLAG_RESET        |       \
 407                        FLASH_FLAG_DYB_LOCKING)
 408        { "s25fl128s0", 0x012018, 0x0300,  256 * 1024, 64, S25FLXXXS_FLAG, 80,
 409          stfsm_s25fl_config },
 410        { "s25fl128s1", 0x012018, 0x0301,  64 * 1024, 256, S25FLXXXS_FLAG, 80,
 411          stfsm_s25fl_config },
 412        { "s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128,
 413          S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config },
 414        { "s25fl256s1", 0x010219, 0x4d01,  64 * 1024, 512,
 415          S25FLXXXS_FLAG | FLASH_FLAG_32BIT_ADDR, 80, stfsm_s25fl_config },
 416
 417        /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
 418#define W25X_FLAG (FLASH_FLAG_READ_WRITE       |        \
 419                   FLASH_FLAG_READ_FAST         |       \
 420                   FLASH_FLAG_READ_1_1_2        |       \
 421                   FLASH_FLAG_WRITE_1_1_2)
 422        { "w25x40",  0xef3013, 0,  64 * 1024,   8, W25X_FLAG, 75, NULL },
 423        { "w25x80",  0xef3014, 0,  64 * 1024,  16, W25X_FLAG, 75, NULL },
 424        { "w25x16",  0xef3015, 0,  64 * 1024,  32, W25X_FLAG, 75, NULL },
 425        { "w25x32",  0xef3016, 0,  64 * 1024,  64, W25X_FLAG, 75, NULL },
 426        { "w25x64",  0xef3017, 0,  64 * 1024, 128, W25X_FLAG, 75, NULL },
 427
 428        /* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
 429#define W25Q_FLAG (FLASH_FLAG_READ_WRITE       |        \
 430                   FLASH_FLAG_READ_FAST         |       \
 431                   FLASH_FLAG_READ_1_1_2        |       \
 432                   FLASH_FLAG_READ_1_2_2        |       \
 433                   FLASH_FLAG_READ_1_1_4        |       \
 434                   FLASH_FLAG_READ_1_4_4        |       \
 435                   FLASH_FLAG_WRITE_1_1_4)
 436        { "w25q80",  0xef4014, 0,  64 * 1024,  16, W25Q_FLAG, 80,
 437          stfsm_w25q_config },
 438        { "w25q16",  0xef4015, 0,  64 * 1024,  32, W25Q_FLAG, 80,
 439          stfsm_w25q_config },
 440        { "w25q32",  0xef4016, 0,  64 * 1024,  64, W25Q_FLAG, 80,
 441          stfsm_w25q_config },
 442        { "w25q64",  0xef4017, 0,  64 * 1024, 128, W25Q_FLAG, 80,
 443          stfsm_w25q_config },
 444
 445        /* Sentinel */
 446        { NULL, 0x000000, 0, 0, 0, 0, 0, NULL },
 447};
 448
 449/*
 450 * FSM message sequence configurations:
 451 *
 452 * All configs are presented in order of preference
 453 */
 454
 455/* Default READ configurations, in order of preference */
 456static struct seq_rw_config default_read_configs[] = {
 457        {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4,   0, 4, 4, 0x00, 2, 4},
 458        {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4,   0, 1, 4, 0x00, 4, 0},
 459        {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2,   0, 2, 2, 0x00, 4, 0},
 460        {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2,   0, 1, 2, 0x00, 0, 8},
 461        {FLASH_FLAG_READ_FAST,  SPINOR_OP_READ_FAST,    0, 1, 1, 0x00, 0, 8},
 462        {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ,         0, 1, 1, 0x00, 0, 0},
 463        {0x00,                  0,                      0, 0, 0, 0x00, 0, 0},
 464};
 465
 466/* Default WRITE configurations */
 467static struct seq_rw_config default_write_configs[] = {
 468        {FLASH_FLAG_WRITE_1_4_4, SPINOR_OP_WRITE_1_4_4, 1, 4, 4, 0x00, 0, 0},
 469        {FLASH_FLAG_WRITE_1_1_4, SPINOR_OP_WRITE_1_1_4, 1, 1, 4, 0x00, 0, 0},
 470        {FLASH_FLAG_WRITE_1_2_2, SPINOR_OP_WRITE_1_2_2, 1, 2, 2, 0x00, 0, 0},
 471        {FLASH_FLAG_WRITE_1_1_2, SPINOR_OP_WRITE_1_1_2, 1, 1, 2, 0x00, 0, 0},
 472        {FLASH_FLAG_READ_WRITE,  SPINOR_OP_WRITE,       1, 1, 1, 0x00, 0, 0},
 473        {0x00,                   0,                     0, 0, 0, 0x00, 0, 0},
 474};
 475
 476/*
 477 * [N25Qxxx] Configuration
 478 */
 479#define N25Q_VCR_DUMMY_CYCLES(x)        (((x) & 0xf) << 4)
 480#define N25Q_VCR_XIP_DISABLED           ((uint8_t)0x1 << 3)
 481#define N25Q_VCR_WRAP_CONT              0x3
 482
 483/* N25Q 3-byte Address READ configurations
 484 *      - 'FAST' variants configured for 8 dummy cycles.
 485 *
 486 * Note, the number of dummy cycles used for 'FAST' READ operations is
 487 * configurable and would normally be tuned according to the READ command and
 488 * operating frequency.  However, this applies universally to all 'FAST' READ
 489 * commands, including those used by the SPIBoot controller, and remains in
 490 * force until the device is power-cycled.  Since the SPIBoot controller is
 491 * hard-wired to use 8 dummy cycles, we must configure the device to also use 8
 492 * cycles.
 493 */
 494static struct seq_rw_config n25q_read3_configs[] = {
 495        {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4,   0, 4, 4, 0x00, 0, 8},
 496        {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4,   0, 1, 4, 0x00, 0, 8},
 497        {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2,   0, 2, 2, 0x00, 0, 8},
 498        {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2,   0, 1, 2, 0x00, 0, 8},
 499        {FLASH_FLAG_READ_FAST,  SPINOR_OP_READ_FAST,    0, 1, 1, 0x00, 0, 8},
 500        {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ,         0, 1, 1, 0x00, 0, 0},
 501        {0x00,                  0,                      0, 0, 0, 0x00, 0, 0},
 502};
 503
 504/* N25Q 4-byte Address READ configurations
 505 *      - use special 4-byte address READ commands (reduces overheads, and
 506 *        reduces risk of hitting watchdog reset issues).
 507 *      - 'FAST' variants configured for 8 dummy cycles (see note above.)
 508 */
 509static struct seq_rw_config n25q_read4_configs[] = {
 510        {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4,  0, 4, 4, 0x00, 0, 8},
 511        {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4,  0, 1, 4, 0x00, 0, 8},
 512        {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2,  0, 2, 2, 0x00, 0, 8},
 513        {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2,  0, 1, 2, 0x00, 0, 8},
 514        {FLASH_FLAG_READ_FAST,  SPINOR_OP_READ4_FAST,   0, 1, 1, 0x00, 0, 8},
 515        {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4,        0, 1, 1, 0x00, 0, 0},
 516        {0x00,                  0,                      0, 0, 0, 0x00, 0, 0},
 517};
 518
 519/*
 520 * [MX25xxx] Configuration
 521 */
 522#define MX25_STATUS_QE                  (0x1 << 6)
 523
 524static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)
 525{
 526        seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 527                           SEQ_OPC_CYCLES(8) |
 528                           SEQ_OPC_OPCODE(SPINOR_OP_EN4B) |
 529                           SEQ_OPC_CSDEASSERT);
 530
 531        seq->seq[0] = STFSM_INST_CMD1;
 532        seq->seq[1] = STFSM_INST_WAIT;
 533        seq->seq[2] = STFSM_INST_STOP;
 534
 535        seq->seq_cfg = (SEQ_CFG_PADS_1 |
 536                        SEQ_CFG_ERASE |
 537                        SEQ_CFG_READNOTWRITE |
 538                        SEQ_CFG_CSDEASSERT |
 539                        SEQ_CFG_STARTSEQ);
 540
 541        return 0;
 542}
 543
 544/*
 545 * [S25FLxxx] Configuration
 546 */
 547#define STFSM_S25FL_CONFIG_QE           (0x1 << 1)
 548
 549/*
 550 * S25FLxxxS devices provide three ways of supporting 32-bit addressing: Bank
 551 * Register, Extended Address Modes, and a 32-bit address command set.  The
 552 * 32-bit address command set is used here, since it avoids any problems with
 553 * entering a state that is incompatible with the SPIBoot Controller.
 554 */
 555static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
 556        {FLASH_FLAG_READ_1_4_4,  SPINOR_OP_READ4_1_4_4,  0, 4, 4, 0x00, 2, 4},
 557        {FLASH_FLAG_READ_1_1_4,  SPINOR_OP_READ4_1_1_4,  0, 1, 4, 0x00, 0, 8},
 558        {FLASH_FLAG_READ_1_2_2,  SPINOR_OP_READ4_1_2_2,  0, 2, 2, 0x00, 4, 0},
 559        {FLASH_FLAG_READ_1_1_2,  SPINOR_OP_READ4_1_1_2,  0, 1, 2, 0x00, 0, 8},
 560        {FLASH_FLAG_READ_FAST,   SPINOR_OP_READ4_FAST,   0, 1, 1, 0x00, 0, 8},
 561        {FLASH_FLAG_READ_WRITE,  SPINOR_OP_READ4,        0, 1, 1, 0x00, 0, 0},
 562        {0x00,                   0,                      0, 0, 0, 0x00, 0, 0},
 563};
 564
 565static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
 566        {FLASH_FLAG_WRITE_1_1_4, S25FL_CMD_WRITE4_1_1_4, 1, 1, 4, 0x00, 0, 0},
 567        {FLASH_FLAG_READ_WRITE,  S25FL_CMD_WRITE4,       1, 1, 1, 0x00, 0, 0},
 568        {0x00,                   0,                      0, 0, 0, 0x00, 0, 0},
 569};
 570
 571/*
 572 * [W25Qxxx] Configuration
 573 */
 574#define W25Q_STATUS_QE                  (0x1 << 1)
 575
 576static struct stfsm_seq stfsm_seq_read_jedec = {
 577        .data_size = TRANSFER_SIZE(8),
 578        .seq_opc[0] = (SEQ_OPC_PADS_1 |
 579                       SEQ_OPC_CYCLES(8) |
 580                       SEQ_OPC_OPCODE(SPINOR_OP_RDID)),
 581        .seq = {
 582                STFSM_INST_CMD1,
 583                STFSM_INST_DATA_READ,
 584                STFSM_INST_STOP,
 585        },
 586        .seq_cfg = (SEQ_CFG_PADS_1 |
 587                    SEQ_CFG_READNOTWRITE |
 588                    SEQ_CFG_CSDEASSERT |
 589                    SEQ_CFG_STARTSEQ),
 590};
 591
 592static struct stfsm_seq stfsm_seq_read_status_fifo = {
 593        .data_size = TRANSFER_SIZE(4),
 594        .seq_opc[0] = (SEQ_OPC_PADS_1 |
 595                       SEQ_OPC_CYCLES(8) |
 596                       SEQ_OPC_OPCODE(SPINOR_OP_RDSR)),
 597        .seq = {
 598                STFSM_INST_CMD1,
 599                STFSM_INST_DATA_READ,
 600                STFSM_INST_STOP,
 601        },
 602        .seq_cfg = (SEQ_CFG_PADS_1 |
 603                    SEQ_CFG_READNOTWRITE |
 604                    SEQ_CFG_CSDEASSERT |
 605                    SEQ_CFG_STARTSEQ),
 606};
 607
 608static struct stfsm_seq stfsm_seq_erase_sector = {
 609        /* 'addr_cfg' configured during initialisation */
 610        .seq_opc = {
 611                (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 612                 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 613
 614                (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 615                 SEQ_OPC_OPCODE(SPINOR_OP_SE)),
 616        },
 617        .seq = {
 618                STFSM_INST_CMD1,
 619                STFSM_INST_CMD2,
 620                STFSM_INST_ADD1,
 621                STFSM_INST_ADD2,
 622                STFSM_INST_STOP,
 623        },
 624        .seq_cfg = (SEQ_CFG_PADS_1 |
 625                    SEQ_CFG_READNOTWRITE |
 626                    SEQ_CFG_CSDEASSERT |
 627                    SEQ_CFG_STARTSEQ),
 628};
 629
 630static struct stfsm_seq stfsm_seq_erase_chip = {
 631        .seq_opc = {
 632                (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 633                 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 634
 635                (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 636                 SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT),
 637        },
 638        .seq = {
 639                STFSM_INST_CMD1,
 640                STFSM_INST_CMD2,
 641                STFSM_INST_WAIT,
 642                STFSM_INST_STOP,
 643        },
 644        .seq_cfg = (SEQ_CFG_PADS_1 |
 645                    SEQ_CFG_ERASE |
 646                    SEQ_CFG_READNOTWRITE |
 647                    SEQ_CFG_CSDEASSERT |
 648                    SEQ_CFG_STARTSEQ),
 649};
 650
 651static struct stfsm_seq stfsm_seq_write_status = {
 652        .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 653                       SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 654        .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 655                       SEQ_OPC_OPCODE(SPINOR_OP_WRSR)),
 656        .seq = {
 657                STFSM_INST_CMD1,
 658                STFSM_INST_CMD2,
 659                STFSM_INST_STA_WR1,
 660                STFSM_INST_STOP,
 661        },
 662        .seq_cfg = (SEQ_CFG_PADS_1 |
 663                    SEQ_CFG_READNOTWRITE |
 664                    SEQ_CFG_CSDEASSERT |
 665                    SEQ_CFG_STARTSEQ),
 666};
 667
 668/* Dummy sequence to read one byte of data from flash into the FIFO */
 669static const struct stfsm_seq stfsm_seq_load_fifo_byte = {
 670        .data_size = TRANSFER_SIZE(1),
 671        .seq_opc[0] = (SEQ_OPC_PADS_1 |
 672                       SEQ_OPC_CYCLES(8) |
 673                       SEQ_OPC_OPCODE(SPINOR_OP_RDID)),
 674        .seq = {
 675                STFSM_INST_CMD1,
 676                STFSM_INST_DATA_READ,
 677                STFSM_INST_STOP,
 678        },
 679        .seq_cfg = (SEQ_CFG_PADS_1 |
 680                    SEQ_CFG_READNOTWRITE |
 681                    SEQ_CFG_CSDEASSERT |
 682                    SEQ_CFG_STARTSEQ),
 683};
 684
 685static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
 686{
 687        seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 688                           SEQ_OPC_OPCODE(SPINOR_OP_EN4B));
 689        seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 690                           SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
 691                           SEQ_OPC_CSDEASSERT);
 692
 693        seq->seq[0] = STFSM_INST_CMD2;
 694        seq->seq[1] = STFSM_INST_CMD1;
 695        seq->seq[2] = STFSM_INST_WAIT;
 696        seq->seq[3] = STFSM_INST_STOP;
 697
 698        seq->seq_cfg = (SEQ_CFG_PADS_1 |
 699                        SEQ_CFG_ERASE |
 700                        SEQ_CFG_READNOTWRITE |
 701                        SEQ_CFG_CSDEASSERT |
 702                        SEQ_CFG_STARTSEQ);
 703
 704        return 0;
 705}
 706
 707static inline int stfsm_is_idle(struct stfsm *fsm)
 708{
 709        return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;
 710}
 711
 712static inline uint32_t stfsm_fifo_available(struct stfsm *fsm)
 713{
 714        return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;
 715}
 716
 717static inline void stfsm_load_seq(struct stfsm *fsm,
 718                                  const struct stfsm_seq *seq)
 719{
 720        void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;
 721        const uint32_t *src = (const uint32_t *)seq;
 722        int words = sizeof(*seq) / sizeof(*src);
 723
 724        BUG_ON(!stfsm_is_idle(fsm));
 725
 726        while (words--) {
 727                writel(*src, dst);
 728                src++;
 729                dst += 4;
 730        }
 731}
 732
 733static void stfsm_wait_seq(struct stfsm *fsm)
 734{
 735        unsigned long deadline;
 736        int timeout = 0;
 737
 738        deadline = jiffies + msecs_to_jiffies(STFSM_MAX_WAIT_SEQ_MS);
 739
 740        while (!timeout) {
 741                if (time_after_eq(jiffies, deadline))
 742                        timeout = 1;
 743
 744                if (stfsm_is_idle(fsm))
 745                        return;
 746
 747                cond_resched();
 748        }
 749
 750        dev_err(fsm->dev, "timeout on sequence completion\n");
 751}
 752
 753static void stfsm_read_fifo(struct stfsm *fsm, uint32_t *buf, uint32_t size)
 754{
 755        uint32_t remaining = size >> 2;
 756        uint32_t avail;
 757        uint32_t words;
 758
 759        dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);
 760
 761        BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3));
 762
 763        while (remaining) {
 764                for (;;) {
 765                        avail = stfsm_fifo_available(fsm);
 766                        if (avail)
 767                                break;
 768                        udelay(1);
 769                }
 770                words = min(avail, remaining);
 771                remaining -= words;
 772
 773                readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
 774                buf += words;
 775        }
 776}
 777
 778/*
 779 * Clear the data FIFO
 780 *
 781 * Typically, this is only required during driver initialisation, where no
 782 * assumptions can be made regarding the state of the FIFO.
 783 *
 784 * The process of clearing the FIFO is complicated by fact that while it is
 785 * possible for the FIFO to contain an arbitrary number of bytes [1], the
 786 * SPI_FAST_SEQ_STA register only reports the number of complete 32-bit words
 787 * present.  Furthermore, data can only be drained from the FIFO by reading
 788 * complete 32-bit words.
 789 *
 790 * With this in mind, a two stage process is used to the clear the FIFO:
 791 *
 792 *     1. Read any complete 32-bit words from the FIFO, as reported by the
 793 *        SPI_FAST_SEQ_STA register.
 794 *
 795 *     2. Mop up any remaining bytes.  At this point, it is not known if there
 796 *        are 0, 1, 2, or 3 bytes in the FIFO.  To handle all cases, a dummy FSM
 797 *        sequence is used to load one byte at a time, until a complete 32-bit
 798 *        word is formed; at most, 4 bytes will need to be loaded.
 799 *
 800 * [1] It is theoretically possible for the FIFO to contain an arbitrary number
 801 *     of bits.  However, since there are no known use-cases that leave
 802 *     incomplete bytes in the FIFO, only words and bytes are considered here.
 803 */
 804static void stfsm_clear_fifo(struct stfsm *fsm)
 805{
 806        const struct stfsm_seq *seq = &stfsm_seq_load_fifo_byte;
 807        uint32_t words, i;
 808
 809        /* 1. Clear any 32-bit words */
 810        words = stfsm_fifo_available(fsm);
 811        if (words) {
 812                for (i = 0; i < words; i++)
 813                        readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
 814                dev_dbg(fsm->dev, "cleared %d words from FIFO\n", words);
 815        }
 816
 817        /*
 818         * 2. Clear any remaining bytes
 819         *    - Load the FIFO, one byte at a time, until a complete 32-bit word
 820         *      is available.
 821         */
 822        for (i = 0, words = 0; i < 4 && !words; i++) {
 823                stfsm_load_seq(fsm, seq);
 824                stfsm_wait_seq(fsm);
 825                words = stfsm_fifo_available(fsm);
 826        }
 827
 828        /*    - A single word must be available now */
 829        if (words != 1) {
 830                dev_err(fsm->dev, "failed to clear bytes from the data FIFO\n");
 831                return;
 832        }
 833
 834        /*    - Read the 32-bit word */
 835        readl(fsm->base + SPI_FAST_SEQ_DATA_REG);
 836
 837        dev_dbg(fsm->dev, "cleared %d byte(s) from the data FIFO\n", 4 - i);
 838}
 839
 840static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf,
 841                            uint32_t size)
 842{
 843        uint32_t words = size >> 2;
 844
 845        dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size);
 846
 847        BUG_ON((((uintptr_t)buf) & 0x3) || (size & 0x3));
 848
 849        writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);
 850
 851        return size;
 852}
 853
 854static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
 855{
 856        struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;
 857        uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
 858
 859        seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 860                           SEQ_OPC_CYCLES(8) |
 861                           SEQ_OPC_OPCODE(cmd) |
 862                           SEQ_OPC_CSDEASSERT);
 863
 864        stfsm_load_seq(fsm, seq);
 865
 866        stfsm_wait_seq(fsm);
 867
 868        return 0;
 869}
 870
 871static uint8_t stfsm_wait_busy(struct stfsm *fsm)
 872{
 873        struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;
 874        unsigned long deadline;
 875        uint32_t status;
 876        int timeout = 0;
 877
 878        /* Use RDRS1 */
 879        seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 880                           SEQ_OPC_CYCLES(8) |
 881                           SEQ_OPC_OPCODE(SPINOR_OP_RDSR));
 882
 883        /* Load read_status sequence */
 884        stfsm_load_seq(fsm, seq);
 885
 886        /*
 887         * Repeat until busy bit is deasserted, or timeout, or error (S25FLxxxS)
 888         */
 889        deadline = jiffies + FLASH_MAX_BUSY_WAIT;
 890        while (!timeout) {
 891                if (time_after_eq(jiffies, deadline))
 892                        timeout = 1;
 893
 894                stfsm_wait_seq(fsm);
 895
 896                stfsm_read_fifo(fsm, &status, 4);
 897
 898                if ((status & FLASH_STATUS_BUSY) == 0)
 899                        return 0;
 900
 901                if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) &&
 902                    ((status & S25FL_STATUS_P_ERR) ||
 903                     (status & S25FL_STATUS_E_ERR)))
 904                        return (uint8_t)(status & 0xff);
 905
 906                if (!timeout)
 907                        /* Restart */
 908                        writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG);
 909
 910                cond_resched();
 911        }
 912
 913        dev_err(fsm->dev, "timeout on wait_busy\n");
 914
 915        return FLASH_STATUS_TIMEOUT;
 916}
 917
 918static int stfsm_read_status(struct stfsm *fsm, uint8_t cmd,
 919                             uint8_t *data, int bytes)
 920{
 921        struct stfsm_seq *seq = &stfsm_seq_read_status_fifo;
 922        uint32_t tmp;
 923        uint8_t *t = (uint8_t *)&tmp;
 924        int i;
 925
 926        dev_dbg(fsm->dev, "read 'status' register [0x%02x], %d byte(s)\n",
 927                cmd, bytes);
 928
 929        BUG_ON(bytes != 1 && bytes != 2);
 930
 931        seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 932                           SEQ_OPC_OPCODE(cmd)),
 933
 934        stfsm_load_seq(fsm, seq);
 935
 936        stfsm_read_fifo(fsm, &tmp, 4);
 937
 938        for (i = 0; i < bytes; i++)
 939                data[i] = t[i];
 940
 941        stfsm_wait_seq(fsm);
 942
 943        return 0;
 944}
 945
 946static int stfsm_write_status(struct stfsm *fsm, uint8_t cmd,
 947                            uint16_t data, int bytes, int wait_busy)
 948{
 949        struct stfsm_seq *seq = &stfsm_seq_write_status;
 950
 951        dev_dbg(fsm->dev,
 952                "write 'status' register [0x%02x], %d byte(s), 0x%04x\n"
 953                " %s wait-busy\n", cmd, bytes, data, wait_busy ? "with" : "no");
 954
 955        BUG_ON(bytes != 1 && bytes != 2);
 956
 957        seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 958                           SEQ_OPC_OPCODE(cmd));
 959
 960        seq->status = (uint32_t)data | STA_PADS_1 | STA_CSDEASSERT;
 961        seq->seq[2] = (bytes == 1) ? STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2;
 962
 963        stfsm_load_seq(fsm, seq);
 964
 965        stfsm_wait_seq(fsm);
 966
 967        if (wait_busy)
 968                stfsm_wait_busy(fsm);
 969
 970        return 0;
 971}
 972
 973/*
 974 * SoC reset on 'boot-from-spi' systems
 975 *
 976 * Certain modes of operation cause the Flash device to enter a particular state
 977 * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit
 978 * Addr' commands).  On boot-from-spi systems, it is important to consider what
 979 * happens if a warm reset occurs during this period.  The SPIBoot controller
 980 * assumes that Flash device is in its default reset state, 24-bit address mode,
 981 * and ready to accept commands.  This can be achieved using some form of
 982 * on-board logic/controller to force a device POR in response to a SoC-level
 983 * reset or by making use of the device reset signal if available (limited
 984 * number of devices only).
 985 *
 986 * Failure to take such precautions can cause problems following a warm reset.
 987 * For some operations (e.g. ERASE), there is little that can be done.  For
 988 * other modes of operation (e.g. 32-bit addressing), options are often
 989 * available that can help minimise the window in which a reset could cause a
 990 * problem.
 991 *
 992 */
 993static bool stfsm_can_handle_soc_reset(struct stfsm *fsm)
 994{
 995        /* Reset signal is available on the board and supported by the device */
 996        if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET)
 997                return true;
 998
 999        /* Board-level logic forces a power-on-reset */
1000        if (fsm->reset_por)
1001                return true;
1002
1003        /* Reset is not properly handled and may result in failure to reboot */
1004        return false;
1005}
1006
1007/* Configure 'addr_cfg' according to addressing mode */
1008static void stfsm_prepare_erasesec_seq(struct stfsm *fsm,
1009                                       struct stfsm_seq *seq)
1010{
1011        int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8;
1012
1013        seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) |
1014                         ADR_CFG_PADS_1_ADD1 |
1015                         ADR_CFG_CYCLES_ADD2(16) |
1016                         ADR_CFG_PADS_1_ADD2 |
1017                         ADR_CFG_CSDEASSERT_ADD2);
1018}
1019
1020/* Search for preferred configuration based on available flags */
1021static struct seq_rw_config *
1022stfsm_search_seq_rw_configs(struct stfsm *fsm,
1023                            struct seq_rw_config cfgs[])
1024{
1025        struct seq_rw_config *config;
1026        int flags = fsm->info->flags;
1027
1028        for (config = cfgs; config->cmd != 0; config++)
1029                if ((config->flags & flags) == config->flags)
1030                        return config;
1031
1032        return NULL;
1033}
1034
1035/* Prepare a READ/WRITE sequence according to configuration parameters */
1036static void stfsm_prepare_rw_seq(struct stfsm *fsm,
1037                                 struct stfsm_seq *seq,
1038                                 struct seq_rw_config *cfg)
1039{
1040        int addr1_cycles, addr2_cycles;
1041        int i = 0;
1042
1043        memset(seq, 0, sizeof(*seq));
1044
1045        /* Add READ/WRITE OPC  */
1046        seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
1047                             SEQ_OPC_CYCLES(8) |
1048                             SEQ_OPC_OPCODE(cfg->cmd));
1049
1050        /* Add WREN OPC for a WRITE sequence */
1051        if (cfg->write)
1052                seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |
1053                                     SEQ_OPC_CYCLES(8) |
1054                                     SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
1055                                     SEQ_OPC_CSDEASSERT);
1056
1057        /* Address configuration (24 or 32-bit addresses) */
1058        addr1_cycles  = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;
1059        addr1_cycles /= cfg->addr_pads;
1060        addr2_cycles  = 16 / cfg->addr_pads;
1061        seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 |   /* ADD1 cycles */
1062                         (cfg->addr_pads - 1) << 6 |    /* ADD1 pads */
1063                         (addr2_cycles & 0x3f) << 16 |  /* ADD2 cycles */
1064                         ((cfg->addr_pads - 1) << 22)); /* ADD2 pads */
1065
1066        /* Data/Sequence configuration */
1067        seq->seq_cfg = ((cfg->data_pads - 1) << 16 |
1068                        SEQ_CFG_STARTSEQ |
1069                        SEQ_CFG_CSDEASSERT);
1070        if (!cfg->write)
1071                seq->seq_cfg |= SEQ_CFG_READNOTWRITE;
1072
1073        /* Mode configuration (no. of pads taken from addr cfg) */
1074        seq->mode = ((cfg->mode_data & 0xff) << 0 |     /* data */
1075                     (cfg->mode_cycles & 0x3f) << 16 |  /* cycles */
1076                     (cfg->addr_pads - 1) << 22);       /* pads */
1077
1078        /* Dummy configuration (no. of pads taken from addr cfg) */
1079        seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 |        /* cycles */
1080                      (cfg->addr_pads - 1) << 22);              /* pads */
1081
1082
1083        /* Instruction sequence */
1084        i = 0;
1085        if (cfg->write)
1086                seq->seq[i++] = STFSM_INST_CMD2;
1087
1088        seq->seq[i++] = STFSM_INST_CMD1;
1089
1090        seq->seq[i++] = STFSM_INST_ADD1;
1091        seq->seq[i++] = STFSM_INST_ADD2;
1092
1093        if (cfg->mode_cycles)
1094                seq->seq[i++] = STFSM_INST_MODE;
1095
1096        if (cfg->dummy_cycles)
1097                seq->seq[i++] = STFSM_INST_DUMMY;
1098
1099        seq->seq[i++] =
1100                cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;
1101        seq->seq[i++] = STFSM_INST_STOP;
1102}
1103
1104static int stfsm_search_prepare_rw_seq(struct stfsm *fsm,
1105                                       struct stfsm_seq *seq,
1106                                       struct seq_rw_config *cfgs)
1107{
1108        struct seq_rw_config *config;
1109
1110        config = stfsm_search_seq_rw_configs(fsm, cfgs);
1111        if (!config) {
1112                dev_err(fsm->dev, "failed to find suitable config\n");
1113                return -EINVAL;
1114        }
1115
1116        stfsm_prepare_rw_seq(fsm, seq, config);
1117
1118        return 0;
1119}
1120
1121/* Prepare a READ/WRITE/ERASE 'default' sequences */
1122static int stfsm_prepare_rwe_seqs_default(struct stfsm *fsm)
1123{
1124        uint32_t flags = fsm->info->flags;
1125        int ret;
1126
1127        /* Configure 'READ' sequence */
1128        ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1129                                          default_read_configs);
1130        if (ret) {
1131                dev_err(fsm->dev,
1132                        "failed to prep READ sequence with flags [0x%08x]\n",
1133                        flags);
1134                return ret;
1135        }
1136
1137        /* Configure 'WRITE' sequence */
1138        ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
1139                                          default_write_configs);
1140        if (ret) {
1141                dev_err(fsm->dev,
1142                        "failed to prep WRITE sequence with flags [0x%08x]\n",
1143                        flags);
1144                return ret;
1145        }
1146
1147        /* Configure 'ERASE_SECTOR' sequence */
1148        stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector);
1149
1150        return 0;
1151}
1152
1153static int stfsm_mx25_config(struct stfsm *fsm)
1154{
1155        uint32_t flags = fsm->info->flags;
1156        uint32_t data_pads;
1157        uint8_t sta;
1158        int ret;
1159        bool soc_reset;
1160
1161        /*
1162         * Use default READ/WRITE sequences
1163         */
1164        ret = stfsm_prepare_rwe_seqs_default(fsm);
1165        if (ret)
1166                return ret;
1167
1168        /*
1169         * Configure 32-bit Address Support
1170         */
1171        if (flags & FLASH_FLAG_32BIT_ADDR) {
1172                /* Configure 'enter_32bitaddr' FSM sequence */
1173                stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);
1174
1175                soc_reset = stfsm_can_handle_soc_reset(fsm);
1176                if (soc_reset || !fsm->booted_from_spi)
1177                        /* If we can handle SoC resets, we enable 32-bit address
1178                         * mode pervasively */
1179                        stfsm_enter_32bit_addr(fsm, 1);
1180
1181                else
1182                        /* Else, enable/disable 32-bit addressing before/after
1183                         * each operation */
1184                        fsm->configuration = (CFG_READ_TOGGLE_32BIT_ADDR |
1185                                              CFG_WRITE_TOGGLE_32BIT_ADDR |
1186                                              CFG_ERASESEC_TOGGLE_32BIT_ADDR);
1187        }
1188
1189        /* Check status of 'QE' bit, update if required. */
1190        stfsm_read_status(fsm, SPINOR_OP_RDSR, &sta, 1);
1191        data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1192        if (data_pads == 4) {
1193                if (!(sta & MX25_STATUS_QE)) {
1194                        /* Set 'QE' */
1195                        sta |= MX25_STATUS_QE;
1196
1197                        stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1);
1198                }
1199        } else {
1200                if (sta & MX25_STATUS_QE) {
1201                        /* Clear 'QE' */
1202                        sta &= ~MX25_STATUS_QE;
1203
1204                        stfsm_write_status(fsm, SPINOR_OP_WRSR, sta, 1, 1);
1205                }
1206        }
1207
1208        return 0;
1209}
1210
1211static int stfsm_n25q_config(struct stfsm *fsm)
1212{
1213        uint32_t flags = fsm->info->flags;
1214        uint8_t vcr;
1215        int ret = 0;
1216        bool soc_reset;
1217
1218        /* Configure 'READ' sequence */
1219        if (flags & FLASH_FLAG_32BIT_ADDR)
1220                ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1221                                                  n25q_read4_configs);
1222        else
1223                ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1224                                                  n25q_read3_configs);
1225        if (ret) {
1226                dev_err(fsm->dev,
1227                        "failed to prepare READ sequence with flags [0x%08x]\n",
1228                        flags);
1229                return ret;
1230        }
1231
1232        /* Configure 'WRITE' sequence (default configs) */
1233        ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
1234                                          default_write_configs);
1235        if (ret) {
1236                dev_err(fsm->dev,
1237                        "preparing WRITE sequence using flags [0x%08x] failed\n",
1238                        flags);
1239                return ret;
1240        }
1241
1242        /* * Configure 'ERASE_SECTOR' sequence */
1243        stfsm_prepare_erasesec_seq(fsm, &stfsm_seq_erase_sector);
1244
1245        /* Configure 32-bit address support */
1246        if (flags & FLASH_FLAG_32BIT_ADDR) {
1247                stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);
1248
1249                soc_reset = stfsm_can_handle_soc_reset(fsm);
1250                if (soc_reset || !fsm->booted_from_spi) {
1251                        /*
1252                         * If we can handle SoC resets, we enable 32-bit
1253                         * address mode pervasively
1254                         */
1255                        stfsm_enter_32bit_addr(fsm, 1);
1256                } else {
1257                        /*
1258                         * If not, enable/disable for WRITE and ERASE
1259                         * operations (READ uses special commands)
1260                         */
1261                        fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR |
1262                                              CFG_ERASESEC_TOGGLE_32BIT_ADDR);
1263                }
1264        }
1265
1266        /*
1267         * Configure device to use 8 dummy cycles
1268         */
1269        vcr = (N25Q_VCR_DUMMY_CYCLES(8) | N25Q_VCR_XIP_DISABLED |
1270               N25Q_VCR_WRAP_CONT);
1271        stfsm_write_status(fsm, N25Q_CMD_WRVCR, vcr, 1, 0);
1272
1273        return 0;
1274}
1275
1276static void stfsm_s25fl_prepare_erasesec_seq_32(struct stfsm_seq *seq)
1277{
1278        seq->seq_opc[1] = (SEQ_OPC_PADS_1 |
1279                           SEQ_OPC_CYCLES(8) |
1280                           SEQ_OPC_OPCODE(S25FL_CMD_SE4));
1281
1282        seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |
1283                         ADR_CFG_PADS_1_ADD1 |
1284                         ADR_CFG_CYCLES_ADD2(16) |
1285                         ADR_CFG_PADS_1_ADD2 |
1286                         ADR_CFG_CSDEASSERT_ADD2);
1287}
1288
1289static void stfsm_s25fl_read_dyb(struct stfsm *fsm, uint32_t offs, uint8_t *dby)
1290{
1291        uint32_t tmp;
1292        struct stfsm_seq seq = {
1293                .data_size = TRANSFER_SIZE(4),
1294                .seq_opc[0] = (SEQ_OPC_PADS_1 |
1295                               SEQ_OPC_CYCLES(8) |
1296                               SEQ_OPC_OPCODE(S25FL_CMD_DYBRD)),
1297                .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |
1298                             ADR_CFG_PADS_1_ADD1 |
1299                             ADR_CFG_CYCLES_ADD2(16) |
1300                             ADR_CFG_PADS_1_ADD2),
1301                .addr1 = (offs >> 16) & 0xffff,
1302                .addr2 = offs & 0xffff,
1303                .seq = {
1304                        STFSM_INST_CMD1,
1305                        STFSM_INST_ADD1,
1306                        STFSM_INST_ADD2,
1307                        STFSM_INST_DATA_READ,
1308                        STFSM_INST_STOP,
1309                },
1310                .seq_cfg = (SEQ_CFG_PADS_1 |
1311                            SEQ_CFG_READNOTWRITE |
1312                            SEQ_CFG_CSDEASSERT |
1313                            SEQ_CFG_STARTSEQ),
1314        };
1315
1316        stfsm_load_seq(fsm, &seq);
1317
1318        stfsm_read_fifo(fsm, &tmp, 4);
1319
1320        *dby = (uint8_t)(tmp >> 24);
1321
1322        stfsm_wait_seq(fsm);
1323}
1324
1325static void stfsm_s25fl_write_dyb(struct stfsm *fsm, uint32_t offs, uint8_t dby)
1326{
1327        struct stfsm_seq seq = {
1328                .seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
1329                               SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
1330                               SEQ_OPC_CSDEASSERT),
1331                .seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
1332                               SEQ_OPC_OPCODE(S25FL_CMD_DYBWR)),
1333                .addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |
1334                             ADR_CFG_PADS_1_ADD1 |
1335                             ADR_CFG_CYCLES_ADD2(16) |
1336                             ADR_CFG_PADS_1_ADD2),
1337                .status = (uint32_t)dby | STA_PADS_1 | STA_CSDEASSERT,
1338                .addr1 = (offs >> 16) & 0xffff,
1339                .addr2 = offs & 0xffff,
1340                .seq = {
1341                        STFSM_INST_CMD1,
1342                        STFSM_INST_CMD2,
1343                        STFSM_INST_ADD1,
1344                        STFSM_INST_ADD2,
1345                        STFSM_INST_STA_WR1,
1346                        STFSM_INST_STOP,
1347                },
1348                .seq_cfg = (SEQ_CFG_PADS_1 |
1349                            SEQ_CFG_READNOTWRITE |
1350                            SEQ_CFG_CSDEASSERT |
1351                            SEQ_CFG_STARTSEQ),
1352        };
1353
1354        stfsm_load_seq(fsm, &seq);
1355        stfsm_wait_seq(fsm);
1356
1357        stfsm_wait_busy(fsm);
1358}
1359
1360static int stfsm_s25fl_clear_status_reg(struct stfsm *fsm)
1361{
1362        struct stfsm_seq seq = {
1363                .seq_opc[0] = (SEQ_OPC_PADS_1 |
1364                               SEQ_OPC_CYCLES(8) |
1365                               SEQ_OPC_OPCODE(S25FL_CMD_CLSR) |
1366                               SEQ_OPC_CSDEASSERT),
1367                .seq_opc[1] = (SEQ_OPC_PADS_1 |
1368                               SEQ_OPC_CYCLES(8) |
1369                               SEQ_OPC_OPCODE(SPINOR_OP_WRDI) |
1370                               SEQ_OPC_CSDEASSERT),
1371                .seq = {
1372                        STFSM_INST_CMD1,
1373                        STFSM_INST_CMD2,
1374                        STFSM_INST_WAIT,
1375                        STFSM_INST_STOP,
1376                },
1377                .seq_cfg = (SEQ_CFG_PADS_1 |
1378                            SEQ_CFG_ERASE |
1379                            SEQ_CFG_READNOTWRITE |
1380                            SEQ_CFG_CSDEASSERT |
1381                            SEQ_CFG_STARTSEQ),
1382        };
1383
1384        stfsm_load_seq(fsm, &seq);
1385
1386        stfsm_wait_seq(fsm);
1387
1388        return 0;
1389}
1390
1391static int stfsm_s25fl_config(struct stfsm *fsm)
1392{
1393        struct flash_info *info = fsm->info;
1394        uint32_t flags = info->flags;
1395        uint32_t data_pads;
1396        uint32_t offs;
1397        uint16_t sta_wr;
1398        uint8_t sr1, cr1, dyb;
1399        int update_sr = 0;
1400        int ret;
1401
1402        if (flags & FLASH_FLAG_32BIT_ADDR) {
1403                /*
1404                 * Prepare Read/Write/Erase sequences according to S25FLxxx
1405                 * 32-bit address command set
1406                 */
1407                ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,
1408                                                  stfsm_s25fl_read4_configs);
1409                if (ret)
1410                        return ret;
1411
1412                ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,
1413                                                  stfsm_s25fl_write4_configs);
1414                if (ret)
1415                        return ret;
1416
1417                stfsm_s25fl_prepare_erasesec_seq_32(&stfsm_seq_erase_sector);
1418
1419        } else {
1420                /* Use default configurations for 24-bit addressing */
1421                ret = stfsm_prepare_rwe_seqs_default(fsm);
1422                if (ret)
1423                        return ret;
1424        }
1425
1426        /*
1427         * For devices that support 'DYB' sector locking, check lock status and
1428         * unlock sectors if necessary (some variants power-on with sectors
1429         * locked by default)
1430         */
1431        if (flags & FLASH_FLAG_DYB_LOCKING) {
1432                offs = 0;
1433                for (offs = 0; offs < info->sector_size * info->n_sectors;) {
1434                        stfsm_s25fl_read_dyb(fsm, offs, &dyb);
1435                        if (dyb == 0x00)
1436                                stfsm_s25fl_write_dyb(fsm, offs, 0xff);
1437
1438                        /* Handle bottom/top 4KiB parameter sectors */
1439                        if ((offs < info->sector_size * 2) ||
1440                            (offs >= (info->sector_size - info->n_sectors * 4)))
1441                                offs += 0x1000;
1442                        else
1443                                offs += 0x10000;
1444                }
1445        }
1446
1447        /* Check status of 'QE' bit, update if required. */
1448        stfsm_read_status(fsm, SPINOR_OP_RDSR2, &cr1, 1);
1449        data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1450        if (data_pads == 4) {
1451                if (!(cr1 & STFSM_S25FL_CONFIG_QE)) {
1452                        /* Set 'QE' */
1453                        cr1 |= STFSM_S25FL_CONFIG_QE;
1454
1455                        update_sr = 1;
1456                }
1457        } else {
1458                if (cr1 & STFSM_S25FL_CONFIG_QE) {
1459                        /* Clear 'QE' */
1460                        cr1 &= ~STFSM_S25FL_CONFIG_QE;
1461
1462                        update_sr = 1;
1463                }
1464        }
1465        if (update_sr) {
1466                stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);
1467                sta_wr = ((uint16_t)cr1  << 8) | sr1;
1468                stfsm_write_status(fsm, SPINOR_OP_WRSR, sta_wr, 2, 1);
1469        }
1470
1471        /*
1472         * S25FLxxx devices support Program and Error error flags.
1473         * Configure driver to check flags and clear if necessary.
1474         */
1475        fsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS;
1476
1477        return 0;
1478}
1479
1480static int stfsm_w25q_config(struct stfsm *fsm)
1481{
1482        uint32_t data_pads;
1483        uint8_t sr1, sr2;
1484        uint16_t sr_wr;
1485        int update_sr = 0;
1486        int ret;
1487
1488        ret = stfsm_prepare_rwe_seqs_default(fsm);
1489        if (ret)
1490                return ret;
1491
1492        /* Check status of 'QE' bit, update if required. */
1493        stfsm_read_status(fsm, SPINOR_OP_RDSR2, &sr2, 1);
1494        data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;
1495        if (data_pads == 4) {
1496                if (!(sr2 & W25Q_STATUS_QE)) {
1497                        /* Set 'QE' */
1498                        sr2 |= W25Q_STATUS_QE;
1499                        update_sr = 1;
1500                }
1501        } else {
1502                if (sr2 & W25Q_STATUS_QE) {
1503                        /* Clear 'QE' */
1504                        sr2 &= ~W25Q_STATUS_QE;
1505                        update_sr = 1;
1506                }
1507        }
1508        if (update_sr) {
1509                /* Write status register */
1510                stfsm_read_status(fsm, SPINOR_OP_RDSR, &sr1, 1);
1511                sr_wr = ((uint16_t)sr2 << 8) | sr1;
1512                stfsm_write_status(fsm, SPINOR_OP_WRSR, sr_wr, 2, 1);
1513        }
1514
1515        return 0;
1516}
1517
1518static int stfsm_read(struct stfsm *fsm, uint8_t *buf, uint32_t size,
1519                      uint32_t offset)
1520{
1521        struct stfsm_seq *seq = &fsm->stfsm_seq_read;
1522        uint32_t data_pads;
1523        uint32_t read_mask;
1524        uint32_t size_ub;
1525        uint32_t size_lb;
1526        uint32_t size_mop;
1527        uint32_t tmp[4];
1528        uint32_t page_buf[FLASH_PAGESIZE_32];
1529        uint8_t *p;
1530
1531        dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset);
1532
1533        /* Enter 32-bit address mode, if required */
1534        if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)
1535                stfsm_enter_32bit_addr(fsm, 1);
1536
1537        /* Must read in multiples of 32 cycles (or 32*pads/8 Bytes) */
1538        data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;
1539        read_mask = (data_pads << 2) - 1;
1540
1541        /* Handle non-aligned buf */
1542        p = ((uintptr_t)buf & 0x3) ? (uint8_t *)page_buf : buf;
1543
1544        /* Handle non-aligned size */
1545        size_ub = (size + read_mask) & ~read_mask;
1546        size_lb = size & ~read_mask;
1547        size_mop = size & read_mask;
1548
1549        seq->data_size = TRANSFER_SIZE(size_ub);
1550        seq->addr1 = (offset >> 16) & 0xffff;
1551        seq->addr2 = offset & 0xffff;
1552
1553        stfsm_load_seq(fsm, seq);
1554
1555        if (size_lb)
1556                stfsm_read_fifo(fsm, (uint32_t *)p, size_lb);
1557
1558        if (size_mop) {
1559                stfsm_read_fifo(fsm, tmp, read_mask + 1);
1560                memcpy(p + size_lb, &tmp, size_mop);
1561        }
1562
1563        /* Handle non-aligned buf */
1564        if ((uintptr_t)buf & 0x3)
1565                memcpy(buf, page_buf, size);
1566
1567        /* Wait for sequence to finish */
1568        stfsm_wait_seq(fsm);
1569
1570        stfsm_clear_fifo(fsm);
1571
1572        /* Exit 32-bit address mode, if required */
1573        if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)
1574                stfsm_enter_32bit_addr(fsm, 0);
1575
1576        return 0;
1577}
1578
1579static int stfsm_write(struct stfsm *fsm, const uint8_t *buf,
1580                       uint32_t size, uint32_t offset)
1581{
1582        struct stfsm_seq *seq = &fsm->stfsm_seq_write;
1583        uint32_t data_pads;
1584        uint32_t write_mask;
1585        uint32_t size_ub;
1586        uint32_t size_lb;
1587        uint32_t size_mop;
1588        uint32_t tmp[4];
1589        uint32_t i;
1590        uint32_t page_buf[FLASH_PAGESIZE_32];
1591        uint8_t *t = (uint8_t *)&tmp;
1592        const uint8_t *p;
1593        int ret;
1594
1595        dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset);
1596
1597        /* Enter 32-bit address mode, if required */
1598        if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)
1599                stfsm_enter_32bit_addr(fsm, 1);
1600
1601        /* Must write in multiples of 32 cycles (or 32*pads/8 bytes) */
1602        data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;
1603        write_mask = (data_pads << 2) - 1;
1604
1605        /* Handle non-aligned buf */
1606        if ((uintptr_t)buf & 0x3) {
1607                memcpy(page_buf, buf, size);
1608                p = (uint8_t *)page_buf;
1609        } else {
1610                p = buf;
1611        }
1612
1613        /* Handle non-aligned size */
1614        size_ub = (size + write_mask) & ~write_mask;
1615        size_lb = size & ~write_mask;
1616        size_mop = size & write_mask;
1617
1618        seq->data_size = TRANSFER_SIZE(size_ub);
1619        seq->addr1 = (offset >> 16) & 0xffff;
1620        seq->addr2 = offset & 0xffff;
1621
1622        /* Need to set FIFO to write mode, before writing data to FIFO (see
1623         * GNBvb79594)
1624         */
1625        writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG);
1626
1627        /*
1628         * Before writing data to the FIFO, apply a small delay to allow a
1629         * potential change of FIFO direction to complete.
1630         */
1631        if (fsm->fifo_dir_delay == 0)
1632                readl(fsm->base + SPI_FAST_SEQ_CFG);
1633        else
1634                udelay(fsm->fifo_dir_delay);
1635
1636
1637        /* Write data to FIFO, before starting sequence (see GNBvd79593) */
1638        if (size_lb) {
1639                stfsm_write_fifo(fsm, (uint32_t *)p, size_lb);
1640                p += size_lb;
1641        }
1642
1643        /* Handle non-aligned size */
1644        if (size_mop) {
1645                memset(t, 0xff, write_mask + 1);        /* fill with 0xff's */
1646                for (i = 0; i < size_mop; i++)
1647                        t[i] = *p++;
1648
1649                stfsm_write_fifo(fsm, tmp, write_mask + 1);
1650        }
1651
1652        /* Start sequence */
1653        stfsm_load_seq(fsm, seq);
1654
1655        /* Wait for sequence to finish */
1656        stfsm_wait_seq(fsm);
1657
1658        /* Wait for completion */
1659        ret = stfsm_wait_busy(fsm);
1660        if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)
1661                stfsm_s25fl_clear_status_reg(fsm);
1662
1663        /* Exit 32-bit address mode, if required */
1664        if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)
1665                stfsm_enter_32bit_addr(fsm, 0);
1666
1667        return 0;
1668}
1669
1670/*
1671 * Read an address range from the flash chip. The address range
1672 * may be any size provided it is within the physical boundaries.
1673 */
1674static int stfsm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
1675                          size_t *retlen, u_char *buf)
1676{
1677        struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1678        uint32_t bytes;
1679
1680        dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n",
1681                __func__, (u32)from, len);
1682
1683        mutex_lock(&fsm->lock);
1684
1685        while (len > 0) {
1686                bytes = min_t(size_t, len, FLASH_PAGESIZE);
1687
1688                stfsm_read(fsm, buf, bytes, from);
1689
1690                buf += bytes;
1691                from += bytes;
1692                len -= bytes;
1693
1694                *retlen += bytes;
1695        }
1696
1697        mutex_unlock(&fsm->lock);
1698
1699        return 0;
1700}
1701
1702static int stfsm_erase_sector(struct stfsm *fsm, uint32_t offset)
1703{
1704        struct stfsm_seq *seq = &stfsm_seq_erase_sector;
1705        int ret;
1706
1707        dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset);
1708
1709        /* Enter 32-bit address mode, if required */
1710        if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)
1711                stfsm_enter_32bit_addr(fsm, 1);
1712
1713        seq->addr1 = (offset >> 16) & 0xffff;
1714        seq->addr2 = offset & 0xffff;
1715
1716        stfsm_load_seq(fsm, seq);
1717
1718        stfsm_wait_seq(fsm);
1719
1720        /* Wait for completion */
1721        ret = stfsm_wait_busy(fsm);
1722        if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)
1723                stfsm_s25fl_clear_status_reg(fsm);
1724
1725        /* Exit 32-bit address mode, if required */
1726        if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)
1727                stfsm_enter_32bit_addr(fsm, 0);
1728
1729        return ret;
1730}
1731
1732static int stfsm_erase_chip(struct stfsm *fsm)
1733{
1734        const struct stfsm_seq *seq = &stfsm_seq_erase_chip;
1735
1736        dev_dbg(fsm->dev, "erasing chip\n");
1737
1738        stfsm_load_seq(fsm, seq);
1739
1740        stfsm_wait_seq(fsm);
1741
1742        return stfsm_wait_busy(fsm);
1743}
1744
1745/*
1746 * Write an address range to the flash chip.  Data must be written in
1747 * FLASH_PAGESIZE chunks.  The address range may be any size provided
1748 * it is within the physical boundaries.
1749 */
1750static int stfsm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
1751                           size_t *retlen, const u_char *buf)
1752{
1753        struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1754
1755        u32 page_offs;
1756        u32 bytes;
1757        uint8_t *b = (uint8_t *)buf;
1758        int ret = 0;
1759
1760        dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len);
1761
1762        /* Offset within page */
1763        page_offs = to % FLASH_PAGESIZE;
1764
1765        mutex_lock(&fsm->lock);
1766
1767        while (len) {
1768                /* Write up to page boundary */
1769                bytes = min_t(size_t, FLASH_PAGESIZE - page_offs, len);
1770
1771                ret = stfsm_write(fsm, b, bytes, to);
1772                if (ret)
1773                        goto out1;
1774
1775                b += bytes;
1776                len -= bytes;
1777                to += bytes;
1778
1779                /* We are now page-aligned */
1780                page_offs = 0;
1781
1782                *retlen += bytes;
1783
1784        }
1785
1786out1:
1787        mutex_unlock(&fsm->lock);
1788
1789        return ret;
1790}
1791
1792/*
1793 * Erase an address range on the flash chip. The address range may extend
1794 * one or more erase sectors.  Return an error is there is a problem erasing.
1795 */
1796static int stfsm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
1797{
1798        struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);
1799        u32 addr, len;
1800        int ret;
1801
1802        dev_dbg(fsm->dev, "%s at 0x%llx, len %lld\n", __func__,
1803                (long long)instr->addr, (long long)instr->len);
1804
1805        addr = instr->addr;
1806        len = instr->len;
1807
1808        mutex_lock(&fsm->lock);
1809
1810        /* Whole-chip erase? */
1811        if (len == mtd->size) {
1812                ret = stfsm_erase_chip(fsm);
1813                if (ret)
1814                        goto out1;
1815        } else {
1816                while (len) {
1817                        ret = stfsm_erase_sector(fsm, addr);
1818                        if (ret)
1819                                goto out1;
1820
1821                        addr += mtd->erasesize;
1822                        len -= mtd->erasesize;
1823                }
1824        }
1825
1826        mutex_unlock(&fsm->lock);
1827
1828        instr->state = MTD_ERASE_DONE;
1829        mtd_erase_callback(instr);
1830
1831        return 0;
1832
1833out1:
1834        instr->state = MTD_ERASE_FAILED;
1835        mutex_unlock(&fsm->lock);
1836
1837        return ret;
1838}
1839
1840static void stfsm_read_jedec(struct stfsm *fsm, uint8_t *jedec)
1841{
1842        const struct stfsm_seq *seq = &stfsm_seq_read_jedec;
1843        uint32_t tmp[2];
1844
1845        stfsm_load_seq(fsm, seq);
1846
1847        stfsm_read_fifo(fsm, tmp, 8);
1848
1849        memcpy(jedec, tmp, 5);
1850
1851        stfsm_wait_seq(fsm);
1852}
1853
1854static struct flash_info *stfsm_jedec_probe(struct stfsm *fsm)
1855{
1856        struct flash_info       *info;
1857        u16                     ext_jedec;
1858        u32                     jedec;
1859        u8                      id[5];
1860
1861        stfsm_read_jedec(fsm, id);
1862
1863        jedec     = id[0] << 16 | id[1] << 8 | id[2];
1864        /*
1865         * JEDEC also defines an optional "extended device information"
1866         * string for after vendor-specific data, after the three bytes
1867         * we use here. Supporting some chips might require using it.
1868         */
1869        ext_jedec = id[3] << 8  | id[4];
1870
1871        dev_dbg(fsm->dev, "JEDEC =  0x%08x [%02x %02x %02x %02x %02x]\n",
1872                jedec, id[0], id[1], id[2], id[3], id[4]);
1873
1874        for (info = flash_types; info->name; info++) {
1875                if (info->jedec_id == jedec) {
1876                        if (info->ext_id && info->ext_id != ext_jedec)
1877                                continue;
1878                        return info;
1879                }
1880        }
1881        dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);
1882
1883        return NULL;
1884}
1885
1886static int stfsm_set_mode(struct stfsm *fsm, uint32_t mode)
1887{
1888        int ret, timeout = 10;
1889
1890        /* Wait for controller to accept mode change */
1891        while (--timeout) {
1892                ret = readl(fsm->base + SPI_STA_MODE_CHANGE);
1893                if (ret & 0x1)
1894                        break;
1895                udelay(1);
1896        }
1897
1898        if (!timeout)
1899                return -EBUSY;
1900
1901        writel(mode, fsm->base + SPI_MODESELECT);
1902
1903        return 0;
1904}
1905
1906static void stfsm_set_freq(struct stfsm *fsm, uint32_t spi_freq)
1907{
1908        uint32_t emi_freq;
1909        uint32_t clk_div;
1910
1911        emi_freq = clk_get_rate(fsm->clk);
1912
1913        /*
1914         * Calculate clk_div - values between 2 and 128
1915         * Multiple of 2, rounded up
1916         */
1917        clk_div = 2 * DIV_ROUND_UP(emi_freq, 2 * spi_freq);
1918        if (clk_div < 2)
1919                clk_div = 2;
1920        else if (clk_div > 128)
1921                clk_div = 128;
1922
1923        /*
1924         * Determine a suitable delay for the IP to complete a change of
1925         * direction of the FIFO. The required delay is related to the clock
1926         * divider used. The following heuristics are based on empirical tests,
1927         * using a 100MHz EMI clock.
1928         */
1929        if (clk_div <= 4)
1930                fsm->fifo_dir_delay = 0;
1931        else if (clk_div <= 10)
1932                fsm->fifo_dir_delay = 1;
1933        else
1934                fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);
1935
1936        dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",
1937                emi_freq, spi_freq, clk_div);
1938
1939        writel(clk_div, fsm->base + SPI_CLOCKDIV);
1940}
1941
1942static int stfsm_init(struct stfsm *fsm)
1943{
1944        int ret;
1945
1946        /* Perform a soft reset of the FSM controller */
1947        writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);
1948        udelay(1);
1949        writel(0, fsm->base + SPI_FAST_SEQ_CFG);
1950
1951        /* Set clock to 'safe' frequency initially */
1952        stfsm_set_freq(fsm, STFSM_FLASH_SAFE_FREQ);
1953
1954        /* Switch to FSM */
1955        ret = stfsm_set_mode(fsm, SPI_MODESELECT_FSM);
1956        if (ret)
1957                return ret;
1958
1959        /* Set timing parameters */
1960        writel(SPI_CFG_DEVICE_ST            |
1961               SPI_CFG_DEFAULT_MIN_CS_HIGH  |
1962               SPI_CFG_DEFAULT_CS_SETUPHOLD |
1963               SPI_CFG_DEFAULT_DATA_HOLD,
1964               fsm->base + SPI_CONFIGDATA);
1965        writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);
1966
1967        /*
1968         * Set the FSM 'WAIT' delay to the minimum workable value.  Note, for
1969         * our purposes, the WAIT instruction is used purely to achieve
1970         * "sequence validity" rather than actually implement a delay.
1971         */
1972        writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME);
1973
1974        /* Clear FIFO, just in case */
1975        stfsm_clear_fifo(fsm);
1976
1977        return 0;
1978}
1979
1980static void stfsm_fetch_platform_configs(struct platform_device *pdev)
1981{
1982        struct stfsm *fsm = platform_get_drvdata(pdev);
1983        struct device_node *np = pdev->dev.of_node;
1984        struct regmap *regmap;
1985        uint32_t boot_device_reg;
1986        uint32_t boot_device_spi;
1987        uint32_t boot_device;     /* Value we read from *boot_device_reg */
1988        int ret;
1989
1990        /* Booting from SPI NOR Flash is the default */
1991        fsm->booted_from_spi = true;
1992
1993        regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1994        if (IS_ERR(regmap))
1995                goto boot_device_fail;
1996
1997        fsm->reset_signal = of_property_read_bool(np, "st,reset-signal");
1998
1999        fsm->reset_por = of_property_read_bool(np, "st,reset-por");
2000
2001        /* Where in the syscon the boot device information lives */
2002        ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg);
2003        if (ret)
2004                goto boot_device_fail;
2005
2006        /* Boot device value when booted from SPI NOR */
2007        ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi);
2008        if (ret)
2009                goto boot_device_fail;
2010
2011        ret = regmap_read(regmap, boot_device_reg, &boot_device);
2012        if (ret)
2013                goto boot_device_fail;
2014
2015        if (boot_device != boot_device_spi)
2016                fsm->booted_from_spi = false;
2017
2018        return;
2019
2020boot_device_fail:
2021        dev_warn(&pdev->dev,
2022                 "failed to fetch boot device, assuming boot from SPI\n");
2023}
2024
2025static int stfsm_probe(struct platform_device *pdev)
2026{
2027        struct device_node *np = pdev->dev.of_node;
2028        struct mtd_part_parser_data ppdata;
2029        struct flash_info *info;
2030        struct resource *res;
2031        struct stfsm *fsm;
2032        int ret;
2033
2034        if (!np) {
2035                dev_err(&pdev->dev, "No DT found\n");
2036                return -EINVAL;
2037        }
2038        ppdata.of_node = np;
2039
2040        fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);
2041        if (!fsm)
2042                return -ENOMEM;
2043
2044        fsm->dev = &pdev->dev;
2045
2046        platform_set_drvdata(pdev, fsm);
2047
2048        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2049        if (!res) {
2050                dev_err(&pdev->dev, "Resource not found\n");
2051                return -ENODEV;
2052        }
2053
2054        fsm->base = devm_ioremap_resource(&pdev->dev, res);
2055        if (IS_ERR(fsm->base)) {
2056                dev_err(&pdev->dev,
2057                        "Failed to reserve memory region %pR\n", res);
2058                return PTR_ERR(fsm->base);
2059        }
2060
2061        fsm->clk = devm_clk_get(&pdev->dev, NULL);
2062        if (IS_ERR(fsm->clk)) {
2063                dev_err(fsm->dev, "Couldn't find EMI clock.\n");
2064                return PTR_ERR(fsm->clk);
2065        }
2066
2067        ret = clk_prepare_enable(fsm->clk);
2068        if (ret) {
2069                dev_err(fsm->dev, "Failed to enable EMI clock.\n");
2070                return ret;
2071        }
2072
2073        mutex_init(&fsm->lock);
2074
2075        ret = stfsm_init(fsm);
2076        if (ret) {
2077                dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");
2078                return ret;
2079        }
2080
2081        stfsm_fetch_platform_configs(pdev);
2082
2083        /* Detect SPI FLASH device */
2084        info = stfsm_jedec_probe(fsm);
2085        if (!info)
2086                return -ENODEV;
2087        fsm->info = info;
2088
2089        /* Use device size to determine address width */
2090        if (info->sector_size * info->n_sectors > 0x1000000)
2091                info->flags |= FLASH_FLAG_32BIT_ADDR;
2092
2093        /*
2094         * Configure READ/WRITE/ERASE sequences according to platform and
2095         * device flags.
2096         */
2097        if (info->config) {
2098                ret = info->config(fsm);
2099                if (ret)
2100                        return ret;
2101        } else {
2102                ret = stfsm_prepare_rwe_seqs_default(fsm);
2103                if (ret)
2104                        return ret;
2105        }
2106
2107        fsm->mtd.name           = info->name;
2108        fsm->mtd.dev.parent     = &pdev->dev;
2109        fsm->mtd.type           = MTD_NORFLASH;
2110        fsm->mtd.writesize      = 4;
2111        fsm->mtd.writebufsize   = fsm->mtd.writesize;
2112        fsm->mtd.flags          = MTD_CAP_NORFLASH;
2113        fsm->mtd.size           = info->sector_size * info->n_sectors;
2114        fsm->mtd.erasesize      = info->sector_size;
2115
2116        fsm->mtd._read  = stfsm_mtd_read;
2117        fsm->mtd._write = stfsm_mtd_write;
2118        fsm->mtd._erase = stfsm_mtd_erase;
2119
2120        dev_info(&pdev->dev,
2121                "Found serial flash device: %s\n"
2122                " size = %llx (%lldMiB) erasesize = 0x%08x (%uKiB)\n",
2123                info->name,
2124                (long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),
2125                fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));
2126
2127        return mtd_device_parse_register(&fsm->mtd, NULL, &ppdata, NULL, 0);
2128}
2129
2130static int stfsm_remove(struct platform_device *pdev)
2131{
2132        struct stfsm *fsm = platform_get_drvdata(pdev);
2133
2134        return mtd_device_unregister(&fsm->mtd);
2135}
2136
2137#ifdef CONFIG_PM_SLEEP
2138static int stfsmfsm_suspend(struct device *dev)
2139{
2140        struct stfsm *fsm = dev_get_drvdata(dev);
2141
2142        clk_disable_unprepare(fsm->clk);
2143
2144        return 0;
2145}
2146
2147static int stfsmfsm_resume(struct device *dev)
2148{
2149        struct stfsm *fsm = dev_get_drvdata(dev);
2150
2151        clk_prepare_enable(fsm->clk);
2152
2153        return 0;
2154}
2155#endif
2156
2157static SIMPLE_DEV_PM_OPS(stfsm_pm_ops, stfsmfsm_suspend, stfsmfsm_resume);
2158
2159static const struct of_device_id stfsm_match[] = {
2160        { .compatible = "st,spi-fsm", },
2161        {},
2162};
2163MODULE_DEVICE_TABLE(of, stfsm_match);
2164
2165static struct platform_driver stfsm_driver = {
2166        .probe          = stfsm_probe,
2167        .remove         = stfsm_remove,
2168        .driver         = {
2169                .name   = "st-spi-fsm",
2170                .of_match_table = stfsm_match,
2171                .pm     = &stfsm_pm_ops,
2172        },
2173};
2174module_platform_driver(stfsm_driver);
2175
2176MODULE_AUTHOR("Angus Clark <angus.clark@st.com>");
2177MODULE_DESCRIPTION("ST SPI FSM driver");
2178MODULE_LICENSE("GPL");
2179