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38#include "e1000.h"
39
40static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
41static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
42static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
43static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
44static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
46static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
47static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
48static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
49static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
50static s32 e1000_led_on_82574(struct e1000_hw *hw);
51static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
52static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
53static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
54static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
55static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
56static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
57static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
58
59
60
61
62
63static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
64{
65 struct e1000_phy_info *phy = &hw->phy;
66 s32 ret_val;
67
68 if (hw->phy.media_type != e1000_media_type_copper) {
69 phy->type = e1000_phy_none;
70 return 0;
71 }
72
73 phy->addr = 1;
74 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
75 phy->reset_delay_us = 100;
76
77 phy->ops.power_up = e1000_power_up_phy_copper;
78 phy->ops.power_down = e1000_power_down_phy_copper_82571;
79
80 switch (hw->mac.type) {
81 case e1000_82571:
82 case e1000_82572:
83 phy->type = e1000_phy_igp_2;
84 break;
85 case e1000_82573:
86 phy->type = e1000_phy_m88;
87 break;
88 case e1000_82574:
89 case e1000_82583:
90 phy->type = e1000_phy_bm;
91 phy->ops.acquire = e1000_get_hw_semaphore_82574;
92 phy->ops.release = e1000_put_hw_semaphore_82574;
93 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
94 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
95 break;
96 default:
97 return -E1000_ERR_PHY;
98 }
99
100
101 ret_val = e1000_get_phy_id_82571(hw);
102 if (ret_val) {
103 e_dbg("Error getting PHY ID\n");
104 return ret_val;
105 }
106
107
108 switch (hw->mac.type) {
109 case e1000_82571:
110 case e1000_82572:
111 if (phy->id != IGP01E1000_I_PHY_ID)
112 ret_val = -E1000_ERR_PHY;
113 break;
114 case e1000_82573:
115 if (phy->id != M88E1111_I_PHY_ID)
116 ret_val = -E1000_ERR_PHY;
117 break;
118 case e1000_82574:
119 case e1000_82583:
120 if (phy->id != BME1000_E_PHY_ID_R2)
121 ret_val = -E1000_ERR_PHY;
122 break;
123 default:
124 ret_val = -E1000_ERR_PHY;
125 break;
126 }
127
128 if (ret_val)
129 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
130
131 return ret_val;
132}
133
134
135
136
137
138static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
139{
140 struct e1000_nvm_info *nvm = &hw->nvm;
141 u32 eecd = er32(EECD);
142 u16 size;
143
144 nvm->opcode_bits = 8;
145 nvm->delay_usec = 1;
146 switch (nvm->override) {
147 case e1000_nvm_override_spi_large:
148 nvm->page_size = 32;
149 nvm->address_bits = 16;
150 break;
151 case e1000_nvm_override_spi_small:
152 nvm->page_size = 8;
153 nvm->address_bits = 8;
154 break;
155 default:
156 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
157 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
158 break;
159 }
160
161 switch (hw->mac.type) {
162 case e1000_82573:
163 case e1000_82574:
164 case e1000_82583:
165 if (((eecd >> 15) & 0x3) == 0x3) {
166 nvm->type = e1000_nvm_flash_hw;
167 nvm->word_size = 2048;
168
169
170
171 eecd &= ~E1000_EECD_AUPDEN;
172 ew32(EECD, eecd);
173 break;
174 }
175
176 default:
177 nvm->type = e1000_nvm_eeprom_spi;
178 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
179 E1000_EECD_SIZE_EX_SHIFT);
180
181
182
183 size += NVM_WORD_SIZE_BASE_SHIFT;
184
185
186 if (size > 14)
187 size = 14;
188 nvm->word_size = 1 << size;
189 break;
190 }
191
192
193 switch (hw->mac.type) {
194 case e1000_82574:
195 case e1000_82583:
196 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
197 nvm->ops.release = e1000_put_hw_semaphore_82574;
198 break;
199 default:
200 break;
201 }
202
203 return 0;
204}
205
206
207
208
209
210static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
211{
212 struct e1000_mac_info *mac = &hw->mac;
213 u32 swsm = 0;
214 u32 swsm2 = 0;
215 bool force_clear_smbi = false;
216
217
218 switch (hw->adapter->pdev->device) {
219 case E1000_DEV_ID_82571EB_FIBER:
220 case E1000_DEV_ID_82572EI_FIBER:
221 case E1000_DEV_ID_82571EB_QUAD_FIBER:
222 hw->phy.media_type = e1000_media_type_fiber;
223 mac->ops.setup_physical_interface =
224 e1000_setup_fiber_serdes_link_82571;
225 mac->ops.check_for_link = e1000e_check_for_fiber_link;
226 mac->ops.get_link_up_info =
227 e1000e_get_speed_and_duplex_fiber_serdes;
228 break;
229 case E1000_DEV_ID_82571EB_SERDES:
230 case E1000_DEV_ID_82571EB_SERDES_DUAL:
231 case E1000_DEV_ID_82571EB_SERDES_QUAD:
232 case E1000_DEV_ID_82572EI_SERDES:
233 hw->phy.media_type = e1000_media_type_internal_serdes;
234 mac->ops.setup_physical_interface =
235 e1000_setup_fiber_serdes_link_82571;
236 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
237 mac->ops.get_link_up_info =
238 e1000e_get_speed_and_duplex_fiber_serdes;
239 break;
240 default:
241 hw->phy.media_type = e1000_media_type_copper;
242 mac->ops.setup_physical_interface =
243 e1000_setup_copper_link_82571;
244 mac->ops.check_for_link = e1000e_check_for_copper_link;
245 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
246 break;
247 }
248
249
250 mac->mta_reg_count = 128;
251
252 mac->rar_entry_count = E1000_RAR_ENTRIES;
253
254 mac->adaptive_ifs = true;
255
256
257 switch (hw->mac.type) {
258 case e1000_82573:
259 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
260 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
261 mac->ops.led_on = e1000e_led_on_generic;
262 mac->ops.blink_led = e1000e_blink_led_generic;
263
264
265 mac->has_fwsm = true;
266
267
268
269 mac->arc_subsystem_valid = !!(er32(FWSM) &
270 E1000_FWSM_MODE_MASK);
271 break;
272 case e1000_82574:
273 case e1000_82583:
274 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
275 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
276 mac->ops.led_on = e1000_led_on_82574;
277 break;
278 default:
279 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
280 mac->ops.led_on = e1000e_led_on_generic;
281 mac->ops.blink_led = e1000e_blink_led_generic;
282
283
284 mac->has_fwsm = true;
285 break;
286 }
287
288
289
290
291
292
293
294 switch (hw->mac.type) {
295 case e1000_82571:
296 case e1000_82572:
297 swsm2 = er32(SWSM2);
298
299 if (!(swsm2 & E1000_SWSM2_LOCK)) {
300
301 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
302 force_clear_smbi = true;
303 } else {
304 force_clear_smbi = false;
305 }
306 break;
307 default:
308 force_clear_smbi = true;
309 break;
310 }
311
312 if (force_clear_smbi) {
313
314 swsm = er32(SWSM);
315 if (swsm & E1000_SWSM_SMBI) {
316
317
318
319
320 e_dbg("Please update your 82571 Bootagent\n");
321 }
322 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
323 }
324
325
326 hw->dev_spec.e82571.smb_counter = 0;
327
328 return 0;
329}
330
331static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
332{
333 struct e1000_hw *hw = &adapter->hw;
334 static int global_quad_port_a;
335 struct pci_dev *pdev = adapter->pdev;
336 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
337 s32 rc;
338
339 rc = e1000_init_mac_params_82571(hw);
340 if (rc)
341 return rc;
342
343 rc = e1000_init_nvm_params_82571(hw);
344 if (rc)
345 return rc;
346
347 rc = e1000_init_phy_params_82571(hw);
348 if (rc)
349 return rc;
350
351
352 switch (pdev->device) {
353 case E1000_DEV_ID_82571EB_QUAD_COPPER:
354 case E1000_DEV_ID_82571EB_QUAD_FIBER:
355 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
356 case E1000_DEV_ID_82571PT_QUAD_COPPER:
357 adapter->flags |= FLAG_IS_QUAD_PORT;
358
359 if (global_quad_port_a == 0)
360 adapter->flags |= FLAG_IS_QUAD_PORT_A;
361
362 global_quad_port_a++;
363 if (global_quad_port_a == 4)
364 global_quad_port_a = 0;
365 break;
366 default:
367 break;
368 }
369
370 switch (adapter->hw.mac.type) {
371 case e1000_82571:
372
373 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
374 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
375 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
376 (is_port_b))
377 adapter->flags &= ~FLAG_HAS_WOL;
378
379 if (adapter->flags & FLAG_IS_QUAD_PORT &&
380 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
381 adapter->flags &= ~FLAG_HAS_WOL;
382
383 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
384 adapter->flags &= ~FLAG_HAS_WOL;
385 break;
386 case e1000_82573:
387 if (pdev->device == E1000_DEV_ID_82573L) {
388 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
389 adapter->max_hw_frame_size = DEFAULT_JUMBO;
390 }
391 break;
392 default:
393 break;
394 }
395
396 return 0;
397}
398
399
400
401
402
403
404
405
406static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
407{
408 struct e1000_phy_info *phy = &hw->phy;
409 s32 ret_val;
410 u16 phy_id = 0;
411
412 switch (hw->mac.type) {
413 case e1000_82571:
414 case e1000_82572:
415
416
417
418
419
420 phy->id = IGP01E1000_I_PHY_ID;
421 break;
422 case e1000_82573:
423 return e1000e_get_phy_id(hw);
424 case e1000_82574:
425 case e1000_82583:
426 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
427 if (ret_val)
428 return ret_val;
429
430 phy->id = (u32)(phy_id << 16);
431 usleep_range(20, 40);
432 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
433 if (ret_val)
434 return ret_val;
435
436 phy->id |= (u32)(phy_id);
437 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
438 break;
439 default:
440 return -E1000_ERR_PHY;
441 }
442
443 return 0;
444}
445
446
447
448
449
450
451
452static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
453{
454 u32 swsm;
455 s32 sw_timeout = hw->nvm.word_size + 1;
456 s32 fw_timeout = hw->nvm.word_size + 1;
457 s32 i = 0;
458
459
460
461
462
463
464
465
466 if (hw->dev_spec.e82571.smb_counter > 2)
467 sw_timeout = 1;
468
469
470 while (i < sw_timeout) {
471 swsm = er32(SWSM);
472 if (!(swsm & E1000_SWSM_SMBI))
473 break;
474
475 usleep_range(50, 100);
476 i++;
477 }
478
479 if (i == sw_timeout) {
480 e_dbg("Driver can't access device - SMBI bit is set.\n");
481 hw->dev_spec.e82571.smb_counter++;
482 }
483
484 for (i = 0; i < fw_timeout; i++) {
485 swsm = er32(SWSM);
486 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
487
488
489 if (er32(SWSM) & E1000_SWSM_SWESMBI)
490 break;
491
492 usleep_range(50, 100);
493 }
494
495 if (i == fw_timeout) {
496
497 e1000_put_hw_semaphore_82571(hw);
498 e_dbg("Driver can't access the NVM\n");
499 return -E1000_ERR_NVM;
500 }
501
502 return 0;
503}
504
505
506
507
508
509
510
511static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
512{
513 u32 swsm;
514
515 swsm = er32(SWSM);
516 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
517 ew32(SWSM, swsm);
518}
519
520
521
522
523
524
525
526
527static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
528{
529 u32 extcnf_ctrl;
530 s32 i = 0;
531
532 extcnf_ctrl = er32(EXTCNF_CTRL);
533 do {
534 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
535 ew32(EXTCNF_CTRL, extcnf_ctrl);
536 extcnf_ctrl = er32(EXTCNF_CTRL);
537
538 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
539 break;
540
541 usleep_range(2000, 4000);
542 i++;
543 } while (i < MDIO_OWNERSHIP_TIMEOUT);
544
545 if (i == MDIO_OWNERSHIP_TIMEOUT) {
546
547 e1000_put_hw_semaphore_82573(hw);
548 e_dbg("Driver can't access the PHY\n");
549 return -E1000_ERR_PHY;
550 }
551
552 return 0;
553}
554
555
556
557
558
559
560
561
562static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
563{
564 u32 extcnf_ctrl;
565
566 extcnf_ctrl = er32(EXTCNF_CTRL);
567 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
568 ew32(EXTCNF_CTRL, extcnf_ctrl);
569}
570
571static DEFINE_MUTEX(swflag_mutex);
572
573
574
575
576
577
578
579
580static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
581{
582 s32 ret_val;
583
584 mutex_lock(&swflag_mutex);
585 ret_val = e1000_get_hw_semaphore_82573(hw);
586 if (ret_val)
587 mutex_unlock(&swflag_mutex);
588 return ret_val;
589}
590
591
592
593
594
595
596
597
598static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
599{
600 e1000_put_hw_semaphore_82573(hw);
601 mutex_unlock(&swflag_mutex);
602}
603
604
605
606
607
608
609
610
611
612
613
614
615
616static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
617{
618 u32 data = er32(POEMB);
619
620 if (active)
621 data |= E1000_PHY_CTRL_D0A_LPLU;
622 else
623 data &= ~E1000_PHY_CTRL_D0A_LPLU;
624
625 ew32(POEMB, data);
626 return 0;
627}
628
629
630
631
632
633
634
635
636
637
638
639
640static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
641{
642 u32 data = er32(POEMB);
643
644 if (!active) {
645 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
646 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
647 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
648 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
649 data |= E1000_PHY_CTRL_NOND0A_LPLU;
650 }
651
652 ew32(POEMB, data);
653 return 0;
654}
655
656
657
658
659
660
661
662
663
664
665static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
666{
667 s32 ret_val;
668
669 ret_val = e1000_get_hw_semaphore_82571(hw);
670 if (ret_val)
671 return ret_val;
672
673 switch (hw->mac.type) {
674 case e1000_82573:
675 break;
676 default:
677 ret_val = e1000e_acquire_nvm(hw);
678 break;
679 }
680
681 if (ret_val)
682 e1000_put_hw_semaphore_82571(hw);
683
684 return ret_val;
685}
686
687
688
689
690
691
692
693static void e1000_release_nvm_82571(struct e1000_hw *hw)
694{
695 e1000e_release_nvm(hw);
696 e1000_put_hw_semaphore_82571(hw);
697}
698
699
700
701
702
703
704
705
706
707
708
709
710
711static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
712 u16 *data)
713{
714 s32 ret_val;
715
716 switch (hw->mac.type) {
717 case e1000_82573:
718 case e1000_82574:
719 case e1000_82583:
720 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
721 break;
722 case e1000_82571:
723 case e1000_82572:
724 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
725 break;
726 default:
727 ret_val = -E1000_ERR_NVM;
728 break;
729 }
730
731 return ret_val;
732}
733
734
735
736
737
738
739
740
741
742static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
743{
744 u32 eecd;
745 s32 ret_val;
746 u16 i;
747
748 ret_val = e1000e_update_nvm_checksum_generic(hw);
749 if (ret_val)
750 return ret_val;
751
752
753
754
755 if (hw->nvm.type != e1000_nvm_flash_hw)
756 return 0;
757
758
759 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
760 usleep_range(1000, 2000);
761 if (!(er32(EECD) & E1000_EECD_FLUPD))
762 break;
763 }
764
765 if (i == E1000_FLASH_UPDATES)
766 return -E1000_ERR_NVM;
767
768
769 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
770
771
772
773 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
774 e1e_flush();
775 ew32(HICR, E1000_HICR_FW_RESET);
776 }
777
778
779 eecd = er32(EECD) | E1000_EECD_FLUPD;
780 ew32(EECD, eecd);
781
782 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
783 usleep_range(1000, 2000);
784 if (!(er32(EECD) & E1000_EECD_FLUPD))
785 break;
786 }
787
788 if (i == E1000_FLASH_UPDATES)
789 return -E1000_ERR_NVM;
790
791 return 0;
792}
793
794
795
796
797
798
799
800
801static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
802{
803 if (hw->nvm.type == e1000_nvm_flash_hw)
804 e1000_fix_nvm_checksum_82571(hw);
805
806 return e1000e_validate_nvm_checksum_generic(hw);
807}
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
824 u16 words, u16 *data)
825{
826 struct e1000_nvm_info *nvm = &hw->nvm;
827 u32 i, eewr = 0;
828 s32 ret_val = 0;
829
830
831
832
833 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
834 (words == 0)) {
835 e_dbg("nvm parameter(s) out of bounds\n");
836 return -E1000_ERR_NVM;
837 }
838
839 for (i = 0; i < words; i++) {
840 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
841 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
842 E1000_NVM_RW_REG_START);
843
844 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
845 if (ret_val)
846 break;
847
848 ew32(EEWR, eewr);
849
850 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
851 if (ret_val)
852 break;
853 }
854
855 return ret_val;
856}
857
858
859
860
861
862
863
864static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
865{
866 s32 timeout = PHY_CFG_TIMEOUT;
867
868 while (timeout) {
869 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
870 break;
871 usleep_range(1000, 2000);
872 timeout--;
873 }
874 if (!timeout) {
875 e_dbg("MNG configuration cycle has not completed.\n");
876 return -E1000_ERR_RESET;
877 }
878
879 return 0;
880}
881
882
883
884
885
886
887
888
889
890
891
892
893static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
894{
895 struct e1000_phy_info *phy = &hw->phy;
896 s32 ret_val;
897 u16 data;
898
899 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
900 if (ret_val)
901 return ret_val;
902
903 if (active) {
904 data |= IGP02E1000_PM_D0_LPLU;
905 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
906 if (ret_val)
907 return ret_val;
908
909
910 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
911 if (ret_val)
912 return ret_val;
913 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
914 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
915 if (ret_val)
916 return ret_val;
917 } else {
918 data &= ~IGP02E1000_PM_D0_LPLU;
919 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
920
921
922
923
924
925 if (phy->smart_speed == e1000_smart_speed_on) {
926 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
927 &data);
928 if (ret_val)
929 return ret_val;
930
931 data |= IGP01E1000_PSCFR_SMART_SPEED;
932 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
933 data);
934 if (ret_val)
935 return ret_val;
936 } else if (phy->smart_speed == e1000_smart_speed_off) {
937 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
938 &data);
939 if (ret_val)
940 return ret_val;
941
942 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
943 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
944 data);
945 if (ret_val)
946 return ret_val;
947 }
948 }
949
950 return 0;
951}
952
953
954
955
956
957
958
959static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
960{
961 u32 ctrl, ctrl_ext, eecd, tctl;
962 s32 ret_val;
963
964
965
966
967 ret_val = e1000e_disable_pcie_master(hw);
968 if (ret_val)
969 e_dbg("PCI-E Master disable polling has failed.\n");
970
971 e_dbg("Masking off all interrupts\n");
972 ew32(IMC, 0xffffffff);
973
974 ew32(RCTL, 0);
975 tctl = er32(TCTL);
976 tctl &= ~E1000_TCTL_EN;
977 ew32(TCTL, tctl);
978 e1e_flush();
979
980 usleep_range(10000, 20000);
981
982
983
984
985 switch (hw->mac.type) {
986 case e1000_82573:
987 ret_val = e1000_get_hw_semaphore_82573(hw);
988 break;
989 case e1000_82574:
990 case e1000_82583:
991 ret_val = e1000_get_hw_semaphore_82574(hw);
992 break;
993 default:
994 break;
995 }
996
997 ctrl = er32(CTRL);
998
999 e_dbg("Issuing a global reset to MAC\n");
1000 ew32(CTRL, ctrl | E1000_CTRL_RST);
1001
1002
1003 switch (hw->mac.type) {
1004 case e1000_82573:
1005
1006 if (!ret_val)
1007 e1000_put_hw_semaphore_82573(hw);
1008 break;
1009 case e1000_82574:
1010 case e1000_82583:
1011
1012 if (!ret_val)
1013 e1000_put_hw_semaphore_82574(hw);
1014 break;
1015 default:
1016 break;
1017 }
1018
1019 if (hw->nvm.type == e1000_nvm_flash_hw) {
1020 usleep_range(10, 20);
1021 ctrl_ext = er32(CTRL_EXT);
1022 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1023 ew32(CTRL_EXT, ctrl_ext);
1024 e1e_flush();
1025 }
1026
1027 ret_val = e1000e_get_auto_rd_done(hw);
1028 if (ret_val)
1029
1030 return ret_val;
1031
1032
1033
1034
1035
1036
1037 switch (hw->mac.type) {
1038 case e1000_82571:
1039 case e1000_82572:
1040
1041
1042
1043 eecd = er32(EECD);
1044 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1045 ew32(EECD, eecd);
1046 break;
1047 case e1000_82573:
1048 case e1000_82574:
1049 case e1000_82583:
1050 msleep(25);
1051 break;
1052 default:
1053 break;
1054 }
1055
1056
1057 ew32(IMC, 0xffffffff);
1058 er32(ICR);
1059
1060 if (hw->mac.type == e1000_82571) {
1061
1062 ret_val = e1000_check_alt_mac_addr_generic(hw);
1063 if (ret_val)
1064 return ret_val;
1065
1066 e1000e_set_laa_state_82571(hw, true);
1067 }
1068
1069
1070 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1071 hw->mac.serdes_link_state = e1000_serdes_link_down;
1072
1073 return 0;
1074}
1075
1076
1077
1078
1079
1080
1081
1082static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1083{
1084 struct e1000_mac_info *mac = &hw->mac;
1085 u32 reg_data;
1086 s32 ret_val;
1087 u16 i, rar_count = mac->rar_entry_count;
1088
1089 e1000_initialize_hw_bits_82571(hw);
1090
1091
1092 ret_val = mac->ops.id_led_init(hw);
1093
1094 if (ret_val)
1095 e_dbg("Error initializing identification LED\n");
1096
1097
1098 e_dbg("Initializing the IEEE VLAN\n");
1099 mac->ops.clear_vfta(hw);
1100
1101
1102
1103
1104
1105
1106 if (e1000e_get_laa_state_82571(hw))
1107 rar_count--;
1108 e1000e_init_rx_addrs(hw, rar_count);
1109
1110
1111 e_dbg("Zeroing the MTA\n");
1112 for (i = 0; i < mac->mta_reg_count; i++)
1113 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1114
1115
1116 ret_val = mac->ops.setup_link(hw);
1117
1118
1119 reg_data = er32(TXDCTL(0));
1120 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1121 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1122 ew32(TXDCTL(0), reg_data);
1123
1124
1125 switch (mac->type) {
1126 case e1000_82573:
1127 e1000e_enable_tx_pkt_filtering(hw);
1128
1129 case e1000_82574:
1130 case e1000_82583:
1131 reg_data = er32(GCR);
1132 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1133 ew32(GCR, reg_data);
1134 break;
1135 default:
1136 reg_data = er32(TXDCTL(1));
1137 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1138 E1000_TXDCTL_FULL_TX_DESC_WB |
1139 E1000_TXDCTL_COUNT_DESC);
1140 ew32(TXDCTL(1), reg_data);
1141 break;
1142 }
1143
1144
1145
1146
1147
1148
1149 e1000_clear_hw_cntrs_82571(hw);
1150
1151 return ret_val;
1152}
1153
1154
1155
1156
1157
1158
1159
1160static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1161{
1162 u32 reg;
1163
1164
1165 reg = er32(TXDCTL(0));
1166 reg |= (1 << 22);
1167 ew32(TXDCTL(0), reg);
1168
1169
1170 reg = er32(TXDCTL(1));
1171 reg |= (1 << 22);
1172 ew32(TXDCTL(1), reg);
1173
1174
1175 reg = er32(TARC(0));
1176 reg &= ~(0xF << 27);
1177 switch (hw->mac.type) {
1178 case e1000_82571:
1179 case e1000_82572:
1180 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1181 break;
1182 case e1000_82574:
1183 case e1000_82583:
1184 reg |= (1 << 26);
1185 break;
1186 default:
1187 break;
1188 }
1189 ew32(TARC(0), reg);
1190
1191
1192 reg = er32(TARC(1));
1193 switch (hw->mac.type) {
1194 case e1000_82571:
1195 case e1000_82572:
1196 reg &= ~((1 << 29) | (1 << 30));
1197 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1198 if (er32(TCTL) & E1000_TCTL_MULR)
1199 reg &= ~(1 << 28);
1200 else
1201 reg |= (1 << 28);
1202 ew32(TARC(1), reg);
1203 break;
1204 default:
1205 break;
1206 }
1207
1208
1209 switch (hw->mac.type) {
1210 case e1000_82573:
1211 case e1000_82574:
1212 case e1000_82583:
1213 reg = er32(CTRL);
1214 reg &= ~(1 << 29);
1215 ew32(CTRL, reg);
1216 break;
1217 default:
1218 break;
1219 }
1220
1221
1222 switch (hw->mac.type) {
1223 case e1000_82573:
1224 case e1000_82574:
1225 case e1000_82583:
1226 reg = er32(CTRL_EXT);
1227 reg &= ~(1 << 23);
1228 reg |= (1 << 22);
1229 ew32(CTRL_EXT, reg);
1230 break;
1231 default:
1232 break;
1233 }
1234
1235 if (hw->mac.type == e1000_82571) {
1236 reg = er32(PBA_ECC);
1237 reg |= E1000_PBA_ECC_CORR_EN;
1238 ew32(PBA_ECC, reg);
1239 }
1240
1241
1242
1243
1244 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1245 reg = er32(CTRL_EXT);
1246 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1247 ew32(CTRL_EXT, reg);
1248 }
1249
1250
1251
1252
1253 if (hw->mac.type <= e1000_82573) {
1254 reg = er32(RFCTL);
1255 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1256 ew32(RFCTL, reg);
1257 }
1258
1259
1260 switch (hw->mac.type) {
1261 case e1000_82574:
1262 case e1000_82583:
1263 reg = er32(GCR);
1264 reg |= (1 << 22);
1265 ew32(GCR, reg);
1266
1267
1268
1269
1270
1271
1272
1273 reg = er32(GCR2);
1274 reg |= 1;
1275 ew32(GCR2, reg);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282
1283
1284
1285
1286
1287
1288
1289static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1290{
1291 u32 offset;
1292 u32 vfta_value = 0;
1293 u32 vfta_offset = 0;
1294 u32 vfta_bit_in_reg = 0;
1295
1296 switch (hw->mac.type) {
1297 case e1000_82573:
1298 case e1000_82574:
1299 case e1000_82583:
1300 if (hw->mng_cookie.vlan_id != 0) {
1301
1302
1303
1304
1305
1306
1307 vfta_offset = (hw->mng_cookie.vlan_id >>
1308 E1000_VFTA_ENTRY_SHIFT) &
1309 E1000_VFTA_ENTRY_MASK;
1310 vfta_bit_in_reg =
1311 1 << (hw->mng_cookie.vlan_id &
1312 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1313 }
1314 break;
1315 default:
1316 break;
1317 }
1318 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1319
1320
1321
1322
1323 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1324 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1325 e1e_flush();
1326 }
1327}
1328
1329
1330
1331
1332
1333
1334
1335
1336static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1337{
1338 u16 data;
1339
1340 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1341 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1342}
1343
1344
1345
1346
1347
1348
1349
1350static s32 e1000_led_on_82574(struct e1000_hw *hw)
1351{
1352 u32 ctrl;
1353 u32 i;
1354
1355 ctrl = hw->mac.ledctl_mode2;
1356 if (!(E1000_STATUS_LU & er32(STATUS))) {
1357
1358
1359
1360 for (i = 0; i < 4; i++)
1361 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1362 E1000_LEDCTL_MODE_LED_ON)
1363 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1364 }
1365 ew32(LEDCTL, ctrl);
1366
1367 return 0;
1368}
1369
1370
1371
1372
1373
1374
1375
1376bool e1000_check_phy_82574(struct e1000_hw *hw)
1377{
1378 u16 status_1kbt = 0;
1379 u16 receive_errors = 0;
1380 s32 ret_val;
1381
1382
1383
1384
1385 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1386 if (ret_val)
1387 return false;
1388 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1389 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1390 if (ret_val)
1391 return false;
1392 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1393 E1000_IDLE_ERROR_COUNT_MASK)
1394 return true;
1395 }
1396
1397 return false;
1398}
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1411{
1412
1413
1414
1415
1416 switch (hw->mac.type) {
1417 case e1000_82573:
1418 case e1000_82574:
1419 case e1000_82583:
1420 if (hw->fc.requested_mode == e1000_fc_default)
1421 hw->fc.requested_mode = e1000_fc_full;
1422 break;
1423 default:
1424 break;
1425 }
1426
1427 return e1000e_setup_link_generic(hw);
1428}
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1439{
1440 u32 ctrl;
1441 s32 ret_val;
1442
1443 ctrl = er32(CTRL);
1444 ctrl |= E1000_CTRL_SLU;
1445 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1446 ew32(CTRL, ctrl);
1447
1448 switch (hw->phy.type) {
1449 case e1000_phy_m88:
1450 case e1000_phy_bm:
1451 ret_val = e1000e_copper_link_setup_m88(hw);
1452 break;
1453 case e1000_phy_igp_2:
1454 ret_val = e1000e_copper_link_setup_igp(hw);
1455 break;
1456 default:
1457 return -E1000_ERR_PHY;
1458 }
1459
1460 if (ret_val)
1461 return ret_val;
1462
1463 return e1000e_setup_copper_link(hw);
1464}
1465
1466
1467
1468
1469
1470
1471
1472
1473static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1474{
1475 switch (hw->mac.type) {
1476 case e1000_82571:
1477 case e1000_82572:
1478
1479
1480
1481
1482
1483
1484 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1485 break;
1486 default:
1487 break;
1488 }
1489
1490 return e1000e_setup_fiber_serdes_link(hw);
1491}
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1513{
1514 struct e1000_mac_info *mac = &hw->mac;
1515 u32 rxcw;
1516 u32 ctrl;
1517 u32 status;
1518 u32 txcw;
1519 u32 i;
1520 s32 ret_val = 0;
1521
1522 ctrl = er32(CTRL);
1523 status = er32(STATUS);
1524 er32(RXCW);
1525
1526 usleep_range(10, 20);
1527 rxcw = er32(RXCW);
1528
1529 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1530
1531 switch (mac->serdes_link_state) {
1532 case e1000_serdes_link_autoneg_complete:
1533 if (!(status & E1000_STATUS_LU)) {
1534
1535
1536
1537 mac->serdes_link_state =
1538 e1000_serdes_link_autoneg_progress;
1539 mac->serdes_has_link = false;
1540 e_dbg("AN_UP -> AN_PROG\n");
1541 } else {
1542 mac->serdes_has_link = true;
1543 }
1544 break;
1545
1546 case e1000_serdes_link_forced_up:
1547
1548
1549
1550
1551
1552 if (rxcw & E1000_RXCW_C) {
1553
1554 ew32(TXCW, mac->txcw);
1555 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1556 mac->serdes_link_state =
1557 e1000_serdes_link_autoneg_progress;
1558 mac->serdes_has_link = false;
1559 e_dbg("FORCED_UP -> AN_PROG\n");
1560 } else {
1561 mac->serdes_has_link = true;
1562 }
1563 break;
1564
1565 case e1000_serdes_link_autoneg_progress:
1566 if (rxcw & E1000_RXCW_C) {
1567
1568
1569
1570
1571 if (status & E1000_STATUS_LU) {
1572 mac->serdes_link_state =
1573 e1000_serdes_link_autoneg_complete;
1574 e_dbg("AN_PROG -> AN_UP\n");
1575 mac->serdes_has_link = true;
1576 } else {
1577
1578 mac->serdes_link_state =
1579 e1000_serdes_link_down;
1580 e_dbg("AN_PROG -> DOWN\n");
1581 }
1582 } else {
1583
1584
1585
1586
1587 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1588 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1589 ew32(CTRL, ctrl);
1590
1591
1592 ret_val = e1000e_config_fc_after_link_up(hw);
1593 if (ret_val) {
1594 e_dbg("Error config flow control\n");
1595 break;
1596 }
1597 mac->serdes_link_state =
1598 e1000_serdes_link_forced_up;
1599 mac->serdes_has_link = true;
1600 e_dbg("AN_PROG -> FORCED_UP\n");
1601 }
1602 break;
1603
1604 case e1000_serdes_link_down:
1605 default:
1606
1607
1608
1609
1610 ew32(TXCW, mac->txcw);
1611 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1612 mac->serdes_link_state =
1613 e1000_serdes_link_autoneg_progress;
1614 mac->serdes_has_link = false;
1615 e_dbg("DOWN -> AN_PROG\n");
1616 break;
1617 }
1618 } else {
1619 if (!(rxcw & E1000_RXCW_SYNCH)) {
1620 mac->serdes_has_link = false;
1621 mac->serdes_link_state = e1000_serdes_link_down;
1622 e_dbg("ANYSTATE -> DOWN\n");
1623 } else {
1624
1625
1626
1627
1628 for (i = 0; i < AN_RETRY_COUNT; i++) {
1629 usleep_range(10, 20);
1630 rxcw = er32(RXCW);
1631 if ((rxcw & E1000_RXCW_SYNCH) &&
1632 (rxcw & E1000_RXCW_C))
1633 continue;
1634
1635 if (rxcw & E1000_RXCW_IV) {
1636 mac->serdes_has_link = false;
1637 mac->serdes_link_state =
1638 e1000_serdes_link_down;
1639 e_dbg("ANYSTATE -> DOWN\n");
1640 break;
1641 }
1642 }
1643
1644 if (i == AN_RETRY_COUNT) {
1645 txcw = er32(TXCW);
1646 txcw |= E1000_TXCW_ANE;
1647 ew32(TXCW, txcw);
1648 mac->serdes_link_state =
1649 e1000_serdes_link_autoneg_progress;
1650 mac->serdes_has_link = false;
1651 e_dbg("ANYSTATE -> AN_PROG\n");
1652 }
1653 }
1654 }
1655
1656 return ret_val;
1657}
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1668{
1669 s32 ret_val;
1670
1671 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1672 if (ret_val) {
1673 e_dbg("NVM Read Error\n");
1674 return ret_val;
1675 }
1676
1677 switch (hw->mac.type) {
1678 case e1000_82573:
1679 case e1000_82574:
1680 case e1000_82583:
1681 if (*data == ID_LED_RESERVED_F746)
1682 *data = ID_LED_DEFAULT_82573;
1683 break;
1684 default:
1685 if (*data == ID_LED_RESERVED_0000 ||
1686 *data == ID_LED_RESERVED_FFFF)
1687 *data = ID_LED_DEFAULT;
1688 break;
1689 }
1690
1691 return 0;
1692}
1693
1694
1695
1696
1697
1698
1699
1700bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1701{
1702 if (hw->mac.type != e1000_82571)
1703 return false;
1704
1705 return hw->dev_spec.e82571.laa_is_present;
1706}
1707
1708
1709
1710
1711
1712
1713
1714
1715void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1716{
1717 if (hw->mac.type != e1000_82571)
1718 return;
1719
1720 hw->dev_spec.e82571.laa_is_present = state;
1721
1722
1723 if (state)
1724
1725
1726
1727
1728
1729
1730 hw->mac.ops.rar_set(hw, hw->mac.addr,
1731 hw->mac.rar_entry_count - 1);
1732}
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1745{
1746 struct e1000_nvm_info *nvm = &hw->nvm;
1747 s32 ret_val;
1748 u16 data;
1749
1750 if (nvm->type != e1000_nvm_flash_hw)
1751 return 0;
1752
1753
1754
1755
1756 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1757 if (ret_val)
1758 return ret_val;
1759
1760 if (!(data & 0x10)) {
1761
1762
1763
1764
1765
1766
1767
1768 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1769 if (ret_val)
1770 return ret_val;
1771
1772 if (!(data & 0x8000)) {
1773 data |= 0x8000;
1774 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1775 if (ret_val)
1776 return ret_val;
1777 ret_val = e1000e_update_nvm_checksum(hw);
1778 if (ret_val)
1779 return ret_val;
1780 }
1781 }
1782
1783 return 0;
1784}
1785
1786
1787
1788
1789
1790static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1791{
1792 if (hw->mac.type == e1000_82571) {
1793 s32 ret_val;
1794
1795
1796
1797
1798
1799 ret_val = e1000_check_alt_mac_addr_generic(hw);
1800 if (ret_val)
1801 return ret_val;
1802 }
1803
1804 return e1000_read_mac_addr_generic(hw);
1805}
1806
1807
1808
1809
1810
1811
1812
1813
1814static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1815{
1816 struct e1000_phy_info *phy = &hw->phy;
1817 struct e1000_mac_info *mac = &hw->mac;
1818
1819 if (!phy->ops.check_reset_block)
1820 return;
1821
1822
1823 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1824 e1000_power_down_phy_copper(hw);
1825}
1826
1827
1828
1829
1830
1831
1832
1833static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1834{
1835 e1000e_clear_hw_cntrs_base(hw);
1836
1837 er32(PRC64);
1838 er32(PRC127);
1839 er32(PRC255);
1840 er32(PRC511);
1841 er32(PRC1023);
1842 er32(PRC1522);
1843 er32(PTC64);
1844 er32(PTC127);
1845 er32(PTC255);
1846 er32(PTC511);
1847 er32(PTC1023);
1848 er32(PTC1522);
1849
1850 er32(ALGNERRC);
1851 er32(RXERRC);
1852 er32(TNCRS);
1853 er32(CEXTERR);
1854 er32(TSCTC);
1855 er32(TSCTFC);
1856
1857 er32(MGTPRC);
1858 er32(MGTPDC);
1859 er32(MGTPTC);
1860
1861 er32(IAC);
1862 er32(ICRXOC);
1863
1864 er32(ICRXPTC);
1865 er32(ICRXATC);
1866 er32(ICTXPTC);
1867 er32(ICTXATC);
1868 er32(ICTXQEC);
1869 er32(ICTXQMTC);
1870 er32(ICRXDMTC);
1871}
1872
1873static const struct e1000_mac_operations e82571_mac_ops = {
1874
1875
1876 .id_led_init = e1000e_id_led_init_generic,
1877 .cleanup_led = e1000e_cleanup_led_generic,
1878 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1879 .get_bus_info = e1000e_get_bus_info_pcie,
1880 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1881
1882
1883 .led_off = e1000e_led_off_generic,
1884 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1885 .write_vfta = e1000_write_vfta_generic,
1886 .clear_vfta = e1000_clear_vfta_82571,
1887 .reset_hw = e1000_reset_hw_82571,
1888 .init_hw = e1000_init_hw_82571,
1889 .setup_link = e1000_setup_link_82571,
1890
1891 .setup_led = e1000e_setup_led_generic,
1892 .config_collision_dist = e1000e_config_collision_dist_generic,
1893 .read_mac_addr = e1000_read_mac_addr_82571,
1894 .rar_set = e1000e_rar_set_generic,
1895 .rar_get_count = e1000e_rar_get_count_generic,
1896};
1897
1898static const struct e1000_phy_operations e82_phy_ops_igp = {
1899 .acquire = e1000_get_hw_semaphore_82571,
1900 .check_polarity = e1000_check_polarity_igp,
1901 .check_reset_block = e1000e_check_reset_block_generic,
1902 .commit = NULL,
1903 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1904 .get_cfg_done = e1000_get_cfg_done_82571,
1905 .get_cable_length = e1000e_get_cable_length_igp_2,
1906 .get_info = e1000e_get_phy_info_igp,
1907 .read_reg = e1000e_read_phy_reg_igp,
1908 .release = e1000_put_hw_semaphore_82571,
1909 .reset = e1000e_phy_hw_reset_generic,
1910 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1911 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1912 .write_reg = e1000e_write_phy_reg_igp,
1913 .cfg_on_link_up = NULL,
1914};
1915
1916static const struct e1000_phy_operations e82_phy_ops_m88 = {
1917 .acquire = e1000_get_hw_semaphore_82571,
1918 .check_polarity = e1000_check_polarity_m88,
1919 .check_reset_block = e1000e_check_reset_block_generic,
1920 .commit = e1000e_phy_sw_reset,
1921 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1922 .get_cfg_done = e1000e_get_cfg_done_generic,
1923 .get_cable_length = e1000e_get_cable_length_m88,
1924 .get_info = e1000e_get_phy_info_m88,
1925 .read_reg = e1000e_read_phy_reg_m88,
1926 .release = e1000_put_hw_semaphore_82571,
1927 .reset = e1000e_phy_hw_reset_generic,
1928 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1929 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1930 .write_reg = e1000e_write_phy_reg_m88,
1931 .cfg_on_link_up = NULL,
1932};
1933
1934static const struct e1000_phy_operations e82_phy_ops_bm = {
1935 .acquire = e1000_get_hw_semaphore_82571,
1936 .check_polarity = e1000_check_polarity_m88,
1937 .check_reset_block = e1000e_check_reset_block_generic,
1938 .commit = e1000e_phy_sw_reset,
1939 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1940 .get_cfg_done = e1000e_get_cfg_done_generic,
1941 .get_cable_length = e1000e_get_cable_length_m88,
1942 .get_info = e1000e_get_phy_info_m88,
1943 .read_reg = e1000e_read_phy_reg_bm2,
1944 .release = e1000_put_hw_semaphore_82571,
1945 .reset = e1000e_phy_hw_reset_generic,
1946 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1947 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1948 .write_reg = e1000e_write_phy_reg_bm2,
1949 .cfg_on_link_up = NULL,
1950};
1951
1952static const struct e1000_nvm_operations e82571_nvm_ops = {
1953 .acquire = e1000_acquire_nvm_82571,
1954 .read = e1000e_read_nvm_eerd,
1955 .release = e1000_release_nvm_82571,
1956 .reload = e1000e_reload_nvm_generic,
1957 .update = e1000_update_nvm_checksum_82571,
1958 .valid_led_default = e1000_valid_led_default_82571,
1959 .validate = e1000_validate_nvm_checksum_82571,
1960 .write = e1000_write_nvm_82571,
1961};
1962
1963const struct e1000_info e1000_82571_info = {
1964 .mac = e1000_82571,
1965 .flags = FLAG_HAS_HW_VLAN_FILTER
1966 | FLAG_HAS_JUMBO_FRAMES
1967 | FLAG_HAS_WOL
1968 | FLAG_APME_IN_CTRL3
1969 | FLAG_HAS_CTRLEXT_ON_LOAD
1970 | FLAG_HAS_SMART_POWER_DOWN
1971 | FLAG_RESET_OVERWRITES_LAA
1972 | FLAG_TARC_SPEED_MODE_BIT
1973 | FLAG_APME_CHECK_PORT_B,
1974 .flags2 = FLAG2_DISABLE_ASPM_L1
1975 | FLAG2_DMA_BURST,
1976 .pba = 38,
1977 .max_hw_frame_size = DEFAULT_JUMBO,
1978 .get_variants = e1000_get_variants_82571,
1979 .mac_ops = &e82571_mac_ops,
1980 .phy_ops = &e82_phy_ops_igp,
1981 .nvm_ops = &e82571_nvm_ops,
1982};
1983
1984const struct e1000_info e1000_82572_info = {
1985 .mac = e1000_82572,
1986 .flags = FLAG_HAS_HW_VLAN_FILTER
1987 | FLAG_HAS_JUMBO_FRAMES
1988 | FLAG_HAS_WOL
1989 | FLAG_APME_IN_CTRL3
1990 | FLAG_HAS_CTRLEXT_ON_LOAD
1991 | FLAG_TARC_SPEED_MODE_BIT,
1992 .flags2 = FLAG2_DISABLE_ASPM_L1
1993 | FLAG2_DMA_BURST,
1994 .pba = 38,
1995 .max_hw_frame_size = DEFAULT_JUMBO,
1996 .get_variants = e1000_get_variants_82571,
1997 .mac_ops = &e82571_mac_ops,
1998 .phy_ops = &e82_phy_ops_igp,
1999 .nvm_ops = &e82571_nvm_ops,
2000};
2001
2002const struct e1000_info e1000_82573_info = {
2003 .mac = e1000_82573,
2004 .flags = FLAG_HAS_HW_VLAN_FILTER
2005 | FLAG_HAS_WOL
2006 | FLAG_APME_IN_CTRL3
2007 | FLAG_HAS_SMART_POWER_DOWN
2008 | FLAG_HAS_AMT
2009 | FLAG_HAS_SWSM_ON_LOAD,
2010 .flags2 = FLAG2_DISABLE_ASPM_L1
2011 | FLAG2_DISABLE_ASPM_L0S,
2012 .pba = 20,
2013 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2014 .get_variants = e1000_get_variants_82571,
2015 .mac_ops = &e82571_mac_ops,
2016 .phy_ops = &e82_phy_ops_m88,
2017 .nvm_ops = &e82571_nvm_ops,
2018};
2019
2020const struct e1000_info e1000_82574_info = {
2021 .mac = e1000_82574,
2022 .flags = FLAG_HAS_HW_VLAN_FILTER
2023 | FLAG_HAS_MSIX
2024 | FLAG_HAS_JUMBO_FRAMES
2025 | FLAG_HAS_WOL
2026 | FLAG_HAS_HW_TIMESTAMP
2027 | FLAG_APME_IN_CTRL3
2028 | FLAG_HAS_SMART_POWER_DOWN
2029 | FLAG_HAS_AMT
2030 | FLAG_HAS_CTRLEXT_ON_LOAD,
2031 .flags2 = FLAG2_CHECK_PHY_HANG
2032 | FLAG2_DISABLE_ASPM_L0S
2033 | FLAG2_DISABLE_ASPM_L1
2034 | FLAG2_NO_DISABLE_RX
2035 | FLAG2_DMA_BURST,
2036 .pba = 32,
2037 .max_hw_frame_size = DEFAULT_JUMBO,
2038 .get_variants = e1000_get_variants_82571,
2039 .mac_ops = &e82571_mac_ops,
2040 .phy_ops = &e82_phy_ops_bm,
2041 .nvm_ops = &e82571_nvm_ops,
2042};
2043
2044const struct e1000_info e1000_82583_info = {
2045 .mac = e1000_82583,
2046 .flags = FLAG_HAS_HW_VLAN_FILTER
2047 | FLAG_HAS_WOL
2048 | FLAG_HAS_HW_TIMESTAMP
2049 | FLAG_APME_IN_CTRL3
2050 | FLAG_HAS_SMART_POWER_DOWN
2051 | FLAG_HAS_AMT
2052 | FLAG_HAS_JUMBO_FRAMES
2053 | FLAG_HAS_CTRLEXT_ON_LOAD,
2054 .flags2 = FLAG2_DISABLE_ASPM_L0S
2055 | FLAG2_DISABLE_ASPM_L1
2056 | FLAG2_NO_DISABLE_RX,
2057 .pba = 32,
2058 .max_hw_frame_size = DEFAULT_JUMBO,
2059 .get_variants = e1000_get_variants_82571,
2060 .mac_ops = &e82571_mac_ops,
2061 .phy_ops = &e82_phy_ops_bm,
2062 .nvm_ops = &e82571_nvm_ops,
2063};
2064