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22#ifndef _E1000_DEFINES_H_
23#define _E1000_DEFINES_H_
24
25
26#define REQ_TX_DESCRIPTOR_MULTIPLE 8
27#define REQ_RX_DESCRIPTOR_MULTIPLE 8
28
29
30
31#define E1000_WUC_APME 0x00000001
32#define E1000_WUC_PME_EN 0x00000002
33#define E1000_WUC_PME_STATUS 0x00000004
34#define E1000_WUC_APMPME 0x00000008
35#define E1000_WUC_PHY_WAKE 0x00000100
36
37
38#define E1000_WUFC_LNKC 0x00000001
39#define E1000_WUFC_MAG 0x00000002
40#define E1000_WUFC_EX 0x00000004
41#define E1000_WUFC_MC 0x00000008
42#define E1000_WUFC_BC 0x00000010
43#define E1000_WUFC_ARP 0x00000020
44
45
46#define E1000_WUS_LNKC E1000_WUFC_LNKC
47#define E1000_WUS_MAG E1000_WUFC_MAG
48#define E1000_WUS_EX E1000_WUFC_EX
49#define E1000_WUS_MC E1000_WUFC_MC
50#define E1000_WUS_BC E1000_WUFC_BC
51
52
53#define E1000_CTRL_EXT_LPCD 0x00000004
54#define E1000_CTRL_EXT_SDP3_DATA 0x00000080
55#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800
56#define E1000_CTRL_EXT_EE_RST 0x00002000
57#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
58#define E1000_CTRL_EXT_RO_DIS 0x00020000
59#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000
60#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
61#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
62#define E1000_CTRL_EXT_EIAME 0x01000000
63#define E1000_CTRL_EXT_DRV_LOAD 0x10000000
64#define E1000_CTRL_EXT_IAME 0x08000000
65#define E1000_CTRL_EXT_PBA_CLR 0x80000000
66#define E1000_CTRL_EXT_LSECCK 0x00001000
67#define E1000_CTRL_EXT_PHYPDEN 0x00100000
68
69
70#define E1000_RXD_STAT_DD 0x01
71#define E1000_RXD_STAT_EOP 0x02
72#define E1000_RXD_STAT_IXSM 0x04
73#define E1000_RXD_STAT_VP 0x08
74#define E1000_RXD_STAT_UDPCS 0x10
75#define E1000_RXD_STAT_TCPCS 0x20
76#define E1000_RXD_ERR_CE 0x01
77#define E1000_RXD_ERR_SE 0x02
78#define E1000_RXD_ERR_SEQ 0x04
79#define E1000_RXD_ERR_CXE 0x10
80#define E1000_RXD_ERR_TCPE 0x20
81#define E1000_RXD_ERR_IPE 0x40
82#define E1000_RXD_ERR_RXE 0x80
83#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
84
85#define E1000_RXDEXT_STATERR_TST 0x00000100
86#define E1000_RXDEXT_STATERR_CE 0x01000000
87#define E1000_RXDEXT_STATERR_SE 0x02000000
88#define E1000_RXDEXT_STATERR_SEQ 0x04000000
89#define E1000_RXDEXT_STATERR_CXE 0x10000000
90#define E1000_RXDEXT_STATERR_RXE 0x80000000
91
92
93#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
94 E1000_RXD_ERR_CE | \
95 E1000_RXD_ERR_SE | \
96 E1000_RXD_ERR_SEQ | \
97 E1000_RXD_ERR_CXE | \
98 E1000_RXD_ERR_RXE)
99
100
101#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
102 E1000_RXDEXT_STATERR_CE | \
103 E1000_RXDEXT_STATERR_SE | \
104 E1000_RXDEXT_STATERR_SEQ | \
105 E1000_RXDEXT_STATERR_CXE | \
106 E1000_RXDEXT_STATERR_RXE)
107
108#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
109#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
110#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
111#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
112#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
113#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
114
115#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
116
117
118#define E1000_MANC_SMBUS_EN 0x00000001
119#define E1000_MANC_ASF_EN 0x00000002
120#define E1000_MANC_ARP_EN 0x00002000
121#define E1000_MANC_RCV_TCO_EN 0x00020000
122#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
123
124#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
125
126#define E1000_MANC_EN_MNG2HOST 0x00200000
127
128#define E1000_MANC2H_PORT_623 0x00000020
129#define E1000_MANC2H_PORT_664 0x00000040
130#define E1000_MDEF_PORT_623 0x00000800
131#define E1000_MDEF_PORT_664 0x00000400
132
133
134#define E1000_RCTL_EN 0x00000002
135#define E1000_RCTL_SBP 0x00000004
136#define E1000_RCTL_UPE 0x00000008
137#define E1000_RCTL_MPE 0x00000010
138#define E1000_RCTL_LPE 0x00000020
139#define E1000_RCTL_LBM_NO 0x00000000
140#define E1000_RCTL_LBM_MAC 0x00000040
141#define E1000_RCTL_LBM_TCVR 0x000000C0
142#define E1000_RCTL_DTYP_PS 0x00000400
143#define E1000_RCTL_RDMTS_HALF 0x00000000
144#define E1000_RCTL_MO_SHIFT 12
145#define E1000_RCTL_MO_3 0x00003000
146#define E1000_RCTL_BAM 0x00008000
147
148#define E1000_RCTL_SZ_2048 0x00000000
149#define E1000_RCTL_SZ_1024 0x00010000
150#define E1000_RCTL_SZ_512 0x00020000
151#define E1000_RCTL_SZ_256 0x00030000
152
153#define E1000_RCTL_SZ_16384 0x00010000
154#define E1000_RCTL_SZ_8192 0x00020000
155#define E1000_RCTL_SZ_4096 0x00030000
156#define E1000_RCTL_VFE 0x00040000
157#define E1000_RCTL_CFIEN 0x00080000
158#define E1000_RCTL_CFI 0x00100000
159#define E1000_RCTL_DPF 0x00400000
160#define E1000_RCTL_PMCF 0x00800000
161#define E1000_RCTL_BSEX 0x02000000
162#define E1000_RCTL_SECRC 0x04000000
163
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179
180#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
181#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
182#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
183#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
184
185#define E1000_PSRCTL_BSIZE0_SHIFT 7
186#define E1000_PSRCTL_BSIZE1_SHIFT 2
187#define E1000_PSRCTL_BSIZE2_SHIFT 6
188#define E1000_PSRCTL_BSIZE3_SHIFT 14
189
190
191#define E1000_SWFW_EEP_SM 0x1
192#define E1000_SWFW_PHY0_SM 0x2
193#define E1000_SWFW_PHY1_SM 0x4
194#define E1000_SWFW_CSR_SM 0x8
195
196
197#define E1000_CTRL_FD 0x00000001
198#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
199#define E1000_CTRL_LRST 0x00000008
200#define E1000_CTRL_ASDE 0x00000020
201#define E1000_CTRL_SLU 0x00000040
202#define E1000_CTRL_ILOS 0x00000080
203#define E1000_CTRL_SPD_SEL 0x00000300
204#define E1000_CTRL_SPD_10 0x00000000
205#define E1000_CTRL_SPD_100 0x00000100
206#define E1000_CTRL_SPD_1000 0x00000200
207#define E1000_CTRL_FRCSPD 0x00000800
208#define E1000_CTRL_FRCDPX 0x00001000
209#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000
210#define E1000_CTRL_LANPHYPC_VALUE 0x00020000
211#define E1000_CTRL_MEHE 0x00080000
212#define E1000_CTRL_SWDPIN0 0x00040000
213#define E1000_CTRL_SWDPIN1 0x00080000
214#define E1000_CTRL_ADVD3WUC 0x00100000
215#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
216#define E1000_CTRL_SWDPIO0 0x00400000
217#define E1000_CTRL_RST 0x04000000
218#define E1000_CTRL_RFCE 0x08000000
219#define E1000_CTRL_TFCE 0x10000000
220#define E1000_CTRL_VME 0x40000000
221#define E1000_CTRL_PHY_RST 0x80000000
222
223#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
224
225#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
226
227
228#define E1000_STATUS_FD 0x00000001
229#define E1000_STATUS_LU 0x00000002
230#define E1000_STATUS_FUNC_MASK 0x0000000C
231#define E1000_STATUS_FUNC_SHIFT 2
232#define E1000_STATUS_FUNC_1 0x00000004
233#define E1000_STATUS_TXOFF 0x00000010
234#define E1000_STATUS_SPEED_MASK 0x000000C0
235#define E1000_STATUS_SPEED_10 0x00000000
236#define E1000_STATUS_SPEED_100 0x00000040
237#define E1000_STATUS_SPEED_1000 0x00000080
238#define E1000_STATUS_LAN_INIT_DONE 0x00000200
239#define E1000_STATUS_PHYRA 0x00000400
240#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
241
242#define HALF_DUPLEX 1
243#define FULL_DUPLEX 2
244
245#define ADVERTISE_10_HALF 0x0001
246#define ADVERTISE_10_FULL 0x0002
247#define ADVERTISE_100_HALF 0x0004
248#define ADVERTISE_100_FULL 0x0008
249#define ADVERTISE_1000_HALF 0x0010
250#define ADVERTISE_1000_FULL 0x0020
251
252
253#define E1000_ALL_SPEED_DUPLEX ( \
254 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
255 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
256#define E1000_ALL_NOT_GIG ( \
257 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
258 ADVERTISE_100_FULL)
259#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
260#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
261#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
262
263#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
264
265
266#define E1000_PHY_LED0_MODE_MASK 0x00000007
267#define E1000_PHY_LED0_IVRT 0x00000008
268#define E1000_PHY_LED0_MASK 0x0000001F
269
270#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
271#define E1000_LEDCTL_LED0_MODE_SHIFT 0
272#define E1000_LEDCTL_LED0_IVRT 0x00000040
273#define E1000_LEDCTL_LED0_BLINK 0x00000080
274
275#define E1000_LEDCTL_MODE_LINK_UP 0x2
276#define E1000_LEDCTL_MODE_LED_ON 0xE
277#define E1000_LEDCTL_MODE_LED_OFF 0xF
278
279
280#define E1000_TXD_DTYP_D 0x00100000
281#define E1000_TXD_POPTS_IXSM 0x01
282#define E1000_TXD_POPTS_TXSM 0x02
283#define E1000_TXD_CMD_EOP 0x01000000
284#define E1000_TXD_CMD_IFCS 0x02000000
285#define E1000_TXD_CMD_IC 0x04000000
286#define E1000_TXD_CMD_RS 0x08000000
287#define E1000_TXD_CMD_RPS 0x10000000
288#define E1000_TXD_CMD_DEXT 0x20000000
289#define E1000_TXD_CMD_VLE 0x40000000
290#define E1000_TXD_CMD_IDE 0x80000000
291#define E1000_TXD_STAT_DD 0x00000001
292#define E1000_TXD_STAT_EC 0x00000002
293#define E1000_TXD_STAT_LC 0x00000004
294#define E1000_TXD_STAT_TU 0x00000008
295#define E1000_TXD_CMD_TCP 0x01000000
296#define E1000_TXD_CMD_IP 0x02000000
297#define E1000_TXD_CMD_TSE 0x04000000
298#define E1000_TXD_STAT_TC 0x00000004
299#define E1000_TXD_EXTCMD_TSTAMP 0x00000010
300
301
302#define E1000_TCTL_EN 0x00000002
303#define E1000_TCTL_PSP 0x00000008
304#define E1000_TCTL_CT 0x00000ff0
305#define E1000_TCTL_COLD 0x003ff000
306#define E1000_TCTL_RTLC 0x01000000
307#define E1000_TCTL_MULR 0x10000000
308
309
310#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
311#define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
312
313
314#define E1000_RXCSUM_TUOFL 0x00000200
315#define E1000_RXCSUM_IPPCSE 0x00001000
316#define E1000_RXCSUM_PCSD 0x00002000
317
318
319#define E1000_RFCTL_NFSW_DIS 0x00000040
320#define E1000_RFCTL_NFSR_DIS 0x00000080
321#define E1000_RFCTL_ACK_DIS 0x00001000
322#define E1000_RFCTL_EXTEN 0x00008000
323#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
324#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
325
326
327#define E1000_COLLISION_THRESHOLD 15
328#define E1000_CT_SHIFT 4
329#define E1000_COLLISION_DISTANCE 63
330#define E1000_COLD_SHIFT 12
331
332
333#define DEFAULT_82543_TIPG_IPGT_COPPER 8
334
335#define E1000_TIPG_IPGT_MASK 0x000003FF
336
337#define DEFAULT_82543_TIPG_IPGR1 8
338#define E1000_TIPG_IPGR1_SHIFT 10
339
340#define DEFAULT_82543_TIPG_IPGR2 6
341#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
342#define E1000_TIPG_IPGR2_SHIFT 20
343
344#define MAX_JUMBO_FRAME_SIZE 0x3F00
345#define E1000_TX_PTR_GAP 0x1F
346
347
348#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
349#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
350#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
351#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
352#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
353#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
354#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
355#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
356#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
357
358#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
359#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
360#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
361#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
362
363#define E1000_KABGTXD_BGSQLBIAS 0x00050000
364
365
366#define E1000_LPIC_LPIET_SHIFT 24
367
368
369#define E1000_PBA_8K 0x0008
370#define E1000_PBA_16K 0x0010
371
372#define E1000_PBA_RXA_MASK 0xFFFF
373
374#define E1000_PBS_16K E1000_PBA_16K
375
376
377#define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
378#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
379#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8
380#define E1000_PBECCSTS_ECC_ENABLE 0x00010000
381
382#define IFS_MAX 80
383#define IFS_MIN 40
384#define IFS_RATIO 4
385#define IFS_STEP 10
386#define MIN_NUM_XMITS 1000
387
388
389#define E1000_SWSM_SMBI 0x00000001
390#define E1000_SWSM_SWESMBI 0x00000002
391#define E1000_SWSM_DRV_LOAD 0x00000008
392
393#define E1000_SWSM2_LOCK 0x00000002
394
395
396#define E1000_ICR_TXDW 0x00000001
397#define E1000_ICR_LSC 0x00000004
398#define E1000_ICR_RXSEQ 0x00000008
399#define E1000_ICR_RXDMT0 0x00000010
400#define E1000_ICR_RXT0 0x00000080
401#define E1000_ICR_ECCER 0x00400000
402
403#define E1000_ICR_INT_ASSERTED 0x80000000
404#define E1000_ICR_RXQ0 0x00100000
405#define E1000_ICR_RXQ1 0x00200000
406#define E1000_ICR_TXQ0 0x00400000
407#define E1000_ICR_TXQ1 0x00800000
408#define E1000_ICR_OTHER 0x01000000
409
410
411#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000
412#define E1000_PBA_ECC_COUNTER_SHIFT 20
413#define E1000_PBA_ECC_CORR_EN 0x00000001
414#define E1000_PBA_ECC_STAT_CLR 0x00000002
415#define E1000_PBA_ECC_INT_EN 0x00000004
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422
423
424
425#define IMS_ENABLE_MASK ( \
426 E1000_IMS_RXT0 | \
427 E1000_IMS_TXDW | \
428 E1000_IMS_RXDMT0 | \
429 E1000_IMS_RXSEQ | \
430 E1000_IMS_LSC)
431
432
433#define E1000_IMS_TXDW E1000_ICR_TXDW
434#define E1000_IMS_LSC E1000_ICR_LSC
435#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
436#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
437#define E1000_IMS_RXT0 E1000_ICR_RXT0
438#define E1000_IMS_ECCER E1000_ICR_ECCER
439#define E1000_IMS_RXQ0 E1000_ICR_RXQ0
440#define E1000_IMS_RXQ1 E1000_ICR_RXQ1
441#define E1000_IMS_TXQ0 E1000_ICR_TXQ0
442#define E1000_IMS_TXQ1 E1000_ICR_TXQ1
443#define E1000_IMS_OTHER E1000_ICR_OTHER
444
445
446#define E1000_ICS_LSC E1000_ICR_LSC
447#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
448#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
449
450
451#define E1000_TXDCTL_PTHRESH 0x0000003F
452#define E1000_TXDCTL_HTHRESH 0x00003F00
453#define E1000_TXDCTL_WTHRESH 0x003F0000
454#define E1000_TXDCTL_GRAN 0x01000000
455#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
456#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F
457
458#define E1000_TXDCTL_COUNT_DESC 0x00400000
459
460
461#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
462#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
463#define FLOW_CONTROL_TYPE 0x8808
464
465
466#define E1000_VLAN_FILTER_TBL_SIZE 128
467
468
469
470
471
472
473
474
475#define E1000_RAR_ENTRIES 15
476#define E1000_RAH_AV 0x80000000
477#define E1000_RAL_MAC_ADDR_LEN 4
478#define E1000_RAH_MAC_ADDR_LEN 2
479
480
481#define E1000_ERR_NVM 1
482#define E1000_ERR_PHY 2
483#define E1000_ERR_CONFIG 3
484#define E1000_ERR_PARAM 4
485#define E1000_ERR_MAC_INIT 5
486#define E1000_ERR_PHY_TYPE 6
487#define E1000_ERR_RESET 9
488#define E1000_ERR_MASTER_REQUESTS_PENDING 10
489#define E1000_ERR_HOST_INTERFACE_COMMAND 11
490#define E1000_BLK_PHY_RESET 12
491#define E1000_ERR_SWFW_SYNC 13
492#define E1000_NOT_IMPLEMENTED 14
493#define E1000_ERR_INVALID_ARGUMENT 16
494#define E1000_ERR_NO_SPACE 17
495#define E1000_ERR_NVM_PBA_SECTION 18
496
497
498#define FIBER_LINK_UP_LIMIT 50
499#define COPPER_LINK_UP_LIMIT 10
500#define PHY_AUTO_NEG_LIMIT 45
501#define PHY_FORCE_LIMIT 20
502
503#define MASTER_DISABLE_TIMEOUT 800
504
505#define PHY_CFG_TIMEOUT 100
506
507#define MDIO_OWNERSHIP_TIMEOUT 10
508
509#define AUTO_READ_DONE_TIMEOUT 10
510
511
512#define E1000_FCRTH_RTH 0x0000FFF8
513#define E1000_FCRTL_RTL 0x0000FFF8
514#define E1000_FCRTL_XONE 0x80000000
515
516
517#define E1000_TXCW_FD 0x00000020
518#define E1000_TXCW_PAUSE 0x00000080
519#define E1000_TXCW_ASM_DIR 0x00000100
520#define E1000_TXCW_PAUSE_MASK 0x00000180
521#define E1000_TXCW_ANE 0x80000000
522
523
524#define E1000_RXCW_CW 0x0000ffff
525#define E1000_RXCW_IV 0x08000000
526#define E1000_RXCW_C 0x20000000
527#define E1000_RXCW_SYNCH 0x40000000
528
529#define E1000_TSYNCTXCTL_VALID 0x00000001
530#define E1000_TSYNCTXCTL_ENABLED 0x00000010
531
532#define E1000_TSYNCRXCTL_VALID 0x00000001
533#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E
534#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
535#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
536#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
537#define E1000_TSYNCRXCTL_TYPE_ALL 0x08
538#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
539#define E1000_TSYNCRXCTL_ENABLED 0x00000010
540#define E1000_TSYNCRXCTL_SYSCFI 0x00000020
541
542#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
543#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
544
545#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
546#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
547
548#define E1000_TIMINCA_INCPERIOD_SHIFT 24
549#define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
550
551
552#define E1000_GCR_RXD_NO_SNOOP 0x00000001
553#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
554#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
555#define E1000_GCR_TXD_NO_SNOOP 0x00000008
556#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
557#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
558
559#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
560 E1000_GCR_RXDSCW_NO_SNOOP | \
561 E1000_GCR_RXDSCR_NO_SNOOP | \
562 E1000_GCR_TXD_NO_SNOOP | \
563 E1000_GCR_TXDSCW_NO_SNOOP | \
564 E1000_GCR_TXDSCR_NO_SNOOP)
565
566
567#define E1000_EECD_SK 0x00000001
568#define E1000_EECD_CS 0x00000002
569#define E1000_EECD_DI 0x00000004
570#define E1000_EECD_DO 0x00000008
571#define E1000_EECD_REQ 0x00000040
572#define E1000_EECD_GNT 0x00000080
573#define E1000_EECD_PRES 0x00000100
574#define E1000_EECD_SIZE 0x00000200
575
576#define E1000_EECD_ADDR_BITS 0x00000400
577#define E1000_NVM_GRANT_ATTEMPTS 1000
578#define E1000_EECD_AUTO_RD 0x00000200
579#define E1000_EECD_SIZE_EX_MASK 0x00007800
580#define E1000_EECD_SIZE_EX_SHIFT 11
581#define E1000_EECD_FLUPD 0x00080000
582#define E1000_EECD_AUPDEN 0x00100000
583#define E1000_EECD_SEC1VAL 0x00400000
584#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
585
586#define E1000_NVM_RW_REG_DATA 16
587#define E1000_NVM_RW_REG_DONE 2
588#define E1000_NVM_RW_REG_START 1
589#define E1000_NVM_RW_ADDR_SHIFT 2
590#define E1000_NVM_POLL_WRITE 1
591#define E1000_NVM_POLL_READ 0
592#define E1000_FLASH_UPDATES 2000
593
594
595#define NVM_COMPAT 0x0003
596#define NVM_ID_LED_SETTINGS 0x0004
597#define NVM_FUTURE_INIT_WORD1 0x0019
598#define NVM_COMPAT_VALID_CSUM 0x0001
599#define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
600
601#define NVM_INIT_CONTROL2_REG 0x000F
602#define NVM_INIT_CONTROL3_PORT_B 0x0014
603#define NVM_INIT_3GIO_3 0x001A
604#define NVM_INIT_CONTROL3_PORT_A 0x0024
605#define NVM_CFG 0x0012
606#define NVM_ALT_MAC_ADDR_PTR 0x0037
607#define NVM_CHECKSUM_REG 0x003F
608
609#define E1000_NVM_CFG_DONE_PORT_0 0x40000
610#define E1000_NVM_CFG_DONE_PORT_1 0x80000
611
612
613#define NVM_WORD0F_PAUSE_MASK 0x3000
614#define NVM_WORD0F_PAUSE 0x1000
615#define NVM_WORD0F_ASM_DIR 0x2000
616
617
618#define NVM_WORD1A_ASPM_MASK 0x000C
619
620
621#define NVM_COMPAT_LOM 0x0800
622
623
624#define E1000_PBANUM_LENGTH 11
625
626
627#define NVM_SUM 0xBABA
628
629
630#define NVM_PBA_OFFSET_0 8
631#define NVM_PBA_OFFSET_1 9
632#define NVM_PBA_PTR_GUARD 0xFAFA
633#define NVM_WORD_SIZE_BASE_SHIFT 6
634
635
636#define NVM_MAX_RETRY_SPI 5000
637#define NVM_READ_OPCODE_SPI 0x03
638#define NVM_WRITE_OPCODE_SPI 0x02
639#define NVM_A8_OPCODE_SPI 0x08
640#define NVM_WREN_OPCODE_SPI 0x06
641#define NVM_RDSR_OPCODE_SPI 0x05
642
643
644#define NVM_STATUS_RDY_SPI 0x01
645
646
647#define ID_LED_RESERVED_0000 0x0000
648#define ID_LED_RESERVED_FFFF 0xFFFF
649#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
650 (ID_LED_OFF1_OFF2 << 8) | \
651 (ID_LED_DEF1_DEF2 << 4) | \
652 (ID_LED_DEF1_DEF2))
653#define ID_LED_DEF1_DEF2 0x1
654#define ID_LED_DEF1_ON2 0x2
655#define ID_LED_DEF1_OFF2 0x3
656#define ID_LED_ON1_DEF2 0x4
657#define ID_LED_ON1_ON2 0x5
658#define ID_LED_ON1_OFF2 0x6
659#define ID_LED_OFF1_DEF2 0x7
660#define ID_LED_OFF1_ON2 0x8
661#define ID_LED_OFF1_OFF2 0x9
662
663#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
664#define IGP_ACTIVITY_LED_ENABLE 0x0300
665#define IGP_LED3_MODE 0x07000000
666
667
668#define PCI_HEADER_TYPE_REGISTER 0x0E
669#define PCIE_LINK_STATUS 0x12
670
671#define PCI_HEADER_TYPE_MULTIFUNC 0x80
672#define PCIE_LINK_WIDTH_MASK 0x3F0
673#define PCIE_LINK_WIDTH_SHIFT 4
674
675#define PHY_REVISION_MASK 0xFFFFFFF0
676#define MAX_PHY_REG_ADDRESS 0x1F
677#define MAX_PHY_MULTI_PAGE_REG 0xF
678
679
680
681
682
683#define M88E1000_E_PHY_ID 0x01410C50
684#define M88E1000_I_PHY_ID 0x01410C30
685#define M88E1011_I_PHY_ID 0x01410C20
686#define IGP01E1000_I_PHY_ID 0x02A80380
687#define M88E1111_I_PHY_ID 0x01410CC0
688#define GG82563_E_PHY_ID 0x01410CA0
689#define IGP03E1000_E_PHY_ID 0x02A80390
690#define IFE_E_PHY_ID 0x02A80330
691#define IFE_PLUS_E_PHY_ID 0x02A80320
692#define IFE_C_E_PHY_ID 0x02A80310
693#define BME1000_E_PHY_ID 0x01410CB0
694#define BME1000_E_PHY_ID_R2 0x01410CB1
695#define I82577_E_PHY_ID 0x01540050
696#define I82578_E_PHY_ID 0x004DD040
697#define I82579_E_PHY_ID 0x01540090
698#define I217_E_PHY_ID 0x015400A0
699
700
701#define M88E1000_PHY_SPEC_CTRL 0x10
702#define M88E1000_PHY_SPEC_STATUS 0x11
703#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
704
705#define M88E1000_PHY_PAGE_SELECT 0x1D
706#define M88E1000_PHY_GEN_CONTROL 0x1E
707
708
709#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
710#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
711
712#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
713
714#define M88E1000_PSCR_AUTO_X_1000T 0x0040
715
716#define M88E1000_PSCR_AUTO_X_MODE 0x0060
717#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
718
719
720#define M88E1000_PSSR_REV_POLARITY 0x0002
721#define M88E1000_PSSR_DOWNSHIFT 0x0020
722#define M88E1000_PSSR_MDIX 0x0040
723
724#define M88E1000_PSSR_CABLE_LENGTH 0x0380
725#define M88E1000_PSSR_SPEED 0xC000
726#define M88E1000_PSSR_1000MBS 0x8000
727
728#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
729
730
731
732
733#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
734#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
735
736
737
738#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
739#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
740#define M88E1000_EPSCR_TX_CLK_25 0x0070
741
742
743#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
744#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
745
746#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
747#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
748
749
750#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800
751
752
753
754
755
756#define GG82563_PAGE_SHIFT 5
757#define GG82563_REG(page, reg) \
758 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
759#define GG82563_MIN_ALT_REG 30
760
761
762#define GG82563_PHY_SPEC_CTRL \
763 GG82563_REG(0, 16)
764#define GG82563_PHY_PAGE_SELECT \
765 GG82563_REG(0, 22)
766#define GG82563_PHY_SPEC_CTRL_2 \
767 GG82563_REG(0, 26)
768#define GG82563_PHY_PAGE_SELECT_ALT \
769 GG82563_REG(0, 29)
770
771#define GG82563_PHY_MAC_SPEC_CTRL \
772 GG82563_REG(2, 21)
773
774#define GG82563_PHY_DSP_DISTANCE \
775 GG82563_REG(5, 26)
776
777
778#define GG82563_PHY_KMRN_MODE_CTRL \
779 GG82563_REG(193, 16)
780#define GG82563_PHY_PWR_MGMT_CTRL \
781 GG82563_REG(193, 20)
782
783
784#define GG82563_PHY_INBAND_CTRL \
785 GG82563_REG(194, 18)
786
787
788#define E1000_MDIC_REG_MASK 0x001F0000
789#define E1000_MDIC_REG_SHIFT 16
790#define E1000_MDIC_PHY_SHIFT 21
791#define E1000_MDIC_OP_WRITE 0x04000000
792#define E1000_MDIC_OP_READ 0x08000000
793#define E1000_MDIC_READY 0x10000000
794#define E1000_MDIC_ERROR 0x40000000
795
796
797#define E1000_GEN_POLL_TIMEOUT 640
798
799#endif
800