linux/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
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   1/*
   2 * QLogic qlcnic NIC Driver
   3 * Copyright (c) 2009-2013 QLogic Corporation
   4 *
   5 * See LICENSE.qlcnic for copyright and licensing details.
   6 */
   7
   8#include "qlcnic.h"
   9#include "qlcnic_hdr.h"
  10
  11#include <linux/slab.h>
  12#include <net/ip.h>
  13#include <linux/bitops.h>
  14
  15#define MASK(n) ((1ULL<<(n))-1)
  16#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  17
  18#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  19
  20#define CRB_BLK(off)    ((off >> 20) & 0x3f)
  21#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  22#define CRB_WINDOW_2M   (0x130060)
  23#define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  24#define CRB_INDIRECT_2M (0x1e0000UL)
  25
  26struct qlcnic_ms_reg_ctrl {
  27        u32 ocm_window;
  28        u32 control;
  29        u32 hi;
  30        u32 low;
  31        u32 rd[4];
  32        u32 wd[4];
  33        u64 off;
  34};
  35
  36#ifndef readq
  37static inline u64 readq(void __iomem *addr)
  38{
  39        return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  40}
  41#endif
  42
  43#ifndef writeq
  44static inline void writeq(u64 val, void __iomem *addr)
  45{
  46        writel(((u32) (val)), (addr));
  47        writel(((u32) (val >> 32)), (addr + 4));
  48}
  49#endif
  50
  51static struct crb_128M_2M_block_map
  52crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  53    {{{0, 0,         0,         0} } },         /* 0: PCI */
  54    {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  55          {1, 0x0110000, 0x0120000, 0x130000},
  56          {1, 0x0120000, 0x0122000, 0x124000},
  57          {1, 0x0130000, 0x0132000, 0x126000},
  58          {1, 0x0140000, 0x0142000, 0x128000},
  59          {1, 0x0150000, 0x0152000, 0x12a000},
  60          {1, 0x0160000, 0x0170000, 0x110000},
  61          {1, 0x0170000, 0x0172000, 0x12e000},
  62          {0, 0x0000000, 0x0000000, 0x000000},
  63          {0, 0x0000000, 0x0000000, 0x000000},
  64          {0, 0x0000000, 0x0000000, 0x000000},
  65          {0, 0x0000000, 0x0000000, 0x000000},
  66          {0, 0x0000000, 0x0000000, 0x000000},
  67          {0, 0x0000000, 0x0000000, 0x000000},
  68          {1, 0x01e0000, 0x01e0800, 0x122000},
  69          {0, 0x0000000, 0x0000000, 0x000000} } },
  70        {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  71    {{{0, 0,         0,         0} } },     /* 3: */
  72    {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  73    {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  74    {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  75    {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  76    {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  77      {0, 0x0000000, 0x0000000, 0x000000},
  78      {0, 0x0000000, 0x0000000, 0x000000},
  79      {0, 0x0000000, 0x0000000, 0x000000},
  80      {0, 0x0000000, 0x0000000, 0x000000},
  81      {0, 0x0000000, 0x0000000, 0x000000},
  82      {0, 0x0000000, 0x0000000, 0x000000},
  83      {0, 0x0000000, 0x0000000, 0x000000},
  84      {0, 0x0000000, 0x0000000, 0x000000},
  85      {0, 0x0000000, 0x0000000, 0x000000},
  86      {0, 0x0000000, 0x0000000, 0x000000},
  87      {0, 0x0000000, 0x0000000, 0x000000},
  88      {0, 0x0000000, 0x0000000, 0x000000},
  89      {0, 0x0000000, 0x0000000, 0x000000},
  90      {0, 0x0000000, 0x0000000, 0x000000},
  91      {1, 0x08f0000, 0x08f2000, 0x172000} } },
  92    {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  93      {0, 0x0000000, 0x0000000, 0x000000},
  94      {0, 0x0000000, 0x0000000, 0x000000},
  95      {0, 0x0000000, 0x0000000, 0x000000},
  96      {0, 0x0000000, 0x0000000, 0x000000},
  97      {0, 0x0000000, 0x0000000, 0x000000},
  98      {0, 0x0000000, 0x0000000, 0x000000},
  99      {0, 0x0000000, 0x0000000, 0x000000},
 100      {0, 0x0000000, 0x0000000, 0x000000},
 101      {0, 0x0000000, 0x0000000, 0x000000},
 102      {0, 0x0000000, 0x0000000, 0x000000},
 103      {0, 0x0000000, 0x0000000, 0x000000},
 104      {0, 0x0000000, 0x0000000, 0x000000},
 105      {0, 0x0000000, 0x0000000, 0x000000},
 106      {0, 0x0000000, 0x0000000, 0x000000},
 107      {1, 0x09f0000, 0x09f2000, 0x176000} } },
 108    {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 109      {0, 0x0000000, 0x0000000, 0x000000},
 110      {0, 0x0000000, 0x0000000, 0x000000},
 111      {0, 0x0000000, 0x0000000, 0x000000},
 112      {0, 0x0000000, 0x0000000, 0x000000},
 113      {0, 0x0000000, 0x0000000, 0x000000},
 114      {0, 0x0000000, 0x0000000, 0x000000},
 115      {0, 0x0000000, 0x0000000, 0x000000},
 116      {0, 0x0000000, 0x0000000, 0x000000},
 117      {0, 0x0000000, 0x0000000, 0x000000},
 118      {0, 0x0000000, 0x0000000, 0x000000},
 119      {0, 0x0000000, 0x0000000, 0x000000},
 120      {0, 0x0000000, 0x0000000, 0x000000},
 121      {0, 0x0000000, 0x0000000, 0x000000},
 122      {0, 0x0000000, 0x0000000, 0x000000},
 123      {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 124    {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 125      {0, 0x0000000, 0x0000000, 0x000000},
 126      {0, 0x0000000, 0x0000000, 0x000000},
 127      {0, 0x0000000, 0x0000000, 0x000000},
 128      {0, 0x0000000, 0x0000000, 0x000000},
 129      {0, 0x0000000, 0x0000000, 0x000000},
 130      {0, 0x0000000, 0x0000000, 0x000000},
 131      {0, 0x0000000, 0x0000000, 0x000000},
 132      {0, 0x0000000, 0x0000000, 0x000000},
 133      {0, 0x0000000, 0x0000000, 0x000000},
 134      {0, 0x0000000, 0x0000000, 0x000000},
 135      {0, 0x0000000, 0x0000000, 0x000000},
 136      {0, 0x0000000, 0x0000000, 0x000000},
 137      {0, 0x0000000, 0x0000000, 0x000000},
 138      {0, 0x0000000, 0x0000000, 0x000000},
 139      {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 140        {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 141        {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 142        {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 143        {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 144        {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 145        {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 146        {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 147        {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 148        {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 149        {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 150        {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 151        {{{0, 0,         0,         0} } },     /* 23: */
 152        {{{0, 0,         0,         0} } },     /* 24: */
 153        {{{0, 0,         0,         0} } },     /* 25: */
 154        {{{0, 0,         0,         0} } },     /* 26: */
 155        {{{0, 0,         0,         0} } },     /* 27: */
 156        {{{0, 0,         0,         0} } },     /* 28: */
 157        {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 158    {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 159    {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 160        {{{0} } },                              /* 32: PCI */
 161        {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 162          {1, 0x2110000, 0x2120000, 0x130000},
 163          {1, 0x2120000, 0x2122000, 0x124000},
 164          {1, 0x2130000, 0x2132000, 0x126000},
 165          {1, 0x2140000, 0x2142000, 0x128000},
 166          {1, 0x2150000, 0x2152000, 0x12a000},
 167          {1, 0x2160000, 0x2170000, 0x110000},
 168          {1, 0x2170000, 0x2172000, 0x12e000},
 169          {0, 0x0000000, 0x0000000, 0x000000},
 170          {0, 0x0000000, 0x0000000, 0x000000},
 171          {0, 0x0000000, 0x0000000, 0x000000},
 172          {0, 0x0000000, 0x0000000, 0x000000},
 173          {0, 0x0000000, 0x0000000, 0x000000},
 174          {0, 0x0000000, 0x0000000, 0x000000},
 175          {0, 0x0000000, 0x0000000, 0x000000},
 176          {0, 0x0000000, 0x0000000, 0x000000} } },
 177        {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 178        {{{0} } },                              /* 35: */
 179        {{{0} } },                              /* 36: */
 180        {{{0} } },                              /* 37: */
 181        {{{0} } },                              /* 38: */
 182        {{{0} } },                              /* 39: */
 183        {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 184        {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 185        {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 186        {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 187        {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 188        {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 189        {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 190        {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 191        {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 192        {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 193        {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 194        {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 195        {{{0} } },                              /* 52: */
 196        {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 197        {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 198        {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 199        {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 200        {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 201        {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 202        {{{0} } },                              /* 59: I2C0 */
 203        {{{0} } },                              /* 60: I2C1 */
 204        {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 205        {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 206        {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 207};
 208
 209/*
 210 * top 12 bits of crb internal address (hub, agent)
 211 */
 212static const unsigned crb_hub_agt[64] = {
 213        0,
 214        QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 215        QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 216        QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 217        0,
 218        QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 219        QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 220        QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 221        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 222        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 223        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 224        QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 225        QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 226        QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 227        QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 228        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 229        QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 230        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 231        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 232        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 233        QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 234        QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 235        QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 236        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 237        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 238        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 239        QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 240        0,
 241        QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 242        QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 243        0,
 244        QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 245        0,
 246        QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 247        QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 248        0,
 249        0,
 250        0,
 251        0,
 252        0,
 253        QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 254        0,
 255        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 256        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 257        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 258        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 259        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 260        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 261        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 262        QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 263        QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 264        QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 265        0,
 266        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 267        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 268        QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 269        QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 270        0,
 271        QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 272        QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 273        QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 274        0,
 275        QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 276        0,
 277};
 278
 279static const u32 msi_tgt_status[8] = {
 280        ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
 281        ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
 282        ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
 283        ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
 284};
 285
 286/*  PCI Windowing for DDR regions.  */
 287
 288#define QLCNIC_PCIE_SEM_TIMEOUT 10000
 289
 290static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
 291{
 292        u32 dest;
 293        void __iomem *val;
 294
 295        dest = addr & 0xFFFF0000;
 296        val = bar0 + QLCNIC_FW_DUMP_REG1;
 297        writel(dest, val);
 298        readl(val);
 299        val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 300        *data = readl(val);
 301}
 302
 303static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
 304{
 305        u32 dest;
 306        void __iomem *val;
 307
 308        dest = addr & 0xFFFF0000;
 309        val = bar0 + QLCNIC_FW_DUMP_REG1;
 310        writel(dest, val);
 311        readl(val);
 312        val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 313        writel(data, val);
 314        readl(val);
 315}
 316
 317int
 318qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 319{
 320        int timeout = 0, err = 0, done = 0;
 321
 322        while (!done) {
 323                done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
 324                               &err);
 325                if (done == 1)
 326                        break;
 327                if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 328                        if (id_reg) {
 329                                done = QLCRD32(adapter, id_reg, &err);
 330                                if (done != -1)
 331                                        dev_err(&adapter->pdev->dev,
 332                                                "Failed to acquire sem=%d lock held by=%d\n",
 333                                                sem, done);
 334                                else
 335                                        dev_err(&adapter->pdev->dev,
 336                                                "Failed to acquire sem=%d lock",
 337                                                sem);
 338                        } else {
 339                                dev_err(&adapter->pdev->dev,
 340                                        "Failed to acquire sem=%d lock", sem);
 341                        }
 342                        return -EIO;
 343                }
 344                usleep_range(1000, 1500);
 345        }
 346
 347        if (id_reg)
 348                QLCWR32(adapter, id_reg, adapter->portnum);
 349
 350        return 0;
 351}
 352
 353void
 354qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 355{
 356        int err = 0;
 357
 358        QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
 359}
 360
 361int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
 362{
 363        int err = 0;
 364        u32 data;
 365
 366        if (qlcnic_82xx_check(adapter))
 367                qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
 368        else {
 369                data = QLCRD32(adapter, addr, &err);
 370                if (err == -EIO)
 371                        return err;
 372        }
 373        return data;
 374}
 375
 376int qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
 377{
 378        int ret = 0;
 379
 380        if (qlcnic_82xx_check(adapter))
 381                qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
 382        else
 383                ret = qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
 384
 385        return ret;
 386}
 387
 388static int
 389qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 390                struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 391{
 392        u32 i, producer;
 393        struct qlcnic_cmd_buffer *pbuf;
 394        struct cmd_desc_type0 *cmd_desc;
 395        struct qlcnic_host_tx_ring *tx_ring;
 396
 397        i = 0;
 398
 399        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 400                return -EIO;
 401
 402        tx_ring = &adapter->tx_ring[0];
 403        __netif_tx_lock_bh(tx_ring->txq);
 404
 405        producer = tx_ring->producer;
 406
 407        if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 408                netif_tx_stop_queue(tx_ring->txq);
 409                smp_mb();
 410                if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 411                        if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 412                                netif_tx_wake_queue(tx_ring->txq);
 413                } else {
 414                        adapter->stats.xmit_off++;
 415                        __netif_tx_unlock_bh(tx_ring->txq);
 416                        return -EBUSY;
 417                }
 418        }
 419
 420        do {
 421                cmd_desc = &cmd_desc_arr[i];
 422
 423                pbuf = &tx_ring->cmd_buf_arr[producer];
 424                pbuf->skb = NULL;
 425                pbuf->frag_count = 0;
 426
 427                memcpy(&tx_ring->desc_head[producer],
 428                       cmd_desc, sizeof(struct cmd_desc_type0));
 429
 430                producer = get_next_index(producer, tx_ring->num_desc);
 431                i++;
 432
 433        } while (i != nr_desc);
 434
 435        tx_ring->producer = producer;
 436
 437        qlcnic_update_cmd_producer(tx_ring);
 438
 439        __netif_tx_unlock_bh(tx_ring->txq);
 440
 441        return 0;
 442}
 443
 444int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 445                                   u16 vlan_id, u8 op)
 446{
 447        struct qlcnic_nic_req req;
 448        struct qlcnic_mac_req *mac_req;
 449        struct qlcnic_vlan_req *vlan_req;
 450        u64 word;
 451
 452        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 453        req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 454
 455        word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 456        req.req_hdr = cpu_to_le64(word);
 457
 458        mac_req = (struct qlcnic_mac_req *)&req.words[0];
 459        mac_req->op = op;
 460        memcpy(mac_req->mac_addr, addr, ETH_ALEN);
 461
 462        vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 463        vlan_req->vlan_id = cpu_to_le16(vlan_id);
 464
 465        return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 466}
 467
 468int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 469{
 470        struct qlcnic_mac_vlan_list *cur;
 471        struct list_head *head;
 472        int err = -EINVAL;
 473
 474        /* Delete MAC from the existing list */
 475        list_for_each(head, &adapter->mac_list) {
 476                cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 477                if (ether_addr_equal(addr, cur->mac_addr)) {
 478                        err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 479                                                        0, QLCNIC_MAC_DEL);
 480                        if (err)
 481                                return err;
 482                        list_del(&cur->list);
 483                        kfree(cur);
 484                        return err;
 485                }
 486        }
 487        return err;
 488}
 489
 490int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan,
 491                       enum qlcnic_mac_type mac_type)
 492{
 493        struct qlcnic_mac_vlan_list *cur;
 494        struct list_head *head;
 495
 496        /* look up if already exists */
 497        list_for_each(head, &adapter->mac_list) {
 498                cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 499                if (ether_addr_equal(addr, cur->mac_addr) &&
 500                    cur->vlan_id == vlan)
 501                        return 0;
 502        }
 503
 504        cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
 505        if (cur == NULL)
 506                return -ENOMEM;
 507
 508        memcpy(cur->mac_addr, addr, ETH_ALEN);
 509
 510        if (qlcnic_sre_macaddr_change(adapter,
 511                                cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
 512                kfree(cur);
 513                return -EIO;
 514        }
 515
 516        cur->vlan_id = vlan;
 517        cur->mac_type = mac_type;
 518
 519        list_add_tail(&cur->list, &adapter->mac_list);
 520        return 0;
 521}
 522
 523void qlcnic_flush_mcast_mac(struct qlcnic_adapter *adapter)
 524{
 525        struct qlcnic_mac_vlan_list *cur;
 526        struct list_head *head, *tmp;
 527
 528        list_for_each_safe(head, tmp, &adapter->mac_list) {
 529                cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 530                if (cur->mac_type != QLCNIC_MULTICAST_MAC)
 531                        continue;
 532
 533                qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 534                                          cur->vlan_id, QLCNIC_MAC_DEL);
 535                list_del(&cur->list);
 536                kfree(cur);
 537        }
 538}
 539
 540static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
 541{
 542        struct qlcnic_adapter *adapter = netdev_priv(netdev);
 543        struct qlcnic_hardware_context *ahw = adapter->ahw;
 544        struct netdev_hw_addr *ha;
 545        static const u8 bcast_addr[ETH_ALEN] = {
 546                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 547        };
 548        u32 mode = VPORT_MISS_MODE_DROP;
 549
 550        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 551                return;
 552
 553        qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan,
 554                           QLCNIC_UNICAST_MAC);
 555        qlcnic_nic_add_mac(adapter, bcast_addr, vlan, QLCNIC_BROADCAST_MAC);
 556
 557        if (netdev->flags & IFF_PROMISC) {
 558                if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 559                        mode = VPORT_MISS_MODE_ACCEPT_ALL;
 560        } else if ((netdev->flags & IFF_ALLMULTI) ||
 561                   (netdev_mc_count(netdev) > ahw->max_mc_count)) {
 562                mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 563        } else if (!netdev_mc_empty(netdev)) {
 564                qlcnic_flush_mcast_mac(adapter);
 565                netdev_for_each_mc_addr(ha, netdev)
 566                        qlcnic_nic_add_mac(adapter, ha->addr, vlan,
 567                                           QLCNIC_MULTICAST_MAC);
 568        }
 569
 570        /* configure unicast MAC address, if there is not sufficient space
 571         * to store all the unicast addresses then enable promiscuous mode
 572         */
 573        if (netdev_uc_count(netdev) > ahw->max_uc_count) {
 574                mode = VPORT_MISS_MODE_ACCEPT_ALL;
 575        } else if (!netdev_uc_empty(netdev)) {
 576                netdev_for_each_uc_addr(ha, netdev)
 577                        qlcnic_nic_add_mac(adapter, ha->addr, vlan,
 578                                           QLCNIC_UNICAST_MAC);
 579        }
 580
 581        if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
 582            !adapter->fdb_mac_learn) {
 583                qlcnic_alloc_lb_filters_mem(adapter);
 584                adapter->drv_mac_learn = 1;
 585                if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
 586                        adapter->rx_mac_learn = true;
 587        } else {
 588                adapter->drv_mac_learn = 0;
 589                adapter->rx_mac_learn = false;
 590        }
 591
 592        qlcnic_nic_set_promisc(adapter, mode);
 593}
 594
 595void qlcnic_set_multi(struct net_device *netdev)
 596{
 597        struct qlcnic_adapter *adapter = netdev_priv(netdev);
 598
 599        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 600                return;
 601
 602        if (qlcnic_sriov_vf_check(adapter))
 603                qlcnic_sriov_vf_set_multi(netdev);
 604        else
 605                __qlcnic_set_multi(netdev, 0);
 606}
 607
 608int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 609{
 610        struct qlcnic_nic_req req;
 611        u64 word;
 612
 613        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 614
 615        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 616
 617        word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
 618                        ((u64)adapter->portnum << 16);
 619        req.req_hdr = cpu_to_le64(word);
 620
 621        req.words[0] = cpu_to_le64(mode);
 622
 623        return qlcnic_send_cmd_descs(adapter,
 624                                (struct cmd_desc_type0 *)&req, 1);
 625}
 626
 627void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
 628{
 629        struct list_head *head = &adapter->mac_list;
 630        struct qlcnic_mac_vlan_list *cur;
 631
 632        while (!list_empty(head)) {
 633                cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
 634                qlcnic_sre_macaddr_change(adapter,
 635                                cur->mac_addr, 0, QLCNIC_MAC_DEL);
 636                list_del(&cur->list);
 637                kfree(cur);
 638        }
 639}
 640
 641void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 642{
 643        struct qlcnic_filter *tmp_fil;
 644        struct hlist_node *n;
 645        struct hlist_head *head;
 646        int i;
 647        unsigned long expires;
 648        u8 cmd;
 649
 650        for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 651                head = &(adapter->fhash.fhead[i]);
 652                hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 653                        cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 654                                                  QLCNIC_MAC_DEL;
 655                        expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
 656                        if (time_before(expires, jiffies)) {
 657                                qlcnic_sre_macaddr_change(adapter,
 658                                                          tmp_fil->faddr,
 659                                                          tmp_fil->vlan_id,
 660                                                          cmd);
 661                                spin_lock_bh(&adapter->mac_learn_lock);
 662                                adapter->fhash.fnum--;
 663                                hlist_del(&tmp_fil->fnode);
 664                                spin_unlock_bh(&adapter->mac_learn_lock);
 665                                kfree(tmp_fil);
 666                        }
 667                }
 668        }
 669        for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
 670                head = &(adapter->rx_fhash.fhead[i]);
 671
 672                hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
 673                {
 674                        expires = tmp_fil->ftime + QLCNIC_FILTER_AGE * HZ;
 675                        if (time_before(expires, jiffies)) {
 676                                spin_lock_bh(&adapter->rx_mac_learn_lock);
 677                                adapter->rx_fhash.fnum--;
 678                                hlist_del(&tmp_fil->fnode);
 679                                spin_unlock_bh(&adapter->rx_mac_learn_lock);
 680                                kfree(tmp_fil);
 681                        }
 682                }
 683        }
 684}
 685
 686void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 687{
 688        struct qlcnic_filter *tmp_fil;
 689        struct hlist_node *n;
 690        struct hlist_head *head;
 691        int i;
 692        u8 cmd;
 693
 694        for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 695                head = &(adapter->fhash.fhead[i]);
 696                hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 697                        cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 698                                                  QLCNIC_MAC_DEL;
 699                        qlcnic_sre_macaddr_change(adapter,
 700                                                  tmp_fil->faddr,
 701                                                  tmp_fil->vlan_id,
 702                                                  cmd);
 703                        spin_lock_bh(&adapter->mac_learn_lock);
 704                        adapter->fhash.fnum--;
 705                        hlist_del(&tmp_fil->fnode);
 706                        spin_unlock_bh(&adapter->mac_learn_lock);
 707                        kfree(tmp_fil);
 708                }
 709        }
 710}
 711
 712static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
 713{
 714        struct qlcnic_nic_req req;
 715        int rv;
 716
 717        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 718
 719        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 720        req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
 721                ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
 722
 723        req.words[0] = cpu_to_le64(flag);
 724
 725        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 726        if (rv != 0)
 727                dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
 728                                flag ? "Set" : "Reset");
 729        return rv;
 730}
 731
 732int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 733{
 734        if (qlcnic_set_fw_loopback(adapter, mode))
 735                return -EIO;
 736
 737        if (qlcnic_nic_set_promisc(adapter,
 738                                   VPORT_MISS_MODE_ACCEPT_ALL)) {
 739                qlcnic_set_fw_loopback(adapter, 0);
 740                return -EIO;
 741        }
 742
 743        msleep(1000);
 744        return 0;
 745}
 746
 747int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 748{
 749        struct net_device *netdev = adapter->netdev;
 750
 751        mode = VPORT_MISS_MODE_DROP;
 752        qlcnic_set_fw_loopback(adapter, 0);
 753
 754        if (netdev->flags & IFF_PROMISC)
 755                mode = VPORT_MISS_MODE_ACCEPT_ALL;
 756        else if (netdev->flags & IFF_ALLMULTI)
 757                mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 758
 759        qlcnic_nic_set_promisc(adapter, mode);
 760        msleep(1000);
 761        return 0;
 762}
 763
 764int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
 765{
 766        u8 mac[ETH_ALEN];
 767        int ret;
 768
 769        ret = qlcnic_get_mac_address(adapter, mac,
 770                                     adapter->ahw->physical_port);
 771        if (ret)
 772                return ret;
 773
 774        memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
 775        adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
 776
 777        return 0;
 778}
 779
 780int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter)
 781{
 782        struct qlcnic_nic_req req;
 783        int rv;
 784
 785        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 786
 787        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 788
 789        req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
 790                ((u64) adapter->portnum << 16));
 791
 792        req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
 793        req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
 794                        ((u64) adapter->ahw->coal.rx_time_us) << 16);
 795        req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
 796                        ((u64) adapter->ahw->coal.type) << 32 |
 797                        ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
 798        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 799        if (rv != 0)
 800                dev_err(&adapter->netdev->dev,
 801                        "Could not send interrupt coalescing parameters\n");
 802
 803        return rv;
 804}
 805
 806/* Send the interrupt coalescing parameter set by ethtool to the card. */
 807int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter,
 808                                     struct ethtool_coalesce *ethcoal)
 809{
 810        struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
 811        int rv;
 812
 813        coal->flag = QLCNIC_INTR_DEFAULT;
 814        coal->rx_time_us = ethcoal->rx_coalesce_usecs;
 815        coal->rx_packets = ethcoal->rx_max_coalesced_frames;
 816
 817        rv = qlcnic_82xx_set_rx_coalesce(adapter);
 818
 819        if (rv)
 820                netdev_err(adapter->netdev,
 821                           "Failed to set Rx coalescing parametrs\n");
 822
 823        return rv;
 824}
 825
 826#define QLCNIC_ENABLE_IPV4_LRO          BIT_0
 827#define QLCNIC_ENABLE_IPV6_LRO          (BIT_1 | BIT_9)
 828
 829int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 830{
 831        struct qlcnic_nic_req req;
 832        u64 word;
 833        int rv;
 834
 835        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 836                return 0;
 837
 838        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 839
 840        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 841
 842        word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 843        req.req_hdr = cpu_to_le64(word);
 844
 845        word = 0;
 846        if (enable) {
 847                word = QLCNIC_ENABLE_IPV4_LRO;
 848                if (adapter->ahw->extra_capability[0] &
 849                    QLCNIC_FW_CAP2_HW_LRO_IPV6)
 850                        word |= QLCNIC_ENABLE_IPV6_LRO;
 851        }
 852
 853        req.words[0] = cpu_to_le64(word);
 854
 855        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 856        if (rv != 0)
 857                dev_err(&adapter->netdev->dev,
 858                        "Could not send configure hw lro request\n");
 859
 860        return rv;
 861}
 862
 863int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 864{
 865        struct qlcnic_nic_req req;
 866        u64 word;
 867        int rv;
 868
 869        if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 870                return 0;
 871
 872        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 873
 874        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 875
 876        word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 877                ((u64)adapter->portnum << 16);
 878        req.req_hdr = cpu_to_le64(word);
 879
 880        req.words[0] = cpu_to_le64(enable);
 881
 882        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 883        if (rv != 0)
 884                dev_err(&adapter->netdev->dev,
 885                        "Could not send configure bridge mode request\n");
 886
 887        adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 888
 889        return rv;
 890}
 891
 892
 893#define QLCNIC_RSS_HASHTYPE_IP_TCP      0x3
 894#define QLCNIC_ENABLE_TYPE_C_RSS        BIT_10
 895#define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
 896#define QLCNIC_RSS_IND_TABLE_MASK       0x7ULL
 897
 898int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
 899{
 900        struct qlcnic_nic_req req;
 901        u64 word;
 902        int i, rv;
 903
 904        static const u64 key[] = {
 905                0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 906                0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 907                0x255b0ec26d5a56daULL
 908        };
 909
 910        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 911        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 912
 913        word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 914        req.req_hdr = cpu_to_le64(word);
 915
 916        /*
 917         * RSS request:
 918         * bits 3-0: hash_method
 919         *      5-4: hash_type_ipv4
 920         *      7-6: hash_type_ipv6
 921         *        8: enable
 922         *        9: use indirection table
 923         *       10: type-c rss
 924         *       11: udp rss
 925         *    47-12: reserved
 926         *    62-48: indirection table mask
 927         *       63: feature flag
 928         */
 929        word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 930                ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 931                ((u64)(enable & 0x1) << 8) |
 932                ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
 933                (u64)QLCNIC_ENABLE_TYPE_C_RSS |
 934                (u64)QLCNIC_RSS_FEATURE_FLAG;
 935
 936        req.words[0] = cpu_to_le64(word);
 937        for (i = 0; i < 5; i++)
 938                req.words[i+1] = cpu_to_le64(key[i]);
 939
 940        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 941        if (rv != 0)
 942                dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 943
 944        return rv;
 945}
 946
 947void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
 948                               __be32 ip, int cmd)
 949{
 950        struct qlcnic_nic_req req;
 951        struct qlcnic_ipaddr *ipa;
 952        u64 word;
 953        int rv;
 954
 955        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 956        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 957
 958        word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 959        req.req_hdr = cpu_to_le64(word);
 960
 961        req.words[0] = cpu_to_le64(cmd);
 962        ipa = (struct qlcnic_ipaddr *)&req.words[1];
 963        ipa->ipv4 = ip;
 964
 965        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 966        if (rv != 0)
 967                dev_err(&adapter->netdev->dev,
 968                                "could not notify %s IP 0x%x request\n",
 969                                (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 970}
 971
 972int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 973{
 974        struct qlcnic_nic_req req;
 975        u64 word;
 976        int rv;
 977        memset(&req, 0, sizeof(struct qlcnic_nic_req));
 978        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 979
 980        word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 981        req.req_hdr = cpu_to_le64(word);
 982        req.words[0] = cpu_to_le64(enable | (enable << 8));
 983        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 984        if (rv != 0)
 985                dev_err(&adapter->netdev->dev,
 986                                "could not configure link notification\n");
 987
 988        return rv;
 989}
 990
 991static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 992{
 993        struct qlcnic_nic_req req;
 994        u64 word;
 995        int rv;
 996
 997        if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 998                return 0;
 999
1000        memset(&req, 0, sizeof(struct qlcnic_nic_req));
1001        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1002
1003        word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
1004                ((u64)adapter->portnum << 16) |
1005                ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
1006
1007        req.req_hdr = cpu_to_le64(word);
1008
1009        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1010        if (rv != 0)
1011                dev_err(&adapter->netdev->dev,
1012                                 "could not cleanup lro flows\n");
1013
1014        return rv;
1015}
1016
1017/*
1018 * qlcnic_change_mtu - Change the Maximum Transfer Unit
1019 * @returns 0 on success, negative on failure
1020 */
1021
1022int qlcnic_change_mtu(struct net_device *netdev, int mtu)
1023{
1024        struct qlcnic_adapter *adapter = netdev_priv(netdev);
1025        int rc = 0;
1026
1027        if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
1028                dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
1029                        " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
1030                return -EINVAL;
1031        }
1032
1033        rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
1034
1035        if (!rc)
1036                netdev->mtu = mtu;
1037
1038        return rc;
1039}
1040
1041static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1042                                              netdev_features_t features)
1043{
1044        u32 offload_flags = adapter->offload_flags;
1045
1046        if (offload_flags & BIT_0) {
1047                features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1048                            NETIF_F_IPV6_CSUM;
1049                adapter->rx_csum = 1;
1050                if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1051                        if (!(offload_flags & BIT_1))
1052                                features &= ~NETIF_F_TSO;
1053                        else
1054                                features |= NETIF_F_TSO;
1055
1056                        if (!(offload_flags & BIT_2))
1057                                features &= ~NETIF_F_TSO6;
1058                        else
1059                                features |= NETIF_F_TSO6;
1060                }
1061        } else {
1062                features &= ~(NETIF_F_RXCSUM |
1063                              NETIF_F_IP_CSUM |
1064                              NETIF_F_IPV6_CSUM);
1065
1066                if (QLCNIC_IS_TSO_CAPABLE(adapter))
1067                        features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1068                adapter->rx_csum = 0;
1069        }
1070
1071        return features;
1072}
1073
1074netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1075        netdev_features_t features)
1076{
1077        struct qlcnic_adapter *adapter = netdev_priv(netdev);
1078        netdev_features_t changed;
1079
1080        if (qlcnic_82xx_check(adapter) &&
1081            (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1082                if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1083                        features = qlcnic_process_flags(adapter, features);
1084                } else {
1085                        changed = features ^ netdev->features;
1086                        features ^= changed & (NETIF_F_RXCSUM |
1087                                               NETIF_F_IP_CSUM |
1088                                               NETIF_F_IPV6_CSUM |
1089                                               NETIF_F_TSO |
1090                                               NETIF_F_TSO6);
1091                }
1092        }
1093
1094        if (!(features & NETIF_F_RXCSUM))
1095                features &= ~NETIF_F_LRO;
1096
1097        return features;
1098}
1099
1100
1101int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1102{
1103        struct qlcnic_adapter *adapter = netdev_priv(netdev);
1104        netdev_features_t changed = netdev->features ^ features;
1105        int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1106
1107        if (!(changed & NETIF_F_LRO))
1108                return 0;
1109
1110        netdev->features ^= NETIF_F_LRO;
1111
1112        if (qlcnic_config_hw_lro(adapter, hw_lro))
1113                return -EIO;
1114
1115        if (!hw_lro && qlcnic_82xx_check(adapter)) {
1116                if (qlcnic_send_lro_cleanup(adapter))
1117                        return -EIO;
1118        }
1119
1120        return 0;
1121}
1122
1123/*
1124 * Changes the CRB window to the specified window.
1125 */
1126 /* Returns < 0 if off is not valid,
1127 *       1 if window access is needed. 'off' is set to offset from
1128 *         CRB space in 128M pci map
1129 *       0 if no window access is needed. 'off' is set to 2M addr
1130 * In: 'off' is offset from base in 128M pci map
1131 */
1132static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1133                                      ulong off, void __iomem **addr)
1134{
1135        const struct crb_128M_2M_sub_block_map *m;
1136
1137        if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1138                return -EINVAL;
1139
1140        off -= QLCNIC_PCI_CRBSPACE;
1141
1142        /*
1143         * Try direct map
1144         */
1145        m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1146
1147        if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1148                *addr = ahw->pci_base0 + m->start_2M +
1149                        (off - m->start_128M);
1150                return 0;
1151        }
1152
1153        /*
1154         * Not in direct map, use crb window
1155         */
1156        *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1157        return 1;
1158}
1159
1160/*
1161 * In: 'off' is offset from CRB space in 128M pci map
1162 * Out: 'off' is 2M pci map addr
1163 * side effect: lock crb window
1164 */
1165static int
1166qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1167{
1168        u32 window;
1169        void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1170
1171        off -= QLCNIC_PCI_CRBSPACE;
1172
1173        window = CRB_HI(off);
1174        if (window == 0) {
1175                dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1176                return -EIO;
1177        }
1178
1179        writel(window, addr);
1180        if (readl(addr) != window) {
1181                if (printk_ratelimit())
1182                        dev_warn(&adapter->pdev->dev,
1183                                "failed to set CRB window to %d off 0x%lx\n",
1184                                window, off);
1185                return -EIO;
1186        }
1187        return 0;
1188}
1189
1190int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1191                               u32 data)
1192{
1193        unsigned long flags;
1194        int rv;
1195        void __iomem *addr = NULL;
1196
1197        rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1198
1199        if (rv == 0) {
1200                writel(data, addr);
1201                return 0;
1202        }
1203
1204        if (rv > 0) {
1205                /* indirect access */
1206                write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1207                crb_win_lock(adapter);
1208                rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1209                if (!rv)
1210                        writel(data, addr);
1211                crb_win_unlock(adapter);
1212                write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1213                return rv;
1214        }
1215
1216        dev_err(&adapter->pdev->dev,
1217                        "%s: invalid offset: 0x%016lx\n", __func__, off);
1218        dump_stack();
1219        return -EIO;
1220}
1221
1222int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1223                              int *err)
1224{
1225        unsigned long flags;
1226        int rv;
1227        u32 data = -1;
1228        void __iomem *addr = NULL;
1229
1230        rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1231
1232        if (rv == 0)
1233                return readl(addr);
1234
1235        if (rv > 0) {
1236                /* indirect access */
1237                write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1238                crb_win_lock(adapter);
1239                if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1240                        data = readl(addr);
1241                crb_win_unlock(adapter);
1242                write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1243                return data;
1244        }
1245
1246        dev_err(&adapter->pdev->dev,
1247                        "%s: invalid offset: 0x%016lx\n", __func__, off);
1248        dump_stack();
1249        return -1;
1250}
1251
1252void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1253                                u32 offset)
1254{
1255        void __iomem *addr = NULL;
1256
1257        WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1258
1259        return addr;
1260}
1261
1262static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1263                                        u32 window, u64 off, u64 *data, int op)
1264{
1265        void __iomem *addr;
1266        u32 start;
1267
1268        mutex_lock(&adapter->ahw->mem_lock);
1269
1270        writel(window, adapter->ahw->ocm_win_crb);
1271        /* read back to flush */
1272        readl(adapter->ahw->ocm_win_crb);
1273        start = QLCNIC_PCI_OCM0_2M + off;
1274
1275        addr = adapter->ahw->pci_base0 + start;
1276
1277        if (op == 0)    /* read */
1278                *data = readq(addr);
1279        else            /* write */
1280                writeq(*data, addr);
1281
1282        /* Set window to 0 */
1283        writel(0, adapter->ahw->ocm_win_crb);
1284        readl(adapter->ahw->ocm_win_crb);
1285
1286        mutex_unlock(&adapter->ahw->mem_lock);
1287        return 0;
1288}
1289
1290static void
1291qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1292{
1293        void __iomem *addr = adapter->ahw->pci_base0 +
1294                QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1295
1296        mutex_lock(&adapter->ahw->mem_lock);
1297        *data = readq(addr);
1298        mutex_unlock(&adapter->ahw->mem_lock);
1299}
1300
1301static void
1302qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1303{
1304        void __iomem *addr = adapter->ahw->pci_base0 +
1305                QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1306
1307        mutex_lock(&adapter->ahw->mem_lock);
1308        writeq(data, addr);
1309        mutex_unlock(&adapter->ahw->mem_lock);
1310}
1311
1312
1313
1314/* Set MS memory control data for different adapters */
1315static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1316                                   struct qlcnic_ms_reg_ctrl *ms)
1317{
1318        ms->control = QLCNIC_MS_CTRL;
1319        ms->low = QLCNIC_MS_ADDR_LO;
1320        ms->hi = QLCNIC_MS_ADDR_HI;
1321        if (off & 0xf) {
1322                ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1323                ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1324                ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1325                ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1326                ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1327                ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1328                ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1329                ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1330        } else {
1331                ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1332                ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1333                ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1334                ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1335                ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1336                ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1337                ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1338                ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1339        }
1340
1341        ms->ocm_window = OCM_WIN_P3P(off);
1342        ms->off = GET_MEM_OFFS_2M(off);
1343}
1344
1345int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1346{
1347        int j, ret = 0;
1348        u32 temp, off8;
1349        struct qlcnic_ms_reg_ctrl ms;
1350
1351        /* Only 64-bit aligned access */
1352        if (off & 7)
1353                return -EIO;
1354
1355        memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1356        if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1357                            QLCNIC_ADDR_QDR_NET_MAX) ||
1358              ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1359                            QLCNIC_ADDR_DDR_NET_MAX)))
1360                return -EIO;
1361
1362        qlcnic_set_ms_controls(adapter, off, &ms);
1363
1364        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1365                return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1366                                                    ms.off, &data, 1);
1367
1368        off8 = off & ~0xf;
1369
1370        mutex_lock(&adapter->ahw->mem_lock);
1371
1372        qlcnic_ind_wr(adapter, ms.low, off8);
1373        qlcnic_ind_wr(adapter, ms.hi, 0);
1374
1375        qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1376        qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1377
1378        for (j = 0; j < MAX_CTL_CHECK; j++) {
1379                temp = qlcnic_ind_rd(adapter, ms.control);
1380                if ((temp & TA_CTL_BUSY) == 0)
1381                        break;
1382        }
1383
1384        if (j >= MAX_CTL_CHECK) {
1385                ret = -EIO;
1386                goto done;
1387        }
1388
1389        /* This is the modify part of read-modify-write */
1390        qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1391        qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1392        /* This is the write part of read-modify-write */
1393        qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1394        qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1395
1396        qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1397        qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1398
1399        for (j = 0; j < MAX_CTL_CHECK; j++) {
1400                temp = qlcnic_ind_rd(adapter, ms.control);
1401                if ((temp & TA_CTL_BUSY) == 0)
1402                        break;
1403        }
1404
1405        if (j >= MAX_CTL_CHECK) {
1406                if (printk_ratelimit())
1407                        dev_err(&adapter->pdev->dev,
1408                                        "failed to write through agent\n");
1409                ret = -EIO;
1410        } else
1411                ret = 0;
1412
1413done:
1414        mutex_unlock(&adapter->ahw->mem_lock);
1415
1416        return ret;
1417}
1418
1419int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1420{
1421        int j, ret;
1422        u32 temp, off8;
1423        u64 val;
1424        struct qlcnic_ms_reg_ctrl ms;
1425
1426        /* Only 64-bit aligned access */
1427        if (off & 7)
1428                return -EIO;
1429        if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1430                            QLCNIC_ADDR_QDR_NET_MAX) ||
1431              ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1432                            QLCNIC_ADDR_DDR_NET_MAX)))
1433                return -EIO;
1434
1435        memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1436        qlcnic_set_ms_controls(adapter, off, &ms);
1437
1438        if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1439                return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1440                                                    ms.off, data, 0);
1441
1442        mutex_lock(&adapter->ahw->mem_lock);
1443
1444        off8 = off & ~0xf;
1445
1446        qlcnic_ind_wr(adapter, ms.low, off8);
1447        qlcnic_ind_wr(adapter, ms.hi, 0);
1448
1449        qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1450        qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1451
1452        for (j = 0; j < MAX_CTL_CHECK; j++) {
1453                temp = qlcnic_ind_rd(adapter, ms.control);
1454                if ((temp & TA_CTL_BUSY) == 0)
1455                        break;
1456        }
1457
1458        if (j >= MAX_CTL_CHECK) {
1459                if (printk_ratelimit())
1460                        dev_err(&adapter->pdev->dev,
1461                                        "failed to read through agent\n");
1462                ret = -EIO;
1463        } else {
1464
1465                temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1466                val = (u64)temp << 32;
1467                val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1468                *data = val;
1469                ret = 0;
1470        }
1471
1472        mutex_unlock(&adapter->ahw->mem_lock);
1473
1474        return ret;
1475}
1476
1477int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1478{
1479        int offset, board_type, magic, err = 0;
1480        struct pci_dev *pdev = adapter->pdev;
1481
1482        offset = QLCNIC_FW_MAGIC_OFFSET;
1483        if (qlcnic_rom_fast_read(adapter, offset, &magic))
1484                return -EIO;
1485
1486        if (magic != QLCNIC_BDINFO_MAGIC) {
1487                dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1488                        magic);
1489                return -EIO;
1490        }
1491
1492        offset = QLCNIC_BRDTYPE_OFFSET;
1493        if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1494                return -EIO;
1495
1496        adapter->ahw->board_type = board_type;
1497
1498        if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1499                u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1500                if (err == -EIO)
1501                        return err;
1502                if ((gpio & 0x8000) == 0)
1503                        board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1504        }
1505
1506        switch (board_type) {
1507        case QLCNIC_BRDTYPE_P3P_HMEZ:
1508        case QLCNIC_BRDTYPE_P3P_XG_LOM:
1509        case QLCNIC_BRDTYPE_P3P_10G_CX4:
1510        case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1511        case QLCNIC_BRDTYPE_P3P_IMEZ:
1512        case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1513        case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1514        case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1515        case QLCNIC_BRDTYPE_P3P_10G_XFP:
1516        case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1517                adapter->ahw->port_type = QLCNIC_XGBE;
1518                break;
1519        case QLCNIC_BRDTYPE_P3P_REF_QG:
1520        case QLCNIC_BRDTYPE_P3P_4_GB:
1521        case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1522                adapter->ahw->port_type = QLCNIC_GBE;
1523                break;
1524        case QLCNIC_BRDTYPE_P3P_10G_TP:
1525                adapter->ahw->port_type = (adapter->portnum < 2) ?
1526                        QLCNIC_XGBE : QLCNIC_GBE;
1527                break;
1528        default:
1529                dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1530                adapter->ahw->port_type = QLCNIC_XGBE;
1531                break;
1532        }
1533
1534        return 0;
1535}
1536
1537static int
1538qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1539{
1540        u32 wol_cfg;
1541        int err = 0;
1542
1543        wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1544        if (wol_cfg & (1UL << adapter->portnum)) {
1545                wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1546                if (err == -EIO)
1547                        return err;
1548                if (wol_cfg & (1 << adapter->portnum))
1549                        return 1;
1550        }
1551
1552        return 0;
1553}
1554
1555int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1556{
1557        struct qlcnic_nic_req   req;
1558        int rv;
1559        u64 word;
1560
1561        memset(&req, 0, sizeof(struct qlcnic_nic_req));
1562        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1563
1564        word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1565        req.req_hdr = cpu_to_le64(word);
1566
1567        req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1568        req.words[1] = cpu_to_le64(state);
1569
1570        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1571        if (rv)
1572                dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1573
1574        return rv;
1575}
1576
1577void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1578{
1579        struct qlcnic_hardware_context *ahw = adapter->ahw;
1580        struct qlcnic_cmd_args cmd;
1581        u8 beacon_state;
1582        int err = 0;
1583
1584        if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1585                err = qlcnic_alloc_mbx_args(&cmd, adapter,
1586                                            QLCNIC_CMD_GET_LED_STATUS);
1587                if (!err) {
1588                        err = qlcnic_issue_cmd(adapter, &cmd);
1589                        if (err) {
1590                                netdev_err(adapter->netdev,
1591                                           "Failed to get current beacon state, err=%d\n",
1592                                           err);
1593                        } else {
1594                                beacon_state = cmd.rsp.arg[1];
1595                                if (beacon_state == QLCNIC_BEACON_DISABLE)
1596                                        ahw->beacon_state = QLCNIC_BEACON_OFF;
1597                                else if (beacon_state == QLCNIC_BEACON_EANBLE)
1598                                        ahw->beacon_state = QLCNIC_BEACON_ON;
1599                        }
1600                }
1601                qlcnic_free_mbx_args(&cmd);
1602        }
1603
1604        return;
1605}
1606
1607void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1608{
1609        void __iomem *msix_base_addr;
1610        u32 func;
1611        u32 msix_base;
1612
1613        pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1614        msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1615        msix_base = readl(msix_base_addr);
1616        func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1617        adapter->ahw->pci_func = func;
1618}
1619
1620void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1621                          loff_t offset, size_t size)
1622{
1623        int err = 0;
1624        u32 data;
1625        u64 qmdata;
1626
1627        if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1628                qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1629                memcpy(buf, &qmdata, size);
1630        } else {
1631                data = QLCRD32(adapter, offset, &err);
1632                memcpy(buf, &data, size);
1633        }
1634}
1635
1636void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1637                           loff_t offset, size_t size)
1638{
1639        u32 data;
1640        u64 qmdata;
1641
1642        if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1643                memcpy(&qmdata, buf, size);
1644                qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1645        } else {
1646                memcpy(&data, buf, size);
1647                QLCWR32(adapter, offset, data);
1648        }
1649}
1650
1651int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1652{
1653        return qlcnic_pcie_sem_lock(adapter, 5, 0);
1654}
1655
1656void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1657{
1658        qlcnic_pcie_sem_unlock(adapter, 5);
1659}
1660
1661int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1662{
1663        struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1664        struct net_device *netdev = adapter->netdev;
1665        int retval;
1666
1667        netif_device_detach(netdev);
1668
1669        qlcnic_cancel_idc_work(adapter);
1670
1671        if (netif_running(netdev))
1672                qlcnic_down(adapter, netdev);
1673
1674        qlcnic_clr_all_drv_state(adapter, 0);
1675
1676        clear_bit(__QLCNIC_RESETTING, &adapter->state);
1677
1678        retval = pci_save_state(pdev);
1679        if (retval)
1680                return retval;
1681
1682        if (qlcnic_wol_supported(adapter)) {
1683                pci_enable_wake(pdev, PCI_D3cold, 1);
1684                pci_enable_wake(pdev, PCI_D3hot, 1);
1685        }
1686
1687        return 0;
1688}
1689
1690int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1691{
1692        struct net_device *netdev = adapter->netdev;
1693        int err;
1694
1695        err = qlcnic_start_firmware(adapter);
1696        if (err) {
1697                dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1698                return err;
1699        }
1700
1701        if (netif_running(netdev)) {
1702                err = qlcnic_up(adapter, netdev);
1703                if (!err)
1704                        qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1705        }
1706
1707        netif_device_attach(netdev);
1708        qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1709        return err;
1710}
1711