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43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45#include <linux/module.h>
46#include <linux/delay.h>
47#include <linux/dma-mapping.h>
48#include <linux/hardirq.h>
49#include <linux/if.h>
50#include <linux/io.h>
51#include <linux/netdevice.h>
52#include <linux/cache.h>
53#include <linux/ethtool.h>
54#include <linux/uaccess.h>
55#include <linux/slab.h>
56#include <linux/etherdevice.h>
57#include <linux/nl80211.h>
58
59#include <net/cfg80211.h>
60#include <net/ieee80211_radiotap.h>
61
62#include <asm/unaligned.h>
63
64#include <net/mac80211.h>
65#include "base.h"
66#include "reg.h"
67#include "debug.h"
68#include "ani.h"
69#include "ath5k.h"
70#include "../regd.h"
71
72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
75bool ath5k_modparam_nohwcrypt;
76module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
77MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78
79static bool modparam_fastchanswitch;
80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82
83static bool ath5k_modparam_no_hw_rfkill_switch;
84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
85 bool, S_IRUGO);
86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
87
88
89
90MODULE_AUTHOR("Jiri Slaby");
91MODULE_AUTHOR("Nick Kossifidis");
92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
94MODULE_LICENSE("Dual BSD/GPL");
95
96static int ath5k_init(struct ieee80211_hw *hw);
97static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
98 bool skip_pcu);
99
100
101static const struct ath5k_srev_name srev_names[] = {
102#ifdef CONFIG_ATH5K_AHB
103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
110#else
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129#endif
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
145#ifdef CONFIG_ATH5K_AHB
146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
148#endif
149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
150};
151
152static const struct ieee80211_rate ath5k_rates[] = {
153 { .bitrate = 10,
154 .hw_value = ATH5K_RATE_CODE_1M, },
155 { .bitrate = 20,
156 .hw_value = ATH5K_RATE_CODE_2M,
157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 55,
160 .hw_value = ATH5K_RATE_CODE_5_5M,
161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 { .bitrate = 110,
164 .hw_value = ATH5K_RATE_CODE_11M,
165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
166 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
167 { .bitrate = 60,
168 .hw_value = ATH5K_RATE_CODE_6M,
169 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
170 IEEE80211_RATE_SUPPORTS_10MHZ },
171 { .bitrate = 90,
172 .hw_value = ATH5K_RATE_CODE_9M,
173 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
174 IEEE80211_RATE_SUPPORTS_10MHZ },
175 { .bitrate = 120,
176 .hw_value = ATH5K_RATE_CODE_12M,
177 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
178 IEEE80211_RATE_SUPPORTS_10MHZ },
179 { .bitrate = 180,
180 .hw_value = ATH5K_RATE_CODE_18M,
181 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
182 IEEE80211_RATE_SUPPORTS_10MHZ },
183 { .bitrate = 240,
184 .hw_value = ATH5K_RATE_CODE_24M,
185 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
186 IEEE80211_RATE_SUPPORTS_10MHZ },
187 { .bitrate = 360,
188 .hw_value = ATH5K_RATE_CODE_36M,
189 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
190 IEEE80211_RATE_SUPPORTS_10MHZ },
191 { .bitrate = 480,
192 .hw_value = ATH5K_RATE_CODE_48M,
193 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
194 IEEE80211_RATE_SUPPORTS_10MHZ },
195 { .bitrate = 540,
196 .hw_value = ATH5K_RATE_CODE_54M,
197 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
198 IEEE80211_RATE_SUPPORTS_10MHZ },
199};
200
201static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
202{
203 u64 tsf = ath5k_hw_get_tsf64(ah);
204
205 if ((tsf & 0x7fff) < rstamp)
206 tsf -= 0x8000;
207
208 return (tsf & ~0x7fff) | rstamp;
209}
210
211const char *
212ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
213{
214 const char *name = "xxxxx";
215 unsigned int i;
216
217 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
218 if (srev_names[i].sr_type != type)
219 continue;
220
221 if ((val & 0xf0) == srev_names[i].sr_val)
222 name = srev_names[i].sr_name;
223
224 if ((val & 0xff) == srev_names[i].sr_val) {
225 name = srev_names[i].sr_name;
226 break;
227 }
228 }
229
230 return name;
231}
232static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
233{
234 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
235 return ath5k_hw_reg_read(ah, reg_offset);
236}
237
238static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
239{
240 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
241 ath5k_hw_reg_write(ah, val, reg_offset);
242}
243
244static const struct ath_ops ath5k_common_ops = {
245 .read = ath5k_ioread32,
246 .write = ath5k_iowrite32,
247};
248
249
250
251
252
253static void ath5k_reg_notifier(struct wiphy *wiphy,
254 struct regulatory_request *request)
255{
256 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
257 struct ath5k_hw *ah = hw->priv;
258 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
259
260 ath_reg_notifier_apply(wiphy, request, regulatory);
261}
262
263
264
265
266
267
268
269
270#ifdef CONFIG_ATH5K_TEST_CHANNELS
271static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
272{
273 return true;
274}
275
276#else
277static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
278{
279 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
280 return true;
281
282 return
283 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
284
285 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
286
287 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
288
289 (chan == 8 || chan == 12 || chan == 16) ||
290
291 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
292}
293#endif
294
295static unsigned int
296ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
297 unsigned int mode, unsigned int max)
298{
299 unsigned int count, size, freq, ch;
300 enum ieee80211_band band;
301
302 switch (mode) {
303 case AR5K_MODE_11A:
304
305 size = 220;
306 band = IEEE80211_BAND_5GHZ;
307 break;
308 case AR5K_MODE_11B:
309 case AR5K_MODE_11G:
310 size = 26;
311 band = IEEE80211_BAND_2GHZ;
312 break;
313 default:
314 ATH5K_WARN(ah, "bad mode, not copying channels\n");
315 return 0;
316 }
317
318 count = 0;
319 for (ch = 1; ch <= size && count < max; ch++) {
320 freq = ieee80211_channel_to_frequency(ch, band);
321
322 if (freq == 0)
323 continue;
324
325
326 channels[count].center_freq = freq;
327 channels[count].band = band;
328 channels[count].hw_value = mode;
329
330
331 if (!ath5k_channel_ok(ah, &channels[count]))
332 continue;
333
334 if (!ath5k_is_standard_channel(ch, band))
335 continue;
336
337 count++;
338 }
339
340 return count;
341}
342
343static void
344ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
345{
346 u8 i;
347
348 for (i = 0; i < AR5K_MAX_RATES; i++)
349 ah->rate_idx[b->band][i] = -1;
350
351 for (i = 0; i < b->n_bitrates; i++) {
352 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
353 if (b->bitrates[i].hw_value_short)
354 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
355 }
356}
357
358static int
359ath5k_setup_bands(struct ieee80211_hw *hw)
360{
361 struct ath5k_hw *ah = hw->priv;
362 struct ieee80211_supported_band *sband;
363 int max_c, count_c = 0;
364 int i;
365
366 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
367 max_c = ARRAY_SIZE(ah->channels);
368
369
370 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
371 sband->band = IEEE80211_BAND_2GHZ;
372 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
373
374 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
375
376 memcpy(sband->bitrates, &ath5k_rates[0],
377 sizeof(struct ieee80211_rate) * 12);
378 sband->n_bitrates = 12;
379
380 sband->channels = ah->channels;
381 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
382 AR5K_MODE_11G, max_c);
383
384 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
385 count_c = sband->n_channels;
386 max_c -= count_c;
387 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
388
389 memcpy(sband->bitrates, &ath5k_rates[0],
390 sizeof(struct ieee80211_rate) * 4);
391 sband->n_bitrates = 4;
392
393
394
395
396
397 if (ah->ah_version == AR5K_AR5211) {
398 for (i = 0; i < 4; i++) {
399 sband->bitrates[i].hw_value =
400 sband->bitrates[i].hw_value & 0xF;
401 sband->bitrates[i].hw_value_short =
402 sband->bitrates[i].hw_value_short & 0xF;
403 }
404 }
405
406 sband->channels = ah->channels;
407 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
408 AR5K_MODE_11B, max_c);
409
410 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
411 count_c = sband->n_channels;
412 max_c -= count_c;
413 }
414 ath5k_setup_rate_idx(ah, sband);
415
416
417 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
418 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
419 sband->band = IEEE80211_BAND_5GHZ;
420 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
421
422 memcpy(sband->bitrates, &ath5k_rates[4],
423 sizeof(struct ieee80211_rate) * 8);
424 sband->n_bitrates = 8;
425
426 sband->channels = &ah->channels[count_c];
427 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
428 AR5K_MODE_11A, max_c);
429
430 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
431 }
432 ath5k_setup_rate_idx(ah, sband);
433
434 ath5k_debug_dump_bands(ah);
435
436 return 0;
437}
438
439
440
441
442
443
444
445
446int
447ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef)
448{
449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
450 "channel set, resetting (%u -> %u MHz)\n",
451 ah->curchan->center_freq, chandef->chan->center_freq);
452
453 switch (chandef->width) {
454 case NL80211_CHAN_WIDTH_20:
455 case NL80211_CHAN_WIDTH_20_NOHT:
456 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
457 break;
458 case NL80211_CHAN_WIDTH_5:
459 ah->ah_bwmode = AR5K_BWMODE_5MHZ;
460 break;
461 case NL80211_CHAN_WIDTH_10:
462 ah->ah_bwmode = AR5K_BWMODE_10MHZ;
463 break;
464 default:
465 WARN_ON(1);
466 return -EINVAL;
467 }
468
469
470
471
472
473
474
475 return ath5k_reset(ah, chandef->chan, true);
476}
477
478void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
479{
480 struct ath5k_vif_iter_data *iter_data = data;
481 int i;
482 struct ath5k_vif *avf = (void *)vif->drv_priv;
483
484 if (iter_data->hw_macaddr)
485 for (i = 0; i < ETH_ALEN; i++)
486 iter_data->mask[i] &=
487 ~(iter_data->hw_macaddr[i] ^ mac[i]);
488
489 if (!iter_data->found_active) {
490 iter_data->found_active = true;
491 memcpy(iter_data->active_mac, mac, ETH_ALEN);
492 }
493
494 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
495 if (ether_addr_equal(iter_data->hw_macaddr, mac))
496 iter_data->need_set_hw_addr = false;
497
498 if (!iter_data->any_assoc) {
499 if (avf->assoc)
500 iter_data->any_assoc = true;
501 }
502
503
504
505
506
507
508 if (avf->opmode == NL80211_IFTYPE_AP)
509 iter_data->opmode = NL80211_IFTYPE_AP;
510 else {
511 if (avf->opmode == NL80211_IFTYPE_STATION)
512 iter_data->n_stas++;
513 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
514 iter_data->opmode = avf->opmode;
515 }
516}
517
518void
519ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
520 struct ieee80211_vif *vif)
521{
522 struct ath_common *common = ath5k_hw_common(ah);
523 struct ath5k_vif_iter_data iter_data;
524 u32 rfilt;
525
526
527
528
529
530 iter_data.hw_macaddr = common->macaddr;
531 memset(&iter_data.mask, 0xff, ETH_ALEN);
532 iter_data.found_active = false;
533 iter_data.need_set_hw_addr = true;
534 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
535 iter_data.n_stas = 0;
536
537 if (vif)
538 ath5k_vif_iter(&iter_data, vif->addr, vif);
539
540
541 ieee80211_iterate_active_interfaces_atomic(
542 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
543 ath5k_vif_iter, &iter_data);
544 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
545
546 ah->opmode = iter_data.opmode;
547 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
548
549 ah->opmode = NL80211_IFTYPE_STATION;
550
551 ath5k_hw_set_opmode(ah, ah->opmode);
552 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
553 ah->opmode, ath_opmode_to_string(ah->opmode));
554
555 if (iter_data.need_set_hw_addr && iter_data.found_active)
556 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
557
558 if (ath5k_hw_hasbssidmask(ah))
559 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
560
561
562 if (iter_data.n_stas > 1) {
563
564
565
566
567 ah->filter_flags |= AR5K_RX_FILTER_PROM;
568 }
569
570 rfilt = ah->filter_flags;
571 ath5k_hw_set_rx_filter(ah, rfilt);
572 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
573}
574
575static inline int
576ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
577{
578 int rix;
579
580
581 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
582 "hw_rix out of bounds: %x\n", hw_rix))
583 return 0;
584
585 rix = ah->rate_idx[ah->curchan->band][hw_rix];
586 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
587 rix = 0;
588
589 return rix;
590}
591
592
593
594
595
596static
597struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
598{
599 struct ath_common *common = ath5k_hw_common(ah);
600 struct sk_buff *skb;
601
602
603
604
605
606 skb = ath_rxbuf_alloc(common,
607 common->rx_bufsize,
608 GFP_ATOMIC);
609
610 if (!skb) {
611 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
612 common->rx_bufsize);
613 return NULL;
614 }
615
616 *skb_addr = dma_map_single(ah->dev,
617 skb->data, common->rx_bufsize,
618 DMA_FROM_DEVICE);
619
620 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
621 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
622 dev_kfree_skb(skb);
623 return NULL;
624 }
625 return skb;
626}
627
628static int
629ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
630{
631 struct sk_buff *skb = bf->skb;
632 struct ath5k_desc *ds;
633 int ret;
634
635 if (!skb) {
636 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
637 if (!skb)
638 return -ENOMEM;
639 bf->skb = skb;
640 }
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657 ds = bf->desc;
658 ds->ds_link = bf->daddr;
659 ds->ds_data = bf->skbaddr;
660 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
661 if (ret) {
662 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
663 return ret;
664 }
665
666 if (ah->rxlink != NULL)
667 *ah->rxlink = bf->daddr;
668 ah->rxlink = &ds->ds_link;
669 return 0;
670}
671
672static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
673{
674 struct ieee80211_hdr *hdr;
675 enum ath5k_pkt_type htype;
676 __le16 fc;
677
678 hdr = (struct ieee80211_hdr *)skb->data;
679 fc = hdr->frame_control;
680
681 if (ieee80211_is_beacon(fc))
682 htype = AR5K_PKT_TYPE_BEACON;
683 else if (ieee80211_is_probe_resp(fc))
684 htype = AR5K_PKT_TYPE_PROBE_RESP;
685 else if (ieee80211_is_atim(fc))
686 htype = AR5K_PKT_TYPE_ATIM;
687 else if (ieee80211_is_pspoll(fc))
688 htype = AR5K_PKT_TYPE_PSPOLL;
689 else
690 htype = AR5K_PKT_TYPE_NORMAL;
691
692 return htype;
693}
694
695static struct ieee80211_rate *
696ath5k_get_rate(const struct ieee80211_hw *hw,
697 const struct ieee80211_tx_info *info,
698 struct ath5k_buf *bf, int idx)
699{
700
701
702
703
704 if (bf->rates[idx].idx < 0) {
705 return NULL;
706 }
707
708 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ];
709}
710
711static u16
712ath5k_get_rate_hw_value(const struct ieee80211_hw *hw,
713 const struct ieee80211_tx_info *info,
714 struct ath5k_buf *bf, int idx)
715{
716 struct ieee80211_rate *rate;
717 u16 hw_rate;
718 u8 rc_flags;
719
720 rate = ath5k_get_rate(hw, info, bf, idx);
721 if (!rate)
722 return 0;
723
724 rc_flags = bf->rates[idx].flags;
725 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
726 rate->hw_value_short : rate->hw_value;
727
728 return hw_rate;
729}
730
731static int
732ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
733 struct ath5k_txq *txq, int padsize,
734 struct ieee80211_tx_control *control)
735{
736 struct ath5k_desc *ds = bf->desc;
737 struct sk_buff *skb = bf->skb;
738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
739 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
740 struct ieee80211_rate *rate;
741 unsigned int mrr_rate[3], mrr_tries[3];
742 int i, ret;
743 u16 hw_rate;
744 u16 cts_rate = 0;
745 u16 duration = 0;
746 u8 rc_flags;
747
748 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
749
750
751 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
752 DMA_TO_DEVICE);
753
754 if (dma_mapping_error(ah->dev, bf->skbaddr))
755 return -ENOSPC;
756
757 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates,
758 ARRAY_SIZE(bf->rates));
759
760 rate = ath5k_get_rate(ah->hw, info, bf, 0);
761
762 if (!rate) {
763 ret = -EINVAL;
764 goto err_unmap;
765 }
766
767 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
768 flags |= AR5K_TXDESC_NOACK;
769
770 rc_flags = info->control.rates[0].flags;
771
772 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0);
773
774 pktlen = skb->len;
775
776
777
778
779 if (info->control.hw_key) {
780 keyidx = info->control.hw_key->hw_key_idx;
781 pktlen += info->control.hw_key->icv_len;
782 }
783 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
784 flags |= AR5K_TXDESC_RTSENA;
785 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
786 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
787 info->control.vif, pktlen, info));
788 }
789 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
790 flags |= AR5K_TXDESC_CTSENA;
791 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
792 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
793 info->control.vif, pktlen, info));
794 }
795
796 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
797 ieee80211_get_hdrlen_from_skb(skb), padsize,
798 get_hw_packet_type(skb),
799 (ah->ah_txpower.txp_requested * 2),
800 hw_rate,
801 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags,
802 cts_rate, duration);
803 if (ret)
804 goto err_unmap;
805
806
807 if (ah->ah_capabilities.cap_has_mrr_support) {
808 memset(mrr_rate, 0, sizeof(mrr_rate));
809 memset(mrr_tries, 0, sizeof(mrr_tries));
810
811 for (i = 0; i < 3; i++) {
812
813 rate = ath5k_get_rate(ah->hw, info, bf, i);
814 if (!rate)
815 break;
816
817 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i);
818 mrr_tries[i] = bf->rates[i].count;
819 }
820
821 ath5k_hw_setup_mrr_tx_desc(ah, ds,
822 mrr_rate[0], mrr_tries[0],
823 mrr_rate[1], mrr_tries[1],
824 mrr_rate[2], mrr_tries[2]);
825 }
826
827 ds->ds_link = 0;
828 ds->ds_data = bf->skbaddr;
829
830 spin_lock_bh(&txq->lock);
831 list_add_tail(&bf->list, &txq->q);
832 txq->txq_len++;
833 if (txq->link == NULL)
834 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
835 else
836 *txq->link = bf->daddr;
837
838 txq->link = &ds->ds_link;
839 ath5k_hw_start_tx_dma(ah, txq->qnum);
840 mmiowb();
841 spin_unlock_bh(&txq->lock);
842
843 return 0;
844err_unmap:
845 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
846 return ret;
847}
848
849
850
851
852
853static int
854ath5k_desc_alloc(struct ath5k_hw *ah)
855{
856 struct ath5k_desc *ds;
857 struct ath5k_buf *bf;
858 dma_addr_t da;
859 unsigned int i;
860 int ret;
861
862
863 ah->desc_len = sizeof(struct ath5k_desc) *
864 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
865
866 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
867 &ah->desc_daddr, GFP_KERNEL);
868 if (ah->desc == NULL) {
869 ATH5K_ERR(ah, "can't allocate descriptors\n");
870 ret = -ENOMEM;
871 goto err;
872 }
873 ds = ah->desc;
874 da = ah->desc_daddr;
875 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
876 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
877
878 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
879 sizeof(struct ath5k_buf), GFP_KERNEL);
880 if (bf == NULL) {
881 ATH5K_ERR(ah, "can't allocate bufptr\n");
882 ret = -ENOMEM;
883 goto err_free;
884 }
885 ah->bufptr = bf;
886
887 INIT_LIST_HEAD(&ah->rxbuf);
888 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
889 bf->desc = ds;
890 bf->daddr = da;
891 list_add_tail(&bf->list, &ah->rxbuf);
892 }
893
894 INIT_LIST_HEAD(&ah->txbuf);
895 ah->txbuf_len = ATH_TXBUF;
896 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
897 bf->desc = ds;
898 bf->daddr = da;
899 list_add_tail(&bf->list, &ah->txbuf);
900 }
901
902
903 INIT_LIST_HEAD(&ah->bcbuf);
904 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
905 bf->desc = ds;
906 bf->daddr = da;
907 list_add_tail(&bf->list, &ah->bcbuf);
908 }
909
910 return 0;
911err_free:
912 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
913err:
914 ah->desc = NULL;
915 return ret;
916}
917
918void
919ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
920{
921 BUG_ON(!bf);
922 if (!bf->skb)
923 return;
924 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
925 DMA_TO_DEVICE);
926 ieee80211_free_txskb(ah->hw, bf->skb);
927 bf->skb = NULL;
928 bf->skbaddr = 0;
929 bf->desc->ds_data = 0;
930}
931
932void
933ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
934{
935 struct ath_common *common = ath5k_hw_common(ah);
936
937 BUG_ON(!bf);
938 if (!bf->skb)
939 return;
940 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
941 DMA_FROM_DEVICE);
942 dev_kfree_skb_any(bf->skb);
943 bf->skb = NULL;
944 bf->skbaddr = 0;
945 bf->desc->ds_data = 0;
946}
947
948static void
949ath5k_desc_free(struct ath5k_hw *ah)
950{
951 struct ath5k_buf *bf;
952
953 list_for_each_entry(bf, &ah->txbuf, list)
954 ath5k_txbuf_free_skb(ah, bf);
955 list_for_each_entry(bf, &ah->rxbuf, list)
956 ath5k_rxbuf_free_skb(ah, bf);
957 list_for_each_entry(bf, &ah->bcbuf, list)
958 ath5k_txbuf_free_skb(ah, bf);
959
960
961 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
962 ah->desc = NULL;
963 ah->desc_daddr = 0;
964
965 kfree(ah->bufptr);
966 ah->bufptr = NULL;
967}
968
969
970
971
972
973
974static struct ath5k_txq *
975ath5k_txq_setup(struct ath5k_hw *ah,
976 int qtype, int subtype)
977{
978 struct ath5k_txq *txq;
979 struct ath5k_txq_info qi = {
980 .tqi_subtype = subtype,
981
982
983 .tqi_aifs = AR5K_TUNE_AIFS,
984 .tqi_cw_min = AR5K_TUNE_CWMIN,
985 .tqi_cw_max = AR5K_TUNE_CWMAX
986 };
987 int qnum;
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1002 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1003 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1004 if (qnum < 0) {
1005
1006
1007
1008
1009 return ERR_PTR(qnum);
1010 }
1011 txq = &ah->txqs[qnum];
1012 if (!txq->setup) {
1013 txq->qnum = qnum;
1014 txq->link = NULL;
1015 INIT_LIST_HEAD(&txq->q);
1016 spin_lock_init(&txq->lock);
1017 txq->setup = true;
1018 txq->txq_len = 0;
1019 txq->txq_max = ATH5K_TXQ_LEN_MAX;
1020 txq->txq_poll_mark = false;
1021 txq->txq_stuck = 0;
1022 }
1023 return &ah->txqs[qnum];
1024}
1025
1026static int
1027ath5k_beaconq_setup(struct ath5k_hw *ah)
1028{
1029 struct ath5k_txq_info qi = {
1030
1031
1032 .tqi_aifs = AR5K_TUNE_AIFS,
1033 .tqi_cw_min = AR5K_TUNE_CWMIN,
1034 .tqi_cw_max = AR5K_TUNE_CWMAX,
1035
1036 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1037 };
1038
1039 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1040}
1041
1042static int
1043ath5k_beaconq_config(struct ath5k_hw *ah)
1044{
1045 struct ath5k_txq_info qi;
1046 int ret;
1047
1048 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
1049 if (ret)
1050 goto err;
1051
1052 if (ah->opmode == NL80211_IFTYPE_AP ||
1053 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1054
1055
1056
1057
1058 qi.tqi_aifs = 0;
1059 qi.tqi_cw_min = 0;
1060 qi.tqi_cw_max = 0;
1061 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
1062
1063
1064
1065 qi.tqi_aifs = 0;
1066 qi.tqi_cw_min = 0;
1067 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1068 }
1069
1070 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1071 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1072 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1073
1074 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1075 if (ret) {
1076 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1077 "hardware queue!\n", __func__);
1078 goto err;
1079 }
1080 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq);
1081 if (ret)
1082 goto err;
1083
1084
1085 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1086 if (ret)
1087 goto err;
1088
1089 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1090 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1091 if (ret)
1092 goto err;
1093
1094 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1095err:
1096 return ret;
1097}
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110static void
1111ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1112{
1113 struct ath5k_txq *txq;
1114 struct ath5k_buf *bf, *bf0;
1115 int i;
1116
1117 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1118 if (ah->txqs[i].setup) {
1119 txq = &ah->txqs[i];
1120 spin_lock_bh(&txq->lock);
1121 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1122 ath5k_debug_printtxbuf(ah, bf);
1123
1124 ath5k_txbuf_free_skb(ah, bf);
1125
1126 spin_lock(&ah->txbuflock);
1127 list_move_tail(&bf->list, &ah->txbuf);
1128 ah->txbuf_len++;
1129 txq->txq_len--;
1130 spin_unlock(&ah->txbuflock);
1131 }
1132 txq->link = NULL;
1133 txq->txq_poll_mark = false;
1134 spin_unlock_bh(&txq->lock);
1135 }
1136 }
1137}
1138
1139static void
1140ath5k_txq_release(struct ath5k_hw *ah)
1141{
1142 struct ath5k_txq *txq = ah->txqs;
1143 unsigned int i;
1144
1145 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1146 if (txq->setup) {
1147 ath5k_hw_release_tx_queue(ah, txq->qnum);
1148 txq->setup = false;
1149 }
1150}
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160static int
1161ath5k_rx_start(struct ath5k_hw *ah)
1162{
1163 struct ath_common *common = ath5k_hw_common(ah);
1164 struct ath5k_buf *bf;
1165 int ret;
1166
1167 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1168
1169 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1170 common->cachelsz, common->rx_bufsize);
1171
1172 spin_lock_bh(&ah->rxbuflock);
1173 ah->rxlink = NULL;
1174 list_for_each_entry(bf, &ah->rxbuf, list) {
1175 ret = ath5k_rxbuf_setup(ah, bf);
1176 if (ret != 0) {
1177 spin_unlock_bh(&ah->rxbuflock);
1178 goto err;
1179 }
1180 }
1181 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1182 ath5k_hw_set_rxdp(ah, bf->daddr);
1183 spin_unlock_bh(&ah->rxbuflock);
1184
1185 ath5k_hw_start_rx_dma(ah);
1186 ath5k_update_bssid_mask_and_opmode(ah, NULL);
1187 ath5k_hw_start_rx_pcu(ah);
1188
1189 return 0;
1190err:
1191 return ret;
1192}
1193
1194
1195
1196
1197
1198
1199
1200
1201static void
1202ath5k_rx_stop(struct ath5k_hw *ah)
1203{
1204
1205 ath5k_hw_set_rx_filter(ah, 0);
1206 ath5k_hw_stop_rx_pcu(ah);
1207
1208 ath5k_debug_printrxbuffs(ah);
1209}
1210
1211static unsigned int
1212ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1213 struct ath5k_rx_status *rs)
1214{
1215 struct ath_common *common = ath5k_hw_common(ah);
1216 struct ieee80211_hdr *hdr = (void *)skb->data;
1217 unsigned int keyix, hlen;
1218
1219 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1220 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1221 return RX_FLAG_DECRYPTED;
1222
1223
1224
1225
1226 hlen = ieee80211_hdrlen(hdr->frame_control);
1227 if (ieee80211_has_protected(hdr->frame_control) &&
1228 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1229 skb->len >= hlen + 4) {
1230 keyix = skb->data[hlen + 3] >> 6;
1231
1232 if (test_bit(keyix, common->keymap))
1233 return RX_FLAG_DECRYPTED;
1234 }
1235
1236 return 0;
1237}
1238
1239
1240static void
1241ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1242 struct ieee80211_rx_status *rxs)
1243{
1244 u64 tsf, bc_tstamp;
1245 u32 hw_tu;
1246 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1247
1248 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) {
1249
1250
1251
1252
1253
1254 tsf = ath5k_hw_get_tsf64(ah);
1255 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1256 hw_tu = TSF_TO_TU(tsf);
1257
1258 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1259 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1260 (unsigned long long)bc_tstamp,
1261 (unsigned long long)rxs->mactime,
1262 (unsigned long long)(rxs->mactime - bc_tstamp),
1263 (unsigned long long)tsf);
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276 if (bc_tstamp > rxs->mactime) {
1277 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1278 "fixing mactime from %llx to %llx\n",
1279 (unsigned long long)rxs->mactime,
1280 (unsigned long long)tsf);
1281 rxs->mactime = tsf;
1282 }
1283
1284
1285
1286
1287
1288
1289
1290 if (hw_tu >= ah->nexttbtt)
1291 ath5k_beacon_update_timers(ah, bc_tstamp);
1292
1293
1294
1295
1296 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1297 ath5k_beacon_update_timers(ah, bc_tstamp);
1298 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1299 "fixed beacon timers after beacon receive\n");
1300 }
1301 }
1302}
1303
1304
1305
1306
1307static int ath5k_common_padpos(struct sk_buff *skb)
1308{
1309 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1310 __le16 frame_control = hdr->frame_control;
1311 int padpos = 24;
1312
1313 if (ieee80211_has_a4(frame_control))
1314 padpos += ETH_ALEN;
1315
1316 if (ieee80211_is_data_qos(frame_control))
1317 padpos += IEEE80211_QOS_CTL_LEN;
1318
1319 return padpos;
1320}
1321
1322
1323
1324
1325
1326static int ath5k_add_padding(struct sk_buff *skb)
1327{
1328 int padpos = ath5k_common_padpos(skb);
1329 int padsize = padpos & 3;
1330
1331 if (padsize && skb->len > padpos) {
1332
1333 if (skb_headroom(skb) < padsize)
1334 return -1;
1335
1336 skb_push(skb, padsize);
1337 memmove(skb->data, skb->data + padsize, padpos);
1338 return padsize;
1339 }
1340
1341 return 0;
1342}
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357static int ath5k_remove_padding(struct sk_buff *skb)
1358{
1359 int padpos = ath5k_common_padpos(skb);
1360 int padsize = padpos & 3;
1361
1362 if (padsize && skb->len >= padpos + padsize) {
1363 memmove(skb->data + padsize, skb->data, padpos);
1364 skb_pull(skb, padsize);
1365 return padsize;
1366 }
1367
1368 return 0;
1369}
1370
1371static void
1372ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1373 struct ath5k_rx_status *rs)
1374{
1375 struct ieee80211_rx_status *rxs;
1376 struct ath_common *common = ath5k_hw_common(ah);
1377
1378 ath5k_remove_padding(skb);
1379
1380 rxs = IEEE80211_SKB_RXCB(skb);
1381
1382 rxs->flag = 0;
1383 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1384 rxs->flag |= RX_FLAG_MMIC_ERROR;
1385 if (unlikely(rs->rs_status & AR5K_RXERR_CRC))
1386 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1399 rxs->flag |= RX_FLAG_MACTIME_END;
1400
1401 rxs->freq = ah->curchan->center_freq;
1402 rxs->band = ah->curchan->band;
1403
1404 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1405
1406 rxs->antenna = rs->rs_antenna;
1407
1408 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1409 ah->stats.antenna_rx[rs->rs_antenna]++;
1410 else
1411 ah->stats.antenna_rx[0]++;
1412
1413 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1414 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1415 switch (ah->ah_bwmode) {
1416 case AR5K_BWMODE_5MHZ:
1417 rxs->flag |= RX_FLAG_5MHZ;
1418 break;
1419 case AR5K_BWMODE_10MHZ:
1420 rxs->flag |= RX_FLAG_10MHZ;
1421 break;
1422 default:
1423 break;
1424 }
1425
1426 if (rs->rs_rate ==
1427 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1428 rxs->flag |= RX_FLAG_SHORTPRE;
1429
1430 trace_ath5k_rx(ah, skb);
1431
1432 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) {
1433 ewma_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi);
1434
1435
1436 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1437 ath5k_check_ibss_tsf(ah, skb, rxs);
1438 }
1439
1440 ieee80211_rx(ah->hw, skb);
1441}
1442
1443
1444
1445
1446
1447
1448static bool
1449ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1450{
1451 ah->stats.rx_all_count++;
1452 ah->stats.rx_bytes_count += rs->rs_datalen;
1453
1454 if (unlikely(rs->rs_status)) {
1455 unsigned int filters;
1456
1457 if (rs->rs_status & AR5K_RXERR_CRC)
1458 ah->stats.rxerr_crc++;
1459 if (rs->rs_status & AR5K_RXERR_FIFO)
1460 ah->stats.rxerr_fifo++;
1461 if (rs->rs_status & AR5K_RXERR_PHY) {
1462 ah->stats.rxerr_phy++;
1463 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1464 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1465
1466
1467
1468
1469
1470
1471
1472 if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART ||
1473 rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) {
1474 rs->rs_status |= AR5K_RXERR_CRC;
1475 rs->rs_status &= ~AR5K_RXERR_PHY;
1476 } else {
1477 return false;
1478 }
1479 }
1480 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491 ah->stats.rxerr_decrypt++;
1492 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1493 !(rs->rs_status & AR5K_RXERR_CRC))
1494 return true;
1495 }
1496 if (rs->rs_status & AR5K_RXERR_MIC) {
1497 ah->stats.rxerr_mic++;
1498 return true;
1499 }
1500
1501
1502
1503
1504
1505 filters = AR5K_RXERR_DECRYPT;
1506 if (ah->fif_filter_flags & FIF_FCSFAIL)
1507 filters |= AR5K_RXERR_CRC;
1508
1509 if (rs->rs_status & ~filters)
1510 return false;
1511 }
1512
1513 if (unlikely(rs->rs_more)) {
1514 ah->stats.rxerr_jumbo++;
1515 return false;
1516 }
1517 return true;
1518}
1519
1520static void
1521ath5k_set_current_imask(struct ath5k_hw *ah)
1522{
1523 enum ath5k_int imask;
1524 unsigned long flags;
1525
1526 spin_lock_irqsave(&ah->irqlock, flags);
1527 imask = ah->imask;
1528 if (ah->rx_pending)
1529 imask &= ~AR5K_INT_RX_ALL;
1530 if (ah->tx_pending)
1531 imask &= ~AR5K_INT_TX_ALL;
1532 ath5k_hw_set_imr(ah, imask);
1533 spin_unlock_irqrestore(&ah->irqlock, flags);
1534}
1535
1536static void
1537ath5k_tasklet_rx(unsigned long data)
1538{
1539 struct ath5k_rx_status rs = {};
1540 struct sk_buff *skb, *next_skb;
1541 dma_addr_t next_skb_addr;
1542 struct ath5k_hw *ah = (void *)data;
1543 struct ath_common *common = ath5k_hw_common(ah);
1544 struct ath5k_buf *bf;
1545 struct ath5k_desc *ds;
1546 int ret;
1547
1548 spin_lock(&ah->rxbuflock);
1549 if (list_empty(&ah->rxbuf)) {
1550 ATH5K_WARN(ah, "empty rx buf pool\n");
1551 goto unlock;
1552 }
1553 do {
1554 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1555 BUG_ON(bf->skb == NULL);
1556 skb = bf->skb;
1557 ds = bf->desc;
1558
1559
1560 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1561 break;
1562
1563 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1564 if (unlikely(ret == -EINPROGRESS))
1565 break;
1566 else if (unlikely(ret)) {
1567 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1568 ah->stats.rxerr_proc++;
1569 break;
1570 }
1571
1572 if (ath5k_receive_frame_ok(ah, &rs)) {
1573 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1574
1575
1576
1577
1578
1579 if (!next_skb)
1580 goto next;
1581
1582 dma_unmap_single(ah->dev, bf->skbaddr,
1583 common->rx_bufsize,
1584 DMA_FROM_DEVICE);
1585
1586 skb_put(skb, rs.rs_datalen);
1587
1588 ath5k_receive_frame(ah, skb, &rs);
1589
1590 bf->skb = next_skb;
1591 bf->skbaddr = next_skb_addr;
1592 }
1593next:
1594 list_move_tail(&bf->list, &ah->rxbuf);
1595 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1596unlock:
1597 spin_unlock(&ah->rxbuflock);
1598 ah->rx_pending = false;
1599 ath5k_set_current_imask(ah);
1600}
1601
1602
1603
1604
1605
1606
1607void
1608ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1609 struct ath5k_txq *txq, struct ieee80211_tx_control *control)
1610{
1611 struct ath5k_hw *ah = hw->priv;
1612 struct ath5k_buf *bf;
1613 unsigned long flags;
1614 int padsize;
1615
1616 trace_ath5k_tx(ah, skb, txq);
1617
1618
1619
1620
1621
1622 padsize = ath5k_add_padding(skb);
1623 if (padsize < 0) {
1624 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1625 " headroom to pad");
1626 goto drop_packet;
1627 }
1628
1629 if (txq->txq_len >= txq->txq_max &&
1630 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1631 ieee80211_stop_queue(hw, txq->qnum);
1632
1633 spin_lock_irqsave(&ah->txbuflock, flags);
1634 if (list_empty(&ah->txbuf)) {
1635 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1636 spin_unlock_irqrestore(&ah->txbuflock, flags);
1637 ieee80211_stop_queues(hw);
1638 goto drop_packet;
1639 }
1640 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1641 list_del(&bf->list);
1642 ah->txbuf_len--;
1643 if (list_empty(&ah->txbuf))
1644 ieee80211_stop_queues(hw);
1645 spin_unlock_irqrestore(&ah->txbuflock, flags);
1646
1647 bf->skb = skb;
1648
1649 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) {
1650 bf->skb = NULL;
1651 spin_lock_irqsave(&ah->txbuflock, flags);
1652 list_add_tail(&bf->list, &ah->txbuf);
1653 ah->txbuf_len++;
1654 spin_unlock_irqrestore(&ah->txbuflock, flags);
1655 goto drop_packet;
1656 }
1657 return;
1658
1659drop_packet:
1660 ieee80211_free_txskb(hw, skb);
1661}
1662
1663static void
1664ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1665 struct ath5k_txq *txq, struct ath5k_tx_status *ts,
1666 struct ath5k_buf *bf)
1667{
1668 struct ieee80211_tx_info *info;
1669 u8 tries[3];
1670 int i;
1671 int size = 0;
1672
1673 ah->stats.tx_all_count++;
1674 ah->stats.tx_bytes_count += skb->len;
1675 info = IEEE80211_SKB_CB(skb);
1676
1677 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates));
1678 memcpy(info->status.rates, bf->rates, size);
1679
1680 tries[0] = info->status.rates[0].count;
1681 tries[1] = info->status.rates[1].count;
1682 tries[2] = info->status.rates[2].count;
1683
1684 ieee80211_tx_info_clear_status(info);
1685
1686 for (i = 0; i < ts->ts_final_idx; i++) {
1687 struct ieee80211_tx_rate *r =
1688 &info->status.rates[i];
1689
1690 r->count = tries[i];
1691 }
1692
1693 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1694 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1695
1696 if (unlikely(ts->ts_status)) {
1697 ah->stats.ack_fail++;
1698 if (ts->ts_status & AR5K_TXERR_FILT) {
1699 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1700 ah->stats.txerr_filt++;
1701 }
1702 if (ts->ts_status & AR5K_TXERR_XRETRY)
1703 ah->stats.txerr_retry++;
1704 if (ts->ts_status & AR5K_TXERR_FIFO)
1705 ah->stats.txerr_fifo++;
1706 } else {
1707 info->flags |= IEEE80211_TX_STAT_ACK;
1708 info->status.ack_signal = ts->ts_rssi;
1709
1710
1711 info->status.rates[ts->ts_final_idx].count++;
1712 }
1713
1714
1715
1716
1717
1718 ath5k_remove_padding(skb);
1719
1720 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1721 ah->stats.antenna_tx[ts->ts_antenna]++;
1722 else
1723 ah->stats.antenna_tx[0]++;
1724
1725 trace_ath5k_tx_complete(ah, skb, txq, ts);
1726 ieee80211_tx_status(ah->hw, skb);
1727}
1728
1729static void
1730ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1731{
1732 struct ath5k_tx_status ts = {};
1733 struct ath5k_buf *bf, *bf0;
1734 struct ath5k_desc *ds;
1735 struct sk_buff *skb;
1736 int ret;
1737
1738 spin_lock(&txq->lock);
1739 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1740
1741 txq->txq_poll_mark = false;
1742
1743
1744 if (bf->skb != NULL) {
1745 ds = bf->desc;
1746
1747 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1748 if (unlikely(ret == -EINPROGRESS))
1749 break;
1750 else if (unlikely(ret)) {
1751 ATH5K_ERR(ah,
1752 "error %d while processing "
1753 "queue %u\n", ret, txq->qnum);
1754 break;
1755 }
1756
1757 skb = bf->skb;
1758 bf->skb = NULL;
1759
1760 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1761 DMA_TO_DEVICE);
1762 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf);
1763 }
1764
1765
1766
1767
1768
1769
1770
1771 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1772 spin_lock(&ah->txbuflock);
1773 list_move_tail(&bf->list, &ah->txbuf);
1774 ah->txbuf_len++;
1775 txq->txq_len--;
1776 spin_unlock(&ah->txbuflock);
1777 }
1778 }
1779 spin_unlock(&txq->lock);
1780 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1781 ieee80211_wake_queue(ah->hw, txq->qnum);
1782}
1783
1784static void
1785ath5k_tasklet_tx(unsigned long data)
1786{
1787 int i;
1788 struct ath5k_hw *ah = (void *)data;
1789
1790 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1791 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1792 ath5k_tx_processq(ah, &ah->txqs[i]);
1793
1794 ah->tx_pending = false;
1795 ath5k_set_current_imask(ah);
1796}
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806static int
1807ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1808{
1809 struct sk_buff *skb = bf->skb;
1810 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1811 struct ath5k_desc *ds;
1812 int ret = 0;
1813 u8 antenna;
1814 u32 flags;
1815 const int padsize = 0;
1816
1817 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1818 DMA_TO_DEVICE);
1819 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1820 "skbaddr %llx\n", skb, skb->data, skb->len,
1821 (unsigned long long)bf->skbaddr);
1822
1823 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1824 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1825 dev_kfree_skb_any(skb);
1826 bf->skb = NULL;
1827 return -EIO;
1828 }
1829
1830 ds = bf->desc;
1831 antenna = ah->ah_tx_ant;
1832
1833 flags = AR5K_TXDESC_NOACK;
1834 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1835 ds->ds_link = bf->daddr;
1836 flags |= AR5K_TXDESC_VEOL;
1837 } else
1838 ds->ds_link = 0;
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1859 antenna = ah->bsent & 4 ? 2 : 1;
1860
1861
1862
1863
1864
1865 ds->ds_data = bf->skbaddr;
1866 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1867 ieee80211_get_hdrlen_from_skb(skb), padsize,
1868 AR5K_PKT_TYPE_BEACON,
1869 (ah->ah_txpower.txp_requested * 2),
1870 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1871 1, AR5K_TXKEYIX_INVALID,
1872 antenna, flags, 0, 0);
1873 if (ret)
1874 goto err_unmap;
1875
1876 return 0;
1877err_unmap:
1878 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1879 return ret;
1880}
1881
1882
1883
1884
1885
1886
1887
1888
1889int
1890ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1891{
1892 int ret;
1893 struct ath5k_hw *ah = hw->priv;
1894 struct ath5k_vif *avf;
1895 struct sk_buff *skb;
1896
1897 if (WARN_ON(!vif)) {
1898 ret = -EINVAL;
1899 goto out;
1900 }
1901
1902 skb = ieee80211_beacon_get(hw, vif);
1903
1904 if (!skb) {
1905 ret = -ENOMEM;
1906 goto out;
1907 }
1908
1909 avf = (void *)vif->drv_priv;
1910 ath5k_txbuf_free_skb(ah, avf->bbuf);
1911 avf->bbuf->skb = skb;
1912 ret = ath5k_beacon_setup(ah, avf->bbuf);
1913out:
1914 return ret;
1915}
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925static void
1926ath5k_beacon_send(struct ath5k_hw *ah)
1927{
1928 struct ieee80211_vif *vif;
1929 struct ath5k_vif *avf;
1930 struct ath5k_buf *bf;
1931 struct sk_buff *skb;
1932 int err;
1933
1934 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1935
1936
1937
1938
1939
1940
1941
1942
1943 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1944 ah->bmisscount++;
1945 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1946 "missed %u consecutive beacons\n", ah->bmisscount);
1947 if (ah->bmisscount > 10) {
1948 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1949 "stuck beacon time (%u missed)\n",
1950 ah->bmisscount);
1951 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1952 "stuck beacon, resetting\n");
1953 ieee80211_queue_work(ah->hw, &ah->reset_work);
1954 }
1955 return;
1956 }
1957 if (unlikely(ah->bmisscount != 0)) {
1958 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1959 "resume beacon xmit after %u misses\n",
1960 ah->bmisscount);
1961 ah->bmisscount = 0;
1962 }
1963
1964 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1965 ah->num_mesh_vifs > 1) ||
1966 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1967 u64 tsf = ath5k_hw_get_tsf64(ah);
1968 u32 tsftu = TSF_TO_TU(tsf);
1969 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1970 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1971 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1972 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1973 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1974 } else
1975 vif = ah->bslot[0];
1976
1977 if (!vif)
1978 return;
1979
1980 avf = (void *)vif->drv_priv;
1981 bf = avf->bbuf;
1982
1983
1984
1985
1986
1987
1988 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1989 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1990
1991 }
1992
1993
1994 if (ah->opmode == NL80211_IFTYPE_AP ||
1995 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1996 err = ath5k_beacon_update(ah->hw, vif);
1997 if (err)
1998 return;
1999 }
2000
2001 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
2002 ah->opmode == NL80211_IFTYPE_MONITOR)) {
2003 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
2004 return;
2005 }
2006
2007 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
2008
2009 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
2010 ath5k_hw_start_tx_dma(ah, ah->bhalq);
2011 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2012 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
2013
2014 skb = ieee80211_get_buffered_bc(ah->hw, vif);
2015 while (skb) {
2016 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL);
2017
2018 if (ah->cabq->txq_len >= ah->cabq->txq_max)
2019 break;
2020
2021 skb = ieee80211_get_buffered_bc(ah->hw, vif);
2022 }
2023
2024 ah->bsent++;
2025}
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043void
2044ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
2045{
2046 u32 nexttbtt, intval, hw_tu, bc_tu;
2047 u64 hw_tsf;
2048
2049 intval = ah->bintval & AR5K_BEACON_PERIOD;
2050 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
2051 + ah->num_mesh_vifs > 1) {
2052 intval /= ATH_BCBUF;
2053 if (intval < 15)
2054 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
2055 intval);
2056 }
2057 if (WARN_ON(!intval))
2058 return;
2059
2060
2061 bc_tu = TSF_TO_TU(bc_tsf);
2062
2063
2064 hw_tsf = ath5k_hw_get_tsf64(ah);
2065 hw_tu = TSF_TO_TU(hw_tsf);
2066
2067#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
2068
2069
2070
2071
2072 if (bc_tsf == -1) {
2073
2074
2075
2076
2077 nexttbtt = roundup(hw_tu + FUDGE, intval);
2078 } else if (bc_tsf == 0) {
2079
2080
2081
2082
2083 nexttbtt = intval;
2084 intval |= AR5K_BEACON_RESET_TSF;
2085 } else if (bc_tsf > hw_tsf) {
2086
2087
2088
2089
2090
2091
2092
2093 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2094 "need to wait for HW TSF sync\n");
2095 return;
2096 } else {
2097
2098
2099
2100
2101
2102
2103
2104 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2105 }
2106#undef FUDGE
2107
2108 ah->nexttbtt = nexttbtt;
2109
2110 intval |= AR5K_BEACON_ENA;
2111 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2112
2113
2114
2115
2116
2117 if (bc_tsf == -1)
2118 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2119 "reconfigured timers based on HW TSF\n");
2120 else if (bc_tsf == 0)
2121 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2122 "reset HW TSF and timers\n");
2123 else
2124 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2125 "updated timers based on beacon TSF\n");
2126
2127 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2128 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2129 (unsigned long long) bc_tsf,
2130 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2131 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2132 intval & AR5K_BEACON_PERIOD,
2133 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2134 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2135}
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145void
2146ath5k_beacon_config(struct ath5k_hw *ah)
2147{
2148 spin_lock_bh(&ah->block);
2149 ah->bmisscount = 0;
2150 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2151
2152 if (ah->enable_beacon) {
2153
2154
2155
2156
2157
2158
2159
2160 ath5k_beaconq_config(ah);
2161
2162 ah->imask |= AR5K_INT_SWBA;
2163
2164 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2165 if (ath5k_hw_hasveol(ah))
2166 ath5k_beacon_send(ah);
2167 } else
2168 ath5k_beacon_update_timers(ah, -1);
2169 } else {
2170 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2171 }
2172
2173 ath5k_hw_set_imr(ah, ah->imask);
2174 mmiowb();
2175 spin_unlock_bh(&ah->block);
2176}
2177
2178static void ath5k_tasklet_beacon(unsigned long data)
2179{
2180 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2191
2192 u64 tsf = ath5k_hw_get_tsf64(ah);
2193 ah->nexttbtt += ah->bintval;
2194 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2195 "SWBA nexttbtt: %x hw_tu: %x "
2196 "TSF: %llx\n",
2197 ah->nexttbtt,
2198 TSF_TO_TU(tsf),
2199 (unsigned long long) tsf);
2200 } else {
2201 spin_lock(&ah->block);
2202 ath5k_beacon_send(ah);
2203 spin_unlock(&ah->block);
2204 }
2205}
2206
2207
2208
2209
2210
2211
2212static void
2213ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2214{
2215 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2216 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2217 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2218
2219
2220
2221 ah->ah_cal_next_ani = jiffies +
2222 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2223 tasklet_schedule(&ah->ani_tasklet);
2224
2225 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2226 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2227 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2228
2229
2230
2231
2232
2233
2234
2235
2236 ah->ah_cal_next_short = jiffies +
2237 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2238 ieee80211_queue_work(ah->hw, &ah->calib_work);
2239 }
2240
2241
2242
2243}
2244
2245static void
2246ath5k_schedule_rx(struct ath5k_hw *ah)
2247{
2248 ah->rx_pending = true;
2249 tasklet_schedule(&ah->rxtq);
2250}
2251
2252static void
2253ath5k_schedule_tx(struct ath5k_hw *ah)
2254{
2255 ah->tx_pending = true;
2256 tasklet_schedule(&ah->txtq);
2257}
2258
2259static irqreturn_t
2260ath5k_intr(int irq, void *dev_id)
2261{
2262 struct ath5k_hw *ah = dev_id;
2263 enum ath5k_int status;
2264 unsigned int counter = 1000;
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2278 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2279 !ath5k_hw_is_intr_pending(ah))))
2280 return IRQ_NONE;
2281
2282
2283 do {
2284 ath5k_hw_get_isr(ah, &status);
2285
2286 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2287 status, ah->imask);
2288
2289
2290
2291
2292
2293
2294
2295
2296 if (unlikely(status & AR5K_INT_FATAL)) {
2297
2298 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2299 "fatal int, resetting\n");
2300 ieee80211_queue_work(ah->hw, &ah->reset_work);
2301
2302
2303
2304
2305
2306
2307
2308
2309 } else if (unlikely(status & AR5K_INT_RXORN)) {
2310
2311
2312
2313
2314
2315
2316
2317 ah->stats.rxorn_intr++;
2318
2319 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2320 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2321 "rx overrun, resetting\n");
2322 ieee80211_queue_work(ah->hw, &ah->reset_work);
2323 } else
2324 ath5k_schedule_rx(ah);
2325
2326 } else {
2327
2328
2329 if (status & AR5K_INT_SWBA)
2330 tasklet_hi_schedule(&ah->beacontq);
2331
2332
2333
2334
2335
2336
2337
2338
2339 if (status & AR5K_INT_RXEOL)
2340 ah->stats.rxeol_intr++;
2341
2342
2343
2344 if (status & AR5K_INT_TXURN)
2345 ath5k_hw_update_tx_triglevel(ah, true);
2346
2347
2348 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2349 ath5k_schedule_rx(ah);
2350
2351
2352 if (status & (AR5K_INT_TXOK
2353 | AR5K_INT_TXDESC
2354 | AR5K_INT_TXERR
2355 | AR5K_INT_TXEOL))
2356 ath5k_schedule_tx(ah);
2357
2358
2359
2360
2361
2362
2363 if (status & AR5K_INT_MIB) {
2364 ah->stats.mib_intr++;
2365 ath5k_hw_update_mib_counters(ah);
2366 ath5k_ani_mib_intr(ah);
2367 }
2368
2369
2370 if (status & AR5K_INT_GPIO)
2371 tasklet_schedule(&ah->rf_kill.toggleq);
2372
2373 }
2374
2375 if (ath5k_get_bus_type(ah) == ATH_AHB)
2376 break;
2377
2378 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2379
2380
2381
2382
2383
2384
2385
2386 if (ah->rx_pending || ah->tx_pending)
2387 ath5k_set_current_imask(ah);
2388
2389 if (unlikely(!counter))
2390 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2391
2392
2393 ath5k_intr_calibration_poll(ah);
2394
2395 return IRQ_HANDLED;
2396}
2397
2398
2399
2400
2401
2402static void
2403ath5k_calibrate_work(struct work_struct *work)
2404{
2405 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2406 calib_work);
2407
2408
2409 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2410
2411 ah->ah_cal_next_full = jiffies +
2412 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2413 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2414
2415 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2416 "running full calibration\n");
2417
2418 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2419
2420
2421
2422
2423 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2424 "got new rfgain, resetting\n");
2425 ieee80211_queue_work(ah->hw, &ah->reset_work);
2426 }
2427 } else
2428 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2429
2430
2431 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2432 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2433 ah->curchan->hw_value);
2434
2435 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2436 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2437 ieee80211_frequency_to_channel(
2438 ah->curchan->center_freq));
2439
2440
2441 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2442 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2443 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2444 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2445}
2446
2447
2448static void
2449ath5k_tasklet_ani(unsigned long data)
2450{
2451 struct ath5k_hw *ah = (void *)data;
2452
2453 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2454 ath5k_ani_calibration(ah);
2455 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2456}
2457
2458
2459static void
2460ath5k_tx_complete_poll_work(struct work_struct *work)
2461{
2462 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2463 tx_complete_work.work);
2464 struct ath5k_txq *txq;
2465 int i;
2466 bool needreset = false;
2467
2468 if (!test_bit(ATH_STAT_STARTED, ah->status))
2469 return;
2470
2471 mutex_lock(&ah->lock);
2472
2473 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2474 if (ah->txqs[i].setup) {
2475 txq = &ah->txqs[i];
2476 spin_lock_bh(&txq->lock);
2477 if (txq->txq_len > 1) {
2478 if (txq->txq_poll_mark) {
2479 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2480 "TX queue stuck %d\n",
2481 txq->qnum);
2482 needreset = true;
2483 txq->txq_stuck++;
2484 spin_unlock_bh(&txq->lock);
2485 break;
2486 } else {
2487 txq->txq_poll_mark = true;
2488 }
2489 }
2490 spin_unlock_bh(&txq->lock);
2491 }
2492 }
2493
2494 if (needreset) {
2495 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2496 "TX queues stuck, resetting\n");
2497 ath5k_reset(ah, NULL, true);
2498 }
2499
2500 mutex_unlock(&ah->lock);
2501
2502 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2503 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2504}
2505
2506
2507
2508
2509
2510
2511static const struct ieee80211_iface_limit if_limits[] = {
2512 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2513 { .max = 4, .types =
2514#ifdef CONFIG_MAC80211_MESH
2515 BIT(NL80211_IFTYPE_MESH_POINT) |
2516#endif
2517 BIT(NL80211_IFTYPE_AP) },
2518};
2519
2520static const struct ieee80211_iface_combination if_comb = {
2521 .limits = if_limits,
2522 .n_limits = ARRAY_SIZE(if_limits),
2523 .max_interfaces = 2048,
2524 .num_different_channels = 1,
2525};
2526
2527int
2528ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2529{
2530 struct ieee80211_hw *hw = ah->hw;
2531 struct ath_common *common;
2532 int ret;
2533 int csz;
2534
2535
2536 SET_IEEE80211_DEV(hw, ah->dev);
2537 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2538 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2539 IEEE80211_HW_SIGNAL_DBM |
2540 IEEE80211_HW_MFP_CAPABLE |
2541 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
2542 IEEE80211_HW_SUPPORTS_RC_TABLE;
2543
2544 hw->wiphy->interface_modes =
2545 BIT(NL80211_IFTYPE_AP) |
2546 BIT(NL80211_IFTYPE_STATION) |
2547 BIT(NL80211_IFTYPE_ADHOC) |
2548 BIT(NL80211_IFTYPE_MESH_POINT);
2549
2550 hw->wiphy->iface_combinations = &if_comb;
2551 hw->wiphy->n_iface_combinations = 1;
2552
2553
2554 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2555
2556 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2557
2558
2559 hw->wiphy->available_antennas_tx = 0x3;
2560 hw->wiphy->available_antennas_rx = 0x3;
2561
2562 hw->extra_tx_headroom = 2;
2563
2564
2565
2566
2567
2568 __set_bit(ATH_STAT_INVALID, ah->status);
2569
2570 ah->opmode = NL80211_IFTYPE_STATION;
2571 ah->bintval = 1000;
2572 mutex_init(&ah->lock);
2573 spin_lock_init(&ah->rxbuflock);
2574 spin_lock_init(&ah->txbuflock);
2575 spin_lock_init(&ah->block);
2576 spin_lock_init(&ah->irqlock);
2577
2578
2579 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2580 if (ret) {
2581 ATH5K_ERR(ah, "request_irq failed\n");
2582 goto err;
2583 }
2584
2585 common = ath5k_hw_common(ah);
2586 common->ops = &ath5k_common_ops;
2587 common->bus_ops = bus_ops;
2588 common->ah = ah;
2589 common->hw = hw;
2590 common->priv = ah;
2591 common->clockrate = 40;
2592
2593
2594
2595
2596
2597 ath5k_read_cachesize(common, &csz);
2598 common->cachelsz = csz << 2;
2599
2600 spin_lock_init(&common->cc_lock);
2601
2602
2603 ret = ath5k_hw_init(ah);
2604 if (ret)
2605 goto err_irq;
2606
2607
2608 if (ah->ah_capabilities.cap_has_mrr_support) {
2609 hw->max_rates = 4;
2610 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2611 AR5K_INIT_RETRY_LONG);
2612 }
2613
2614 hw->vif_data_size = sizeof(struct ath5k_vif);
2615
2616
2617 ret = ath5k_init(hw);
2618 if (ret)
2619 goto err_ah;
2620
2621 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2622 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2623 ah->ah_mac_srev,
2624 ah->ah_phy_revision);
2625
2626 if (!ah->ah_single_chip) {
2627
2628 if (ah->ah_radio_5ghz_revision &&
2629 !ah->ah_radio_2ghz_revision) {
2630
2631 if (!test_bit(AR5K_MODE_11A,
2632 ah->ah_capabilities.cap_mode)) {
2633 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2634 ath5k_chip_name(AR5K_VERSION_RAD,
2635 ah->ah_radio_5ghz_revision),
2636 ah->ah_radio_5ghz_revision);
2637
2638
2639 } else if (!test_bit(AR5K_MODE_11B,
2640 ah->ah_capabilities.cap_mode)) {
2641 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2642 ath5k_chip_name(AR5K_VERSION_RAD,
2643 ah->ah_radio_5ghz_revision),
2644 ah->ah_radio_5ghz_revision);
2645
2646 } else {
2647 ATH5K_INFO(ah, "RF%s multiband radio found"
2648 " (0x%x)\n",
2649 ath5k_chip_name(AR5K_VERSION_RAD,
2650 ah->ah_radio_5ghz_revision),
2651 ah->ah_radio_5ghz_revision);
2652 }
2653 }
2654
2655
2656 else if (ah->ah_radio_5ghz_revision &&
2657 ah->ah_radio_2ghz_revision) {
2658 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2659 ath5k_chip_name(AR5K_VERSION_RAD,
2660 ah->ah_radio_5ghz_revision),
2661 ah->ah_radio_5ghz_revision);
2662 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2663 ath5k_chip_name(AR5K_VERSION_RAD,
2664 ah->ah_radio_2ghz_revision),
2665 ah->ah_radio_2ghz_revision);
2666 }
2667 }
2668
2669 ath5k_debug_init_device(ah);
2670
2671
2672 __clear_bit(ATH_STAT_INVALID, ah->status);
2673
2674 return 0;
2675err_ah:
2676 ath5k_hw_deinit(ah);
2677err_irq:
2678 free_irq(ah->irq, ah);
2679err:
2680 return ret;
2681}
2682
2683static int
2684ath5k_stop_locked(struct ath5k_hw *ah)
2685{
2686
2687 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2688 test_bit(ATH_STAT_INVALID, ah->status));
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705 ieee80211_stop_queues(ah->hw);
2706
2707 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2708 ath5k_led_off(ah);
2709 ath5k_hw_set_imr(ah, 0);
2710 synchronize_irq(ah->irq);
2711 ath5k_rx_stop(ah);
2712 ath5k_hw_dma_stop(ah);
2713 ath5k_drain_tx_buffs(ah);
2714 ath5k_hw_phy_disable(ah);
2715 }
2716
2717 return 0;
2718}
2719
2720int ath5k_start(struct ieee80211_hw *hw)
2721{
2722 struct ath5k_hw *ah = hw->priv;
2723 struct ath_common *common = ath5k_hw_common(ah);
2724 int ret, i;
2725
2726 mutex_lock(&ah->lock);
2727
2728 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2729
2730
2731
2732
2733
2734 ath5k_stop_locked(ah);
2735
2736
2737
2738
2739
2740
2741
2742
2743 ah->curchan = ah->hw->conf.chandef.chan;
2744 ah->imask = AR5K_INT_RXOK
2745 | AR5K_INT_RXERR
2746 | AR5K_INT_RXEOL
2747 | AR5K_INT_RXORN
2748 | AR5K_INT_TXDESC
2749 | AR5K_INT_TXEOL
2750 | AR5K_INT_FATAL
2751 | AR5K_INT_GLOBAL
2752 | AR5K_INT_MIB;
2753
2754 ret = ath5k_reset(ah, NULL, false);
2755 if (ret)
2756 goto done;
2757
2758 if (!ath5k_modparam_no_hw_rfkill_switch)
2759 ath5k_rfkill_hw_start(ah);
2760
2761
2762
2763
2764
2765 for (i = 0; i < common->keymax; i++)
2766 ath_hw_keyreset(common, (u16) i);
2767
2768
2769
2770 ah->ah_ack_bitrate_high = true;
2771
2772 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2773 ah->bslot[i] = NULL;
2774
2775 ret = 0;
2776done:
2777 mmiowb();
2778 mutex_unlock(&ah->lock);
2779
2780 set_bit(ATH_STAT_STARTED, ah->status);
2781 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2782 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2783
2784 return ret;
2785}
2786
2787static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2788{
2789 ah->rx_pending = false;
2790 ah->tx_pending = false;
2791 tasklet_kill(&ah->rxtq);
2792 tasklet_kill(&ah->txtq);
2793 tasklet_kill(&ah->beacontq);
2794 tasklet_kill(&ah->ani_tasklet);
2795}
2796
2797
2798
2799
2800
2801
2802
2803void ath5k_stop(struct ieee80211_hw *hw)
2804{
2805 struct ath5k_hw *ah = hw->priv;
2806 int ret;
2807
2808 mutex_lock(&ah->lock);
2809 ret = ath5k_stop_locked(ah);
2810 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831 ret = ath5k_hw_on_hold(ah);
2832
2833 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2834 "putting device to sleep\n");
2835 }
2836
2837 mmiowb();
2838 mutex_unlock(&ah->lock);
2839
2840 ath5k_stop_tasklets(ah);
2841
2842 clear_bit(ATH_STAT_STARTED, ah->status);
2843 cancel_delayed_work_sync(&ah->tx_complete_work);
2844
2845 if (!ath5k_modparam_no_hw_rfkill_switch)
2846 ath5k_rfkill_hw_stop(ah);
2847}
2848
2849
2850
2851
2852
2853
2854
2855static int
2856ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2857 bool skip_pcu)
2858{
2859 struct ath_common *common = ath5k_hw_common(ah);
2860 int ret, ani_mode;
2861 bool fast;
2862
2863 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2864
2865 ath5k_hw_set_imr(ah, 0);
2866 synchronize_irq(ah->irq);
2867 ath5k_stop_tasklets(ah);
2868
2869
2870
2871
2872 ani_mode = ah->ani_state.ani_mode;
2873 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2874
2875
2876
2877
2878 ath5k_drain_tx_buffs(ah);
2879 if (chan)
2880 ah->curchan = chan;
2881
2882 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2883
2884 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2885 if (ret) {
2886 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2887 goto err;
2888 }
2889
2890 ret = ath5k_rx_start(ah);
2891 if (ret) {
2892 ATH5K_ERR(ah, "can't start recv logic\n");
2893 goto err;
2894 }
2895
2896 ath5k_ani_init(ah, ani_mode);
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909 ah->ah_cal_next_full = jiffies +
2910 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2911 ah->ah_cal_next_ani = jiffies +
2912 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2913 ah->ah_cal_next_short = jiffies +
2914 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2915
2916 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2917
2918
2919 memset(&ah->survey, 0, sizeof(ah->survey));
2920 spin_lock_bh(&common->cc_lock);
2921 ath_hw_cycle_counters_update(common);
2922 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2923 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2924 spin_unlock_bh(&common->cc_lock);
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937 ath5k_beacon_config(ah);
2938
2939
2940 ieee80211_wake_queues(ah->hw);
2941
2942 return 0;
2943err:
2944 return ret;
2945}
2946
2947static void ath5k_reset_work(struct work_struct *work)
2948{
2949 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2950 reset_work);
2951
2952 mutex_lock(&ah->lock);
2953 ath5k_reset(ah, NULL, true);
2954 mutex_unlock(&ah->lock);
2955}
2956
2957static int
2958ath5k_init(struct ieee80211_hw *hw)
2959{
2960
2961 struct ath5k_hw *ah = hw->priv;
2962 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2963 struct ath5k_txq *txq;
2964 u8 mac[ETH_ALEN] = {};
2965 int ret;
2966
2967
2968
2969
2970
2971
2972
2973
2974 ret = ath5k_setup_bands(hw);
2975 if (ret) {
2976 ATH5K_ERR(ah, "can't get channels\n");
2977 goto err;
2978 }
2979
2980
2981
2982
2983 ret = ath5k_desc_alloc(ah);
2984 if (ret) {
2985 ATH5K_ERR(ah, "can't allocate descriptors\n");
2986 goto err;
2987 }
2988
2989
2990
2991
2992
2993
2994
2995 ret = ath5k_beaconq_setup(ah);
2996 if (ret < 0) {
2997 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2998 goto err_desc;
2999 }
3000 ah->bhalq = ret;
3001 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
3002 if (IS_ERR(ah->cabq)) {
3003 ATH5K_ERR(ah, "can't setup cab queue\n");
3004 ret = PTR_ERR(ah->cabq);
3005 goto err_bhal;
3006 }
3007
3008
3009
3010 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
3011
3012
3013 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
3014 if (IS_ERR(txq)) {
3015 ATH5K_ERR(ah, "can't setup xmit queue\n");
3016 ret = PTR_ERR(txq);
3017 goto err_queues;
3018 }
3019 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
3020 if (IS_ERR(txq)) {
3021 ATH5K_ERR(ah, "can't setup xmit queue\n");
3022 ret = PTR_ERR(txq);
3023 goto err_queues;
3024 }
3025 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3026 if (IS_ERR(txq)) {
3027 ATH5K_ERR(ah, "can't setup xmit queue\n");
3028 ret = PTR_ERR(txq);
3029 goto err_queues;
3030 }
3031 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
3032 if (IS_ERR(txq)) {
3033 ATH5K_ERR(ah, "can't setup xmit queue\n");
3034 ret = PTR_ERR(txq);
3035 goto err_queues;
3036 }
3037 hw->queues = 4;
3038 } else {
3039
3040 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3041 if (IS_ERR(txq)) {
3042 ATH5K_ERR(ah, "can't setup xmit queue\n");
3043 ret = PTR_ERR(txq);
3044 goto err_queues;
3045 }
3046 hw->queues = 1;
3047 }
3048
3049 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
3050 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
3051 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
3052 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
3053
3054 INIT_WORK(&ah->reset_work, ath5k_reset_work);
3055 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
3056 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
3057
3058 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
3059 if (ret) {
3060 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
3061 goto err_queues;
3062 }
3063
3064 SET_IEEE80211_PERM_ADDR(hw, mac);
3065
3066 ath5k_update_bssid_mask_and_opmode(ah, NULL);
3067
3068 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
3069 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
3070 if (ret) {
3071 ATH5K_ERR(ah, "can't initialize regulatory system\n");
3072 goto err_queues;
3073 }
3074
3075 ret = ieee80211_register_hw(hw);
3076 if (ret) {
3077 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
3078 goto err_queues;
3079 }
3080
3081 if (!ath_is_world_regd(regulatory))
3082 regulatory_hint(hw->wiphy, regulatory->alpha2);
3083
3084 ath5k_init_leds(ah);
3085
3086 ath5k_sysfs_register(ah);
3087
3088 return 0;
3089err_queues:
3090 ath5k_txq_release(ah);
3091err_bhal:
3092 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3093err_desc:
3094 ath5k_desc_free(ah);
3095err:
3096 return ret;
3097}
3098
3099void
3100ath5k_deinit_ah(struct ath5k_hw *ah)
3101{
3102 struct ieee80211_hw *hw = ah->hw;
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117 ieee80211_unregister_hw(hw);
3118 ath5k_desc_free(ah);
3119 ath5k_txq_release(ah);
3120 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3121 ath5k_unregister_leds(ah);
3122
3123 ath5k_sysfs_unregister(ah);
3124
3125
3126
3127
3128
3129 ath5k_hw_deinit(ah);
3130 free_irq(ah->irq, ah);
3131}
3132
3133bool
3134ath5k_any_vif_assoc(struct ath5k_hw *ah)
3135{
3136 struct ath5k_vif_iter_data iter_data;
3137 iter_data.hw_macaddr = NULL;
3138 iter_data.any_assoc = false;
3139 iter_data.need_set_hw_addr = false;
3140 iter_data.found_active = true;
3141
3142 ieee80211_iterate_active_interfaces_atomic(
3143 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3144 ath5k_vif_iter, &iter_data);
3145 return iter_data.any_assoc;
3146}
3147
3148void
3149ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3150{
3151 struct ath5k_hw *ah = hw->priv;
3152 u32 rfilt;
3153 rfilt = ath5k_hw_get_rx_filter(ah);
3154 if (enable)
3155 rfilt |= AR5K_RX_FILTER_BEACON;
3156 else
3157 rfilt &= ~AR5K_RX_FILTER_BEACON;
3158 ath5k_hw_set_rx_filter(ah, rfilt);
3159 ah->filter_flags = rfilt;
3160}
3161
3162void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3163 const char *fmt, ...)
3164{
3165 struct va_format vaf;
3166 va_list args;
3167
3168 va_start(args, fmt);
3169
3170 vaf.fmt = fmt;
3171 vaf.va = &args;
3172
3173 if (ah && ah->hw)
3174 printk("%s" pr_fmt("%s: %pV"),
3175 level, wiphy_name(ah->hw->wiphy), &vaf);
3176 else
3177 printk("%s" pr_fmt("%pV"), level, &vaf);
3178
3179 va_end(args);
3180}
3181