LXR linux/drivers/net/wireless/rtlwifi/pci.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2012  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 * wlanfae <wlanfae@realtek.com>
  23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24 * Hsinchu 300, Taiwan.
  25 *
  26 * Larry Finger <Larry.Finger@lwfinger.net>
  27 *
  28 *****************************************************************************/
  29
  30#ifndef __RTL_PCI_H__
  31#define __RTL_PCI_H__
  32
  33#include <linux/pci.h>
  34/*
  351: MSDU packet queue,
  362: Rx Command Queue
  37*/
  38#define RTL_PCI_RX_MPDU_QUEUE                   0
  39#define RTL_PCI_RX_CMD_QUEUE                    1
  40#define RTL_PCI_MAX_RX_QUEUE                    2
  41
  42#define RTL_PCI_MAX_RX_COUNT                    512/*64*/
  43#define RTL_PCI_MAX_TX_QUEUE_COUNT              9
  44
  45#define RT_TXDESC_NUM                           128
  46#define TX_DESC_NUM_92E                         512
  47#define RT_TXDESC_NUM_BE_QUEUE                  256
  48
  49#define BK_QUEUE                                0
  50#define BE_QUEUE                                1
  51#define VI_QUEUE                                2
  52#define VO_QUEUE                                3
  53#define BEACON_QUEUE                            4
  54#define TXCMD_QUEUE                             5
  55#define MGNT_QUEUE                              6
  56#define HIGH_QUEUE                              7
  57#define HCCA_QUEUE                              8
  58
  59#define RTL_PCI_DEVICE(vend, dev, cfg)  \
  60        .vendor = (vend), \
  61        .device = (dev), \
  62        .subvendor = PCI_ANY_ID, \
  63        .subdevice = PCI_ANY_ID,\
  64        .driver_data = (kernel_ulong_t)&(cfg)
  65
  66#define INTEL_VENDOR_ID                         0x8086
  67#define SIS_VENDOR_ID                           0x1039
  68#define ATI_VENDOR_ID                           0x1002
  69#define ATI_DEVICE_ID                           0x7914
  70#define AMD_VENDOR_ID                           0x1022
  71
  72#define PCI_MAX_BRIDGE_NUMBER                   255
  73#define PCI_MAX_DEVICES                         32
  74#define PCI_MAX_FUNCTION                        8
  75
  76#define PCI_CONF_ADDRESS        0x0CF8  /*PCI Configuration Space Address */
  77#define PCI_CONF_DATA           0x0CFC  /*PCI Configuration Space Data */
  78
  79#define PCI_CLASS_BRIDGE_DEV            0x06
  80#define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  81#define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  82#define PCI_CAP_ID_EXP                  0x10
  83
  84#define U1DONTCARE                      0xFF
  85#define U2DONTCARE                      0xFFFF
  86#define U4DONTCARE                      0xFFFFFFFF
  87
  88#define RTL_PCI_8192_DID        0x8192  /*8192 PCI-E */
  89#define RTL_PCI_8192SE_DID      0x8192  /*8192 SE */
  90#define RTL_PCI_8174_DID        0x8174  /*8192 SE */
  91#define RTL_PCI_8173_DID        0x8173  /*8191 SE Crab */
  92#define RTL_PCI_8172_DID        0x8172  /*8191 SE RE */
  93#define RTL_PCI_8171_DID        0x8171  /*8191 SE Unicron */
  94#define RTL_PCI_8723AE_DID      0x8723  /*8723AE */
  95#define RTL_PCI_0045_DID        0x0045  /*8190 PCI for Ceraga */
  96#define RTL_PCI_0046_DID        0x0046  /*8190 Cardbus for Ceraga */
  97#define RTL_PCI_0044_DID        0x0044  /*8192e PCIE for Ceraga */
  98#define RTL_PCI_0047_DID        0x0047  /*8192e Express Card for Ceraga */
  99#define RTL_PCI_700F_DID        0x700F
 100#define RTL_PCI_701F_DID        0x701F
 101#define RTL_PCI_DLINK_DID       0x3304
 102#define RTL_PCI_8723AE_DID      0x8723  /*8723e */
 103#define RTL_PCI_8192CET_DID     0x8191  /*8192ce */
 104#define RTL_PCI_8192CE_DID      0x8178  /*8192ce */
 105#define RTL_PCI_8191CE_DID      0x8177  /*8192ce */
 106#define RTL_PCI_8188CE_DID      0x8176  /*8192ce */
 107#define RTL_PCI_8192CU_DID      0x8191  /*8192ce */
 108#define RTL_PCI_8192DE_DID      0x8193  /*8192de */
 109#define RTL_PCI_8192DE_DID2     0x002B  /*92DE*/
 110#define RTL_PCI_8188EE_DID      0x8179  /*8188ee*/
 111#define RTL_PCI_8723BE_DID      0xB723  /*8723be*/
 112#define RTL_PCI_8192EE_DID      0x818B  /*8192ee*/
 113#define RTL_PCI_8821AE_DID      0x8821  /*8821ae*/
 114#define RTL_PCI_8812AE_DID      0x8812  /*8812ae*/
 115
 116/*8192 support 16 pages of IO registers*/
 117#define RTL_MEM_MAPPED_IO_RANGE_8190PCI         0x1000
 118#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE        0x4000
 119#define RTL_MEM_MAPPED_IO_RANGE_8192SE          0x4000
 120#define RTL_MEM_MAPPED_IO_RANGE_8192CE          0x4000
 121#define RTL_MEM_MAPPED_IO_RANGE_8192DE          0x4000
 122
 123#define RTL_PCI_REVISION_ID_8190PCI             0x00
 124#define RTL_PCI_REVISION_ID_8192PCIE            0x01
 125#define RTL_PCI_REVISION_ID_8192SE              0x10
 126#define RTL_PCI_REVISION_ID_8192CE              0x1
 127#define RTL_PCI_REVISION_ID_8192DE              0x0
 128
 129#define RTL_DEFAULT_HARDWARE_TYPE       HARDWARE_TYPE_RTL8192CE
 130
 131enum pci_bridge_vendor {
 132        PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
 133        PCI_BRIDGE_VENDOR_ATI,          /*0b'0000,0010*/
 134        PCI_BRIDGE_VENDOR_AMD,          /*0b'0000,0100*/
 135        PCI_BRIDGE_VENDOR_SIS,          /*0b'0000,1000*/
 136        PCI_BRIDGE_VENDOR_UNKNOWN,      /*0b'0100,0000*/
 137        PCI_BRIDGE_VENDOR_MAX,
 138};
 139
 140struct rtl_pci_capabilities_header {
 141        u8 capability_id;
 142        u8 next;
 143};
 144
 145/* In new TRX flow, Buffer_desc is new concept
 146 * But TX wifi info == TX descriptor in old flow
 147 * RX wifi info == RX descriptor in old flow
 148 */
 149struct rtl_tx_buffer_desc {
 150#if (RTL8192EE_SEG_NUM == 2)
 151        u32 dword[2*(DMA_IS_64BIT + 1)*8]; /*seg = 8*/
 152#elif (RTL8192EE_SEG_NUM == 1)
 153        u32 dword[2*(DMA_IS_64BIT + 1)*4]; /*seg = 4*/
 154#elif (RTL8192EE_SEG_NUM == 0)
 155        u32 dword[2*(DMA_IS_64BIT + 1)*2]; /*seg = 2*/
 156#endif
 157} __packed;
 158
 159struct rtl_tx_desc {
 160        u32 dword[16];
 161} __packed;
 162
 163struct rtl_rx_buffer_desc { /*rx buffer desc*/
 164        u32 dword[2];
 165} __packed;
 166
 167struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
 168        u32 dword[8];
 169} __packed;
 170
 171struct rtl_tx_cmd_desc {
 172        u32 dword[16];
 173} __packed;
 174
 175struct rtl8192_tx_ring {
 176        struct rtl_tx_desc *desc;
 177        dma_addr_t dma;
 178        unsigned int idx;
 179        unsigned int entries;
 180        struct sk_buff_head queue;
 181        /*add for new trx flow*/
 182        struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
 183        dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
 184        u16 avl_desc; /* available_desc_to_write */
 185        u16 cur_tx_wp; /* current_tx_write_point */
 186        u16 cur_tx_rp; /* current_tx_read_point */
 187};
 188
 189struct rtl8192_rx_ring {
 190        struct rtl_rx_desc *desc;
 191        dma_addr_t dma;
 192        unsigned int idx;
 193        struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
 194        /*add for new trx flow*/
 195        struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
 196        u16 next_rx_rp; /* next_rx_read_point */
 197};
 198
 199struct rtl_pci {
 200        struct pci_dev *pdev;
 201        bool irq_enabled;
 202
 203        bool driver_is_goingto_unload;
 204        bool up_first_time;
 205        bool first_init;
 206        bool being_init_adapter;
 207        bool init_ready;
 208
 209        /*Tx */
 210        struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
 211        int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
 212        u32 transmit_config;
 213
 214        /*Rx */
 215        struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
 216        int rxringcount;
 217        u16 rxbuffersize;
 218        u32 receive_config;
 219
 220        /*irq */
 221        u8 irq_alloc;
 222        u32 irq_mask[2];
 223        u32 sys_irq_mask;
 224
 225        /*Bcn control register setting */
 226        u32 reg_bcn_ctrl_val;
 227
 228         /*ASPM*/ u8 const_pci_aspm;
 229        u8 const_amdpci_aspm;
 230        u8 const_hwsw_rfoff_d3;
 231        u8 const_support_pciaspm;
 232        /*pci-e bridge */
 233        u8 const_hostpci_aspm_setting;
 234        /*pci-e device */
 235        u8 const_devicepci_aspm_setting;
 236        /*If it supports ASPM, Offset[560h] = 0x40,
 237           otherwise Offset[560h] = 0x00. */
 238        bool support_aspm;
 239        bool support_backdoor;
 240
 241        /*QOS & EDCA */
 242        enum acm_method acm_method;
 243
 244        u16 shortretry_limit;
 245        u16 longretry_limit;
 246
 247        /* MSI support */
 248        bool msi_support;
 249        bool using_msi;
 250};
 251
 252struct mp_adapter {
 253        u8 linkctrl_reg;
 254
 255        u8 busnumber;
 256        u8 devnumber;
 257        u8 funcnumber;
 258
 259        u8 pcibridge_busnum;
 260        u8 pcibridge_devnum;
 261        u8 pcibridge_funcnum;
 262
 263        u8 pcibridge_vendor;
 264        u16 pcibridge_vendorid;
 265        u16 pcibridge_deviceid;
 266
 267        u8 num4bytes;
 268
 269        u8 pcibridge_pciehdr_offset;
 270        u8 pcibridge_linkctrlreg;
 271
 272        bool amd_l1_patch;
 273};
 274
 275struct rtl_pci_priv {
 276        struct rtl_pci dev;
 277        struct mp_adapter ndis_adapter;
 278        struct rtl_led_ctl ledctl;
 279        struct bt_coexist_info bt_coexist;
 280};
 281
 282#define rtl_pcipriv(hw)         (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
 283#define rtl_pcidev(pcipriv)     (&((pcipriv)->dev))
 284
 285int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
 286
 287extern struct rtl_intf_ops rtl_pci_ops;
 288
 289int rtl_pci_probe(struct pci_dev *pdev,
 290                            const struct pci_device_id *id);
 291void rtl_pci_disconnect(struct pci_dev *pdev);
 292#ifdef CONFIG_PM_SLEEP
 293int rtl_pci_suspend(struct device *dev);
 294int rtl_pci_resume(struct device *dev);
 295#endif /* CONFIG_PM_SLEEP */
 296static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
 297{
 298        return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 299}
 300
 301static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
 302{
 303        return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 304}
 305
 306static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
 307{
 308        return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 309}
 310
 311static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
 312{
 313        writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 314}
 315
 316static inline void pci_write16_async(struct rtl_priv *rtlpriv,
 317                                     u32 addr, u16 val)
 318{
 319        writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 320}
 321
 322static inline void pci_write32_async(struct rtl_priv *rtlpriv,
 323                                     u32 addr, u32 val)
 324{
 325        writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 326}
 327
 328static inline u16 calc_fifo_space(u16 rp, u16 wp)
 329{
 330        if (rp <= wp)
 331                return RTL_PCI_MAX_RX_COUNT - 1 + rp - wp;
 332        return rp - wp - 1;
 333}
 334
 335#endif
 336