LXR linux/drivers/parport/parport

   1/*
   2 * Support for common PCI multi-I/O cards (which is most of them)
   3 *
   4 * Copyright (C) 2001  Tim Waugh <twaugh@redhat.com>
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version
   9 * 2 of the License, or (at your option) any later version.
  10 *
  11 *
  12 * Multi-function PCI cards are supposed to present separate logical
  13 * devices on the bus.  A common thing to do seems to be to just use
  14 * one logical device with lots of base address registers for both
  15 * parallel ports and serial ports.  This driver is for dealing with
  16 * that.
  17 *
  18 */
  19
  20#include <linux/types.h>
  21#include <linux/module.h>
  22#include <linux/init.h>
  23#include <linux/slab.h>
  24#include <linux/pci.h>
  25#include <linux/interrupt.h>
  26#include <linux/parport.h>
  27#include <linux/parport_pc.h>
  28#include <linux/8250_pci.h>
  29
  30enum parport_pc_pci_cards {
  31        titan_110l = 0,
  32        titan_210l,
  33        netmos_9xx5_combo,
  34        netmos_9855,
  35        netmos_9855_2p,
  36        netmos_9900,
  37        netmos_9900_2p,
  38        netmos_99xx_1p,
  39        avlab_1s1p,
  40        avlab_1s2p,
  41        avlab_2s1p,
  42        siig_1s1p_10x,
  43        siig_2s1p_10x,
  44        siig_2p1s_20x,
  45        siig_1s1p_20x,
  46        siig_2s1p_20x,
  47        timedia_4078a,
  48        timedia_4079h,
  49        timedia_4085h,
  50        timedia_4088a,
  51        timedia_4089a,
  52        timedia_4095a,
  53        timedia_4096a,
  54        timedia_4078u,
  55        timedia_4079a,
  56        timedia_4085u,
  57        timedia_4079r,
  58        timedia_4079s,
  59        timedia_4079d,
  60        timedia_4079e,
  61        timedia_4079f,
  62        timedia_9079a,
  63        timedia_9079b,
  64        timedia_9079c,
  65        wch_ch353_1s1p,
  66        wch_ch353_2s1p,
  67        wch_ch382_2s1p,
  68        sunix_2s1p,
  69};
  70
  71/* each element directly indexed from enum list, above */
  72struct parport_pc_pci {
  73        int numports;
  74        struct { /* BAR (base address registers) numbers in the config
  75                    space header */
  76                int lo;
  77                int hi; /* -1 if not there, >6 for offset-method (max
  78                           BAR is 6) */
  79        } addr[4];
  80
  81        /* If set, this is called immediately after pci_enable_device.
  82         * If it returns non-zero, no probing will take place and the
  83         * ports will not be used. */
  84        int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
  85                                int autoirq, int autodma);
  86
  87        /* If set, this is called after probing for ports.  If 'failed'
  88         * is non-zero we couldn't use any of the ports. */
  89        void (*postinit_hook) (struct pci_dev *pdev,
  90                                struct parport_pc_pci *card, int failed);
  91};
  92
  93static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
  94                                int autoirq, int autodma)
  95{
  96        /* the rule described below doesn't hold for this device */
  97        if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
  98                        dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  99                        dev->subsystem_device == 0x0299)
 100                return -ENODEV;
 101
 102        if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
 103                par->numports = 1;
 104        } else {
 105                /*
 106                 * Netmos uses the subdevice ID to indicate the number of parallel
 107                 * and serial ports.  The form is 0x00PS, where <P> is the number of
 108                 * parallel ports and <S> is the number of serial ports.
 109                 */
 110                par->numports = (dev->subsystem_device & 0xf0) >> 4;
 111                if (par->numports > ARRAY_SIZE(par->addr))
 112                        par->numports = ARRAY_SIZE(par->addr);
 113        }
 114
 115        return 0;
 116}
 117
 118static struct parport_pc_pci cards[] = {
 119        /* titan_110l */                { 1, { { 3, -1 }, } },
 120        /* titan_210l */                { 1, { { 3, -1 }, } },
 121        /* netmos_9xx5_combo */         { 1, { { 2, -1 }, }, netmos_parallel_init },
 122        /* netmos_9855 */               { 1, { { 0, -1 }, }, netmos_parallel_init },
 123        /* netmos_9855_2p */            { 2, { { 0, -1 }, { 2, -1 }, } },
 124        /* netmos_9900 */               {1, { { 3, 4 }, }, netmos_parallel_init },
 125        /* netmos_9900_2p */            {2, { { 0, 1 }, { 3, 4 }, } },
 126        /* netmos_99xx_1p */            {1, { { 0, 1 }, } },
 127        /* avlab_1s1p     */            { 1, { { 1, 2}, } },
 128        /* avlab_1s2p     */            { 2, { { 1, 2}, { 3, 4 },} },
 129        /* avlab_2s1p     */            { 1, { { 2, 3}, } },
 130        /* siig_1s1p_10x */             { 1, { { 3, 4 }, } },
 131        /* siig_2s1p_10x */             { 1, { { 4, 5 }, } },
 132        /* siig_2p1s_20x */             { 2, { { 1, 2 }, { 3, 4 }, } },
 133        /* siig_1s1p_20x */             { 1, { { 1, 2 }, } },
 134        /* siig_2s1p_20x */             { 1, { { 2, 3 }, } },
 135        /* timedia_4078a */             { 1, { { 2, -1 }, } },
 136        /* timedia_4079h */             { 1, { { 2, 3 }, } },
 137        /* timedia_4085h */             { 2, { { 2, -1 }, { 4, -1 }, } },
 138        /* timedia_4088a */             { 2, { { 2, 3 }, { 4, 5 }, } },
 139        /* timedia_4089a */             { 2, { { 2, 3 }, { 4, 5 }, } },
 140        /* timedia_4095a */             { 2, { { 2, 3 }, { 4, 5 }, } },
 141        /* timedia_4096a */             { 2, { { 2, 3 }, { 4, 5 }, } },
 142        /* timedia_4078u */             { 1, { { 2, -1 }, } },
 143        /* timedia_4079a */             { 1, { { 2, 3 }, } },
 144        /* timedia_4085u */             { 2, { { 2, -1 }, { 4, -1 }, } },
 145        /* timedia_4079r */             { 1, { { 2, 3 }, } },
 146        /* timedia_4079s */             { 1, { { 2, 3 }, } },
 147        /* timedia_4079d */             { 1, { { 2, 3 }, } },
 148        /* timedia_4079e */             { 1, { { 2, 3 }, } },
 149        /* timedia_4079f */             { 1, { { 2, 3 }, } },
 150        /* timedia_9079a */             { 1, { { 2, 3 }, } },
 151        /* timedia_9079b */             { 1, { { 2, 3 }, } },
 152        /* timedia_9079c */             { 1, { { 2, 3 }, } },
 153        /* wch_ch353_1s1p*/             { 1, { { 1, -1}, } },
 154        /* wch_ch353_2s1p*/             { 1, { { 2, -1}, } },
 155        /* wch_ch382_2s1p*/             { 1, { { 2, -1}, } },
 156        /* sunix_2s1p */                { 1, { { 3, -1 }, } },
 157};
 158
 159#define PCI_VENDOR_ID_SUNIX             0x1fd4
 160#define PCI_DEVICE_ID_SUNIX_1999        0x1999
 161
 162static struct pci_device_id parport_serial_pci_tbl[] = {
 163        /* PCI cards */
 164        { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
 165          PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
 166        { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
 167          PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
 168        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
 169          PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
 170        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
 171          PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
 172        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
 173          PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
 174        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
 175          PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
 176        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
 177          0x1000, 0x0020, 0, 0, netmos_9855_2p },
 178        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
 179          0x1000, 0x0022, 0, 0, netmos_9855_2p },
 180        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
 181          PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
 182        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
 183          0xA000, 0x3011, 0, 0, netmos_9900 },
 184        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
 185          0xA000, 0x3012, 0, 0, netmos_9900 },
 186        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
 187          0xA000, 0x3020, 0, 0, netmos_9900_2p },
 188        { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
 189          0xA000, 0x2000, 0, 0, netmos_99xx_1p },
 190        /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
 191        { PCI_VENDOR_ID_AFAVLAB, 0x2110,
 192          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
 193        { PCI_VENDOR_ID_AFAVLAB, 0x2111,
 194          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
 195        { PCI_VENDOR_ID_AFAVLAB, 0x2112,
 196          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
 197        { PCI_VENDOR_ID_AFAVLAB, 0x2140,
 198          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
 199        { PCI_VENDOR_ID_AFAVLAB, 0x2141,
 200          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
 201        { PCI_VENDOR_ID_AFAVLAB, 0x2142,
 202          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
 203        { PCI_VENDOR_ID_AFAVLAB, 0x2160,
 204          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
 205        { PCI_VENDOR_ID_AFAVLAB, 0x2161,
 206          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
 207        { PCI_VENDOR_ID_AFAVLAB, 0x2162,
 208          PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
 209        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
 210          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
 211        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
 212          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
 213        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
 214          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
 215        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
 216          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
 217        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
 218          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
 219        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
 220          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
 221        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
 222          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
 223        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
 224          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
 225        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
 226          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
 227        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
 228          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
 229        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
 230          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
 231        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
 232          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
 233        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
 234          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
 235        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
 236          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
 237        { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
 238          PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
 239        /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
 240        { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
 241        { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
 242        { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
 243        { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
 244        { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
 245        { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
 246        { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
 247        { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
 248        { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
 249        { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
 250        { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
 251        { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
 252        { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
 253        { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
 254        { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
 255        { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
 256        { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
 257        { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
 258
 259        /* WCH CARDS */
 260        { 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
 261        { 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
 262        { 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p},
 263
 264        /*
 265         * More SUNIX variations. At least one of these has part number
 266         * '5079A but subdevice 0x102. That board reports 0x0708 as
 267         * its PCI Class.
 268         */
 269        { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
 270          0x0102, 0, 0, sunix_2s1p },
 271
 272        { 0, } /* terminate list */
 273};
 274MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
 275
 276/*
 277 * This table describes the serial "geometry" of these boards.  Any
 278 * quirks for these can be found in drivers/serial/8250_pci.c
 279 *
 280 * Cards not tested are marked n/t
 281 * If you have one of these cards and it works for you, please tell me..
 282 */
 283static struct pciserial_board pci_parport_serial_boards[] = {
 284        [titan_110l] = {
 285                .flags          = FL_BASE1 | FL_BASE_BARS,
 286                .num_ports      = 1,
 287                .base_baud      = 921600,
 288                .uart_offset    = 8,
 289        },
 290        [titan_210l] = {
 291                .flags          = FL_BASE1 | FL_BASE_BARS,
 292                .num_ports      = 2,
 293                .base_baud      = 921600,
 294                .uart_offset    = 8,
 295        },
 296        [netmos_9xx5_combo] = {
 297                .flags          = FL_BASE0 | FL_BASE_BARS,
 298                .num_ports      = 1,
 299                .base_baud      = 115200,
 300                .uart_offset    = 8,
 301        },
 302        [netmos_9855] = {
 303                .flags          = FL_BASE2 | FL_BASE_BARS,
 304                .num_ports      = 1,
 305                .base_baud      = 115200,
 306                .uart_offset    = 8,
 307        },
 308        [netmos_9855_2p] = {
 309                .flags          = FL_BASE4 | FL_BASE_BARS,
 310                .num_ports      = 1,
 311                .base_baud      = 115200,
 312                .uart_offset    = 8,
 313        },
 314        [netmos_9900] = { /* n/t */
 315                .flags          = FL_BASE0 | FL_BASE_BARS,
 316                .num_ports      = 1,
 317                .base_baud      = 115200,
 318                .uart_offset    = 8,
 319        },
 320        [netmos_9900_2p] = { /* parallel only */ /* n/t */
 321                .flags          = FL_BASE0,
 322                .num_ports      = 0,
 323                .base_baud      = 115200,
 324                .uart_offset    = 8,
 325        },
 326        [netmos_99xx_1p] = { /* parallel only */ /* n/t */
 327                .flags          = FL_BASE0,
 328                .num_ports      = 0,
 329                .base_baud      = 115200,
 330                .uart_offset    = 8,
 331        },
 332        [avlab_1s1p] = { /* n/t */
 333                .flags          = FL_BASE0 | FL_BASE_BARS,
 334                .num_ports      = 1,
 335                .base_baud      = 115200,
 336                .uart_offset    = 8,
 337        },
 338        [avlab_1s2p] = { /* n/t */
 339                .flags          = FL_BASE0 | FL_BASE_BARS,
 340                .num_ports      = 1,
 341                .base_baud      = 115200,
 342                .uart_offset    = 8,
 343        },
 344        [avlab_2s1p] = { /* n/t */
 345                .flags          = FL_BASE0 | FL_BASE_BARS,
 346                .num_ports      = 2,
 347                .base_baud      = 115200,
 348                .uart_offset    = 8,
 349        },
 350        [siig_1s1p_10x] = {
 351                .flags          = FL_BASE2,
 352                .num_ports      = 1,
 353                .base_baud      = 460800,
 354                .uart_offset    = 8,
 355        },
 356        [siig_2s1p_10x] = {
 357                .flags          = FL_BASE2,
 358                .num_ports      = 1,
 359                .base_baud      = 921600,
 360                .uart_offset    = 8,
 361        },
 362        [siig_2p1s_20x] = {
 363                .flags          = FL_BASE0,
 364                .num_ports      = 1,
 365                .base_baud      = 921600,
 366                .uart_offset    = 8,
 367        },
 368        [siig_1s1p_20x] = {
 369                .flags          = FL_BASE0,
 370                .num_ports      = 1,
 371                .base_baud      = 921600,
 372                .uart_offset    = 8,
 373        },
 374        [siig_2s1p_20x] = {
 375                .flags          = FL_BASE0,
 376                .num_ports      = 1,
 377                .base_baud      = 921600,
 378                .uart_offset    = 8,
 379        },
 380        [timedia_4078a] = {
 381                .flags          = FL_BASE0|FL_BASE_BARS,
 382                .num_ports      = 1,
 383                .base_baud      = 921600,
 384                .uart_offset    = 8,
 385        },
 386        [timedia_4079h] = {
 387                .flags          = FL_BASE0|FL_BASE_BARS,
 388                .num_ports      = 1,
 389                .base_baud      = 921600,
 390                .uart_offset    = 8,
 391        },
 392        [timedia_4085h] = {
 393                .flags          = FL_BASE0|FL_BASE_BARS,
 394                .num_ports      = 1,
 395                .base_baud      = 921600,
 396                .uart_offset    = 8,
 397        },
 398        [timedia_4088a] = {
 399                .flags          = FL_BASE0|FL_BASE_BARS,
 400                .num_ports      = 1,
 401                .base_baud      = 921600,
 402                .uart_offset    = 8,
 403        },
 404        [timedia_4089a] = {
 405                .flags          = FL_BASE0|FL_BASE_BARS,
 406                .num_ports      = 1,
 407                .base_baud      = 921600,
 408                .uart_offset    = 8,
 409        },
 410        [timedia_4095a] = {
 411                .flags          = FL_BASE0|FL_BASE_BARS,
 412                .num_ports      = 1,
 413                .base_baud      = 921600,
 414                .uart_offset    = 8,
 415        },
 416        [timedia_4096a] = {
 417                .flags          = FL_BASE0|FL_BASE_BARS,
 418                .num_ports      = 1,
 419                .base_baud      = 921600,
 420                .uart_offset    = 8,
 421        },
 422        [timedia_4078u] = {
 423                .flags          = FL_BASE0|FL_BASE_BARS,
 424                .num_ports      = 1,
 425                .base_baud      = 921600,
 426                .uart_offset    = 8,
 427        },
 428        [timedia_4079a] = {
 429                .flags          = FL_BASE0|FL_BASE_BARS,
 430                .num_ports      = 1,
 431                .base_baud      = 921600,
 432                .uart_offset    = 8,
 433        },
 434        [timedia_4085u] = {
 435                .flags          = FL_BASE0|FL_BASE_BARS,
 436                .num_ports      = 1,
 437                .base_baud      = 921600,
 438                .uart_offset    = 8,
 439        },
 440        [timedia_4079r] = {
 441                .flags          = FL_BASE0|FL_BASE_BARS,
 442                .num_ports      = 1,
 443                .base_baud      = 921600,
 444                .uart_offset    = 8,
 445        },
 446        [timedia_4079s] = {
 447                .flags          = FL_BASE0|FL_BASE_BARS,
 448                .num_ports      = 1,
 449                .base_baud      = 921600,
 450                .uart_offset    = 8,
 451        },
 452        [timedia_4079d] = {
 453                .flags          = FL_BASE0|FL_BASE_BARS,
 454                .num_ports      = 1,
 455                .base_baud      = 921600,
 456                .uart_offset    = 8,
 457        },
 458        [timedia_4079e] = {
 459                .flags          = FL_BASE0|FL_BASE_BARS,
 460                .num_ports      = 1,
 461                .base_baud      = 921600,
 462                .uart_offset    = 8,
 463        },
 464        [timedia_4079f] = {
 465                .flags          = FL_BASE0|FL_BASE_BARS,
 466                .num_ports      = 1,
 467                .base_baud      = 921600,
 468                .uart_offset    = 8,
 469        },
 470        [timedia_9079a] = {
 471                .flags          = FL_BASE0|FL_BASE_BARS,
 472                .num_ports      = 1,
 473                .base_baud      = 921600,
 474                .uart_offset    = 8,
 475        },
 476        [timedia_9079b] = {
 477                .flags          = FL_BASE0|FL_BASE_BARS,
 478                .num_ports      = 1,
 479                .base_baud      = 921600,
 480                .uart_offset    = 8,
 481        },
 482        [timedia_9079c] = {
 483                .flags          = FL_BASE0|FL_BASE_BARS,
 484                .num_ports      = 1,
 485                .base_baud      = 921600,
 486                .uart_offset    = 8,
 487        },
 488        [wch_ch353_1s1p] = {
 489                .flags          = FL_BASE0|FL_BASE_BARS,
 490                .num_ports      = 1,
 491                .base_baud      = 115200,
 492                .uart_offset    = 8,
 493        },
 494        [wch_ch353_2s1p] = {
 495                .flags          = FL_BASE0|FL_BASE_BARS,
 496                .num_ports      = 2,
 497                .base_baud      = 115200,
 498                .uart_offset    = 8,
 499        },
 500        [wch_ch382_2s1p] = {
 501                .flags          = FL_BASE0,
 502                .num_ports      = 2,
 503                .base_baud      = 115200,
 504                .uart_offset    = 8,
 505                .first_offset   = 0xC0,
 506        },
 507        [sunix_2s1p] = {
 508                .flags          = FL_BASE0|FL_BASE_BARS,
 509                .num_ports      = 2,
 510                .base_baud      = 921600,
 511                .uart_offset    = 8,
 512        },
 513};
 514
 515struct parport_serial_private {
 516        struct serial_private   *serial;
 517        int num_par;
 518        struct parport *port[PARPORT_MAX];
 519        struct parport_pc_pci par;
 520};
 521
 522/* Register the serial port(s) of a PCI card. */
 523static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
 524{
 525        struct parport_serial_private *priv = pci_get_drvdata (dev);
 526        struct pciserial_board *board;
 527        struct serial_private *serial;
 528
 529        board = &pci_parport_serial_boards[id->driver_data];
 530
 531        if (board->num_ports == 0)
 532                return 0;
 533
 534        serial = pciserial_init_ports(dev, board);
 535
 536        if (IS_ERR(serial))
 537                return PTR_ERR(serial);
 538
 539        priv->serial = serial;
 540        return 0;
 541}
 542
 543/* Register the parallel port(s) of a PCI card. */
 544static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
 545{
 546        struct parport_pc_pci *card;
 547        struct parport_serial_private *priv = pci_get_drvdata (dev);
 548        int n, success = 0;
 549
 550        priv->par = cards[id->driver_data];
 551        card = &priv->par;
 552        if (card->preinit_hook &&
 553            card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
 554                return -ENODEV;
 555
 556        for (n = 0; n < card->numports; n++) {
 557                struct parport *port;
 558                int lo = card->addr[n].lo;
 559                int hi = card->addr[n].hi;
 560                unsigned long io_lo, io_hi;
 561                int irq;
 562
 563                if (priv->num_par == ARRAY_SIZE (priv->port)) {
 564                        printk (KERN_WARNING
 565                                "parport_serial: %s: only %zu parallel ports "
 566                                "supported (%d reported)\n", pci_name (dev),
 567                                ARRAY_SIZE(priv->port), card->numports);
 568                        break;
 569                }
 570
 571                io_lo = pci_resource_start (dev, lo);
 572                io_hi = 0;
 573                if ((hi >= 0) && (hi <= 6))
 574                        io_hi = pci_resource_start (dev, hi);
 575                else if (hi > 6)
 576                        io_lo += hi; /* Reinterpret the meaning of
 577                                        "hi" as an offset (see SYBA
 578                                        def.) */
 579                /* TODO: test if sharing interrupts works */
 580                irq = dev->irq;
 581                if (irq == IRQ_NONE) {
 582                        dev_dbg(&dev->dev,
 583                        "PCI parallel port detected: I/O at %#lx(%#lx)\n",
 584                                io_lo, io_hi);
 585                        irq = PARPORT_IRQ_NONE;
 586                } else {
 587                        dev_dbg(&dev->dev,
 588                "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
 589                                io_lo, io_hi, irq);
 590                }
 591                port = parport_pc_probe_port (io_lo, io_hi, irq,
 592                              PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
 593                if (port) {
 594                        priv->port[priv->num_par++] = port;
 595                        success = 1;
 596                }
 597        }
 598
 599        if (card->postinit_hook)
 600                card->postinit_hook (dev, card, !success);
 601
 602        return 0;
 603}
 604
 605static int parport_serial_pci_probe(struct pci_dev *dev,
 606                                    const struct pci_device_id *id)
 607{
 608        struct parport_serial_private *priv;
 609        int err;
 610
 611        priv = kzalloc (sizeof *priv, GFP_KERNEL);
 612        if (!priv)
 613                return -ENOMEM;
 614        pci_set_drvdata (dev, priv);
 615
 616        err = pci_enable_device (dev);
 617        if (err) {
 618                kfree (priv);
 619                return err;
 620        }
 621
 622        if (parport_register (dev, id)) {
 623                kfree (priv);
 624                return -ENODEV;
 625        }
 626
 627        if (serial_register (dev, id)) {
 628                int i;
 629                for (i = 0; i < priv->num_par; i++)
 630                        parport_pc_unregister_port (priv->port[i]);
 631                kfree (priv);
 632                return -ENODEV;
 633        }
 634
 635        return 0;
 636}
 637
 638static void parport_serial_pci_remove(struct pci_dev *dev)
 639{
 640        struct parport_serial_private *priv = pci_get_drvdata (dev);
 641        int i;
 642
 643        // Serial ports
 644        if (priv->serial)
 645                pciserial_remove_ports(priv->serial);
 646
 647        // Parallel ports
 648        for (i = 0; i < priv->num_par; i++)
 649                parport_pc_unregister_port (priv->port[i]);
 650
 651        kfree (priv);
 652        return;
 653}
 654
 655#ifdef CONFIG_PM
 656static int parport_serial_pci_suspend(struct pci_dev *dev, pm_message_t state)
 657{
 658        struct parport_serial_private *priv = pci_get_drvdata(dev);
 659
 660        if (priv->serial)
 661                pciserial_suspend_ports(priv->serial);
 662
 663        /* FIXME: What about parport? */
 664
 665        pci_save_state(dev);
 666        pci_set_power_state(dev, pci_choose_state(dev, state));
 667        return 0;
 668}
 669
 670static int parport_serial_pci_resume(struct pci_dev *dev)
 671{
 672        struct parport_serial_private *priv = pci_get_drvdata(dev);
 673        int err;
 674
 675        pci_set_power_state(dev, PCI_D0);
 676        pci_restore_state(dev);
 677
 678        /*
 679         * The device may have been disabled.  Re-enable it.
 680         */
 681        err = pci_enable_device(dev);
 682        if (err) {
 683                printk(KERN_ERR "parport_serial: %s: error enabling "
 684                        "device for resume (%d)\n", pci_name(dev), err);
 685                return err;
 686        }
 687
 688        if (priv->serial)
 689                pciserial_resume_ports(priv->serial);
 690
 691        /* FIXME: What about parport? */
 692
 693        return 0;
 694}
 695#endif
 696
 697static struct pci_driver parport_serial_pci_driver = {
 698        .name           = "parport_serial",
 699        .id_table       = parport_serial_pci_tbl,
 700        .probe          = parport_serial_pci_probe,
 701        .remove         = parport_serial_pci_remove,
 702#ifdef CONFIG_PM
 703        .suspend        = parport_serial_pci_suspend,
 704        .resume         = parport_serial_pci_resume,
 705#endif
 706};
 707
 708
 709static int __init parport_serial_init (void)
 710{
 711        return pci_register_driver (&parport_serial_pci_driver);
 712}
 713
 714static void __exit parport_serial_exit (void)
 715{
 716        pci_unregister_driver (&parport_serial_pci_driver);
 717        return;
 718}
 719
 720MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
 721MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
 722MODULE_LICENSE("GPL");
 723
 724module_init(parport_serial_init);
 725module_exit(parport_serial_exit);
 726